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lvds-mono-16m
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9 Commits 1 Branch 0 Tags 221 MiB
Verilog 87.4%
VHDL 9.6%
Tcl 1.4%
Perl 1%
Stata 0.3%
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17828169534 9ca6f89b22 对译码数据进行同步处理：修改A_sp_pad引脚； 2024-03-19 15:10:48 +08:00
sim/1123 update mipi.dat, 2024-03-14 02:36:35 -04:00
src 对译码数据进行同步处理：修改A_sp_pad引脚； 2024-03-19 15:10:48 +08:00