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lvds-mono-16m
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initial version.

This commit is contained in:
17828169534 2024-02-19 11:09:38 +08:00
parent c1965ff843
commit 9795616967
54 changed files with 29648 additions and 5406 deletions
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14
src/hg_mp/drx_top/huagao_mipi_top.v
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@ -664,7 +664,7 @@ end
reg en_packet_dly;
wire [3:0] adc_freqdiv;
wire [5:0]debug_1;
wire [4:0]debug_1;
wire [5:0]debug_2;
wire [3:0]debug_3;
wire [31:0] bg_sp_t_a;
@ -960,7 +960,7 @@ sampling_fe #
.start_sp (start_sp_a ),
.rd_done (rd_done ),
.line_sycn (line_sycn_a ),
.debug(debug_1[5:0]),
.debug(debug_1[4:0]),
.cis_sel(cis_sel)
);
@ -1695,12 +1695,12 @@ always @(*) begin
end
assign debug[0] = a_vs ;
assign debug[1] = a_ad_sck;
assign debug[2] = a_ad_sen ;
assign debug[3] = a_ad_sdi;
assign debug[4] = a_ad_sdo ;
assign debug[1] = debug_1[3];
assign debug[2] = debug_1[2] ;
assign debug[3] = debug_1[1];
assign debug[4] = debug_1[0] ;
assign debug[5] = FV_MIPI ;
assign debug[6] = sync_eot ;
assign debug[6] = debug_1[4] ;
assign debug[7] = LV_MIPI;

12
src/hg_mp/fe/prebuffer.v
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@ -9,7 +9,7 @@ module data_prebuffer
dataA_ADC,
dataB_ADC,
dataC_ADC,
data_CTL_ADC,
data_CTL_ADC,
PBUFF_DATA_CONTROL,
trigRAM,
trigCAM,
@ -24,7 +24,9 @@ module data_prebuffer
rd_done_trig,
start_sp_wr,
start_sp_rd,
cis_sel
cis_sel,
soft_n,
debug
);
@ -77,6 +79,8 @@ output rd_done_trig;
input start_sp_wr;
input start_sp_rd;
input cis_sel;
input soft_n;
output wire [4:0]debug;
@ -375,6 +379,7 @@ read_ram #(
(
.clk(camclk),
.rst_n(rst_n),
.soft_n(soft_n),
.trig(trig_cam),
.full(full_sync),
.dou(dou),
@ -386,7 +391,8 @@ read_ram #(
.DVAL(DVAL),
.rd_done_trig(rd_done_trig),
.wr_end(wr_end),
.start_sp(start_sp_rd)
.start_sp(start_sp_rd) ,
.debug(debug)
);
generate

5
src/hg_mp/fe/prebuffer_rev.v
View File

@ -25,7 +25,8 @@ module data_prebuffer_rev
ab_delay_time,
start_sp_wr,
start_sp_rd,
cis_sel
cis_sel,
soft_n
);
@ -79,6 +80,7 @@ input [15:0] ab_delay_time;
input start_sp_wr;
input start_sp_rd;
input cis_sel;
input soft_n;
@ -377,6 +379,7 @@ read_ram_rev #(
(
.clk(camclk),
.rst_n(rst_n),
.soft_n(soft_n),
.trig(trig_cam),
.full(full_sync),
.dou(dou),

13
src/hg_mp/fe/read_ram.v
View File

@ -13,7 +13,9 @@ module read_ram
LVAL,
rd_done_trig,
wr_end,
start_sp
start_sp,
soft_n,
debug
);
parameter integer RD_DONE_WIDTH = 14;
parameter integer PBUFF_TAP_NUM = 8;
@ -32,6 +34,8 @@ output [PBUFF_ADDR_WIDTH*PBUFF_RAM_NUM-1:0] RD_addr_i;
output rd_done_trig;
input wr_end;
input start_sp;
input soft_n;
output wire [4:0]debug;
wire sync_wr_end;
cdc_sync # (
@ -43,7 +47,7 @@ cdc_sync # (
.signal_from(wr_end),
.signal_to (sync_wr_end)
);
read_ram_data #(
.RD_DONE_WIDTH(RD_DONE_WIDTH),
@ -54,6 +58,7 @@ read_ram_data
(
.clk(clk),
.rst_n(rst_n),
.soft_n(soft_n),
.trig(trig),
.full(full),
.rd_done(rd_done),
@ -64,7 +69,8 @@ read_ram_data
.LVAL(LVAL),
.rd_done_trig(rd_done_trig),
.wr_end(sync_wr_end),
.start_sp(start_sp)
.start_sp(start_sp),
.debug(debug)
);
@ -78,6 +84,7 @@ read_ram_addr
(
.clk(clk),
.rst_n(rst_n),
.soft_n(soft_n),
.trig(trig),
.full(full),
.rd_done(rd_done),

8
src/hg_mp/fe/read_ram_addr.v
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@ -8,7 +8,8 @@ module read_ram_addr
RD_addr,
RD_addr_i,
wr_end,
start_sp
start_sp,
soft_n
);
parameter integer PBUFF_ADDR_WIDTH = 13;
parameter integer RD_DONE_WIDTH = 13;
@ -24,6 +25,7 @@ input [RD_DONE_WIDTH-1:0] RD_addr;
output reg [PBUFF_ADDR_WIDTH*PBUFF_RAM_NUM-1:0] RD_addr_i;
input wr_end;
input start_sp;
input soft_n;
//culculate
localparam integer PBUFF_DIV = PBUFF_RAM_NUM / PBUFF_TAP_NUM;
@ -83,6 +85,7 @@ assign end_trig = (cam_end_delay == 4'hf);
always @(posedge clk)
if(~rst_n) current_state <= WAIT_WR;
else if(~soft_n)current_state <= WAIT_WR;
else if(start_sp) current_state <= WAIT_WR;
else if(full) current_state <= current_state;
else current_state <= next_state;
@ -100,16 +103,19 @@ endcase
always @(posedge clk)
if(~rst_n) start_cnt <= 'd0;
else if(~soft_n)start_cnt <= 'd0;
else if(current_state == RD_DELAY) start_cnt <= start_cnt + 1'b1;
else start_cnt <= 'd0;
always @(posedge clk)
if(~rst_n) cam_end_delay <= 'd0;
else if(~soft_n) cam_end_delay <= 'd0;
else if(current_state == RD_END) cam_end_delay <= cam_end_delay + 1'b1;
else cam_end_delay <= 'd0;
always @(posedge clk)//xun huan zhuang hai ji
if(~rst_n) state_index <= 'd0;
else if(~soft_n) state_index <= 'd0;
else case(current_state)
RD_DELAY : state_index <= |start_cnt ? state_index + 1'b1 : 'd0;//delay 1 clk
RD_START : state_index <= state_index + 1'b1;

8
src/hg_mp/fe/read_ram_addr_rev.v
View File

@ -9,7 +9,8 @@ module read_ram_addr_rev
RD_addr_i,
rd_finish,
ab_delay_time,
start_sp
start_sp,
soft_n
);
parameter integer PBUFF_ADDR_WIDTH = 13;
parameter integer RD_DONE_WIDTH = 13;
@ -26,6 +27,7 @@ input rd_finish;
output reg [PBUFF_ADDR_WIDTH*PBUFF_RAM_NUM-1:0] RD_addr_i;
input [15:0]ab_delay_time;
input start_sp;
input soft_n;
//culculate
localparam integer PBUFF_DIV = PBUFF_RAM_NUM / PBUFF_TAP_NUM;
@ -84,6 +86,7 @@ assign end_trig = (cam_end_delay == 4'hf);
always @(posedge clk)
if(~rst_n) current_state <= IDLE_RD;
else if(~soft_n)current_state <= IDLE_RD;
else if(start_sp)current_state <= IDLE_RD;
else if(full) current_state <= current_state;
else current_state <= next_state;
@ -117,16 +120,19 @@ endcase
always @(posedge clk)
if(~rst_n) start_cnt <= 'd0;
else if(~soft_n)start_cnt <= 'd0;
else if(current_state == RD_DELAY) start_cnt <= start_cnt + 1'b1;
else start_cnt <= 'd0;
always @(posedge clk)
if(~rst_n) cam_end_delay <= 'd0;
else if(~soft_n) cam_end_delay <= 'd0;
else if(current_state == RD_END) cam_end_delay <= cam_end_delay + 1'b1;
else cam_end_delay <= 'd0;
always @(posedge clk)//xun huan zhuang hai ji
if(~rst_n) state_index <= 'd0;
else if(~soft_n) state_index <= 'd0;
else case(current_state)
RD_DELAY : state_index <= |start_cnt ? state_index + 1'b1 : 'd0;//delay 1 clk
RD_START : state_index <= state_index + 1'b1;

21
src/hg_mp/fe/read_ram_data.v
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@ -12,7 +12,9 @@ module read_ram_data
LVAL,
rd_done_trig,
wr_end,
start_sp
start_sp,
soft_n,
debug
);
parameter integer RD_DONE_WIDTH = 13;
parameter integer PBUFF_TAP_NUM = 8;
@ -30,6 +32,8 @@ output reg DVAL,LVAL;
output rd_done_trig;
input wr_end;
input start_sp;
input soft_n;
output wire [4:0]debug;
/////////////////////////RD_DATA////////////////////////////////
localparam WAIT_WR = 5'b00001;
@ -61,10 +65,18 @@ else full_r <= full;
always @(posedge clk)
if(~rst_n) current_state <= WAIT_WR;
else if(~soft_n)current_state <= WAIT_WR;
else if(start_sp)current_state <= WAIT_WR;
else if(full) current_state <= current_state;
else current_state <= next_state;
assign debug[0] = wr_end;
assign debug[1] = trig;
assign debug[2] = start_trig;
assign debug[3] = rd_done_trig;
assign debug[4] = end_trig;
always @(current_state,wr_end,trig,start_trig,rd_done_trig,end_trig)
case(current_state)
WAIT_WR:next_state <= wr_end ? IDLE_RD : WAIT_WR;
@ -77,27 +89,32 @@ endcase
always @(posedge clk)
if(~rst_n) start_cnt <= 'd0;
else if(~soft_n)start_cnt <= 'd0;
else if(current_state == RD_DELAY) start_cnt <= start_cnt + 1'b1;
else start_cnt <= 'd0;
always @(posedge clk)
if(~rst_n) cam_end_delay <= 'd0;
else if(~soft_n)cam_end_delay <= 'd0;
else if(current_state == RD_END) cam_end_delay <= cam_end_delay + 1'b1;
else cam_end_delay <= 'd0;
always @(posedge clk)
if(~rst_n) RD_addr <= 'd0;
else if(~soft_n) RD_addr <= 'd0;
else if(current_state == RD_DELAY || current_state == RD_SWITCH)
RD_addr <= full ? RD_addr : RD_addr + 1'b1;
else RD_addr <= 'd0;
always @(posedge clk)//xun huan zhuang hai ji
if(~rst_n) state_index <= 'd0;
else if(~soft_n) state_index <= 'd0;
else if(current_state == RD_SWITCH) state_index <= full ? state_index : (state_index==PBUFF_RAM_NUM-1) ? 'd0 : state_index + 1'b1;
else state_index <= 'd0;
always @(posedge clk)//xun huan zhuang hai ji
if(~rst_n) state_index_d1 <= 'd0;
else if(~soft_n)state_index_d1 <= 'd0;
else state_index_d1 <= state_index;
@ -110,11 +127,13 @@ assign camdata = camdata_tmp ;
always @(posedge clk)
if(~rst_n) DVAL <= 1'b0;
else if(~soft_n)DVAL <= 1'b0;
else if(current_state == RD_SWITCH) DVAL <= full ? 1'b0 : 1'b1;
else DVAL <= 1'b0;
always @(posedge clk)
if(~rst_n) LVAL <= 1'b0;
else if(~soft_n)LVAL <= 1'b0;
else case(current_state)
RD_DELAY: LVAL <= start_trig ? 1'b1 : 1'b0;
RD_SWITCH:LVAL <= full ? 1'b0 : 1'b1;

14
src/hg_mp/fe/read_ram_data_rev.v
View File

@ -12,7 +12,8 @@ module read_ram_data_rev
LVAL,
rd_finish,
ab_delay_time,
start_sp
start_sp,
soft_n
);
parameter integer RD_DONE_WIDTH = 13;
parameter integer PBUFF_TAP_NUM = 8;
@ -30,6 +31,7 @@ output reg DVAL,LVAL;
input rd_finish;
input [15:0] ab_delay_time;
input start_sp;
input soft_n;
/////////////////////////RD_DATA////////////////////////////////
localparam IDLE_RD = 4'b0001;
@ -60,6 +62,7 @@ else full_r <= full;
always @(posedge clk)
if(~rst_n) current_state <= IDLE_RD;
else if(~soft_n)current_state <= IDLE_RD;
else if(start_sp)current_state <= IDLE_RD;
else if(full) current_state <= current_state;
else current_state <= next_state;
@ -91,27 +94,32 @@ endcase
always @(posedge clk)
if(~rst_n) start_cnt <= 'd0;
else if(~soft_n)start_cnt <= 'd0;
else if(current_state == RD_DELAY) start_cnt <= start_cnt + 1'b1;
else start_cnt <= 'd0;
always @(posedge clk)
if(~rst_n) cam_end_delay <= 'd0;
else if(~soft_n)cam_end_delay <= 'd0;
else if(current_state == RD_END) cam_end_delay <= cam_end_delay + 1'b1;
else cam_end_delay <= 'd0;
always @(posedge clk)
if(~rst_n) RD_addr <= 'd0;
else if(~soft_n) RD_addr <= 'd0;
else if( current_state == RD_SWITCH)
RD_addr <= full ? RD_addr : RD_addr + 1'b1;
else RD_addr <= 'd0;
always @(posedge clk)//xun huan zhuang hai ji
if(~rst_n) state_index <= 'd0;
else if(~soft_n) state_index <= 'd0;
else if(current_state == RD_SWITCH) state_index <= full ? state_index : (state_index==PBUFF_RAM_NUM-1) ? 'd0 : state_index + 1'b1;
else state_index <= 'd0;
always @(posedge clk)//xun huan zhuang hai ji
if(~rst_n) state_index_d1 <= 'd0;
else if(~soft_n)state_index_d1 <= 'd0;
else state_index_d1 <= state_index;
@ -124,11 +132,13 @@ assign camdata = camdata_tmp ;
always @(posedge clk)
if(~rst_n) DVAL <= 1'b0;
else if(~soft_n)DVAL <= 1'b0;
else if(current_state == RD_SWITCH) DVAL <= full ? 1'b0 : 1'b1;
else DVAL <= 1'b0;
always @(posedge clk)
if(~rst_n) LVAL <= 1'b0;
else if(~soft_n)LVAL <= 1'b0;
else case(current_state)
RD_DELAY: LVAL <= start_trig ? 1'b1 : 1'b0;
RD_SWITCH:LVAL <= full ? 1'b0 : 1'b1;
@ -138,7 +148,7 @@ endcase
mux_i #(
.WIDTH(8),
.WIDTH(8),
.I_NUM(PBUFF_RAM_NUM),
.O_NUM(PBUFF_TAP_NUM)
) mux_i(

8
src/hg_mp/fe/read_ram_rev.v
View File

@ -13,7 +13,8 @@ module read_ram_rev
LVAL,
rd_end,
ab_delay_time,
start_sp
start_sp,
soft_n
);
parameter integer RD_DONE_WIDTH = 14;
parameter integer PBUFF_TAP_NUM = 8;
@ -32,6 +33,7 @@ output [PBUFF_ADDR_WIDTH*PBUFF_RAM_NUM-1:0] RD_addr_i;
input [15:0] ab_delay_time;
input rd_end;
input start_sp;
input soft_n;
read_ram_data_rev#(
.RD_DONE_WIDTH(RD_DONE_WIDTH),
@ -40,8 +42,9 @@ read_ram_data_rev#(
)
read_ram_data
(
.clk(clk),
.clk(clk),
.rst_n(rst_n),
.soft_n(soft_n),
.trig(trig),
.full(full),
.rd_done(rd_done),
@ -65,6 +68,7 @@ read_ram_addr
(
.clk(clk),
.rst_n(rst_n),
.soft_n(soft_n),
.trig(trig),
.full(full),
.rd_done(rd_done),

2
src/hg_mp/fe/sampling_fe.v
View File

@ -24,7 +24,7 @@ module sampling_fe
output fe_done ,
output rd_done ,
output line_sycn,
output wire [5:0] debug,
output wire [4:0] debug,
output wire [1:0] debug_2,
input cis_sel
// output [23 : 0] rdaddr_a

34
src/hg_mp/fe/sort.v
View File

@ -17,12 +17,12 @@ module sort
input [1 : 0] dpi_mode ,
input cis_mode ,
input [YPIXEL_WIDTH-1: 0] y_pixel ,
output [23: 0] data_o ,
output dval_o ,
output reg [23: 0] data_o ,
output reg dval_o ,
output fe_done ,
output rd_done,
output end_trig ,
output wire [5:0] debug,
output wire [4:0] debug,
input [4:0] lvds_flag ,
input [4:0] set_flag ,
input cis_sel
@ -317,6 +317,7 @@ data_prebuffer u_data_prebuffer
(
.FIFO_rdclk (wrclk),//frequency equal to dataclk_ADCx
.rst_n (reset_n),
.soft_n (sync_rdsoft_n),
.DPIset (dpi_mode),
.dataclk_ADC (wrclk),
.dataA_ADC (ch25_1d),
@ -336,7 +337,8 @@ data_prebuffer u_data_prebuffer
.rd_done_trig(rd_done),
.start_sp_wr(pos_frame_start_wr),
.start_sp_rd(pos_frame_start_rd),
.cis_sel (cis_sel )
.cis_sel (cis_sel ),
.debug(debug)
);
@ -410,8 +412,26 @@ begin
else dval_o_200dpi_d1 <= dval_o_200dpi;
end
assign data_o = cis_sel ? data_o_tmp : (dpi_mode == 2'b01 ? data_o_200dpi : data_o_tmp);
assign dval_o = cis_sel ? dval_o_tmp : (dpi_mode == 2'b01 ? dval_o_200dpi : dval_o_tmp);
always @ (posedge rdclk )
begin
if(!reset_n) data_o <= 24'b0;
else if (~sync_rdsoft_n) data_o <= 24'b0;
else if (cis_sel) data_o <= data_o_tmp;
else if (dpi_mode == 2'b01) data_o <= data_o_200dpi;
else data_o <= data_o_tmp;
end
assign debug[0] = cis_sel;
always @ (posedge rdclk )
begin
if(!reset_n) dval_o <= 1'b0;
else if (~sync_rdsoft_n) dval_o <= 1'b0;
else if (cis_sel) dval_o <= dval_o_tmp;
else if (dpi_mode == 2'b01) dval_o <= dval_o_200dpi;
else dval_o <= dval_o_tmp;
end
//assign data_o = cis_sel ? data_o_tmp : (dpi_mode == 2'b01 ? data_o_200dpi : data_o_tmp);
//assign dval_o = cis_sel ? dval_o_tmp : (dpi_mode == 2'b01 ? dval_o_200dpi : dval_o_tmp);
//assign debug[0] = cis_sel;
endmodule

30
src/hg_mp/fe/sort_rev.v
View File

@ -17,8 +17,8 @@ module sort_rev
input [1 : 0] dpi_mode ,
input cis_mode ,
input [YPIXEL_WIDTH-1: 0] y_pixel ,
output [23: 0] data_o ,
output dval_o ,
output reg [23: 0] data_o ,
output reg dval_o ,
output fe_done ,
input rd_done ,
output wren,
@ -349,8 +349,9 @@ data_prebuffer_rev u_data_prebuffer_rev
(
.FIFO_rdclk (wrclk),//frequency equal to dataclk_ADCx
.rst_n (reset_n),
.soft_n (sync_rdsoft_n),
.DPIset (dpi_mode),
.dataclk_ADC (wrclk),
.dataclk_ADC (wrclk),
.dataA_ADC (ch25_1d),
.dataB_ADC (ch14_1d),
.dataC_ADC (ch03_1d),
@ -447,7 +448,26 @@ begin
end
assign data_o = cis_sel ? data_o_tmp_1d : (dpi_mode == 2'b01 ? data_o_200dpi_d1 : data_o_tmp_1d);
assign dval_o = cis_sel ? dval_o_tmp_1d : (dpi_mode == 2'b01 ? dval_o_200dpi_d1 : dval_o_tmp_1d);
always @ (posedge rdclk )
begin
if(!reset_n) data_o <= 24'b0;
else if (~sync_rdsoft_n) data_o <= 24'b0;
else if (cis_sel) data_o <= data_o_tmp;
else if (dpi_mode == 2'b01) data_o <= data_o_200dpi;
else data_o <= data_o_tmp;
end
always @ (posedge rdclk )
begin
if(!reset_n) dval_o <= 1'b0;
else if (~sync_rdsoft_n) dval_o <= 1'b0;
else if (cis_sel) dval_o <= dval_o_tmp;
else if (dpi_mode == 2'b01) dval_o <= dval_o_200dpi;
else dval_o <= dval_o_tmp;
end
//assign data_o = cis_sel ? data_o_tmp_1d : (dpi_mode == 2'b01 ? data_o_200dpi_d1 : data_o_tmp_1d);
//assign dval_o = cis_sel ? dval_o_tmp_1d : (dpi_mode == 2'b01 ? dval_o_200dpi_d1 : dval_o_tmp_1d);
endmodule

42
src/prj/td_project/hg_anlogic.adc
View File

@ -13,28 +13,28 @@ set_pin_assignment { O_data_lp_p[0] } { LOCATION = P63; IOSTANDARD = LVCMOS25; D
set_pin_assignment { O_data_lp_p[1] } { LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; }
set_pin_assignment { O_data_lp_p[2] } { LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; }
set_pin_assignment { O_data_lp_p[3] } { LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; }
set_pin_assignment { b_ad_sck } { LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { b_ad_sdi } { LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
set_pin_assignment { b_ad_sdo } { LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { b_ad_sen } { LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { b_lvds_clk_p } { LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { b_lvds_data_p[0] } { LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { b_lvds_data_p[1] } { LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { b_lvds_data_p[2] } { LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { b_lvds_data_p[3] } { LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { b_lvds_data_p[4] } { LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { a_ad_sck } { LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { a_ad_sdi } { LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
set_pin_assignment { a_ad_sdo } { LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { a_ad_sen } { LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { a_lvds_clk_p } { LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { a_lvds_data_p[0] } { LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { a_lvds_data_p[1] } { LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { a_lvds_data_p[2] } { LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { a_lvds_data_p[3] } { LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { a_lvds_data_p[4] } { LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { b_sp_pad } { LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { a_ad_sck } { LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { a_ad_sdi } { LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
set_pin_assignment { a_ad_sdo } { LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { a_ad_sen } { LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { a_lvds_clk_p } { LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { a_lvds_data_p[0] } { LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { a_lvds_data_p[1] } { LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { a_lvds_data_p[2] } { LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { a_lvds_data_p[3] } { LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { a_lvds_data_p[4] } { LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { a_sp_pad } { LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { b_ad_sck } { LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { b_ad_sdi } { LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
set_pin_assignment { b_ad_sdo } { LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { b_ad_sen } { LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { b_lvds_clk_p } { LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { b_lvds_data_p[0] } { LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { b_lvds_data_p[1] } { LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { b_lvds_data_p[2] } { LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { b_lvds_data_p[3] } { LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { b_lvds_data_p[4] } { LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { b_sp_pad } { LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { clock_source } { LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
set_pin_assignment { debug[0] } { LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { debug[1] } { LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }

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@ -0,0 +1,422 @@
============================================================
Tang Dynasty, V5.6.71036
Copyright (c) 2012-2023 Anlogic Inc.
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
Built at = 20:34:38 Mar 21 2023
Run by = holdtecs
Run Date = Mon Feb 19 10:30:46 2024
Run on = DESKTOP-5MQL5VE
============================================================
RUN-1002 : start command "open_project hg_anlogic.prj"
RUN-1001 : Print Global Property
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : message | standard | standard |
RUN-1001 : mixed_pack_place_flow | on | on |
RUN-1001 : qor_monitor | off | off |
RUN-1001 : syn_ip_flow | off | off |
RUN-1001 : thread | auto | auto |
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Rtl Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : compress_add | ripple | ripple |
RUN-1001 : elf_sload | off | off |
RUN-1001 : fix_undriven | 0 | 0 |
RUN-1001 : flatten | off | off |
RUN-1001 : gate_sharing | on | on |
RUN-1001 : hdl_warning_level | normal | normal |
RUN-1001 : impl_internal_tribuf | on | on |
RUN-1001 : impl_set_reset | on | on |
RUN-1001 : infer_gsr | off | off |
RUN-1001 : keep_hierarchy | auto | auto |
RUN-1001 : max_fanout | 9999 | 9999 |
RUN-1001 : max_oh2bin_len | 10 | 10 |
RUN-1001 : merge_equal | on | on |
RUN-1001 : merge_equiv | on | on |
RUN-1001 : merge_mux | off | off |
RUN-1001 : min_control_set | 8 | 8 |
RUN-1001 : min_ripple_len | auto | auto |
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
RUN-1001 : opt_adder_fanout | on | on |
RUN-1001 : opt_arith | on | on |
RUN-1001 : opt_big_gate | off | off |
RUN-1001 : opt_const | on | on |
RUN-1001 : opt_const_mult | on | on |
RUN-1001 : opt_lessthan | on | on |
RUN-1001 : opt_mux | off | off |
RUN-1001 : opt_ram | high | high |
RUN-1001 : rtl_sim_model | off | off |
RUN-1001 : seq_syn | on | on |
RUN-1001 : --------------------------------------------------------------
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
This product includes software developed by the OpenSSL Project
for use in the OpenSSL Toolkit (http://www.openssl.org/)
Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
All rights reserved.
This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
RUN-1001 : Project manager successfully analyzed 60 source files.
RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
ARC-1001 : Device Initialization.
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : OPTION | IO | SETTING
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
ARC-1001 : done | P10 | gpio
ARC-1001 : program_b | P134 | dedicate
ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
ARC-1001 : ----------------------------------------------------------------------
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
RUN-1002 : start command "elaborate -top huagao_mipi_top"
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Rtl Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : compress_add | ripple | ripple |
RUN-1001 : elf_sload | off | off |
RUN-1001 : fix_undriven | 0 | 0 |
RUN-1001 : flatten | off | off |
RUN-1001 : gate_sharing | on | on |
RUN-1001 : hdl_warning_level | normal | normal |
RUN-1001 : impl_internal_tribuf | on | on |
RUN-1001 : impl_set_reset | on | on |
RUN-1001 : infer_gsr | off | off |
RUN-1001 : keep_hierarchy | auto | auto |
RUN-1001 : max_fanout | 9999 | 9999 |
RUN-1001 : max_oh2bin_len | 10 | 10 |
RUN-1001 : merge_equal | on | on |
RUN-1001 : merge_equiv | on | on |
RUN-1001 : merge_mux | off | off |
RUN-1001 : min_control_set | 8 | 8 |
RUN-1001 : min_ripple_len | auto | auto |
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
RUN-1001 : opt_adder_fanout | on | on |
RUN-1001 : opt_arith | on | on |
RUN-1001 : opt_big_gate | off | off |
RUN-1001 : opt_const | on | on |
RUN-1001 : opt_const_mult | on | on |
RUN-1001 : opt_lessthan | on | on |
RUN-1001 : opt_mux | off | off |
RUN-1001 : opt_ram | high | high |
RUN-1001 : rtl_sim_model | off | off |
RUN-1001 : seq_syn | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Global Property
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : message | standard | standard |
RUN-1001 : mixed_pack_place_flow | on | on |
RUN-1001 : qor_monitor | off | off |
RUN-1001 : syn_ip_flow | off | off |
RUN-1001 : thread | auto | auto |
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
HDL-7007 CRITICAL-WARNING: instantiate unknown module read_ram in ../../../../hg_mp/fe/prebuffer.v(373)
HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
HDL-5007 WARNING: actual bit length 6 differs from formal bit length 4 for port 'debug' in ../../../../hg_mp/fe/sampling_fe.v(140)
HDL-5007 WARNING: actual bit length 4 differs from formal bit length 6 for port 'debug' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(963)
HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
HDL-8007 ERROR: read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) is a black box in ../../../../hg_mp/fe/prebuffer.v(373)
RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240219_103046.log"

422
src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_103102.log Normal file
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@ -0,0 +1,422 @@
============================================================
Tang Dynasty, V5.6.71036
Copyright (c) 2012-2023 Anlogic Inc.
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
Built at = 20:34:38 Mar 21 2023
Run by = holdtecs
Run Date = Mon Feb 19 10:31:02 2024
Run on = DESKTOP-5MQL5VE
============================================================
RUN-1002 : start command "open_project hg_anlogic.prj"
RUN-1001 : Print Global Property
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : message | standard | standard |
RUN-1001 : mixed_pack_place_flow | on | on |
RUN-1001 : qor_monitor | off | off |
RUN-1001 : syn_ip_flow | off | off |
RUN-1001 : thread | auto | auto |
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Rtl Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : compress_add | ripple | ripple |
RUN-1001 : elf_sload | off | off |
RUN-1001 : fix_undriven | 0 | 0 |
RUN-1001 : flatten | off | off |
RUN-1001 : gate_sharing | on | on |
RUN-1001 : hdl_warning_level | normal | normal |
RUN-1001 : impl_internal_tribuf | on | on |
RUN-1001 : impl_set_reset | on | on |
RUN-1001 : infer_gsr | off | off |
RUN-1001 : keep_hierarchy | auto | auto |
RUN-1001 : max_fanout | 9999 | 9999 |
RUN-1001 : max_oh2bin_len | 10 | 10 |
RUN-1001 : merge_equal | on | on |
RUN-1001 : merge_equiv | on | on |
RUN-1001 : merge_mux | off | off |
RUN-1001 : min_control_set | 8 | 8 |
RUN-1001 : min_ripple_len | auto | auto |
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
RUN-1001 : opt_adder_fanout | on | on |
RUN-1001 : opt_arith | on | on |
RUN-1001 : opt_big_gate | off | off |
RUN-1001 : opt_const | on | on |
RUN-1001 : opt_const_mult | on | on |
RUN-1001 : opt_lessthan | on | on |
RUN-1001 : opt_mux | off | off |
RUN-1001 : opt_ram | high | high |
RUN-1001 : rtl_sim_model | off | off |
RUN-1001 : seq_syn | on | on |
RUN-1001 : --------------------------------------------------------------
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
This product includes software developed by the OpenSSL Project
for use in the OpenSSL Toolkit (http://www.openssl.org/)
Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
All rights reserved.
This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
RUN-1001 : Project manager successfully analyzed 60 source files.
RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
ARC-1001 : Device Initialization.
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : OPTION | IO | SETTING
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
ARC-1001 : done | P10 | gpio
ARC-1001 : program_b | P134 | dedicate
ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
ARC-1001 : ----------------------------------------------------------------------
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
RUN-1002 : start command "elaborate -top huagao_mipi_top"
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Rtl Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : compress_add | ripple | ripple |
RUN-1001 : elf_sload | off | off |
RUN-1001 : fix_undriven | 0 | 0 |
RUN-1001 : flatten | off | off |
RUN-1001 : gate_sharing | on | on |
RUN-1001 : hdl_warning_level | normal | normal |
RUN-1001 : impl_internal_tribuf | on | on |
RUN-1001 : impl_set_reset | on | on |
RUN-1001 : infer_gsr | off | off |
RUN-1001 : keep_hierarchy | auto | auto |
RUN-1001 : max_fanout | 9999 | 9999 |
RUN-1001 : max_oh2bin_len | 10 | 10 |
RUN-1001 : merge_equal | on | on |
RUN-1001 : merge_equiv | on | on |
RUN-1001 : merge_mux | off | off |
RUN-1001 : min_control_set | 8 | 8 |
RUN-1001 : min_ripple_len | auto | auto |
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
RUN-1001 : opt_adder_fanout | on | on |
RUN-1001 : opt_arith | on | on |
RUN-1001 : opt_big_gate | off | off |
RUN-1001 : opt_const | on | on |
RUN-1001 : opt_const_mult | on | on |
RUN-1001 : opt_lessthan | on | on |
RUN-1001 : opt_mux | off | off |
RUN-1001 : opt_ram | high | high |
RUN-1001 : rtl_sim_model | off | off |
RUN-1001 : seq_syn | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Global Property
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : message | standard | standard |
RUN-1001 : mixed_pack_place_flow | on | on |
RUN-1001 : qor_monitor | off | off |
RUN-1001 : syn_ip_flow | off | off |
RUN-1001 : thread | auto | auto |
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
HDL-7007 CRITICAL-WARNING: instantiate unknown module read_ram in ../../../../hg_mp/fe/prebuffer.v(373)
HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
HDL-5007 WARNING: actual bit length 6 differs from formal bit length 4 for port 'debug' in ../../../../hg_mp/fe/sampling_fe.v(140)
HDL-5007 WARNING: actual bit length 4 differs from formal bit length 6 for port 'debug' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(963)
HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
HDL-8007 ERROR: read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) is a black box in ../../../../hg_mp/fe/prebuffer.v(373)
RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240219_103102.log"

424
src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_103120.log Normal file
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@ -0,0 +1,424 @@
============================================================
Tang Dynasty, V5.6.71036
Copyright (c) 2012-2023 Anlogic Inc.
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
Built at = 20:34:38 Mar 21 2023
Run by = holdtecs
Run Date = Mon Feb 19 10:31:20 2024
Run on = DESKTOP-5MQL5VE
============================================================
RUN-1002 : start command "open_project hg_anlogic.prj"
RUN-1001 : Print Global Property
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : message | standard | standard |
RUN-1001 : mixed_pack_place_flow | on | on |
RUN-1001 : qor_monitor | off | off |
RUN-1001 : syn_ip_flow | off | off |
RUN-1001 : thread | auto | auto |
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Rtl Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : compress_add | ripple | ripple |
RUN-1001 : elf_sload | off | off |
RUN-1001 : fix_undriven | 0 | 0 |
RUN-1001 : flatten | off | off |
RUN-1001 : gate_sharing | on | on |
RUN-1001 : hdl_warning_level | normal | normal |
RUN-1001 : impl_internal_tribuf | on | on |
RUN-1001 : impl_set_reset | on | on |
RUN-1001 : infer_gsr | off | off |
RUN-1001 : keep_hierarchy | auto | auto |
RUN-1001 : max_fanout | 9999 | 9999 |
RUN-1001 : max_oh2bin_len | 10 | 10 |
RUN-1001 : merge_equal | on | on |
RUN-1001 : merge_equiv | on | on |
RUN-1001 : merge_mux | off | off |
RUN-1001 : min_control_set | 8 | 8 |
RUN-1001 : min_ripple_len | auto | auto |
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
RUN-1001 : opt_adder_fanout | on | on |
RUN-1001 : opt_arith | on | on |
RUN-1001 : opt_big_gate | off | off |
RUN-1001 : opt_const | on | on |
RUN-1001 : opt_const_mult | on | on |
RUN-1001 : opt_lessthan | on | on |
RUN-1001 : opt_mux | off | off |
RUN-1001 : opt_ram | high | high |
RUN-1001 : rtl_sim_model | off | off |
RUN-1001 : seq_syn | on | on |
RUN-1001 : --------------------------------------------------------------
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
This product includes software developed by the OpenSSL Project
for use in the OpenSSL Toolkit (http://www.openssl.org/)
Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
All rights reserved.
This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
RUN-1001 : Project manager successfully analyzed 61 source files.
RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
ARC-1001 : Device Initialization.
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : OPTION | IO | SETTING
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
ARC-1001 : done | P10 | gpio
ARC-1001 : program_b | P134 | dedicate
ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
ARC-1001 : ----------------------------------------------------------------------
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
RUN-1002 : start command "elaborate -top huagao_mipi_top"
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Rtl Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : compress_add | ripple | ripple |
RUN-1001 : elf_sload | off | off |
RUN-1001 : fix_undriven | 0 | 0 |
RUN-1001 : flatten | off | off |
RUN-1001 : gate_sharing | on | on |
RUN-1001 : hdl_warning_level | normal | normal |
RUN-1001 : impl_internal_tribuf | on | on |
RUN-1001 : impl_set_reset | on | on |
RUN-1001 : infer_gsr | off | off |
RUN-1001 : keep_hierarchy | auto | auto |
RUN-1001 : max_fanout | 9999 | 9999 |
RUN-1001 : max_oh2bin_len | 10 | 10 |
RUN-1001 : merge_equal | on | on |
RUN-1001 : merge_equiv | on | on |
RUN-1001 : merge_mux | off | off |
RUN-1001 : min_control_set | 8 | 8 |
RUN-1001 : min_ripple_len | auto | auto |
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
RUN-1001 : opt_adder_fanout | on | on |
RUN-1001 : opt_arith | on | on |
RUN-1001 : opt_big_gate | off | off |
RUN-1001 : opt_const | on | on |
RUN-1001 : opt_const_mult | on | on |
RUN-1001 : opt_lessthan | on | on |
RUN-1001 : opt_mux | off | off |
RUN-1001 : opt_ram | high | high |
RUN-1001 : rtl_sim_model | off | off |
RUN-1001 : seq_syn | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Global Property
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : message | standard | standard |
RUN-1001 : mixed_pack_place_flow | on | on |
RUN-1001 : qor_monitor | off | off |
RUN-1001 : syn_ip_flow | off | off |
RUN-1001 : thread | auto | auto |
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
HDL-8007 ERROR: index 4 is out of range [3:0] for 'debug' in ../../../../hg_mp/fe/read_ram_data.v(77)
HDL-1007 : module 'read_ram_data' remains a black box due to errors in its contents in ../../../../hg_mp/fe/read_ram_data.v(1)
HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
HDL-5007 WARNING: actual bit length 6 differs from formal bit length 4 for port 'debug' in ../../../../hg_mp/fe/sampling_fe.v(140)
HDL-5007 WARNING: actual bit length 4 differs from formal bit length 6 for port 'debug' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(963)
HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240219_103120.log"

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2
src/prj/td_project/hg_anlogic_Runs/phy_1/.bitgen.begin.f
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@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="20868">
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="13544">
</Process>
</ProcessHandle>

2
src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_place.begin.f
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@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="20868">
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="13544">
</Process>
</ProcessHandle>

2
src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_route.begin.f
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@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="20868">
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="13544">
</Process>
</ProcessHandle>

BIN
src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit
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2
src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.prj
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@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<Project Version="3" Minor="2" RunTime="2024-02-18T16:10:55.365260">
<Project Version="3" Minor="2" RunTime="2024-02-19T10:56:25.015868">
<Project_Created_Time></Project_Created_Time>
<TD_Encoding>UTF-8</TD_Encoding>
<TD_Version>5.6.71036</TD_Version>

BIN
src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.rbf
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BIN
src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_20240218_a002_1615_soft_reset.bin
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src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_2024021_1108_soft_reset.bin Normal file
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src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.area
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@ -8,12 +8,12 @@ IO Statistics
#inout 0
Utilization Statistics
#lut 10320 out of 19600 52.65%
#reg 9363 out of 19600 47.77%
#le 12661
#lut only 3298 out of 12661 26.05%
#reg only 2341 out of 12661 18.49%
#lut&reg 7022 out of 12661 55.46%
#lut 10273 out of 19600 52.41%
#reg 9368 out of 19600 47.80%
#le 12618
#lut only 3250 out of 12618 25.76%
#reg only 2345 out of 12618 18.58%
#lut&reg 7023 out of 12618 55.66%
#dsp 3 out of 29 10.34%
#bram 54 out of 64 84.38%
#bram9k 50
@ -21,24 +21,24 @@ Utilization Statistics
#bram32k 4 out of 16 25.00%
#pad 75 out of 130 57.69%
#ireg 13
#oreg 18
#oreg 19
#treg 0
#pll 3 out of 4 75.00%
#gclk 6 out of 16 37.50%
Clock Resource Statistics
Index ClockNet Type DriverType Driver Fanout
#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1795
#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1417
#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1355
#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 967
#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 139
#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70
#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24
#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1810
#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1425
#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1358
#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 942
#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 143
#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg42_syn_219.f1 3
#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_b/u_ADconfig/reg1_syn_191.f0 2
#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_277.f1 3
#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/reg10_syn_122.f1 3
#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
@ -48,36 +48,36 @@ Index ClockNet Type
Detailed IO Report
Name Direction Location IOStandard DriveStrength PullType PackReg
a_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
a_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
a_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
b_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
b_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
b_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
onoff_in INPUT P133 LVCMOS33 N/A N/A NONE
paper_in INPUT P4 LVCMOS25 N/A N/A NONE
onoff_in INPUT P148 LVCMOS33 N/A N/A NONE
paper_in INPUT P106 LVCMOS25 N/A N/A NONE
rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
@ -99,85 +99,85 @@ Detailed IO Report
O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
a_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
a_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
a_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
a_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
b_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
b_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
b_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
b_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
a_sp_sampling OUTPUT P25 LVCMOS25 8 N/A OREG
b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
fan_pwm OUTPUT P138 LVCMOS33 8 N/A NONE
frame_indicator OUTPUT P16 LVCMOS25 8 N/A OREG
onoff_out OUTPUT P152 LVCMOS33 8 N/A NONE
paper_out OUTPUT P17 LVCMOS25 8 N/A NONE
scan_out OUTPUT P15 LVCMOS25 8 N/A NONE
sys_initial_done OUTPUT P104 LVCMOS25 8 N/A NONE
fan_pwm OUTPUT P139 LVCMOS33 8 N/A NONE
frame_indicator OUTPUT P107 LVCMOS25 8 N/A OREG
onoff_out OUTPUT P169 LVCMOS33 8 N/A NONE
paper_out OUTPUT P91 LVCMOS25 8 N/A NONE
scan_out OUTPUT P66 LVCMOS25 8 N/A NONE
sys_initial_done OUTPUT P39 LVCMOS25 8 N/A NONE
txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
Report Hierarchy Area:
+---------------------------------------------------------------------------------------------------------+
|Instance |Module |le |lut |ripple |seq |bram |dsp |
+---------------------------------------------------------------------------------------------------------+
|top |huagao_mipi_top |12661 |9293 |1027 |9394 |58 |3 |
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |545 |451 |23 |442 |4 |1 |
| U_fifo_w32_d8192 |fifo_w32_d8192 |98 |83 |4 |90 |4 |0 |
| U_crc16_24b |crc16_24b |29 |29 |0 |19 |0 |0 |
| U_ecc_gen |ecc_gen |14 |14 |0 |10 |0 |0 |
| exdev_ctl_a |exdev_ctl |767 |373 |96 |581 |0 |0 |
| u_ADconfig |AD_config |188 |139 |25 |142 |0 |0 |
| u_gen_sp |gen_sp |263 |160 |71 |123 |0 |0 |
| exdev_ctl_b |exdev_ctl |752 |423 |96 |556 |0 |0 |
| u_ADconfig |AD_config |178 |140 |25 |126 |0 |0 |
| u_gen_sp |gen_sp |262 |168 |71 |118 |0 |0 |
| sampling_fe_a |sampling_fe |3094 |2433 |306 |2032 |25 |0 |
|top |huagao_mipi_top |12618 |9246 |1027 |9400 |58 |3 |
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |561 |454 |23 |449 |4 |1 |
| U_fifo_w32_d8192 |fifo_w32_d8192 |110 |93 |4 |93 |4 |0 |
| U_crc16_24b |crc16_24b |32 |32 |0 |22 |0 |0 |
| U_ecc_gen |ecc_gen |12 |12 |0 |9 |0 |0 |
| exdev_ctl_a |exdev_ctl |781 |337 |96 |583 |0 |0 |
| u_ADconfig |AD_config |191 |118 |25 |142 |0 |0 |
| u_gen_sp |gen_sp |269 |158 |71 |120 |0 |0 |
| exdev_ctl_b |exdev_ctl |743 |379 |96 |554 |0 |0 |
| u_ADconfig |AD_config |177 |129 |25 |125 |0 |0 |
| u_gen_sp |gen_sp |259 |144 |71 |122 |0 |0 |
| sampling_fe_a |sampling_fe |3071 |2501 |306 |2076 |25 |0 |
| u0_soft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
| u_ad_sampling |ad_sampling |183 |97 |17 |141 |0 |0 |
| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
| u_sort |sort |2875 |2311 |289 |1855 |25 |0 |
| rddpram_ctl |rddpram_ctl |5 |5 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
| u_data_prebuffer |data_prebuffer |2499 |2063 |253 |1538 |22 |0 |
| channelPart |channel_part_8478 |133 |130 |3 |122 |0 |0 |
| fifo_adc |fifo_adc |62 |53 |9 |44 |0 |0 |
| ram_switch |ram_switch |1994 |1633 |197 |1144 |0 |0 |
| adc_addr_gen |adc_addr_gen |244 |217 |27 |114 |0 |0 |
| [0]$ch_addr_gen |ch_addr_gen |8 |5 |3 |4 |0 |0 |
| [1]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
| [2]$ch_addr_gen |ch_addr_gen |29 |26 |3 |14 |0 |0 |
| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
| [6]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |9 |0 |0 |
| insert |insert |953 |620 |170 |654 |0 |0 |
| ram_switch_state |ram_switch_state |797 |796 |0 |376 |0 |0 |
| read_ram_i |read_ram |265 |209 |44 |186 |0 |0 |
| read_ram_addr |read_ram_addr |213 |173 |40 |147 |0 |0 |
| read_ram_data |read_ram_data |51 |35 |4 |38 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
| u_ad_sampling |ad_sampling |180 |137 |17 |133 |0 |0 |
| u0_soft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
| u_sort |sort |2855 |2346 |289 |1907 |25 |0 |
| rddpram_ctl |rddpram_ctl |2 |1 |0 |2 |0 |0 |
| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
| u0_rdsoft_n |cdc_sync |9 |4 |0 |9 |0 |0 |
| u0_wrsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
| u_data_prebuffer |data_prebuffer |2407 |1999 |253 |1544 |22 |0 |
| channelPart |channel_part_8478 |143 |136 |3 |126 |0 |0 |
| fifo_adc |fifo_adc |58 |49 |9 |41 |0 |0 |
| ram_switch |ram_switch |1870 |1532 |197 |1149 |0 |0 |
| adc_addr_gen |adc_addr_gen |247 |220 |27 |123 |0 |0 |
| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |5 |0 |0 |
| [1]$ch_addr_gen |ch_addr_gen |29 |26 |3 |15 |0 |0 |
| [2]$ch_addr_gen |ch_addr_gen |31 |28 |3 |17 |0 |0 |
| [3]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 |
| [4]$ch_addr_gen |ch_addr_gen |27 |24 |3 |13 |0 |0 |
| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
| [7]$ch_addr_gen |ch_addr_gen |25 |22 |3 |10 |0 |0 |
| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
| insert |insert |965 |654 |170 |661 |0 |0 |
| ram_switch_state |ram_switch_state |658 |658 |0 |365 |0 |0 |
| read_ram_i |read_ram |300 |255 |44 |195 |0 |0 |
| read_ram_addr |read_ram_addr |240 |200 |40 |155 |0 |0 |
| read_ram_data |read_ram_data |56 |51 |4 |36 |0 |0 |
| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_4 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
@ -185,42 +185,41 @@ Report Hierarchy Area:
| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_5 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u_transfer_300_to_200 |transfer_300_to_200 |339 |233 |36 |280 |3 |0 |
| u0_soft_n |cdc_sync |7 |7 |0 |7 |0 |0 |
| u_transfer_300_to_200 |transfer_300_to_200 |337 |245 |36 |283 |3 |0 |
| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
| sampling_fe_b |sampling_fe_rev |3367 |2648 |349 |2114 |25 |1 |
| u0_soft_n |cdc_sync |6 |1 |0 |6 |0 |0 |
| u_ad_sampling |ad_sampling |166 |113 |17 |130 |0 |0 |
| u0_soft_n |cdc_sync |6 |1 |0 |6 |0 |0 |
| u_sort |sort_rev |3165 |2522 |332 |1948 |25 |1 |
| rddpram_ctl |rddpram_ctl_rev |4 |3 |0 |4 |0 |0 |
| u0_rdsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
| u0_rdsoft_n |cdc_sync |7 |2 |0 |7 |0 |0 |
| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
| u_data_prebuffer_rev |data_prebuffer_rev |2731 |2228 |290 |1587 |22 |1 |
| channelPart |channel_part_8478 |238 |235 |3 |135 |0 |0 |
| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
| ram_switch |ram_switch |1983 |1621 |197 |1142 |0 |0 |
| adc_addr_gen |adc_addr_gen |221 |194 |27 |105 |0 |0 |
| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |6 |0 |0 |
| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
| [2]$ch_addr_gen |ch_addr_gen |30 |27 |3 |18 |0 |0 |
| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |8 |0 |0 |
| [6]$ch_addr_gen |ch_addr_gen |21 |18 |3 |10 |0 |0 |
| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
| insert |insert |974 |641 |170 |669 |0 |0 |
| ram_switch_state |ram_switch_state |788 |786 |0 |368 |0 |0 |
| read_ram_i |read_ram_rev |424 |303 |81 |240 |0 |0 |
| read_ram_addr |read_ram_addr_rev |291 |206 |73 |159 |0 |0 |
| read_ram_data |read_ram_data_rev |133 |97 |8 |81 |0 |0 |
| sampling_fe_b |sampling_fe_rev |3397 |2743 |349 |2088 |25 |1 |
| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
| u_ad_sampling |ad_sampling |189 |127 |17 |147 |0 |0 |
| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
| u_sort |sort_rev |3178 |2597 |332 |1911 |25 |1 |
| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
| u_data_prebuffer_rev |data_prebuffer_rev |2741 |2251 |290 |1561 |22 |1 |
| channelPart |channel_part_8478 |243 |238 |3 |137 |0 |0 |
| fifo_adc |fifo_adc |60 |51 |9 |43 |0 |1 |
| ram_switch |ram_switch |2023 |1671 |197 |1132 |0 |0 |
| adc_addr_gen |adc_addr_gen |219 |192 |27 |98 |0 |0 |
| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |6 |0 |0 |
| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
| [3]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 |
| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
| [5]$ch_addr_gen |ch_addr_gen |19 |16 |3 |6 |0 |0 |
| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |8 |0 |0 |
| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
| insert |insert |982 |658 |170 |674 |0 |0 |
| ram_switch_state |ram_switch_state |822 |821 |0 |360 |0 |0 |
| read_ram_i |read_ram_rev |378 |263 |81 |214 |0 |0 |
| read_ram_addr |read_ram_addr_rev |311 |226 |73 |165 |0 |0 |
| read_ram_data |read_ram_data_rev |67 |37 |8 |49 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
@ -243,66 +242,66 @@ Report Hierarchy Area:
| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u_transfer_300_to_200 |transfer_300_to_200 |327 |215 |42 |273 |3 |0 |
| u0_soft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
| u_transfer_300_to_200 |transfer_300_to_200 |342 |260 |42 |277 |3 |0 |
| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
| scan_start_diff |scan_start_diff |23 |23 |0 |15 |0 |0 |
| u0_test_en |cdc_sync |4 |2 |0 |4 |0 |0 |
| u1_test_en |cdc_sync |4 |4 |0 |4 |0 |0 |
| u2_test_en |cdc_sync |3 |3 |0 |3 |0 |0 |
| u_a_pclk |cdc_sync |5 |5 |0 |5 |0 |0 |
| u_a_sp_sampling |cdc_sync |4 |4 |0 |4 |0 |0 |
| u_a_sp_sampling_cam |cdc_sync |5 |1 |0 |5 |0 |0 |
| u_a_sp_sampling_last |cdc_sync |5 |4 |0 |5 |0 |0 |
| u_b_pclk |cdc_sync |4 |3 |0 |4 |0 |0 |
| u_b_sp_sampling |cdc_sync |6 |2 |0 |6 |0 |0 |
| u_b_sp_sampling_cam |cdc_sync |6 |4 |0 |6 |0 |0 |
| u_b_sp_sampling_last |cdc_sync |2 |2 |0 |2 |0 |0 |
| u_bus_top |ubus_top |1297 |1117 |22 |1208 |0 |0 |
| u_local_bus_slve_cis |local_bus_slve_cis |800 |724 |22 |711 |0 |0 |
| u_uart_2dsp |uart_2dsp |98 |86 |12 |61 |0 |0 |
| u_dpi_mode |cdc_sync |4 |4 |0 |4 |0 |0 |
| u_eot |cdc_sync |3 |3 |0 |3 |0 |0 |
| scan_start_diff |scan_start_diff |29 |29 |0 |18 |0 |0 |
| u0_test_en |cdc_sync |3 |3 |0 |3 |0 |0 |
| u1_test_en |cdc_sync |5 |2 |0 |5 |0 |0 |
| u2_test_en |cdc_sync |2 |1 |0 |2 |0 |0 |
| u_a_pclk |cdc_sync |1 |0 |0 |1 |0 |0 |
| u_a_sp_sampling |cdc_sync |3 |2 |0 |3 |0 |0 |
| u_a_sp_sampling_cam |cdc_sync |6 |4 |0 |6 |0 |0 |
| u_a_sp_sampling_last |cdc_sync |4 |4 |0 |4 |0 |0 |
| u_b_pclk |cdc_sync |3 |3 |0 |3 |0 |0 |
| u_b_sp_sampling |cdc_sync |2 |2 |0 |2 |0 |0 |
| u_b_sp_sampling_cam |cdc_sync |5 |5 |0 |5 |0 |0 |
| u_b_sp_sampling_last |cdc_sync |4 |4 |0 |4 |0 |0 |
| u_bus_top |ubus_top |1333 |944 |22 |1243 |0 |0 |
| u_local_bus_slve_cis |local_bus_slve_cis |821 |667 |22 |731 |0 |0 |
| u_uart_2dsp |uart_2dsp |103 |87 |12 |64 |0 |0 |
| u_dpi_mode |cdc_sync |5 |4 |0 |5 |0 |0 |
| u_eot |cdc_sync |5 |4 |0 |5 |0 |0 |
| u_lv_en_flag |cdc_sync |5 |5 |0 |5 |0 |0 |
| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |275 |237 |20 |213 |4 |0 |
| u_hs_tx_wrapper |hs_tx_wrapper |227 |189 |20 |185 |4 |0 |
| [0]$u_data_lane_wrapper |data_lane_wrapper |112 |89 |15 |86 |1 |0 |
| u_data_hs_generate |data_hs_generate |107 |84 |15 |81 |1 |0 |
| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |262 |213 |20 |209 |4 |0 |
| u_hs_tx_wrapper |hs_tx_wrapper |220 |171 |20 |184 |4 |0 |
| [0]$u_data_lane_wrapper |data_lane_wrapper |110 |76 |15 |85 |1 |0 |
| u_data_hs_generate |data_hs_generate |105 |72 |15 |80 |1 |0 |
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
| u_data_lp_generate |data_lp_generate |5 |5 |0 |5 |0 |0 |
| [1]$u_data_lane_wrapper |data_lane_wrapper |27 |17 |0 |27 |1 |0 |
| u_data_hs_generate |data_hs_generate |27 |17 |0 |27 |1 |0 |
| u_data_lp_generate |data_lp_generate |5 |4 |0 |5 |0 |0 |
| [1]$u_data_lane_wrapper |data_lane_wrapper |28 |27 |0 |28 |1 |0 |
| u_data_hs_generate |data_hs_generate |28 |27 |0 |28 |1 |0 |
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
| [2]$u_data_lane_wrapper |data_lane_wrapper |22 |22 |0 |22 |1 |0 |
| u_data_hs_generate |data_hs_generate |22 |22 |0 |22 |1 |0 |
| [2]$u_data_lane_wrapper |data_lane_wrapper |31 |27 |0 |31 |1 |0 |
| u_data_hs_generate |data_hs_generate |31 |27 |0 |31 |1 |0 |
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
| [3]$u_data_lane_wrapper |data_lane_wrapper |24 |24 |0 |24 |1 |0 |
| u_data_hs_generate |data_hs_generate |24 |24 |0 |24 |1 |0 |
| [3]$u_data_lane_wrapper |data_lane_wrapper |19 |14 |0 |19 |1 |0 |
| u_data_hs_generate |data_hs_generate |19 |14 |0 |19 |1 |0 |
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
| u_hs_tx_controler |hs_tx_controler |34 |29 |5 |18 |0 |0 |
| u_clk_lane_wrapper |clk_lane_wrapper |8 |8 |0 |8 |0 |0 |
| u_clk_lp_generate |clk_lp_generate |4 |4 |0 |4 |0 |0 |
| u_hs_tx_controler |hs_tx_controler |26 |21 |5 |15 |0 |0 |
| u_clk_lane_wrapper |clk_lane_wrapper |6 |6 |0 |6 |0 |0 |
| u_clk_lp_generate |clk_lp_generate |2 |2 |0 |2 |0 |0 |
| u_clk_hs_generate |clk_hs_generate |4 |4 |0 |4 |0 |0 |
| u_mipi_eot_min |cdc_sync |58 |58 |0 |58 |0 |0 |
| u_mipi_sot_min |cdc_sync |66 |65 |0 |66 |0 |0 |
| u_pic_cnt |cdc_sync |117 |40 |0 |117 |0 |0 |
| u_pixel_cdc |pixel_cdc |688 |412 |0 |688 |0 |1 |
| u_clk_cis_frame_num |cdc_sync |75 |65 |0 |75 |0 |0 |
| u_clk_cis_pixel_y |cdc_sync |74 |47 |0 |74 |0 |0 |
| u_clk_mipi_pixel_y |cdc_sync |67 |45 |0 |67 |0 |0 |
| u_clka_cis_total_num |cdc_sync |108 |33 |0 |108 |0 |0 |
| u_clka_mipi_total_num |cdc_sync |108 |58 |0 |108 |0 |0 |
| u_clkb_cis_total_num |cdc_sync |104 |65 |0 |104 |0 |0 |
| u_clkb_mipi_total_num |cdc_sync |89 |58 |0 |89 |0 |0 |
| u_mipi_eot_min |cdc_sync |64 |39 |0 |64 |0 |0 |
| u_mipi_sot_min |cdc_sync |58 |46 |0 |58 |0 |0 |
| u_pic_cnt |cdc_sync |108 |58 |0 |108 |0 |0 |
| u_pixel_cdc |pixel_cdc |676 |577 |0 |676 |0 |1 |
| u_clk_cis_frame_num |cdc_sync |77 |77 |0 |77 |0 |0 |
| u_clk_cis_pixel_y |cdc_sync |71 |65 |0 |71 |0 |0 |
| u_clk_mipi_pixel_y |cdc_sync |73 |71 |0 |73 |0 |0 |
| u_clka_cis_total_num |cdc_sync |90 |76 |0 |90 |0 |0 |
| u_clka_mipi_total_num |cdc_sync |102 |87 |0 |102 |0 |0 |
| u_clkb_cis_total_num |cdc_sync |105 |92 |0 |105 |0 |0 |
| u_clkb_mipi_total_num |cdc_sync |95 |77 |0 |95 |0 |0 |
| u_pll |pll |0 |0 |0 |0 |0 |0 |
| u_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |0 |
| u_softrst_done |cdc_sync |2 |0 |0 |2 |0 |0 |
| ua_lvds_rx |lvds_rx |286 |192 |19 |206 |0 |0 |
| ub_lvds_rx |lvds_rx |287 |185 |19 |207 |0 |0 |
| u_softrst_done |cdc_sync |4 |4 |0 |4 |0 |0 |
| ua_lvds_rx |lvds_rx |284 |208 |19 |203 |0 |0 |
| ub_lvds_rx |lvds_rx |290 |191 |19 |211 |0 |0 |
| uu_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |0 |
+---------------------------------------------------------------------------------------------------------+
@ -310,12 +309,12 @@ Report Hierarchy Area:
DataNet Average Fanout:
Index Fanout Nets
#1 1 9824
#2 2 3937
#3 3 1458
#4 4 642
#5 5-10 1062
#6 11-50 587
#7 51-100 24
#1 1 9907
#2 2 3801
#3 3 1374
#4 4 579
#5 5-10 1189
#6 11-50 584
#7 51-100 22
#8 >500 1
Average 2.91
Average 2.92

5714
src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.timing
View File

File diff suppressed because it is too large Load Diff

1958
src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.tsm
View File

File diff suppressed because it is too large Load Diff

BIN
src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db
View File

Binary file not shown.

BIN
src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db
View File

Binary file not shown.

1870
src/prj/td_project/hg_anlogic_Runs/phy_1/run.log
View File

File diff suppressed because it is too large Load Diff

2
src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_gate.begin.f
View File

@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="12880">
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="6996">
</Process>
</ProcessHandle>

2
src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_rtl.begin.f
View File

@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="12880">
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="6996">
</Process>
</ProcessHandle>

2
src/prj/td_project/hg_anlogic_Runs/syn_1/.read_design.begin.f
View File

@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="12880">
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="6996">
</Process>
</ProcessHandle>

2
src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic.prj
View File

@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<Project Version="3" Minor="2" RunTime="2024-02-18T16:10:55.245054">
<Project Version="3" Minor="2" RunTime="2024-02-19T10:56:24.896188">
<Project_Created_Time></Project_Created_Time>
<TD_Encoding>UTF-8</TD_Encoding>
<TD_Version>5.6.71036</TD_Version>

BIN
src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db
View File

Binary file not shown.

76
src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.area
View File

@ -8,16 +8,16 @@ IO Statistics
#inout 0
LUT Statistics
#Total_luts 9995
#lut4 5129
#lut5 2311
#Total_luts 9962
#lut4 5231
#lut5 2176
#lut6 0
#lut5_mx41 0
#lut4_alu1b 2555
Utilization Statistics
#lut 9995 out of 19600 50.99%
#reg 9170 out of 19600 46.79%
#lut 9962 out of 19600 50.83%
#reg 9173 out of 19600 46.80%
#le 0
#dsp 3 out of 29 10.34%
#bram 54 out of 64 84.38%
@ -27,7 +27,7 @@ Utilization Statistics
#dram 16
#pad 75 out of 130 57.69%
#ireg 13
#oreg 18
#oreg 19
#treg 0
#pll 3 out of 4 75.00%
@ -35,30 +35,30 @@ Report Hierarchy Area:
+-------------------------------------------------------------------------------------------------+
|Instance |Module |lut |ripple |seq |bram |dsp |
+-------------------------------------------------------------------------------------------------+
|top |huagao_mipi_top |7440 |2555 |9201 |58 |3 |
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |339 |81 |441 |4 |1 |
| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 |
|top |huagao_mipi_top |7407 |2555 |9205 |58 |3 |
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |342 |81 |441 |4 |1 |
| U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 |
| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
| exdev_ctl_a |exdev_ctl |282 |234 |559 |0 |0 |
| u_ADconfig |AD_config |99 |49 |138 |0 |0 |
| u_gen_sp |gen_sp |125 |185 |104 |0 |0 |
| exdev_ctl_b |exdev_ctl |279 |234 |546 |0 |0 |
| exdev_ctl_b |exdev_ctl |274 |234 |546 |0 |0 |
| u_ADconfig |AD_config |91 |49 |125 |0 |0 |
| u_gen_sp |gen_sp |130 |185 |104 |0 |0 |
| sampling_fe_a |sampling_fe |2067 |738 |1894 |25 |0 |
| u_gen_sp |gen_sp |125 |185 |104 |0 |0 |
| sampling_fe_a |sampling_fe |2317 |738 |1919 |25 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_sort |sort |1997 |691 |1712 |25 |0 |
| u_sort |sort |2247 |691 |1737 |25 |0 |
| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_data_prebuffer |data_prebuffer |1868 |615 |1391 |22 |0 |
| channelPart |channel_part_8478 |147 |11 |144 |0 |0 |
| u_data_prebuffer |data_prebuffer |1906 |615 |1391 |22 |0 |
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
| ram_switch |ram_switch |1448 |422 |1023 |0 |0 |
| ram_switch |ram_switch |1466 |422 |1023 |0 |0 |
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
@ -70,10 +70,10 @@ Report Hierarchy Area:
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| insert |insert |265 |323 |692 |0 |0 |
| ram_switch_state |ram_switch_state |1054 |0 |216 |0 |0 |
| read_ram_i |read_ram |186 |158 |164 |0 |0 |
| read_ram_addr |read_ram_addr |158 |145 |127 |0 |0 |
| read_ram_data |read_ram_data |27 |13 |32 |0 |0 |
| ram_switch_state |ram_switch_state |1072 |0 |216 |0 |0 |
| read_ram_i |read_ram |207 |158 |164 |0 |0 |
| read_ram_addr |read_ram_addr |177 |145 |127 |0 |0 |
| read_ram_data |read_ram_data |29 |13 |32 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
@ -97,22 +97,22 @@ Report Hierarchy Area:
| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u_transfer_300_to_200 |transfer_300_to_200 |122 |76 |276 |3 |0 |
| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
| sampling_fe_b |sampling_fe_rev |2261 |751 |1958 |25 |1 |
| sampling_fe_b |sampling_fe_rev |2335 |751 |1936 |25 |1 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_sort |sort_rev |2191 |704 |1776 |25 |1 |
| u_sort |sort_rev |2265 |704 |1754 |25 |1 |
| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_data_prebuffer_rev |data_prebuffer_rev |2066 |628 |1405 |22 |1 |
| u_data_prebuffer_rev |data_prebuffer_rev |1924 |628 |1408 |22 |1 |
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
| ram_switch |ram_switch |1441 |422 |1023 |0 |0 |
| ram_switch |ram_switch |1479 |422 |1023 |0 |0 |
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
@ -124,10 +124,10 @@ Report Hierarchy Area:
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| insert |insert |265 |323 |692 |0 |0 |
| ram_switch_state |ram_switch_state |1047 |0 |216 |0 |0 |
| read_ram_i |read_ram_rev |390 |171 |178 |0 |0 |
| read_ram_addr |read_ram_addr_rev |176 |145 |136 |0 |0 |
| read_ram_data |read_ram_data_rev |214 |26 |42 |0 |0 |
| ram_switch_state |ram_switch_state |1085 |0 |216 |0 |0 |
| read_ram_i |read_ram_rev |210 |171 |181 |0 |0 |
| read_ram_addr |read_ram_addr_rev |181 |145 |139 |0 |0 |
| read_ram_data |read_ram_data_rev |29 |26 |42 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
@ -150,7 +150,7 @@ Report Hierarchy Area:
| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u_transfer_300_to_200 |transfer_300_to_200 |120 |76 |276 |3 |0 |
| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
| scan_start_diff |scan_start_diff |30 |0 |12 |0 |0 |
@ -165,16 +165,16 @@ Report Hierarchy Area:
| u_b_sp_sampling |cdc_sync |1 |0 |5 |0 |0 |
| u_b_sp_sampling_cam |cdc_sync |1 |0 |5 |0 |0 |
| u_b_sp_sampling_last |cdc_sync |1 |0 |5 |0 |0 |
| u_bus_top |ubus_top |826 |50 |1248 |0 |0 |
| u_local_bus_slve_cis |local_bus_slve_cis |732 |50 |721 |0 |0 |
| u_uart_2dsp |uart_2dsp |119 |31 |52 |0 |0 |
| u_bus_top |ubus_top |805 |50 |1248 |0 |0 |
| u_local_bus_slve_cis |local_bus_slve_cis |711 |50 |721 |0 |0 |
| u_uart_2dsp |uart_2dsp |115 |31 |52 |0 |0 |
| u_dpi_mode |cdc_sync |2 |0 |10 |0 |0 |
| u_eot |cdc_sync |1 |0 |5 |0 |0 |
| u_lv_en_flag |cdc_sync |1 |0 |5 |0 |0 |
| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |170 |61 |226 |4 |0 |
| u_hs_tx_wrapper |hs_tx_wrapper |111 |61 |198 |4 |0 |
| [0]$u_data_lane_wrapper |data_lane_wrapper |54 |52 |93 |1 |0 |
| u_data_hs_generate |data_hs_generate |50 |52 |87 |1 |0 |
| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |166 |61 |226 |4 |0 |
| u_hs_tx_wrapper |hs_tx_wrapper |110 |61 |198 |4 |0 |
| [0]$u_data_lane_wrapper |data_lane_wrapper |52 |52 |93 |1 |0 |
| u_data_hs_generate |data_hs_generate |48 |52 |87 |1 |0 |
| u_dphy_tx_fifo |dphy_tx_fifo |2 |0 |0 |1 |0 |
| u_d1024_w8_fifo |d1024_w8_fifo |2 |0 |0 |1 |0 |
| u_data_lp_generate |data_lp_generate |4 |0 |6 |0 |0 |
@ -193,7 +193,7 @@ Report Hierarchy Area:
| u_clk_lane_wrapper |clk_lane_wrapper |3 |0 |8 |0 |0 |
| u_clk_hs_generate |clk_hs_generate |3 |0 |4 |0 |0 |
| u_clk_lp_generate |clk_lp_generate |0 |0 |4 |0 |0 |
| u_hs_tx_controler |hs_tx_controler |24 |9 |12 |0 |0 |
| u_hs_tx_controler |hs_tx_controler |25 |9 |12 |0 |0 |
| u_mipi_eot_min |cdc_sync |20 |0 |65 |0 |0 |
| u_mipi_sot_min |cdc_sync |20 |0 |65 |0 |0 |
| u_pic_cnt |cdc_sync |38 |0 |120 |0 |0 |

BIN
src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.db
View File

Binary file not shown.

36
src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.area
View File

@ -8,8 +8,8 @@ IO Statistics
#inout 0
Gate Statistics
#Basic gates 13930
#and 2463
#Basic gates 13950
#and 2480
#nand 0
#or 1078
#nor 0
@ -20,19 +20,19 @@ Gate Statistics
#bufif1 5
#MX21 615
#FADD 0
#DFF 9090
#DFF 9093
#LATCH 6
#MACRO_ADD 496
#MACRO_ADD 497
#MACRO_EQ 225
#MACRO_MULT 4
#MACRO_MUX 4819
#MACRO_MUX 4813
#MACRO_OTHERS 73
Report Hierarchy Area:
+----------------------------------------------------------------------------+
|Instance |Module |gates |seq |macros |
+----------------------------------------------------------------------------+
|top |huagao_mipi_top |4834 |9096 |798 |
|top |huagao_mipi_top |4851 |9099 |799 |
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
| U_crc16_24b |crc16_24b |67 |16 |0 |
| U_ecc_gen |ecc_gen |37 |6 |0 |
@ -43,16 +43,16 @@ Report Hierarchy Area:
| exdev_ctl_b |exdev_ctl |158 |546 |41 |
| u_ADconfig |AD_config |81 |125 |18 |
| u_gen_sp |gen_sp |76 |104 |19 |
| sampling_fe_a |sampling_fe |1838 |1894 |269 |
| sampling_fe_a |sampling_fe |1847 |1919 |269 |
| u0_soft_n |cdc_sync |2 |5 |0 |
| u_ad_sampling |ad_sampling |40 |147 |10 |
| u0_soft_n |cdc_sync |2 |5 |0 |
| u_sort |sort |1794 |1712 |258 |
| u_sort |sort |1803 |1737 |258 |
| rddpram_ctl |rddpram_ctl |2 |5 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_wrsoft_n |cdc_sync |2 |5 |0 |
| u_data_prebuffer |data_prebuffer |1539 |1391 |118 |
| u_data_prebuffer |data_prebuffer |1548 |1391 |118 |
| channelPart |channel_part_8478 |865 |144 |8 |
| fifo_adc |fifo_adc |112 |41 |4 |
| ram_switch |ram_switch |60 |1023 |52 |
@ -72,9 +72,9 @@ Report Hierarchy Area:
| mux_addr |mux_e |0 |0 |0 |
| mux_data |mux_e |0 |0 |0 |
| mux_valid |mux_e |0 |0 |0 |
| read_ram_i |read_ram |112 |164 |32 |
| read_ram_addr |read_ram_addr |64 |127 |22 |
| read_ram_data |read_ram_data |46 |32 |10 |
| read_ram_i |read_ram |121 |164 |32 |
| read_ram_addr |read_ram_addr |69 |127 |22 |
| read_ram_data |read_ram_data |50 |32 |10 |
| mux_i |mux_i |0 |0 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
@ -102,16 +102,16 @@ Report Hierarchy Area:
| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
| u0_soft_n |cdc_sync |2 |5 |0 |
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
| sampling_fe_b |sampling_fe_rev |1799 |1958 |267 |
| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 |
| u0_soft_n |cdc_sync |2 |5 |0 |
| u_ad_sampling |ad_sampling |39 |147 |9 |
| u0_soft_n |cdc_sync |2 |5 |0 |
| u_sort |sort_rev |1757 |1776 |257 |
| u_sort |sort_rev |1765 |1754 |258 |
| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_wrsoft_n |cdc_sync |2 |5 |0 |
| u_data_prebuffer_rev |data_prebuffer_rev |1503 |1405 |118 |
| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 |
| channelPart |channel_part_8478 |865 |144 |8 |
| fifo_adc |fifo_adc |112 |41 |4 |
| ram_switch |ram_switch |60 |1023 |52 |
@ -131,9 +131,9 @@ Report Hierarchy Area:
| mux_addr |mux_e |0 |0 |0 |
| mux_data |mux_e |0 |0 |0 |
| mux_valid |mux_e |0 |0 |0 |
| read_ram_i |read_ram_rev |82 |178 |32 |
| read_ram_addr |read_ram_addr_rev |50 |136 |22 |
| read_ram_data |read_ram_data_rev |32 |42 |10 |
| read_ram_i |read_ram_rev |90 |181 |33 |
| read_ram_addr |read_ram_addr_rev |56 |139 |23 |
| read_ram_data |read_ram_data_rev |34 |42 |10 |
| mux_i |mux_i |0 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |

BIN
src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db
View File

Binary file not shown.

279
src/prj/td_project/hg_anlogic_Runs/syn_1/run.log
View File

@ -4,7 +4,7 @@
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
Built at = 20:34:38 Mar 21 2023
Run by = holdtecs
Run Date = Sun Feb 18 16:10:55 2024
Run Date = Mon Feb 19 10:56:25 2024
Run on = DESKTOP-5MQL5VE
============================================================
@ -86,7 +86,7 @@ HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
@ -163,27 +163,27 @@ HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
@ -310,14 +310,14 @@ HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../
HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(192)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
@ -345,11 +345,11 @@ HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF
HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(36)
HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(335)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
@ -362,18 +362,18 @@ HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_m
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(194)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(38)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(367)
HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
@ -422,9 +422,9 @@ HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been re
HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
HDL-1200 : Current top model is huagao_mipi_top
HDL-1100 : Inferred 1 RAMs.
RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.135611s wall, 1.109375s user + 0.015625s system = 1.125000s CPU (99.1%)
RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.112400s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.7%)
RUN-1004 : used memory is 193 MB, reserved memory is 171 MB, peak memory is 233 MB
RUN-1004 : used memory is 193 MB, reserved memory is 171 MB, peak memory is 234 MB
RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
RUN-1001 : Exported /
RUN-1001 : Exported flow parameters
@ -456,28 +456,28 @@ RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; I
RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
@ -499,6 +499,7 @@ RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy
RUN-1001 : Starting of IO setups legality check.
RUN-1001 : Starting of IO setups legality check.
RUN-1001 : Starting of IO vref setups legality check.
USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
@ -508,7 +509,6 @@ USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
USR-6010 WARNING: ADC constraints: top model pin scan_out has no constraint.
USR-6010 Similar messages will be suppressed.
RUN-1002 : start command "optimize_rtl"
RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
@ -654,14 +654,14 @@ RUN-1001 : ub_lvds_rx | false | lvds_rx |
RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
RUN-1001 : ------------------------------------------------------------------------------------------------
SYN-1032 : 53810/19109 useful/useless nets, 20666/1812 useful/useless insts
SYN-1032 : 53909/19207 useful/useless nets, 20692/1826 useful/useless insts
SYN-1001 : Optimize 156 less-than instances
SYN-1016 : Merged 38313 instances.
SYN-1025 : Merged 24 RAM ports.
SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
SYN-1032 : 42352/8970 useful/useless nets, 10953/4743 useful/useless insts
SYN-1032 : 42440/8976 useful/useless nets, 10974/4743 useful/useless insts
SYN-1016 : Merged 1876 instances.
SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
@ -672,7 +672,7 @@ SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfi
SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(283) / pin "d"
SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
@ -1173,7 +1173,7 @@ SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16
SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
SYN-5014 Similar messages will be suppressed.
SYN-5025 WARNING: Using 0 for all undriven pins and nets
SYN-1032 : 40025/363 useful/useless nets, 37222/552 useful/useless insts
SYN-1032 : 40113/363 useful/useless nets, 37310/558 useful/useless insts
SYN-1014 : Optimize round 1
SYN-1017 : Remove 16 const input seq instances
SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
@ -1195,14 +1195,14 @@ SYN-1002 : reg17_syn_2
SYN-1018 : Transformed 91 mux instances.
SYN-1019 : Optimized 127 mux instances.
SYN-1021 : Optimized 297 onehot mux instances.
SYN-1020 : Optimized 3817 distributor mux.
SYN-1020 : Optimized 3951 distributor mux.
SYN-1001 : Optimize 12 less-than instances
SYN-1019 : Optimized 39 mux instances.
SYN-1016 : Merged 6180 instances.
SYN-1015 : Optimize round 1, 29670 better
SYN-1016 : Merged 6256 instances.
SYN-1015 : Optimize round 1, 29880 better
SYN-1014 : Optimize round 2
SYN-1044 : Optimized 15 inv instances.
SYN-1032 : 25763/1547 useful/useless nets, 23052/7489 useful/useless insts
SYN-1032 : 25775/1547 useful/useless nets, 23064/7583 useful/useless insts
SYN-1017 : Remove 29 const input seq instances
SYN-1002 : reg18_syn_2
SYN-1002 : reg22_syn_2
@ -1235,13 +1235,10 @@ SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
SYN-1019 : Optimized 24 mux instances.
SYN-1020 : Optimized 43 distributor mux.
SYN-1016 : Merged 117 instances.
SYN-1015 : Optimize round 2, 9332 better
SYN-1032 : 25515/80 useful/useless nets, 22836/112 useful/useless insts
SYN-1016 : Merged 118 instances.
SYN-1015 : Optimize round 2, 9427 better
SYN-1032 : 25526/80 useful/useless nets, 22847/112 useful/useless insts
SYN-3004 : Optimized 2 const0 DFF(s)
SYN-3003 : Optimized 1 equivalent DFF(s)
SYN-3003 : Optimized 1 equivalent DFF(s)
SYN-3003 : Optimized 1 equivalent DFF(s)
SYN-3004 : Optimized 8 const0 DFF(s)
SYN-3008 : Optimized 1 const1 DFF(s)
SYN-3004 : Optimized 1 const0 DFF(s)
@ -1307,20 +1304,20 @@ SYN-3003 : Optimized 1 equivalent DFF(s)
SYN-3003 : Optimized 1 equivalent DFF(s)
SYN-3003 : Optimized 1 equivalent DFF(s)
SYN-3004 : Optimized 2 const0 DFF(s)
SYN-1032 : 25416/99 useful/useless nets, 22750/7 useful/useless insts
SYN-1032 : 25433/93 useful/useless nets, 22765/6 useful/useless insts
SYN-1014 : Optimize round 1
SYN-1019 : Optimized 228 mux instances.
SYN-1020 : Optimized 2 distributor mux.
SYN-1016 : Merged 3 instances.
SYN-1015 : Optimize round 1, 279 better
SYN-1014 : Optimize round 2
SYN-1032 : 25138/20 useful/useless nets, 22488/2 useful/useless insts
SYN-1032 : 25155/20 useful/useless nets, 22503/2 useful/useless insts
SYN-1015 : Optimize round 2, 2 better
SYN-1014 : Optimize round 3
SYN-1015 : Optimize round 3, 0 better
RUN-1003 : finish command "optimize_rtl" in 19.412269s wall, 17.515625s user + 1.875000s system = 19.390625s CPU (99.9%)
RUN-1003 : finish command "optimize_rtl" in 18.908404s wall, 16.984375s user + 1.906250s system = 18.890625s CPU (99.9%)
RUN-1004 : used memory is 330 MB, reserved memory is 302 MB, peak memory is 350 MB
RUN-1004 : used memory is 331 MB, reserved memory is 303 MB, peak memory is 349 MB
RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
RUN-1001 : standard
***Report Model: huagao_mipi_top Device: EG4D20EG176***
@ -1332,8 +1329,8 @@ IO Statistics
#inout 0
Gate Statistics
#Basic gates 13930
#and 2463
#Basic gates 13950
#and 2480
#nand 0
#or 1078
#nor 0
@ -1344,19 +1341,19 @@ Gate Statistics
#bufif1 5
#MX21 615
#FADD 0
#DFF 9090
#DFF 9093
#LATCH 6
#MACRO_ADD 496
#MACRO_ADD 497
#MACRO_EQ 225
#MACRO_MULT 4
#MACRO_MUX 4819
#MACRO_MUX 4813
#MACRO_OTHERS 73
Report Hierarchy Area:
+----------------------------------------------------------------------------+
|Instance |Module |gates |seq |macros |
+----------------------------------------------------------------------------+
|top |huagao_mipi_top |4834 |9096 |798 |
|top |huagao_mipi_top |4851 |9099 |799 |
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
| U_crc16_24b |crc16_24b |67 |16 |0 |
| U_ecc_gen |ecc_gen |37 |6 |0 |
@ -1367,16 +1364,16 @@ Report Hierarchy Area:
| exdev_ctl_b |exdev_ctl |158 |546 |41 |
| u_ADconfig |AD_config |81 |125 |18 |
| u_gen_sp |gen_sp |76 |104 |19 |
| sampling_fe_a |sampling_fe |1838 |1894 |269 |
| sampling_fe_a |sampling_fe |1847 |1919 |269 |
| u0_soft_n |cdc_sync |2 |5 |0 |
| u_ad_sampling |ad_sampling |40 |147 |10 |
| u0_soft_n |cdc_sync |2 |5 |0 |
| u_sort |sort |1794 |1712 |258 |
| u_sort |sort |1803 |1737 |258 |
| rddpram_ctl |rddpram_ctl |2 |5 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_wrsoft_n |cdc_sync |2 |5 |0 |
| u_data_prebuffer |data_prebuffer |1539 |1391 |118 |
| u_data_prebuffer |data_prebuffer |1548 |1391 |118 |
| channelPart |channel_part_8478 |865 |144 |8 |
| fifo_adc |fifo_adc |112 |41 |4 |
| ram_switch |ram_switch |60 |1023 |52 |
@ -1396,9 +1393,9 @@ Report Hierarchy Area:
| mux_addr |mux_e |0 |0 |0 |
| mux_data |mux_e |0 |0 |0 |
| mux_valid |mux_e |0 |0 |0 |
| read_ram_i |read_ram |112 |164 |32 |
| read_ram_addr |read_ram_addr |64 |127 |22 |
| read_ram_data |read_ram_data |46 |32 |10 |
| read_ram_i |read_ram |121 |164 |32 |
| read_ram_addr |read_ram_addr |69 |127 |22 |
| read_ram_data |read_ram_data |50 |32 |10 |
| mux_i |mux_i |0 |0 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
@ -1426,16 +1423,16 @@ Report Hierarchy Area:
| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
| u0_soft_n |cdc_sync |2 |5 |0 |
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
| sampling_fe_b |sampling_fe_rev |1799 |1958 |267 |
| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 |
| u0_soft_n |cdc_sync |2 |5 |0 |
| u_ad_sampling |ad_sampling |39 |147 |9 |
| u0_soft_n |cdc_sync |2 |5 |0 |
| u_sort |sort_rev |1757 |1776 |257 |
| u_sort |sort_rev |1765 |1754 |258 |
| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_wrsoft_n |cdc_sync |2 |5 |0 |
| u_data_prebuffer_rev |data_prebuffer_rev |1503 |1405 |118 |
| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 |
| channelPart |channel_part_8478 |865 |144 |8 |
| fifo_adc |fifo_adc |112 |41 |4 |
| ram_switch |ram_switch |60 |1023 |52 |
@ -1455,8 +1452,8 @@ Report Hierarchy Area:
| mux_addr |mux_e |0 |0 |0 |
| mux_data |mux_e |0 |0 |0 |
| mux_valid |mux_e |0 |0 |0 |
| read_ram_i |read_ram_rev |82 |178 |32 |
| read_ram_addr |read_ram_addr_rev |50 |136 |22 |
| read_ram_i |read_ram_rev |90 |181 |33 |
| read_ram_addr |read_ram_addr_rev |56 |139 |23 |
|...... |...... |- |- |- |
+----------------------------------------------------------------------------+
@ -1475,9 +1472,9 @@ RUN-1001 : Exported congestions
RUN-1001 : Exported violations
RUN-1001 : Exported IO constraints
RUN-1001 : Exported Inst constraints
RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.150280s wall, 1.781250s user + 0.015625s system = 1.796875s CPU (156.2%)
RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.053069s wall, 1.656250s user + 0.078125s system = 1.734375s CPU (164.7%)
RUN-1004 : used memory is 339 MB, reserved memory is 312 MB, peak memory is 399 MB
RUN-1004 : used memory is 326 MB, reserved memory is 301 MB, peak memory is 399 MB
RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
RUN-1002 : start command "get_ports clock_source"
RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
@ -1567,7 +1564,7 @@ RUN-1001 : report | standard | standard |
RUN-1001 : retiming | off | off |
RUN-1001 : ------------------------------------------------------------------
SYN-2001 : Map 61 IOs to PADs
SYN-1032 : 25172/24 useful/useless nets, 22537/26 useful/useless insts
SYN-1032 : 25189/24 useful/useless nets, 22552/26 useful/useless insts
RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
SYN-2501 : Processed 0 LOGIC_BUF instances.
SYN-2501 : 3 BUFG to GCLK
@ -1631,20 +1628,20 @@ SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
SYN-2571 : Map 4 macro multiplier
SYN-2571 : Optimize after map_dsp, round 1
SYN-1032 : 25490/670 useful/useless nets, 22871/580 useful/useless insts
SYN-1032 : 25507/670 useful/useless nets, 22886/580 useful/useless insts
SYN-1016 : Merged 11 instances.
SYN-2571 : Optimize after map_dsp, round 1, 1181 better
SYN-2571 : Optimize after map_dsp, round 2
SYN-2571 : Optimize after map_dsp, round 2, 0 better
SYN-1001 : Throwback 313 control mux instances
SYN-1001 : Throwback 317 control mux instances
SYN-1001 : Convert 12 adder
SYN-2501 : Optimize round 1
SYN-1032 : 28922/338 useful/useless nets, 26304/38 useful/useless insts
SYN-1032 : 28943/338 useful/useless nets, 26323/38 useful/useless insts
SYN-1016 : Merged 396 instances.
SYN-2501 : Optimize round 1, 1774 better
SYN-2501 : Optimize round 2
SYN-2501 : Optimize round 2, 0 better
SYN-2501 : Map 497 macro adder
SYN-2501 : Map 498 macro adder
SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
@ -1669,18 +1666,18 @@ SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
SYN-2501 : Inferred 22 ROM instances
SYN-1019 : Optimized 9690 mux instances.
SYN-1016 : Merged 12104 instances.
SYN-1032 : 36464/295 useful/useless nets, 33740/0 useful/useless insts
SYN-1016 : Merged 12105 instances.
SYN-1032 : 36487/296 useful/useless nets, 33761/0 useful/useless insts
RUN-1002 : start command "start_timer -prepack"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121620, tnet num: 36466, tinst num: 33740, tnode num: 155576, tedge num: 179063.
TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121685, tnet num: 36489, tinst num: 33761, tnode num: 155649, tedge num: 179150.
TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
TMR-2501 : Timing graph initialized successfully.
RUN-1003 : finish command "start_timer -prepack" in 1.483913s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (99.0%)
RUN-1003 : finish command "start_timer -prepack" in 1.303515s wall, 1.281250s user + 0.031250s system = 1.312500s CPU (100.7%)
RUN-1004 : used memory is 518 MB, reserved memory is 495 MB, peak memory is 518 MB
RUN-1004 : used memory is 517 MB, reserved memory is 495 MB, peak memory is 517 MB
TMR-2503 : Start to update net delay, extr mode = 2.
TMR-2504 : Update delay of 36466 nets completely.
TMR-2504 : Update delay of 36489 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 2.
TMR-3001 : Initiate 12 clocks from SDC.
TMR-3004 : Map sdc constraints, there are 6 constraints in total.
@ -1689,11 +1686,11 @@ TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
SYN-3001 : Running gate level optimization.
SYN-2581 : Mapping with K=5, #lut = 7519 (3.86), #lev = 10 (3.15)
SYN-2581 : Mapping with K=5, #lut = 7497 (3.86), #lev = 10 (3.14)
SYN-2551 : Post LUT mapping optimization.
SYN-2581 : Mapping with K=5, #lut = 7392 (3.95), #lev = 8 (3.06)
SYN-3001 : Logic optimization runtime opt = 1.35 sec, map = 0.00 sec
SYN-3001 : Mapper mapped 18898 instances into 7420 LUTs, name keeping = 59%.
SYN-2581 : Mapping with K=5, #lut = 7359 (3.96), #lev = 7 (3.05)
SYN-3001 : Logic optimization runtime opt = 1.20 sec, map = 0.00 sec
SYN-3001 : Mapper mapped 18916 instances into 7387 LUTs, name keeping = 58%.
SYN-3001 : Mapper removed 2 lut buffers
RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
RUN-1001 : standard
@ -1706,16 +1703,16 @@ IO Statistics
#inout 0
LUT Statistics
#Total_luts 9995
#lut4 5129
#lut5 2311
#Total_luts 9962
#lut4 5231
#lut5 2176
#lut6 0
#lut5_mx41 0
#lut4_alu1b 2555
Utilization Statistics
#lut 9995 out of 19600 50.99%
#reg 9170 out of 19600 46.79%
#lut 9962 out of 19600 50.83%
#reg 9173 out of 19600 46.80%
#le 0
#dsp 3 out of 29 10.34%
#bram 54 out of 64 84.38%
@ -1725,7 +1722,7 @@ Utilization Statistics
#dram 16
#pad 75 out of 130 57.69%
#ireg 13
#oreg 18
#oreg 19
#treg 0
#pll 3 out of 4 75.00%
@ -1733,30 +1730,30 @@ Report Hierarchy Area:
+-------------------------------------------------------------------------------------------------+
|Instance |Module |lut |ripple |seq |bram |dsp |
+-------------------------------------------------------------------------------------------------+
|top |huagao_mipi_top |7440 |2555 |9201 |58 |3 |
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |339 |81 |441 |4 |1 |
| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 |
|top |huagao_mipi_top |7407 |2555 |9205 |58 |3 |
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |342 |81 |441 |4 |1 |
| U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 |
| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
| exdev_ctl_a |exdev_ctl |282 |234 |559 |0 |0 |
| u_ADconfig |AD_config |99 |49 |138 |0 |0 |
| u_gen_sp |gen_sp |125 |185 |104 |0 |0 |
| exdev_ctl_b |exdev_ctl |279 |234 |546 |0 |0 |
| exdev_ctl_b |exdev_ctl |274 |234 |546 |0 |0 |
| u_ADconfig |AD_config |91 |49 |125 |0 |0 |
| u_gen_sp |gen_sp |130 |185 |104 |0 |0 |
| sampling_fe_a |sampling_fe |2067 |738 |1894 |25 |0 |
| u_gen_sp |gen_sp |125 |185 |104 |0 |0 |
| sampling_fe_a |sampling_fe |2317 |738 |1919 |25 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_sort |sort |1997 |691 |1712 |25 |0 |
| u_sort |sort |2247 |691 |1737 |25 |0 |
| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_data_prebuffer |data_prebuffer |1868 |615 |1391 |22 |0 |
| channelPart |channel_part_8478 |147 |11 |144 |0 |0 |
| u_data_prebuffer |data_prebuffer |1906 |615 |1391 |22 |0 |
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
| ram_switch |ram_switch |1448 |422 |1023 |0 |0 |
| ram_switch |ram_switch |1466 |422 |1023 |0 |0 |
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
@ -1768,10 +1765,10 @@ Report Hierarchy Area:
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| insert |insert |265 |323 |692 |0 |0 |
| ram_switch_state |ram_switch_state |1054 |0 |216 |0 |0 |
| read_ram_i |read_ram |186 |158 |164 |0 |0 |
| read_ram_addr |read_ram_addr |158 |145 |127 |0 |0 |
| read_ram_data |read_ram_data |27 |13 |32 |0 |0 |
| ram_switch_state |ram_switch_state |1072 |0 |216 |0 |0 |
| read_ram_i |read_ram |207 |158 |164 |0 |0 |
| read_ram_addr |read_ram_addr |177 |145 |127 |0 |0 |
| read_ram_data |read_ram_data |29 |13 |32 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
@ -1795,22 +1792,22 @@ Report Hierarchy Area:
| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u_transfer_300_to_200 |transfer_300_to_200 |122 |76 |276 |3 |0 |
| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
| sampling_fe_b |sampling_fe_rev |2261 |751 |1958 |25 |1 |
| sampling_fe_b |sampling_fe_rev |2335 |751 |1936 |25 |1 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_sort |sort_rev |2191 |704 |1776 |25 |1 |
| u_sort |sort_rev |2265 |704 |1754 |25 |1 |
| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_data_prebuffer_rev |data_prebuffer_rev |2066 |628 |1405 |22 |1 |
| u_data_prebuffer_rev |data_prebuffer_rev |1924 |628 |1408 |22 |1 |
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
| ram_switch |ram_switch |1441 |422 |1023 |0 |0 |
| ram_switch |ram_switch |1479 |422 |1023 |0 |0 |
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
@ -1822,10 +1819,10 @@ Report Hierarchy Area:
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| insert |insert |265 |323 |692 |0 |0 |
| ram_switch_state |ram_switch_state |1047 |0 |216 |0 |0 |
| read_ram_i |read_ram_rev |390 |171 |178 |0 |0 |
| read_ram_addr |read_ram_addr_rev |176 |145 |136 |0 |0 |
| read_ram_data |read_ram_data_rev |214 |26 |42 |0 |0 |
| ram_switch_state |ram_switch_state |1085 |0 |216 |0 |0 |
| read_ram_i |read_ram_rev |210 |171 |181 |0 |0 |
| read_ram_addr |read_ram_addr_rev |181 |145 |139 |0 |0 |
| read_ram_data |read_ram_data_rev |29 |26 |42 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
@ -1841,7 +1838,7 @@ SYN-1001 : Packing model "huagao_mipi_top" ...
SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
SYN-1014 : Optimize round 1
SYN-1015 : Optimize round 1, 0 better
SYN-4002 : Packing 9170 DFF/LATCH to SEQ ...
SYN-4002 : Packing 9173 DFF/LATCH to SEQ ...
SYN-4009 : Pack 83 carry chain into lslice
SYN-4007 : Packing 1278 adder to BLE ...
SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
@ -1849,9 +1846,9 @@ SYN-4007 : Packing 0 gate4 to BLE ...
SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
SYN-4012 : Packed 0 FxMUX
SYN-4013 : Packed 16 DRAM and 4 SEQ.
RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 63.896196s wall, 63.531250s user + 0.296875s system = 63.828125s CPU (99.9%)
RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 61.071613s wall, 60.671875s user + 0.375000s system = 61.046875s CPU (100.0%)
RUN-1004 : used memory is 395 MB, reserved memory is 386 MB, peak memory is 698 MB
RUN-1004 : used memory is 394 MB, reserved memory is 379 MB, peak memory is 699 MB
RUN-1002 : start command "legalize_phy_inst"
SYN-1011 : Flatten model huagao_mipi_top
SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
@ -1871,8 +1868,8 @@ RUN-1001 : Exported violations
RUN-1001 : Exported timing constraints
RUN-1001 : Exported IO constraints
RUN-1001 : Exported Inst constraints
RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.634628s wall, 2.843750s user + 0.031250s system = 2.875000s CPU (175.9%)
RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.555646s wall, 2.687500s user + 0.031250s system = 2.718750s CPU (174.8%)
RUN-1004 : used memory is 401 MB, reserved memory is 385 MB, peak memory is 698 MB
RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240218_161055.log"
RUN-1004 : used memory is 403 MB, reserved memory is 384 MB, peak memory is 699 MB
RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240219_105625.log"
RUN-1001 : Backing up run's log file succeed.

249
src/prj/td_project/td_2024-02-18_15-33-24.log
View File

@ -0,0 +1,249 @@
============================================================
Tang Dynasty, V5.6.71036
Copyright (c) 2012-2023 Anlogic Inc.
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
Built at = 20:34:38 Mar 21 2023
Run by = holdtecs
Run Date = Sun Feb 18 15:33:24 2024
Run on = DESKTOP-5MQL5VE
============================================================
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
PRG-2014 : Chip validation success: EAGLE_S20_EG176
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.633929s wall, 0.093750s user + 0.328125s system = 0.421875s CPU (2.4%)
RUN-1004 : used memory is 216 MB, reserved memory is 154 MB, peak memory is 248 MB
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.851310s wall, 0.187500s user + 0.359375s system = 0.546875s CPU (3.1%)
RUN-1004 : used memory is 216 MB, reserved memory is 154 MB, peak memory is 248 MB
GUI-1001 : Downloading succeeded!
RUN-1001 : reset_run syn_1 phy_1.
RUN-6001 WARNING: Failed to reset phy_1: some files can't be removed in D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1
GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
RUN-1001 : stop_run syn_1.
RUN-1001 : reset_run syn_1 -step opt_rtl.
RUN-1001 : syn_1: run complete.
HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
RUN-1001 : reset_run syn_1 phy_1.
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
RUN-1001 : syn_1: run complete.
RUN-1001 : phy_1: run complete.
RUN-1001 : open_run phy_1.
RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
RUN-1001 : Database version number 46146.
RUN-1001 : Import flow parameters
PHY-1001 : Generate detailed routing grids ...
PHY-1001 : Generate nets ...
PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
PHY-5010 Similar messages will be suppressed.
PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
PHY-1001 : eco open net = 0
PHY-1001 : 586 feed throughs used by 421 nets
RUN-1001 : Import timing constraints
RUN-1001 : Import IO constraints
RUN-1001 : Import Inst constraints
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 12.298790s wall, 12.000000s user + 0.531250s system = 12.531250s CPU (101.9%)
RUN-1004 : used memory is 971 MB, reserved memory is 936 MB, peak memory is 980 MB
TMR-3509 : Import timing summary.
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode program_spi -v -spd 7 -sec 64 -cable 0 -flashsize 128"
PRG-2014 : Chip validation success: EAGLE_S20_EG176
PRG-1001 : SPI Flash ID is: ef
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m program_spi -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
RUN-1003 : finish command "bit_to_vec -chip EAGLE_S20_EG176 -m program_spi -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit" in 1.749765s wall, 1.640625s user + 0.125000s system = 1.765625s CPU (100.9%)
RUN-1004 : used memory is 1325 MB, reserved memory is 1289 MB, peak memory is 1337 MB
RUN-1002 : start command "program_spi -cable 0 -spd 7"
RUN-1003 : finish command "program_spi -cable 0 -spd 7" in 109.791801s wall, 3.875000s user + 2.125000s system = 6.000000s CPU (5.5%)
RUN-1004 : used memory is 1326 MB, reserved memory is 1289 MB, peak memory is 1337 MB
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m verify_spi -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
RUN-1002 : start command "program -cable 0 -spd 4"
RUN-1003 : finish command "program -cable 0 -spd 4" in 23.103374s wall, 0.359375s user + 0.625000s system = 0.984375s CPU (4.3%)
RUN-1004 : used memory is 1115 MB, reserved memory is 1079 MB, peak memory is 1337 MB
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode program_spi -v -spd 7 -sec 64 -cable 0 -flashsize 128" in 138.788588s wall, 7.625000s user + 2.968750s system = 10.593750s CPU (7.6%)
RUN-1004 : used memory is 1115 MB, reserved memory is 1079 MB, peak memory is 1337 MB
GUI-1001 : Downloading succeeded!
TMR-3509 : Import timing summary.
RUN-1001 : reset_run syn_1 phy_1.
GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
RUN-1001 : syn_1: run complete.
RUN-1001 : phy_1: run complete.
RUN-1001 : open_run phy_1.
RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
RUN-1001 : Database version number 46146.
RUN-1001 : Import flow parameters
PHY-1001 : Generate detailed routing grids ...
PHY-1001 : Generate nets ...
PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
PHY-5010 Similar messages will be suppressed.
PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
PHY-1001 : eco open net = 0
PHY-1001 : 580 feed throughs used by 430 nets
RUN-1001 : Import timing constraints
RUN-1001 : Import IO constraints
RUN-1001 : Import Inst constraints
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 9.264628s wall, 9.171875s user + 0.406250s system = 9.578125s CPU (103.4%)
RUN-1004 : used memory is 1195 MB, reserved memory is 1169 MB, peak memory is 1337 MB
TMR-3509 : Import timing summary.
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
PRG-2014 : Chip validation success: EAGLE_S20_EG176
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.579945s wall, 0.125000s user + 0.156250s system = 0.281250s CPU (1.6%)
RUN-1004 : used memory is 1201 MB, reserved memory is 1172 MB, peak memory is 1337 MB
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.791400s wall, 0.250000s user + 0.156250s system = 0.406250s CPU (2.3%)
RUN-1004 : used memory is 1201 MB, reserved memory is 1172 MB, peak memory is 1337 MB
GUI-1001 : Downloading succeeded!
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
PRG-2014 : Chip validation success: EAGLE_S20_EG176
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.603010s wall, 0.203125s user + 0.421875s system = 0.625000s CPU (3.6%)
RUN-1004 : used memory is 1196 MB, reserved memory is 1168 MB, peak memory is 1337 MB
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.817724s wall, 0.343750s user + 0.437500s system = 0.781250s CPU (4.4%)
RUN-1004 : used memory is 1196 MB, reserved memory is 1168 MB, peak memory is 1337 MB
GUI-1001 : Downloading succeeded!
RUN-1001 : reset_run syn_1 phy_1.
GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
RUN-1001 : syn_1: run complete.
RUN-1001 : phy_1: run complete.
RUN-1001 : open_run phy_1.
RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
RUN-1001 : Database version number 46146.
RUN-1001 : Import flow parameters
PHY-1001 : Generate detailed routing grids ...
PHY-1001 : Generate nets ...
PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
PHY-5010 Similar messages will be suppressed.
PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
PHY-1001 : eco open net = 0
PHY-1001 : 586 feed throughs used by 421 nets
RUN-1001 : Import timing constraints
RUN-1001 : Import IO constraints
RUN-1001 : Import Inst constraints
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 9.434136s wall, 9.281250s user + 0.359375s system = 9.640625s CPU (102.2%)
RUN-1004 : used memory is 1226 MB, reserved memory is 1202 MB, peak memory is 1337 MB
TMR-3509 : Import timing summary.
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
PRG-2014 : Chip validation success: EAGLE_S20_EG176
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.566477s wall, 0.250000s user + 0.328125s system = 0.578125s CPU (3.3%)
RUN-1004 : used memory is 1229 MB, reserved memory is 1204 MB, peak memory is 1337 MB
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.781757s wall, 0.375000s user + 0.328125s system = 0.703125s CPU (4.0%)
RUN-1004 : used memory is 1229 MB, reserved memory is 1204 MB, peak memory is 1337 MB
GUI-1001 : Downloading succeeded!
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
PRG-2014 : Chip validation success: EAGLE_S20_EG176
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.542523s wall, 0.140625s user + 0.281250s system = 0.421875s CPU (2.4%)
RUN-1004 : used memory is 1229 MB, reserved memory is 1204 MB, peak memory is 1337 MB
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.759527s wall, 0.265625s user + 0.281250s system = 0.546875s CPU (3.1%)
RUN-1004 : used memory is 1229 MB, reserved memory is 1204 MB, peak memory is 1337 MB
GUI-1001 : Downloading succeeded!
TMR-3509 : Import timing summary.
TMR-3509 : Import timing summary.

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src/prj/td_project/td_20240218_153322.log
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@ -0,0 +1,207 @@
============================================================
Tang Dynasty, V5.6.71036
Copyright (c) 2012-2023 Anlogic Inc.
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
Built at = 20:34:38 Mar 21 2023
Run by = holdtecs
Run Date = Sun Feb 18 15:33:22 2024
Run on = DESKTOP-5MQL5VE
============================================================
RUN-001 : GUI based run...
RUN-1002 : start command "open_project hg_anlogic.al -update"
RUN-1001 : Print Global Property
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : message | standard | standard |
RUN-1001 : mixed_pack_place_flow | on | on |
RUN-1001 : qor_monitor | off | off |
RUN-1001 : syn_ip_flow | off | off |
RUN-1001 : thread | auto | auto |
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Rtl Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : compress_add | ripple | ripple |
RUN-1001 : elf_sload | off | off |
RUN-1001 : fix_undriven | 0 | 0 |
RUN-1001 : flatten | off | off |
RUN-1001 : gate_sharing | on | on |
RUN-1001 : hdl_warning_level | normal | normal |
RUN-1001 : impl_internal_tribuf | on | on |
RUN-1001 : impl_set_reset | on | on |
RUN-1001 : infer_gsr | off | off |
RUN-1001 : keep_hierarchy | auto | auto |
RUN-1001 : max_fanout | 9999 | 9999 |
RUN-1001 : max_oh2bin_len | 10 | 10 |
RUN-1001 : merge_equal | on | on |
RUN-1001 : merge_equiv | on | on |
RUN-1001 : merge_mux | off | off |
RUN-1001 : min_control_set | 8 | 8 |
RUN-1001 : min_ripple_len | auto | auto |
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
RUN-1001 : opt_adder_fanout | on | on |
RUN-1001 : opt_arith | on | on |
RUN-1001 : opt_big_gate | off | off |
RUN-1001 : opt_const | on | on |
RUN-1001 : opt_const_mult | on | on |
RUN-1001 : opt_lessthan | on | on |
RUN-1001 : opt_mux | off | off |
RUN-1001 : opt_ram | high | high |
RUN-1001 : rtl_sim_model | off | off |
RUN-1001 : seq_syn | on | on |
RUN-1001 : --------------------------------------------------------------
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll/pll.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll/pll.v(99)
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM.v
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
HDL-1007 : analyze verilog file ../../hg_mp/cdc/cdc_sync.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/ad_sampling.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/exdev_ctl.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/fan_ctrl.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/gen_sp.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe_rev.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(399)
HDL-1007 : analyze verilog file ../../hg_mp/fe/wrdpram_ctl.v
HDL-1007 : undeclared symbol 'neg_dval_i', assumed default net type 'wire' in ../../hg_mp/fe/wrdpram_ctl.v(375)
HDL-5007 WARNING: parameter 'DPI300_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(24)
HDL-5007 WARNING: parameter 'DPI600_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(25)
HDL-1007 : analyze verilog file ../../hg_mp/local_bus/CRC4_D16.v
HDL-1007 : analyze verilog file ../../hg_mp/local_bus/local_bus_slve_cis.v
HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
HDL-1007 : analyze verilog file ../../hg_mp/pixel_cdc/pixel_cdc.v
HDL-1007 : analyze verilog file ../../hg_mp/scan_start/scan_start_diff.v
HDL-1007 : analyze verilog file ../../hg_mp/sensor_lane/lscc_sensor.v
HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1332)
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
This product includes software developed by the OpenSSL Project
for use in the OpenSSL Toolkit (http://www.openssl.org/)
Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
All rights reserved.
This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/AD_config.v
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/crc16_24b.v
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/ecc_gen.v
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_hs_generate.v
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lp_generate.v
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
HDL-1007 : analyze verilog file ../../hg_mp/lvds_rx/lvds_rx_enc.v
HDL-1007 : back to file '../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/transfer_300_to_200.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(40)
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(98)
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(123)
HDL-1007 : analyze verilog file ../../hg_mp/fe/ch_addr_gen.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/fifo_adc.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/insert.v
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(77)
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(83)
HDL-1007 : analyze verilog file ../../hg_mp/fe/link_line.v
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/link_line.v(20)
HDL-1007 : analyze verilog file ../../hg_mp/fe/mapping.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_e.v
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/mux_e.v(16)
HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_i.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(211)
HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(42)
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(42)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(57)
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(57)
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(122)
HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(213)
HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data_rev.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_rev.v
HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr_rev.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(44)
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(44)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(139)
HDL-1007 : analyze verilog file ../../hg_mp/local_bus/uart_2dsp_6M_921600.v
HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
RUN-1001 : Project manager successfully analyzed 63 source files.
RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
ARC-1001 : Device Initialization.
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : OPTION | IO | SETTING
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
ARC-1001 : done | P10 | gpio
ARC-1001 : program_b | P134 | dedicate
ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
ARC-1001 : ----------------------------------------------------------------------
ARC-1004 : Device setting, marked 5 dedicate IOs in total.