diff --git a/src/hg_mp/drx_top/huagao_mipi_top.v b/src/hg_mp/drx_top/huagao_mipi_top.v
index 800baeb..4740d9c 100644
--- a/src/hg_mp/drx_top/huagao_mipi_top.v
+++ b/src/hg_mp/drx_top/huagao_mipi_top.v
@@ -664,7 +664,7 @@ end
reg en_packet_dly;
wire [3:0] adc_freqdiv;
-wire [5:0]debug_1;
+wire [4:0]debug_1;
wire [5:0]debug_2;
wire [3:0]debug_3;
wire [31:0] bg_sp_t_a;
@@ -960,7 +960,7 @@ sampling_fe #
.start_sp (start_sp_a ),
.rd_done (rd_done ),
.line_sycn (line_sycn_a ),
-.debug(debug_1[5:0]),
+.debug(debug_1[4:0]),
.cis_sel(cis_sel)
);
@@ -1695,12 +1695,12 @@ always @(*) begin
end
assign debug[0] = a_vs ;
-assign debug[1] = a_ad_sck;
-assign debug[2] = a_ad_sen ;
-assign debug[3] = a_ad_sdi;
-assign debug[4] = a_ad_sdo ;
+assign debug[1] = debug_1[3];
+assign debug[2] = debug_1[2] ;
+assign debug[3] = debug_1[1];
+assign debug[4] = debug_1[0] ;
assign debug[5] = FV_MIPI ;
-assign debug[6] = sync_eot ;
+assign debug[6] = debug_1[4] ;
assign debug[7] = LV_MIPI;
diff --git a/src/hg_mp/fe/prebuffer.v b/src/hg_mp/fe/prebuffer.v
index 0ef12b8..394ed32 100644
--- a/src/hg_mp/fe/prebuffer.v
+++ b/src/hg_mp/fe/prebuffer.v
@@ -9,7 +9,7 @@ module data_prebuffer
dataA_ADC,
dataB_ADC,
dataC_ADC,
- data_CTL_ADC,
+ data_CTL_ADC,
PBUFF_DATA_CONTROL,
trigRAM,
trigCAM,
@@ -24,7 +24,9 @@ module data_prebuffer
rd_done_trig,
start_sp_wr,
start_sp_rd,
- cis_sel
+ cis_sel,
+ soft_n,
+ debug
);
@@ -77,6 +79,8 @@ output rd_done_trig;
input start_sp_wr;
input start_sp_rd;
input cis_sel;
+input soft_n;
+output wire [4:0]debug;
@@ -375,6 +379,7 @@ read_ram #(
(
.clk(camclk),
.rst_n(rst_n),
+ .soft_n(soft_n),
.trig(trig_cam),
.full(full_sync),
.dou(dou),
@@ -386,7 +391,8 @@ read_ram #(
.DVAL(DVAL),
.rd_done_trig(rd_done_trig),
.wr_end(wr_end),
- .start_sp(start_sp_rd)
+ .start_sp(start_sp_rd) ,
+ .debug(debug)
);
generate
diff --git a/src/hg_mp/fe/prebuffer_rev.v b/src/hg_mp/fe/prebuffer_rev.v
index dcf81f8..7fac716 100644
--- a/src/hg_mp/fe/prebuffer_rev.v
+++ b/src/hg_mp/fe/prebuffer_rev.v
@@ -25,7 +25,8 @@ module data_prebuffer_rev
ab_delay_time,
start_sp_wr,
start_sp_rd,
- cis_sel
+ cis_sel,
+ soft_n
);
@@ -79,6 +80,7 @@ input [15:0] ab_delay_time;
input start_sp_wr;
input start_sp_rd;
input cis_sel;
+input soft_n;
@@ -377,6 +379,7 @@ read_ram_rev #(
(
.clk(camclk),
.rst_n(rst_n),
+ .soft_n(soft_n),
.trig(trig_cam),
.full(full_sync),
.dou(dou),
diff --git a/src/hg_mp/fe/read_ram.v b/src/hg_mp/fe/read_ram.v
index 14845d7..9bcd2b6 100644
--- a/src/hg_mp/fe/read_ram.v
+++ b/src/hg_mp/fe/read_ram.v
@@ -13,7 +13,9 @@ module read_ram
LVAL,
rd_done_trig,
wr_end,
- start_sp
+ start_sp,
+ soft_n,
+ debug
);
parameter integer RD_DONE_WIDTH = 14;
parameter integer PBUFF_TAP_NUM = 8;
@@ -32,6 +34,8 @@ output [PBUFF_ADDR_WIDTH*PBUFF_RAM_NUM-1:0] RD_addr_i;
output rd_done_trig;
input wr_end;
input start_sp;
+input soft_n;
+output wire [4:0]debug;
wire sync_wr_end;
cdc_sync # (
@@ -43,7 +47,7 @@ cdc_sync # (
.signal_from(wr_end),
.signal_to (sync_wr_end)
);
-
+
read_ram_data #(
.RD_DONE_WIDTH(RD_DONE_WIDTH),
@@ -54,6 +58,7 @@ read_ram_data
(
.clk(clk),
.rst_n(rst_n),
+ .soft_n(soft_n),
.trig(trig),
.full(full),
.rd_done(rd_done),
@@ -64,7 +69,8 @@ read_ram_data
.LVAL(LVAL),
.rd_done_trig(rd_done_trig),
.wr_end(sync_wr_end),
- .start_sp(start_sp)
+ .start_sp(start_sp),
+ .debug(debug)
);
@@ -78,6 +84,7 @@ read_ram_addr
(
.clk(clk),
.rst_n(rst_n),
+ .soft_n(soft_n),
.trig(trig),
.full(full),
.rd_done(rd_done),
diff --git a/src/hg_mp/fe/read_ram_addr.v b/src/hg_mp/fe/read_ram_addr.v
index b4e3a26..e2063db 100644
--- a/src/hg_mp/fe/read_ram_addr.v
+++ b/src/hg_mp/fe/read_ram_addr.v
@@ -8,7 +8,8 @@ module read_ram_addr
RD_addr,
RD_addr_i,
wr_end,
- start_sp
+ start_sp,
+ soft_n
);
parameter integer PBUFF_ADDR_WIDTH = 13;
parameter integer RD_DONE_WIDTH = 13;
@@ -24,6 +25,7 @@ input [RD_DONE_WIDTH-1:0] RD_addr;
output reg [PBUFF_ADDR_WIDTH*PBUFF_RAM_NUM-1:0] RD_addr_i;
input wr_end;
input start_sp;
+input soft_n;
//culculate
localparam integer PBUFF_DIV = PBUFF_RAM_NUM / PBUFF_TAP_NUM;
@@ -83,6 +85,7 @@ assign end_trig = (cam_end_delay == 4'hf);
always @(posedge clk)
if(~rst_n) current_state <= WAIT_WR;
+else if(~soft_n)current_state <= WAIT_WR;
else if(start_sp) current_state <= WAIT_WR;
else if(full) current_state <= current_state;
else current_state <= next_state;
@@ -100,16 +103,19 @@ endcase
always @(posedge clk)
if(~rst_n) start_cnt <= 'd0;
+else if(~soft_n)start_cnt <= 'd0;
else if(current_state == RD_DELAY) start_cnt <= start_cnt + 1'b1;
else start_cnt <= 'd0;
always @(posedge clk)
if(~rst_n) cam_end_delay <= 'd0;
+else if(~soft_n) cam_end_delay <= 'd0;
else if(current_state == RD_END) cam_end_delay <= cam_end_delay + 1'b1;
else cam_end_delay <= 'd0;
always @(posedge clk)//xun huan zhuang hai ji
if(~rst_n) state_index <= 'd0;
+else if(~soft_n) state_index <= 'd0;
else case(current_state)
RD_DELAY : state_index <= |start_cnt ? state_index + 1'b1 : 'd0;//delay 1 clk
RD_START : state_index <= state_index + 1'b1;
diff --git a/src/hg_mp/fe/read_ram_addr_rev.v b/src/hg_mp/fe/read_ram_addr_rev.v
index 3d3b1e5..b1e7e2a 100644
--- a/src/hg_mp/fe/read_ram_addr_rev.v
+++ b/src/hg_mp/fe/read_ram_addr_rev.v
@@ -9,7 +9,8 @@ module read_ram_addr_rev
RD_addr_i,
rd_finish,
ab_delay_time,
- start_sp
+ start_sp,
+ soft_n
);
parameter integer PBUFF_ADDR_WIDTH = 13;
parameter integer RD_DONE_WIDTH = 13;
@@ -26,6 +27,7 @@ input rd_finish;
output reg [PBUFF_ADDR_WIDTH*PBUFF_RAM_NUM-1:0] RD_addr_i;
input [15:0]ab_delay_time;
input start_sp;
+input soft_n;
//culculate
localparam integer PBUFF_DIV = PBUFF_RAM_NUM / PBUFF_TAP_NUM;
@@ -84,6 +86,7 @@ assign end_trig = (cam_end_delay == 4'hf);
always @(posedge clk)
if(~rst_n) current_state <= IDLE_RD;
+else if(~soft_n)current_state <= IDLE_RD;
else if(start_sp)current_state <= IDLE_RD;
else if(full) current_state <= current_state;
else current_state <= next_state;
@@ -117,16 +120,19 @@ endcase
always @(posedge clk)
if(~rst_n) start_cnt <= 'd0;
+else if(~soft_n)start_cnt <= 'd0;
else if(current_state == RD_DELAY) start_cnt <= start_cnt + 1'b1;
else start_cnt <= 'd0;
always @(posedge clk)
if(~rst_n) cam_end_delay <= 'd0;
+else if(~soft_n) cam_end_delay <= 'd0;
else if(current_state == RD_END) cam_end_delay <= cam_end_delay + 1'b1;
else cam_end_delay <= 'd0;
always @(posedge clk)//xun huan zhuang hai ji
if(~rst_n) state_index <= 'd0;
+else if(~soft_n) state_index <= 'd0;
else case(current_state)
RD_DELAY : state_index <= |start_cnt ? state_index + 1'b1 : 'd0;//delay 1 clk
RD_START : state_index <= state_index + 1'b1;
diff --git a/src/hg_mp/fe/read_ram_data.v b/src/hg_mp/fe/read_ram_data.v
index fc1cda7..2081754 100644
--- a/src/hg_mp/fe/read_ram_data.v
+++ b/src/hg_mp/fe/read_ram_data.v
@@ -12,7 +12,9 @@ module read_ram_data
LVAL,
rd_done_trig,
wr_end,
- start_sp
+ start_sp,
+ soft_n,
+ debug
);
parameter integer RD_DONE_WIDTH = 13;
parameter integer PBUFF_TAP_NUM = 8;
@@ -30,6 +32,8 @@ output reg DVAL,LVAL;
output rd_done_trig;
input wr_end;
input start_sp;
+input soft_n;
+output wire [4:0]debug;
/////////////////////////RD_DATA////////////////////////////////
localparam WAIT_WR = 5'b00001;
@@ -61,10 +65,18 @@ else full_r <= full;
always @(posedge clk)
if(~rst_n) current_state <= WAIT_WR;
+else if(~soft_n)current_state <= WAIT_WR;
else if(start_sp)current_state <= WAIT_WR;
else if(full) current_state <= current_state;
else current_state <= next_state;
+assign debug[0] = wr_end;
+assign debug[1] = trig;
+assign debug[2] = start_trig;
+assign debug[3] = rd_done_trig;
+assign debug[4] = end_trig;
+
+
always @(current_state,wr_end,trig,start_trig,rd_done_trig,end_trig)
case(current_state)
WAIT_WR:next_state <= wr_end ? IDLE_RD : WAIT_WR;
@@ -77,27 +89,32 @@ endcase
always @(posedge clk)
if(~rst_n) start_cnt <= 'd0;
+else if(~soft_n)start_cnt <= 'd0;
else if(current_state == RD_DELAY) start_cnt <= start_cnt + 1'b1;
else start_cnt <= 'd0;
always @(posedge clk)
if(~rst_n) cam_end_delay <= 'd0;
+else if(~soft_n)cam_end_delay <= 'd0;
else if(current_state == RD_END) cam_end_delay <= cam_end_delay + 1'b1;
else cam_end_delay <= 'd0;
always @(posedge clk)
if(~rst_n) RD_addr <= 'd0;
+else if(~soft_n) RD_addr <= 'd0;
else if(current_state == RD_DELAY || current_state == RD_SWITCH)
RD_addr <= full ? RD_addr : RD_addr + 1'b1;
else RD_addr <= 'd0;
always @(posedge clk)//xun huan zhuang hai ji
if(~rst_n) state_index <= 'd0;
+else if(~soft_n) state_index <= 'd0;
else if(current_state == RD_SWITCH) state_index <= full ? state_index : (state_index==PBUFF_RAM_NUM-1) ? 'd0 : state_index + 1'b1;
else state_index <= 'd0;
always @(posedge clk)//xun huan zhuang hai ji
if(~rst_n) state_index_d1 <= 'd0;
+else if(~soft_n)state_index_d1 <= 'd0;
else state_index_d1 <= state_index;
@@ -110,11 +127,13 @@ assign camdata = camdata_tmp ;
always @(posedge clk)
if(~rst_n) DVAL <= 1'b0;
+else if(~soft_n)DVAL <= 1'b0;
else if(current_state == RD_SWITCH) DVAL <= full ? 1'b0 : 1'b1;
else DVAL <= 1'b0;
always @(posedge clk)
if(~rst_n) LVAL <= 1'b0;
+else if(~soft_n)LVAL <= 1'b0;
else case(current_state)
RD_DELAY: LVAL <= start_trig ? 1'b1 : 1'b0;
RD_SWITCH:LVAL <= full ? 1'b0 : 1'b1;
diff --git a/src/hg_mp/fe/read_ram_data_rev.v b/src/hg_mp/fe/read_ram_data_rev.v
index 65f7f07..dc95a9f 100644
--- a/src/hg_mp/fe/read_ram_data_rev.v
+++ b/src/hg_mp/fe/read_ram_data_rev.v
@@ -12,7 +12,8 @@ module read_ram_data_rev
LVAL,
rd_finish,
ab_delay_time,
- start_sp
+ start_sp,
+ soft_n
);
parameter integer RD_DONE_WIDTH = 13;
parameter integer PBUFF_TAP_NUM = 8;
@@ -30,6 +31,7 @@ output reg DVAL,LVAL;
input rd_finish;
input [15:0] ab_delay_time;
input start_sp;
+input soft_n;
/////////////////////////RD_DATA////////////////////////////////
localparam IDLE_RD = 4'b0001;
@@ -60,6 +62,7 @@ else full_r <= full;
always @(posedge clk)
if(~rst_n) current_state <= IDLE_RD;
+else if(~soft_n)current_state <= IDLE_RD;
else if(start_sp)current_state <= IDLE_RD;
else if(full) current_state <= current_state;
else current_state <= next_state;
@@ -91,27 +94,32 @@ endcase
always @(posedge clk)
if(~rst_n) start_cnt <= 'd0;
+else if(~soft_n)start_cnt <= 'd0;
else if(current_state == RD_DELAY) start_cnt <= start_cnt + 1'b1;
else start_cnt <= 'd0;
always @(posedge clk)
if(~rst_n) cam_end_delay <= 'd0;
+else if(~soft_n)cam_end_delay <= 'd0;
else if(current_state == RD_END) cam_end_delay <= cam_end_delay + 1'b1;
else cam_end_delay <= 'd0;
always @(posedge clk)
if(~rst_n) RD_addr <= 'd0;
+else if(~soft_n) RD_addr <= 'd0;
else if( current_state == RD_SWITCH)
RD_addr <= full ? RD_addr : RD_addr + 1'b1;
else RD_addr <= 'd0;
always @(posedge clk)//xun huan zhuang hai ji
if(~rst_n) state_index <= 'd0;
+else if(~soft_n) state_index <= 'd0;
else if(current_state == RD_SWITCH) state_index <= full ? state_index : (state_index==PBUFF_RAM_NUM-1) ? 'd0 : state_index + 1'b1;
else state_index <= 'd0;
always @(posedge clk)//xun huan zhuang hai ji
if(~rst_n) state_index_d1 <= 'd0;
+else if(~soft_n)state_index_d1 <= 'd0;
else state_index_d1 <= state_index;
@@ -124,11 +132,13 @@ assign camdata = camdata_tmp ;
always @(posedge clk)
if(~rst_n) DVAL <= 1'b0;
+else if(~soft_n)DVAL <= 1'b0;
else if(current_state == RD_SWITCH) DVAL <= full ? 1'b0 : 1'b1;
else DVAL <= 1'b0;
always @(posedge clk)
if(~rst_n) LVAL <= 1'b0;
+else if(~soft_n)LVAL <= 1'b0;
else case(current_state)
RD_DELAY: LVAL <= start_trig ? 1'b1 : 1'b0;
RD_SWITCH:LVAL <= full ? 1'b0 : 1'b1;
@@ -138,7 +148,7 @@ endcase
mux_i #(
- .WIDTH(8),
+ .WIDTH(8),
.I_NUM(PBUFF_RAM_NUM),
.O_NUM(PBUFF_TAP_NUM)
) mux_i(
diff --git a/src/hg_mp/fe/read_ram_rev.v b/src/hg_mp/fe/read_ram_rev.v
index e3d23f5..fb429ec 100644
--- a/src/hg_mp/fe/read_ram_rev.v
+++ b/src/hg_mp/fe/read_ram_rev.v
@@ -13,7 +13,8 @@ module read_ram_rev
LVAL,
rd_end,
ab_delay_time,
- start_sp
+ start_sp,
+ soft_n
);
parameter integer RD_DONE_WIDTH = 14;
parameter integer PBUFF_TAP_NUM = 8;
@@ -32,6 +33,7 @@ output [PBUFF_ADDR_WIDTH*PBUFF_RAM_NUM-1:0] RD_addr_i;
input [15:0] ab_delay_time;
input rd_end;
input start_sp;
+input soft_n;
read_ram_data_rev#(
.RD_DONE_WIDTH(RD_DONE_WIDTH),
@@ -40,8 +42,9 @@ read_ram_data_rev#(
)
read_ram_data
(
- .clk(clk),
+ .clk(clk),
.rst_n(rst_n),
+ .soft_n(soft_n),
.trig(trig),
.full(full),
.rd_done(rd_done),
@@ -65,6 +68,7 @@ read_ram_addr
(
.clk(clk),
.rst_n(rst_n),
+ .soft_n(soft_n),
.trig(trig),
.full(full),
.rd_done(rd_done),
diff --git a/src/hg_mp/fe/sampling_fe.v b/src/hg_mp/fe/sampling_fe.v
index 118b5b4..613d836 100644
--- a/src/hg_mp/fe/sampling_fe.v
+++ b/src/hg_mp/fe/sampling_fe.v
@@ -24,7 +24,7 @@ module sampling_fe
output fe_done ,
output rd_done ,
output line_sycn,
- output wire [5:0] debug,
+ output wire [4:0] debug,
output wire [1:0] debug_2,
input cis_sel
// output [23 : 0] rdaddr_a
diff --git a/src/hg_mp/fe/sort.v b/src/hg_mp/fe/sort.v
index 1ba4e49..8eee120 100644
--- a/src/hg_mp/fe/sort.v
+++ b/src/hg_mp/fe/sort.v
@@ -17,12 +17,12 @@ module sort
input [1 : 0] dpi_mode ,
input cis_mode ,
input [YPIXEL_WIDTH-1: 0] y_pixel ,
- output [23: 0] data_o ,
- output dval_o ,
+ output reg [23: 0] data_o ,
+ output reg dval_o ,
output fe_done ,
output rd_done,
output end_trig ,
- output wire [5:0] debug,
+ output wire [4:0] debug,
input [4:0] lvds_flag ,
input [4:0] set_flag ,
input cis_sel
@@ -317,6 +317,7 @@ data_prebuffer u_data_prebuffer
(
.FIFO_rdclk (wrclk),//frequency equal to dataclk_ADCx
.rst_n (reset_n),
+ .soft_n (sync_rdsoft_n),
.DPIset (dpi_mode),
.dataclk_ADC (wrclk),
.dataA_ADC (ch25_1d),
@@ -336,7 +337,8 @@ data_prebuffer u_data_prebuffer
.rd_done_trig(rd_done),
.start_sp_wr(pos_frame_start_wr),
.start_sp_rd(pos_frame_start_rd),
- .cis_sel (cis_sel )
+ .cis_sel (cis_sel ),
+ .debug(debug)
);
@@ -410,8 +412,26 @@ begin
else dval_o_200dpi_d1 <= dval_o_200dpi;
end
-assign data_o = cis_sel ? data_o_tmp : (dpi_mode == 2'b01 ? data_o_200dpi : data_o_tmp);
-assign dval_o = cis_sel ? dval_o_tmp : (dpi_mode == 2'b01 ? dval_o_200dpi : dval_o_tmp);
+ always @ (posedge rdclk )
+begin
+ if(!reset_n) data_o <= 24'b0;
+ else if (~sync_rdsoft_n) data_o <= 24'b0;
+ else if (cis_sel) data_o <= data_o_tmp;
+ else if (dpi_mode == 2'b01) data_o <= data_o_200dpi;
+ else data_o <= data_o_tmp;
+end
-assign debug[0] = cis_sel;
+ always @ (posedge rdclk )
+begin
+ if(!reset_n) dval_o <= 1'b0;
+ else if (~sync_rdsoft_n) dval_o <= 1'b0;
+ else if (cis_sel) dval_o <= dval_o_tmp;
+ else if (dpi_mode == 2'b01) dval_o <= dval_o_200dpi;
+ else dval_o <= dval_o_tmp;
+end
+
+//assign data_o = cis_sel ? data_o_tmp : (dpi_mode == 2'b01 ? data_o_200dpi : data_o_tmp);
+//assign dval_o = cis_sel ? dval_o_tmp : (dpi_mode == 2'b01 ? dval_o_200dpi : dval_o_tmp);
+
+//assign debug[0] = cis_sel;
endmodule
diff --git a/src/hg_mp/fe/sort_rev.v b/src/hg_mp/fe/sort_rev.v
index 84425e1..c14c399 100644
--- a/src/hg_mp/fe/sort_rev.v
+++ b/src/hg_mp/fe/sort_rev.v
@@ -17,8 +17,8 @@ module sort_rev
input [1 : 0] dpi_mode ,
input cis_mode ,
input [YPIXEL_WIDTH-1: 0] y_pixel ,
- output [23: 0] data_o ,
- output dval_o ,
+ output reg [23: 0] data_o ,
+ output reg dval_o ,
output fe_done ,
input rd_done ,
output wren,
@@ -349,8 +349,9 @@ data_prebuffer_rev u_data_prebuffer_rev
(
.FIFO_rdclk (wrclk),//frequency equal to dataclk_ADCx
.rst_n (reset_n),
+ .soft_n (sync_rdsoft_n),
.DPIset (dpi_mode),
- .dataclk_ADC (wrclk),
+ .dataclk_ADC (wrclk),
.dataA_ADC (ch25_1d),
.dataB_ADC (ch14_1d),
.dataC_ADC (ch03_1d),
@@ -447,7 +448,26 @@ begin
end
-assign data_o = cis_sel ? data_o_tmp_1d : (dpi_mode == 2'b01 ? data_o_200dpi_d1 : data_o_tmp_1d);
-assign dval_o = cis_sel ? dval_o_tmp_1d : (dpi_mode == 2'b01 ? dval_o_200dpi_d1 : dval_o_tmp_1d);
+
+ always @ (posedge rdclk )
+begin
+ if(!reset_n) data_o <= 24'b0;
+ else if (~sync_rdsoft_n) data_o <= 24'b0;
+ else if (cis_sel) data_o <= data_o_tmp;
+ else if (dpi_mode == 2'b01) data_o <= data_o_200dpi;
+ else data_o <= data_o_tmp;
+end
+
+ always @ (posedge rdclk )
+begin
+ if(!reset_n) dval_o <= 1'b0;
+ else if (~sync_rdsoft_n) dval_o <= 1'b0;
+ else if (cis_sel) dval_o <= dval_o_tmp;
+ else if (dpi_mode == 2'b01) dval_o <= dval_o_200dpi;
+ else dval_o <= dval_o_tmp;
+end
+
+//assign data_o = cis_sel ? data_o_tmp_1d : (dpi_mode == 2'b01 ? data_o_200dpi_d1 : data_o_tmp_1d);
+//assign dval_o = cis_sel ? dval_o_tmp_1d : (dpi_mode == 2'b01 ? dval_o_200dpi_d1 : dval_o_tmp_1d);
endmodule
diff --git a/src/prj/td_project/hg_anlogic.adc b/src/prj/td_project/hg_anlogic.adc
index 0c6d798..c449a69 100644
--- a/src/prj/td_project/hg_anlogic.adc
+++ b/src/prj/td_project/hg_anlogic.adc
@@ -13,28 +13,28 @@ set_pin_assignment { O_data_lp_p[0] } { LOCATION = P63; IOSTANDARD = LVCMOS25; D
set_pin_assignment { O_data_lp_p[1] } { LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; }
set_pin_assignment { O_data_lp_p[2] } { LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; }
set_pin_assignment { O_data_lp_p[3] } { LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; }
-set_pin_assignment { b_ad_sck } { LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
-set_pin_assignment { b_ad_sdi } { LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
-set_pin_assignment { b_ad_sdo } { LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
-set_pin_assignment { b_ad_sen } { LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
-set_pin_assignment { b_lvds_clk_p } { LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { b_lvds_data_p[0] } { LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { b_lvds_data_p[1] } { LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { b_lvds_data_p[2] } { LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { b_lvds_data_p[3] } { LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { b_lvds_data_p[4] } { LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { a_ad_sck } { LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
+set_pin_assignment { a_ad_sdi } { LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
+set_pin_assignment { a_ad_sdo } { LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
+set_pin_assignment { a_ad_sen } { LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
+set_pin_assignment { a_lvds_clk_p } { LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { a_lvds_data_p[0] } { LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { a_lvds_data_p[1] } { LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { a_lvds_data_p[2] } { LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { a_lvds_data_p[3] } { LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { a_lvds_data_p[4] } { LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { b_sp_pad } { LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
-set_pin_assignment { a_ad_sck } { LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
-set_pin_assignment { a_ad_sdi } { LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
-set_pin_assignment { a_ad_sdo } { LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
-set_pin_assignment { a_ad_sen } { LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
-set_pin_assignment { a_lvds_clk_p } { LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { a_lvds_data_p[0] } { LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { a_lvds_data_p[1] } { LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { a_lvds_data_p[2] } { LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { a_lvds_data_p[3] } { LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { a_lvds_data_p[4] } { LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { a_sp_pad } { LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
+set_pin_assignment { b_ad_sck } { LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
+set_pin_assignment { b_ad_sdi } { LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
+set_pin_assignment { b_ad_sdo } { LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
+set_pin_assignment { b_ad_sen } { LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
+set_pin_assignment { b_lvds_clk_p } { LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { b_lvds_data_p[0] } { LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { b_lvds_data_p[1] } { LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { b_lvds_data_p[2] } { LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { b_lvds_data_p[3] } { LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { b_lvds_data_p[4] } { LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { b_sp_pad } { LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { clock_source } { LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
set_pin_assignment { debug[0] } { LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { debug[1] } { LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240218_174629.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240218_174629.log
new file mode 100644
index 0000000..01d6271
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240218_174629.log
@@ -0,0 +1,1870 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sun Feb 18 17:46:29 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.138821s wall, 1.984375s user + 0.140625s system = 2.125000s CPU (99.4%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 315 MB, peak memory is 341 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (3047 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2213 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2053 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17769 instances
+RUN-0007 : 7403 luts, 9143 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20347 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13281 nets have 2 pins
+RUN-1001 : 5798 nets have [3 - 5] pins
+RUN-1001 : 853 nets have [6 - 10] pins
+RUN-1001 : 158 nets have [11 - 20] pins
+RUN-1001 : 183 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 1968
+RUN-1001 : No | Yes | No | 3573
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17767 instances, 7403 luts, 9143 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 5947 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84881, tnet num: 20169, tinst num: 17767, tnode num: 115265, tedge num: 136154.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.149395s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (99.2%)
+
+RUN-1004 : used memory is 530 MB, reserved memory is 514 MB, peak memory is 530 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20169 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.939376s wall, 1.906250s user + 0.031250s system = 1.937500s CPU (99.9%)
+
+PHY-3001 : Found 1230 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.162e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17767.
+PHY-3001 : Level 1 #clusters 2054.
+PHY-3001 : End clustering; 0.132925s wall, 0.125000s user + 0.015625s system = 0.140625s CPU (105.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.2853e+06, overlap = 501.75
+PHY-3002 : Step(2): len = 1.233e+06, overlap = 469.219
+PHY-3002 : Step(3): len = 860875, overlap = 551.938
+PHY-3002 : Step(4): len = 719918, overlap = 658.406
+PHY-3002 : Step(5): len = 583289, overlap = 805.312
+PHY-3002 : Step(6): len = 547271, overlap = 900.656
+PHY-3002 : Step(7): len = 445745, overlap = 981.406
+PHY-3002 : Step(8): len = 405493, overlap = 1019.38
+PHY-3002 : Step(9): len = 363117, overlap = 1091.91
+PHY-3002 : Step(10): len = 329304, overlap = 1121.38
+PHY-3002 : Step(11): len = 303188, overlap = 1163.59
+PHY-3002 : Step(12): len = 272148, overlap = 1217.34
+PHY-3002 : Step(13): len = 248433, overlap = 1257.53
+PHY-3002 : Step(14): len = 227908, overlap = 1301.97
+PHY-3002 : Step(15): len = 207003, overlap = 1343.69
+PHY-3002 : Step(16): len = 193622, overlap = 1379.62
+PHY-3002 : Step(17): len = 180002, overlap = 1401
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.01622e-06
+PHY-3002 : Step(18): len = 182123, overlap = 1383.91
+PHY-3002 : Step(19): len = 215230, overlap = 1282.84
+PHY-3002 : Step(20): len = 213239, overlap = 1212.84
+PHY-3002 : Step(21): len = 214006, overlap = 1148.56
+PHY-3002 : Step(22): len = 208086, overlap = 1113.41
+PHY-3002 : Step(23): len = 205609, overlap = 1106.66
+PHY-3002 : Step(24): len = 198673, overlap = 1133.22
+PHY-3002 : Step(25): len = 198088, overlap = 1150.72
+PHY-3002 : Step(26): len = 191867, overlap = 1174.03
+PHY-3002 : Step(27): len = 191372, overlap = 1164.56
+PHY-3002 : Step(28): len = 185205, overlap = 1167.16
+PHY-3002 : Step(29): len = 183794, overlap = 1153.84
+PHY-3002 : Step(30): len = 179516, overlap = 1161.16
+PHY-3002 : Step(31): len = 179972, overlap = 1168.62
+PHY-3002 : Step(32): len = 177866, overlap = 1180.72
+PHY-3002 : Step(33): len = 177665, overlap = 1172.19
+PHY-3002 : Step(34): len = 176471, overlap = 1150.62
+PHY-3002 : Step(35): len = 177086, overlap = 1141.09
+PHY-3002 : Step(36): len = 174891, overlap = 1137.72
+PHY-3002 : Step(37): len = 174895, overlap = 1142.38
+PHY-3002 : Step(38): len = 173254, overlap = 1160.41
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.03243e-06
+PHY-3002 : Step(39): len = 176582, overlap = 1136.91
+PHY-3002 : Step(40): len = 187650, overlap = 1113.09
+PHY-3002 : Step(41): len = 192783, overlap = 1090.03
+PHY-3002 : Step(42): len = 197628, overlap = 1048.94
+PHY-3002 : Step(43): len = 200604, overlap = 1020.94
+PHY-3002 : Step(44): len = 203361, overlap = 1007.66
+PHY-3002 : Step(45): len = 204008, overlap = 1005.91
+PHY-3002 : Step(46): len = 204597, overlap = 996.969
+PHY-3002 : Step(47): len = 203418, overlap = 981.406
+PHY-3002 : Step(48): len = 203197, overlap = 991.688
+PHY-3002 : Step(49): len = 200899, overlap = 1001.72
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.06487e-06
+PHY-3002 : Step(50): len = 207065, overlap = 989.688
+PHY-3002 : Step(51): len = 219903, overlap = 990.594
+PHY-3002 : Step(52): len = 224752, overlap = 957.875
+PHY-3002 : Step(53): len = 233321, overlap = 881.219
+PHY-3002 : Step(54): len = 238408, overlap = 869.781
+PHY-3002 : Step(55): len = 242097, overlap = 861
+PHY-3002 : Step(56): len = 244616, overlap = 860.625
+PHY-3002 : Step(57): len = 245490, overlap = 849.469
+PHY-3002 : Step(58): len = 245546, overlap = 838.688
+PHY-3002 : Step(59): len = 244641, overlap = 849.625
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.12974e-06
+PHY-3002 : Step(60): len = 257236, overlap = 815.781
+PHY-3002 : Step(61): len = 276206, overlap = 735.906
+PHY-3002 : Step(62): len = 284785, overlap = 649.562
+PHY-3002 : Step(63): len = 290937, overlap = 608.375
+PHY-3002 : Step(64): len = 292232, overlap = 599.312
+PHY-3002 : Step(65): len = 293835, overlap = 586.625
+PHY-3002 : Step(66): len = 293272, overlap = 587.031
+PHY-3002 : Step(67): len = 294183, overlap = 575.75
+PHY-3002 : Step(68): len = 293786, overlap = 564.062
+PHY-3002 : Step(69): len = 294159, overlap = 569.812
+PHY-3002 : Step(70): len = 292371, overlap = 572.062
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.62595e-05
+PHY-3002 : Step(71): len = 308152, overlap = 529.469
+PHY-3002 : Step(72): len = 324083, overlap = 474.219
+PHY-3002 : Step(73): len = 330239, overlap = 428.875
+PHY-3002 : Step(74): len = 332632, overlap = 417.375
+PHY-3002 : Step(75): len = 331827, overlap = 398.438
+PHY-3002 : Step(76): len = 333036, overlap = 415.344
+PHY-3002 : Step(77): len = 333241, overlap = 415.375
+PHY-3002 : Step(78): len = 334598, overlap = 392.188
+PHY-3002 : Step(79): len = 335117, overlap = 396.188
+PHY-3002 : Step(80): len = 335973, overlap = 370.812
+PHY-3002 : Step(81): len = 336666, overlap = 368.406
+PHY-3002 : Step(82): len = 337453, overlap = 366.969
+PHY-3002 : Step(83): len = 337352, overlap = 364.5
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.2519e-05
+PHY-3002 : Step(84): len = 353737, overlap = 332.438
+PHY-3002 : Step(85): len = 368321, overlap = 322.156
+PHY-3002 : Step(86): len = 372663, overlap = 315.469
+PHY-3002 : Step(87): len = 376855, overlap = 323.125
+PHY-3002 : Step(88): len = 375407, overlap = 323.094
+PHY-3002 : Step(89): len = 377631, overlap = 325.906
+PHY-3002 : Step(90): len = 377836, overlap = 319.875
+PHY-3002 : Step(91): len = 379162, overlap = 321.25
+PHY-3002 : Step(92): len = 378277, overlap = 329.656
+PHY-3002 : Step(93): len = 378834, overlap = 331.25
+PHY-3002 : Step(94): len = 378077, overlap = 316.281
+PHY-3002 : Step(95): len = 378669, overlap = 318
+PHY-3002 : Step(96): len = 378190, overlap = 323.812
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.50379e-05
+PHY-3002 : Step(97): len = 393412, overlap = 301.406
+PHY-3002 : Step(98): len = 405320, overlap = 269.969
+PHY-3002 : Step(99): len = 406795, overlap = 259.125
+PHY-3002 : Step(100): len = 406852, overlap = 268.406
+PHY-3002 : Step(101): len = 408509, overlap = 257.281
+PHY-3002 : Step(102): len = 410743, overlap = 259.875
+PHY-3002 : Step(103): len = 410466, overlap = 254.844
+PHY-3002 : Step(104): len = 412300, overlap = 251.438
+PHY-3002 : Step(105): len = 413900, overlap = 249.656
+PHY-3002 : Step(106): len = 416003, overlap = 233.906
+PHY-3002 : Step(107): len = 415469, overlap = 241.875
+PHY-3002 : Step(108): len = 416695, overlap = 243
+PHY-3002 : Step(109): len = 415844, overlap = 245.438
+PHY-3002 : Step(110): len = 416275, overlap = 248.188
+PHY-3002 : Step(111): len = 414899, overlap = 248.094
+PHY-3002 : Step(112): len = 415219, overlap = 252.594
+PHY-3002 : Step(113): len = 416520, overlap = 246.625
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000130076
+PHY-3002 : Step(114): len = 428910, overlap = 239.75
+PHY-3002 : Step(115): len = 438462, overlap = 228.188
+PHY-3002 : Step(116): len = 437215, overlap = 221.719
+PHY-3002 : Step(117): len = 438682, overlap = 220.844
+PHY-3002 : Step(118): len = 441592, overlap = 212.094
+PHY-3002 : Step(119): len = 443717, overlap = 204.562
+PHY-3002 : Step(120): len = 441387, overlap = 212.625
+PHY-3002 : Step(121): len = 441784, overlap = 205.375
+PHY-3002 : Step(122): len = 443545, overlap = 197.031
+PHY-3002 : Step(123): len = 445907, overlap = 190.031
+PHY-3002 : Step(124): len = 443828, overlap = 195.719
+PHY-3002 : Step(125): len = 443543, overlap = 199.312
+PHY-3002 : Step(126): len = 445067, overlap = 188.656
+PHY-3002 : Step(127): len = 447541, overlap = 188.094
+PHY-3002 : Step(128): len = 445886, overlap = 181.125
+PHY-3002 : Step(129): len = 445614, overlap = 183.562
+PHY-3002 : Step(130): len = 446731, overlap = 180.125
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000260152
+PHY-3002 : Step(131): len = 454313, overlap = 179
+PHY-3002 : Step(132): len = 464242, overlap = 187.344
+PHY-3002 : Step(133): len = 466413, overlap = 172.094
+PHY-3002 : Step(134): len = 468003, overlap = 174.281
+PHY-3002 : Step(135): len = 469917, overlap = 166.219
+PHY-3002 : Step(136): len = 471784, overlap = 162.812
+PHY-3002 : Step(137): len = 470447, overlap = 164.906
+PHY-3002 : Step(138): len = 470947, overlap = 158.594
+PHY-3002 : Step(139): len = 473691, overlap = 158.125
+PHY-3002 : Step(140): len = 475465, overlap = 156.281
+PHY-3002 : Step(141): len = 473479, overlap = 158.812
+PHY-3002 : Step(142): len = 473249, overlap = 158.875
+PHY-3002 : Step(143): len = 475915, overlap = 156.438
+PHY-3002 : Step(144): len = 478350, overlap = 160
+PHY-3002 : Step(145): len = 475911, overlap = 159.688
+PHY-3002 : Step(146): len = 475266, overlap = 157.969
+PHY-3002 : Step(147): len = 476320, overlap = 158.312
+PHY-3002 : Step(148): len = 477685, overlap = 168.75
+PHY-3002 : Step(149): len = 476374, overlap = 164.125
+PHY-3002 : Step(150): len = 476534, overlap = 157.875
+PHY-3002 : Step(151): len = 477767, overlap = 166.375
+PHY-3002 : Step(152): len = 478268, overlap = 167.906
+PHY-3002 : Step(153): len = 477116, overlap = 168.625
+PHY-3002 : Step(154): len = 477032, overlap = 168.906
+PHY-3002 : Step(155): len = 478102, overlap = 167.562
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000508611
+PHY-3002 : Step(156): len = 484627, overlap = 159.656
+PHY-3002 : Step(157): len = 491655, overlap = 150.875
+PHY-3002 : Step(158): len = 492113, overlap = 156.875
+PHY-3002 : Step(159): len = 492847, overlap = 157.562
+PHY-3002 : Step(160): len = 494864, overlap = 158.5
+PHY-3002 : Step(161): len = 496276, overlap = 156.312
+PHY-3002 : Step(162): len = 496447, overlap = 145.906
+PHY-3002 : Step(163): len = 496616, overlap = 150.062
+PHY-3002 : Step(164): len = 497328, overlap = 154.25
+PHY-3002 : Step(165): len = 497891, overlap = 153.938
+PHY-3002 : Step(166): len = 497881, overlap = 160.406
+PHY-3002 : Step(167): len = 498217, overlap = 155.781
+PHY-3002 : Step(168): len = 499724, overlap = 157.188
+PHY-3002 : Step(169): len = 500745, overlap = 160.719
+PHY-3002 : Step(170): len = 499938, overlap = 160.406
+PHY-3002 : Step(171): len = 499824, overlap = 160.094
+PHY-3002 : Step(172): len = 499733, overlap = 156.938
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000916394
+PHY-3002 : Step(173): len = 503790, overlap = 157.219
+PHY-3002 : Step(174): len = 509995, overlap = 151.281
+PHY-3002 : Step(175): len = 511465, overlap = 152.688
+PHY-3002 : Step(176): len = 512336, overlap = 152.656
+PHY-3002 : Step(177): len = 513141, overlap = 151.344
+PHY-3002 : Step(178): len = 513594, overlap = 151.406
+PHY-3002 : Step(179): len = 514035, overlap = 148.406
+PHY-3002 : Step(180): len = 514863, overlap = 149.594
+PHY-3002 : Step(181): len = 515914, overlap = 151.781
+PHY-3002 : Step(182): len = 516409, overlap = 157.781
+PHY-3002 : Step(183): len = 516533, overlap = 156.438
+PHY-3002 : Step(184): len = 516784, overlap = 157
+PHY-3002 : Step(185): len = 517366, overlap = 155.375
+PHY-3002 : Step(186): len = 517825, overlap = 155
+PHY-3002 : Step(187): len = 517802, overlap = 155.688
+PHY-3002 : Step(188): len = 517765, overlap = 151.812
+PHY-3002 : Step(189): len = 517513, overlap = 154.312
+PHY-3002 : Step(190): len = 517781, overlap = 149.719
+PHY-3002 : Step(191): len = 518451, overlap = 154.156
+PHY-3002 : Step(192): len = 518451, overlap = 154.156
+PHY-3002 : Step(193): len = 518408, overlap = 152.531
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.014167s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (110.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20347.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 682472, over cnt = 1568(4%), over = 7348, worst = 60
+PHY-1001 : End global iterations; 0.699928s wall, 0.921875s user + 0.046875s system = 0.968750s CPU (138.4%)
+
+PHY-1001 : Congestion index: top1 = 79.31, top5 = 61.39, top10 = 52.06, top15 = 46.55.
+PHY-3001 : End congestion estimation; 0.940253s wall, 1.140625s user + 0.062500s system = 1.203125s CPU (128.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20169 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.869199s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (98.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00012332
+PHY-3002 : Step(194): len = 623999, overlap = 94.5312
+PHY-3002 : Step(195): len = 626420, overlap = 92.8125
+PHY-3002 : Step(196): len = 619917, overlap = 87.4688
+PHY-3002 : Step(197): len = 613919, overlap = 88.3125
+PHY-3002 : Step(198): len = 612227, overlap = 77.625
+PHY-3002 : Step(199): len = 612245, overlap = 68.3438
+PHY-3002 : Step(200): len = 610809, overlap = 62.6562
+PHY-3002 : Step(201): len = 609693, overlap = 61.125
+PHY-3002 : Step(202): len = 609501, overlap = 60.7188
+PHY-3002 : Step(203): len = 610090, overlap = 58.7188
+PHY-3002 : Step(204): len = 609053, overlap = 55.9375
+PHY-3002 : Step(205): len = 608203, overlap = 54
+PHY-3002 : Step(206): len = 608024, overlap = 50.2812
+PHY-3002 : Step(207): len = 607896, overlap = 46.375
+PHY-3002 : Step(208): len = 607617, overlap = 41.9688
+PHY-3002 : Step(209): len = 608120, overlap = 34.3125
+PHY-3002 : Step(210): len = 608539, overlap = 27.875
+PHY-3002 : Step(211): len = 608209, overlap = 30.875
+PHY-3002 : Step(212): len = 607981, overlap = 29.1875
+PHY-3002 : Step(213): len = 607724, overlap = 30.5
+PHY-3002 : Step(214): len = 607431, overlap = 30.3125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000246641
+PHY-3002 : Step(215): len = 608700, overlap = 29.4688
+PHY-3002 : Step(216): len = 611354, overlap = 30.1562
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 147/20347.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 693304, over cnt = 2596(7%), over = 11544, worst = 74
+PHY-1001 : End global iterations; 1.603136s wall, 2.093750s user + 0.015625s system = 2.109375s CPU (131.6%)
+
+PHY-1001 : Congestion index: top1 = 83.19, top5 = 65.81, top10 = 57.01, top15 = 51.64.
+PHY-3001 : End congestion estimation; 1.866422s wall, 2.343750s user + 0.031250s system = 2.375000s CPU (127.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20169 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.900602s wall, 0.859375s user + 0.046875s system = 0.906250s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.21639e-05
+PHY-3002 : Step(217): len = 611065, overlap = 291.625
+PHY-3002 : Step(218): len = 617614, overlap = 232.812
+PHY-3002 : Step(219): len = 615889, overlap = 218.75
+PHY-3002 : Step(220): len = 612069, overlap = 208.562
+PHY-3002 : Step(221): len = 611948, overlap = 190.719
+PHY-3002 : Step(222): len = 612999, overlap = 188.062
+PHY-3002 : Step(223): len = 609435, overlap = 183.031
+PHY-3002 : Step(224): len = 607576, overlap = 179.281
+PHY-3002 : Step(225): len = 605266, overlap = 167.25
+PHY-3002 : Step(226): len = 603976, overlap = 167.938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000184328
+PHY-3002 : Step(227): len = 604636, overlap = 160.531
+PHY-3002 : Step(228): len = 607725, overlap = 151.688
+PHY-3002 : Step(229): len = 610005, overlap = 144.938
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000368656
+PHY-3002 : Step(230): len = 615061, overlap = 135.406
+PHY-3002 : Step(231): len = 624467, overlap = 114.781
+PHY-3002 : Step(232): len = 629080, overlap = 107.719
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84881, tnet num: 20169, tinst num: 17767, tnode num: 115265, tedge num: 136154.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.498061s wall, 1.406250s user + 0.093750s system = 1.500000s CPU (100.1%)
+
+RUN-1004 : used memory is 573 MB, reserved memory is 562 MB, peak memory is 709 MB
+OPT-1001 : Total overflow 445.22 peak overflow 3.72
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1476/20347.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 727144, over cnt = 3002(8%), over = 11122, worst = 33
+PHY-1001 : End global iterations; 1.153802s wall, 1.750000s user + 0.015625s system = 1.765625s CPU (153.0%)
+
+PHY-1001 : Congestion index: top1 = 71.51, top5 = 57.60, top10 = 51.43, top15 = 47.67.
+PHY-1001 : End incremental global routing; 1.490939s wall, 2.093750s user + 0.015625s system = 2.109375s CPU (141.5%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20169 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.925065s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (99.7%)
+
+OPT-1001 : 52 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17630 has valid locations, 342 needs to be replaced
+PHY-3001 : design contains 18057 instances, 7507 luts, 9329 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 6075 pins
+PHY-3001 : Found 1242 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 652248
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16683/20637.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 739360, over cnt = 3019(8%), over = 11163, worst = 32
+PHY-1001 : End global iterations; 0.244510s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (108.6%)
+
+PHY-1001 : Congestion index: top1 = 72.13, top5 = 58.10, top10 = 51.76, top15 = 47.97.
+PHY-3001 : End congestion estimation; 0.505816s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (101.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86051, tnet num: 20459, tinst num: 18057, tnode num: 117015, tedge num: 137914.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.479877s wall, 1.406250s user + 0.078125s system = 1.484375s CPU (100.3%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 622 MB, peak memory is 712 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20459 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.449831s wall, 2.375000s user + 0.078125s system = 2.453125s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(233): len = 651090, overlap = 0.875
+PHY-3002 : Step(234): len = 650852, overlap = 0.8125
+PHY-3002 : Step(235): len = 650797, overlap = 0.9375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16798/20637.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 737136, over cnt = 3035(8%), over = 11247, worst = 33
+PHY-1001 : End global iterations; 0.199223s wall, 0.328125s user + 0.015625s system = 0.343750s CPU (172.5%)
+
+PHY-1001 : Congestion index: top1 = 71.92, top5 = 58.26, top10 = 51.91, top15 = 48.13.
+PHY-3001 : End congestion estimation; 0.458343s wall, 0.578125s user + 0.015625s system = 0.593750s CPU (129.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20459 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.945735s wall, 0.921875s user + 0.031250s system = 0.953125s CPU (100.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000343529
+PHY-3002 : Step(236): len = 650596, overlap = 110.062
+PHY-3002 : Step(237): len = 650728, overlap = 110.062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000687057
+PHY-3002 : Step(238): len = 650800, overlap = 110.375
+PHY-3002 : Step(239): len = 651471, overlap = 110.562
+PHY-3001 : Final: Len = 651471, Over = 110.562
+PHY-3001 : End incremental placement; 5.063500s wall, 5.546875s user + 0.250000s system = 5.796875s CPU (114.5%)
+
+OPT-1001 : Total overflow 451.06 peak overflow 3.72
+OPT-1001 : End high-fanout net optimization; 8.109533s wall, 9.250000s user + 0.265625s system = 9.515625s CPU (117.3%)
+
+OPT-1001 : Current memory(MB): used = 715, reserve = 709, peak = 732.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16748/20637.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 740304, over cnt = 2976(8%), over = 10280, worst = 31
+PHY-1002 : len = 797744, over cnt = 2050(5%), over = 4998, worst = 28
+PHY-1002 : len = 833368, over cnt = 1040(2%), over = 2255, worst = 20
+PHY-1002 : len = 860352, over cnt = 318(0%), over = 652, worst = 14
+PHY-1002 : len = 871312, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.753485s wall, 2.515625s user + 0.031250s system = 2.546875s CPU (145.2%)
+
+PHY-1001 : Congestion index: top1 = 58.23, top5 = 50.65, top10 = 47.13, top15 = 44.75.
+OPT-1001 : End congestion update; 2.027732s wall, 2.796875s user + 0.031250s system = 2.828125s CPU (139.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20459 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.821821s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (100.8%)
+
+OPT-0007 : Start: WNS -1068 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 64 cells processed and 6700 slack improved
+OPT-0007 : Iter 2: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 13 cells processed and 1300 slack improved
+OPT-0007 : Iter 3: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 13 cells processed and 616 slack improved
+OPT-1001 : End global optimization; 2.895304s wall, 3.656250s user + 0.046875s system = 3.703125s CPU (127.9%)
+
+OPT-1001 : Current memory(MB): used = 692, reserve = 694, peak = 732.
+OPT-1001 : End physical optimization; 13.142629s wall, 15.000000s user + 0.437500s system = 15.437500s CPU (117.5%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7507 LUT to BLE ...
+SYN-4008 : Packed 7507 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6196 remaining SEQ's ...
+SYN-4005 : Packed 3622 SEQ with LUT/SLICE
+SYN-4006 : 1057 single LUT's are left
+SYN-4006 : 2574 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10081/13812 primitive instances ...
+PHY-3001 : End packing; 1.683568s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (100.2%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6931 instances
+RUN-1001 : 3392 mslices, 3391 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17634 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9975 nets have 2 pins
+RUN-1001 : 5997 nets have [3 - 5] pins
+RUN-1001 : 971 nets have [6 - 10] pins
+RUN-1001 : 311 nets have [11 - 20] pins
+RUN-1001 : 348 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6929 instances, 6783 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3567 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 661265, Over = 294.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7588/17634.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 816704, over cnt = 1966(5%), over = 3356, worst = 9
+PHY-1002 : len = 825624, over cnt = 1383(3%), over = 2102, worst = 8
+PHY-1002 : len = 843408, over cnt = 388(1%), over = 548, worst = 8
+PHY-1002 : len = 851880, over cnt = 41(0%), over = 44, worst = 2
+PHY-1002 : len = 853664, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.653912s wall, 2.359375s user + 0.031250s system = 2.390625s CPU (144.5%)
+
+PHY-1001 : Congestion index: top1 = 60.06, top5 = 51.85, top10 = 47.44, top15 = 44.70.
+PHY-3001 : End congestion estimation; 2.048236s wall, 2.750000s user + 0.031250s system = 2.781250s CPU (135.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73753, tnet num: 17456, tinst num: 6929, tnode num: 96323, tedge num: 123805.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.648881s wall, 1.625000s user + 0.015625s system = 1.640625s CPU (99.5%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 611 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17456 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.531108s wall, 2.515625s user + 0.015625s system = 2.531250s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.56714e-05
+PHY-3002 : Step(240): len = 649477, overlap = 291.5
+PHY-3002 : Step(241): len = 642662, overlap = 286.5
+PHY-3002 : Step(242): len = 638039, overlap = 278.25
+PHY-3002 : Step(243): len = 634973, overlap = 290
+PHY-3002 : Step(244): len = 633321, overlap = 295.75
+PHY-3002 : Step(245): len = 631879, overlap = 299.5
+PHY-3002 : Step(246): len = 631044, overlap = 301.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.13427e-05
+PHY-3002 : Step(247): len = 634717, overlap = 285.5
+PHY-3002 : Step(248): len = 638741, overlap = 273.75
+PHY-3002 : Step(249): len = 638599, overlap = 268
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000182685
+PHY-3002 : Step(250): len = 648101, overlap = 263.25
+PHY-3002 : Step(251): len = 658542, overlap = 248.5
+PHY-3002 : Step(252): len = 657720, overlap = 247.25
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000365371
+PHY-3002 : Step(253): len = 664776, overlap = 238.75
+PHY-3002 : Step(254): len = 679743, overlap = 231.5
+PHY-3002 : Step(255): len = 680538, overlap = 218.5
+PHY-3002 : Step(256): len = 679051, overlap = 211.75
+PHY-3002 : Step(257): len = 679003, overlap = 208.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.388369s wall, 0.328125s user + 0.609375s system = 0.937500s CPU (241.4%)
+
+PHY-3001 : Trial Legalized: Len = 756387
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 756/17634.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 876544, over cnt = 2698(7%), over = 4584, worst = 8
+PHY-1002 : len = 893224, over cnt = 1620(4%), over = 2408, worst = 7
+PHY-1002 : len = 912488, over cnt = 602(1%), over = 875, worst = 6
+PHY-1002 : len = 923440, over cnt = 127(0%), over = 189, worst = 5
+PHY-1002 : len = 926264, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations; 2.484192s wall, 3.781250s user + 0.031250s system = 3.812500s CPU (153.5%)
+
+PHY-1001 : Congestion index: top1 = 55.09, top5 = 49.67, top10 = 46.80, top15 = 44.91.
+PHY-3001 : End congestion estimation; 2.972456s wall, 4.265625s user + 0.031250s system = 4.296875s CPU (144.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17456 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.861108s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (101.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000167586
+PHY-3002 : Step(258): len = 729049, overlap = 40.75
+PHY-3002 : Step(259): len = 712627, overlap = 61.25
+PHY-3002 : Step(260): len = 698364, overlap = 92
+PHY-3002 : Step(261): len = 688041, overlap = 120
+PHY-3002 : Step(262): len = 681416, overlap = 143.75
+PHY-3002 : Step(263): len = 676841, overlap = 171.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000335172
+PHY-3002 : Step(264): len = 681856, overlap = 161
+PHY-3002 : Step(265): len = 685823, overlap = 154.5
+PHY-3002 : Step(266): len = 686234, overlap = 151.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000625275
+PHY-3002 : Step(267): len = 689985, overlap = 152
+PHY-3002 : Step(268): len = 697033, overlap = 142.25
+PHY-3002 : Step(269): len = 704808, overlap = 137.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.035670s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (87.6%)
+
+PHY-3001 : Legalized: Len = 734778, Over = 0
+PHY-3001 : Spreading special nets. 426 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.109103s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (100.2%)
+
+PHY-3001 : 621 instances has been re-located, deltaX = 223, deltaY = 383, maxDist = 7.
+PHY-3001 : Final: Len = 745354, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73753, tnet num: 17456, tinst num: 6932, tnode num: 96323, tedge num: 123805.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.874036s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (100.1%)
+
+RUN-1004 : used memory is 647 MB, reserved memory is 663 MB, peak memory is 732 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4554/17634.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 880784, over cnt = 2574(7%), over = 4090, worst = 7
+PHY-1002 : len = 894376, over cnt = 1488(4%), over = 2117, worst = 7
+PHY-1002 : len = 908568, over cnt = 669(1%), over = 908, worst = 7
+PHY-1002 : len = 919736, over cnt = 197(0%), over = 238, worst = 4
+PHY-1002 : len = 923504, over cnt = 9(0%), over = 10, worst = 2
+PHY-1001 : End global iterations; 1.830976s wall, 2.750000s user + 0.031250s system = 2.781250s CPU (151.9%)
+
+PHY-1001 : Congestion index: top1 = 54.55, top5 = 49.49, top10 = 46.55, top15 = 44.59.
+PHY-1001 : End incremental global routing; 2.218778s wall, 3.125000s user + 0.046875s system = 3.171875s CPU (143.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17456 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.889551s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (100.1%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6841 has valid locations, 13 needs to be replaced
+PHY-3001 : design contains 6942 instances, 6793 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3630 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 746167
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16081/17645.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 924104, over cnt = 57(0%), over = 61, worst = 3
+PHY-1002 : len = 924240, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 924264, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 924344, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 924376, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.799504s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (103.6%)
+
+PHY-1001 : Congestion index: top1 = 54.55, top5 = 49.47, top10 = 46.55, top15 = 44.60.
+PHY-3001 : End congestion estimation; 1.133306s wall, 1.140625s user + 0.015625s system = 1.156250s CPU (102.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73816, tnet num: 17467, tinst num: 6942, tnode num: 96403, tedge num: 123883.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.862263s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (100.7%)
+
+RUN-1004 : used memory is 731 MB, reserved memory is 734 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17467 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.751375s wall, 2.750000s user + 0.000000s system = 2.750000s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(270): len = 746171, overlap = 0
+PHY-3002 : Step(271): len = 746171, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16077/17645.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 924256, over cnt = 30(0%), over = 30, worst = 1
+PHY-1002 : len = 924296, over cnt = 16(0%), over = 16, worst = 1
+PHY-1002 : len = 924376, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 924456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.577945s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (110.8%)
+
+PHY-1001 : Congestion index: top1 = 54.55, top5 = 49.47, top10 = 46.54, top15 = 44.58.
+PHY-3001 : End congestion estimation; 0.898928s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (107.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17467 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.863281s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000577723
+PHY-3002 : Step(272): len = 746097, overlap = 0.75
+PHY-3002 : Step(273): len = 746097, overlap = 0.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005903s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (264.7%)
+
+PHY-3001 : Legalized: Len = 746095, Over = 0
+PHY-3001 : End spreading; 0.061408s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.8%)
+
+PHY-3001 : Final: Len = 746095, Over = 0
+PHY-3001 : End incremental placement; 6.152224s wall, 6.375000s user + 0.125000s system = 6.500000s CPU (105.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.774752s wall, 10.968750s user + 0.187500s system = 11.156250s CPU (114.1%)
+
+OPT-1001 : Current memory(MB): used = 747, reserve = 749, peak = 750.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16078/17645.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 924232, over cnt = 25(0%), over = 28, worst = 2
+PHY-1002 : len = 924216, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 924320, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 924320, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 924320, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.760884s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (102.7%)
+
+PHY-1001 : Congestion index: top1 = 54.55, top5 = 49.46, top10 = 46.54, top15 = 44.58.
+OPT-1001 : End congestion update; 1.094785s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (101.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17467 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.746848s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.4%)
+
+OPT-0007 : Start: WNS -1083 TNS -1668 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6854 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6942 instances, 6793 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3630 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 752163, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062527s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.0%)
+
+PHY-3001 : 16 instances has been re-located, deltaX = 20, deltaY = 3, maxDist = 3.
+PHY-3001 : Final: Len = 752299, Over = 0
+PHY-3001 : End incremental legalization; 0.401555s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (101.2%)
+
+OPT-0007 : Iter 1: improved WNS -1033 TNS -1568 NUM_FEPS 2 with 26 cells processed and 9750 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6854 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6942 instances, 6793 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3630 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 752327, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061431s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.7%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 5, deltaY = 1, maxDist = 2.
+PHY-3001 : Final: Len = 752367, Over = 0
+PHY-3001 : End incremental legalization; 0.400264s wall, 0.421875s user + 0.015625s system = 0.437500s CPU (109.3%)
+
+OPT-0007 : Iter 2: improved WNS -1033 TNS -1568 NUM_FEPS 2 with 8 cells processed and 650 slack improved
+OPT-1001 : End path based optimization; 2.907561s wall, 2.937500s user + 0.015625s system = 2.953125s CPU (101.6%)
+
+OPT-1001 : Current memory(MB): used = 747, reserve = 748, peak = 750.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17467 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.737164s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.6%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15962/17645.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 929896, over cnt = 88(0%), over = 100, worst = 3
+PHY-1002 : len = 929736, over cnt = 56(0%), over = 59, worst = 3
+PHY-1002 : len = 929896, over cnt = 40(0%), over = 41, worst = 2
+PHY-1002 : len = 930288, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 930576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.834826s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (110.4%)
+
+PHY-1001 : Congestion index: top1 = 55.47, top5 = 49.60, top10 = 46.55, top15 = 44.55.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17467 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.737338s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.6%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -1083 TNS -1668 NUM_FEPS 2
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 55.137931
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -1083ps with logic level 2
+RUN-1001 : #2 path slack -1047ps with logic level 2
+RUN-1001 : 0 HFN exist on timing critical paths out of 17645 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 17645 nets
+OPT-1001 : End physical optimization; 17.577628s wall, 18.875000s user + 0.218750s system = 19.093750s CPU (108.6%)
+
+RUN-1003 : finish command "place" in 58.909920s wall, 82.796875s user + 5.875000s system = 88.671875s CPU (150.5%)
+
+RUN-1004 : used memory is 652 MB, reserved memory is 644 MB, peak memory is 750 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.700811s wall, 2.953125s user + 0.015625s system = 2.968750s CPU (174.5%)
+
+RUN-1004 : used memory is 652 MB, reserved memory is 644 MB, peak memory is 750 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6944 instances
+RUN-1001 : 3395 mslices, 3398 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17645 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9978 nets have 2 pins
+RUN-1001 : 5997 nets have [3 - 5] pins
+RUN-1001 : 970 nets have [6 - 10] pins
+RUN-1001 : 314 nets have [11 - 20] pins
+RUN-1001 : 356 nets have [21 - 99] pins
+RUN-1001 : 10 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73816, tnet num: 17467, tinst num: 6942, tnode num: 96403, tedge num: 123883.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.608331s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.1%)
+
+RUN-1004 : used memory is 662 MB, reserved memory is 665 MB, peak memory is 750 MB
+PHY-1001 : 3395 mslices, 3398 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17467 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 860472, over cnt = 2755(7%), over = 4598, worst = 9
+PHY-1002 : len = 880168, over cnt = 1588(4%), over = 2277, worst = 7
+PHY-1002 : len = 898880, over cnt = 682(1%), over = 918, worst = 5
+PHY-1002 : len = 911264, over cnt = 67(0%), over = 85, worst = 4
+PHY-1002 : len = 912808, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.040559s wall, 4.109375s user + 0.015625s system = 4.125000s CPU (135.7%)
+
+PHY-1001 : Congestion index: top1 = 54.70, top5 = 49.15, top10 = 46.11, top15 = 44.16.
+PHY-1001 : End global routing; 3.372997s wall, 4.453125s user + 0.015625s system = 4.468750s CPU (132.5%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 717, reserve = 720, peak = 750.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 988, reserve = 991, peak = 988.
+PHY-1001 : End build detailed router design. 4.063946s wall, 4.015625s user + 0.046875s system = 4.062500s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 265192, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.336577s wall, 5.343750s user + 0.000000s system = 5.343750s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 265248, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.470499s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (99.6%)
+
+PHY-1001 : Current memory(MB): used = 1024, reserve = 1028, peak = 1024.
+PHY-1001 : End phase 1; 5.819551s wall, 5.812500s user + 0.000000s system = 5.812500s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.32329e+06, over cnt = 1821(0%), over = 1832, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1040, reserve = 1043, peak = 1040.
+PHY-1001 : End initial routed; 28.845648s wall, 60.859375s user + 0.453125s system = 61.312500s CPU (212.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16568(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.845 | -4.166 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.318824s wall, 3.312500s user + 0.000000s system = 3.312500s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1050, reserve = 1053, peak = 1050.
+PHY-1001 : End phase 2; 32.164536s wall, 64.171875s user + 0.453125s system = 64.625000s CPU (200.9%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -1.801ns STNS -4.118ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.146243s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.2%)
+
+PHY-1022 : len = 2.32329e+06, over cnt = 1824(0%), over = 1835, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.417890s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (101.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2904e+06, over cnt = 745(0%), over = 748, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.724167s wall, 2.796875s user + 0.000000s system = 2.796875s CPU (162.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.28829e+06, over cnt = 168(0%), over = 168, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.857975s wall, 1.312500s user + 0.000000s system = 1.312500s CPU (153.0%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.28979e+06, over cnt = 15(0%), over = 15, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.460764s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (118.7%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.28989e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.244563s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (102.2%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.28994e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.321443s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (102.1%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.28998e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.533387s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (102.5%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.28998e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.804058s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.1%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.28998e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.177346s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (96.9%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.28994e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.170902s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.28994e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.183833s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (102.0%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.28994e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.244372s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (102.3%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.28994e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.383408s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.8%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.28995e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.179264s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (113.3%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.28998e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.168021s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (102.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16568(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.801 | -4.118 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.437471s wall, 3.421875s user + 0.015625s system = 3.437500s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 521 feed throughs used by 383 nets
+PHY-1001 : End commit to database; 2.278330s wall, 2.265625s user + 0.015625s system = 2.281250s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1153, reserve = 1160, peak = 1153.
+PHY-1001 : End phase 3; 13.017591s wall, 14.609375s user + 0.031250s system = 14.640625s CPU (112.5%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.801ns STNS -4.118ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.143598s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (108.8%)
+
+PHY-1022 : len = 2.28998e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.483564s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (96.9%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.801ns, -4.118ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16568(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.801 | -4.118 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.333542s wall, 3.343750s user + 0.000000s system = 3.343750s CPU (100.3%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 521 feed throughs used by 383 nets
+PHY-1001 : End commit to database; 2.388696s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1162, reserve = 1169, peak = 1162.
+PHY-1001 : End phase 4; 6.234351s wall, 6.218750s user + 0.000000s system = 6.218750s CPU (99.7%)
+
+PHY-1003 : Routed, final wirelength = 2.28998e+06
+PHY-1001 : Current memory(MB): used = 1164, reserve = 1172, peak = 1164.
+PHY-1001 : End export database. 0.063938s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (122.2%)
+
+PHY-1001 : End detail routing; 61.768853s wall, 95.296875s user + 0.531250s system = 95.828125s CPU (155.1%)
+
+RUN-1003 : finish command "route" in 67.827364s wall, 102.421875s user + 0.562500s system = 102.984375s CPU (151.8%)
+
+RUN-1004 : used memory is 1091 MB, reserved memory is 1098 MB, peak memory is 1164 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10226 out of 19600 52.17%
+#reg 9465 out of 19600 48.29%
+#le 12733
+ #lut only 3268 out of 12733 25.67%
+ #reg only 2507 out of 12733 19.69%
+ #lut® 6958 out of 12733 54.65%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1848
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1403
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1315
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 948
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice a_frame_pad_d0_reg_syn_17.q0 140
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 68
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 25
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/reg9_syn_157.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg39_syn_205.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P143 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P17 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P133 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P16 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P109 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P88 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P32 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P35 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12733 |9199 |1027 |9497 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |555 |445 |23 |441 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |101 |82 |4 |89 |4 |0 |
+| U_crc16_24b |crc16_24b |29 |29 |0 |19 |0 |0 |
+| U_ecc_gen |ecc_gen |12 |12 |0 |7 |0 |0 |
+| exdev_ctl_a |exdev_ctl |792 |378 |96 |592 |0 |0 |
+| u_ADconfig |AD_config |199 |139 |25 |144 |0 |0 |
+| u_gen_sp |gen_sp |264 |156 |71 |119 |0 |0 |
+| exdev_ctl_b |exdev_ctl |743 |408 |96 |555 |0 |0 |
+| u_ADconfig |AD_config |176 |136 |25 |126 |0 |0 |
+| u_gen_sp |gen_sp |255 |167 |71 |117 |0 |0 |
+| sampling_fe_a |sampling_fe |3215 |2525 |306 |2112 |25 |0 |
+| u0_soft_n |cdc_sync |9 |9 |0 |9 |0 |0 |
+| u_ad_sampling |ad_sampling |175 |95 |17 |140 |0 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_sort |sort |3001 |2418 |289 |1933 |25 |0 |
+| rddpram_ctl |rddpram_ctl |5 |5 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |2 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |6 |3 |0 |6 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2515 |2087 |253 |1544 |22 |0 |
+| channelPart |channel_part_8478 |158 |155 |3 |140 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |42 |0 |0 |
+| ram_switch |ram_switch |1965 |1595 |197 |1128 |0 |0 |
+| adc_addr_gen |adc_addr_gen |211 |182 |27 |121 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |8 |3 |3 |4 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |21 |18 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |23 |20 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |10 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |15 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |28 |25 |3 |13 |0 |0 |
+| insert |insert |933 |592 |170 |634 |0 |0 |
+| ram_switch_state |ram_switch_state |821 |821 |0 |373 |0 |0 |
+| read_ram_i |read_ram |310 |265 |44 |210 |0 |0 |
+| read_ram_addr |read_ram_addr |218 |178 |40 |152 |0 |0 |
+| read_ram_data |read_ram_data |90 |86 |4 |56 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |346 |221 |36 |277 |3 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3347 |2619 |349 |2141 |25 |1 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_ad_sampling |ad_sampling |171 |125 |17 |133 |0 |0 |
+| u0_soft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_sort |sort_rev |3143 |2473 |332 |1975 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |3 |1 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |2 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2694 |2157 |290 |1591 |22 |1 |
+| channelPart |channel_part_8478 |240 |236 |3 |144 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
+| ram_switch |ram_switch |1940 |1524 |197 |1143 |0 |0 |
+| adc_addr_gen |adc_addr_gen |232 |205 |27 |112 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |8 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |9 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 |
+| insert |insert |995 |613 |170 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |713 |706 |0 |339 |0 |0 |
+| read_ram_i |read_ram_rev |431 |330 |81 |236 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |312 |229 |73 |168 |0 |0 |
+| read_ram_data |read_ram_data_rev |119 |101 |8 |68 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9916
+ #2 2 3864
+ #3 3 1477
+ #4 4 653
+ #5 5-10 1025
+ #6 11-50 591
+ #7 51-100 22
+ #8 101-500 1
+ #9 >500 1
+ Average 2.89
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.092928s wall, 3.593750s user + 0.015625s system = 3.609375s CPU (172.5%)
+
+RUN-1004 : used memory is 1092 MB, reserved memory is 1099 MB, peak memory is 1164 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73816, tnet num: 17467, tinst num: 6942, tnode num: 96403, tedge num: 123883.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.615915s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.6%)
+
+RUN-1004 : used memory is 1097 MB, reserved memory is 1104 MB, peak memory is 1164 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17467 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.495773s wall, 1.484375s user + 0.015625s system = 1.500000s CPU (100.3%)
+
+RUN-1004 : used memory is 1100 MB, reserved memory is 1107 MB, peak memory is 1164 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6942
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17645, pip num: 171568
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 521
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3247 valid insts, and 477628 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.875452s wall, 56.546875s user + 0.156250s system = 56.703125s CPU (574.2%)
+
+RUN-1004 : used memory is 1265 MB, reserved memory is 1268 MB, peak memory is 1380 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240218_174629.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240219_101011.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240219_101011.log
new file mode 100644
index 0000000..0ed6e97
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240219_101011.log
@@ -0,0 +1,1870 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Feb 19 10:10:11 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.187999s wall, 2.109375s user + 0.078125s system = 2.187500s CPU (100.0%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 315 MB, peak memory is 341 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (3047 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2213 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2053 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17769 instances
+RUN-0007 : 7403 luts, 9143 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20347 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13281 nets have 2 pins
+RUN-1001 : 5798 nets have [3 - 5] pins
+RUN-1001 : 853 nets have [6 - 10] pins
+RUN-1001 : 158 nets have [11 - 20] pins
+RUN-1001 : 183 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 1968
+RUN-1001 : No | Yes | No | 3573
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17767 instances, 7403 luts, 9143 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 5947 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84881, tnet num: 20169, tinst num: 17767, tnode num: 115265, tedge num: 136154.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.182757s wall, 1.109375s user + 0.078125s system = 1.187500s CPU (100.4%)
+
+RUN-1004 : used memory is 530 MB, reserved memory is 515 MB, peak memory is 530 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20169 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.991392s wall, 1.890625s user + 0.109375s system = 2.000000s CPU (100.4%)
+
+PHY-3001 : Found 1230 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.162e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17767.
+PHY-3001 : Level 1 #clusters 2054.
+PHY-3001 : End clustering; 0.137099s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (114.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.2853e+06, overlap = 501.75
+PHY-3002 : Step(2): len = 1.233e+06, overlap = 469.219
+PHY-3002 : Step(3): len = 860875, overlap = 551.938
+PHY-3002 : Step(4): len = 719918, overlap = 658.406
+PHY-3002 : Step(5): len = 583289, overlap = 805.312
+PHY-3002 : Step(6): len = 547271, overlap = 900.656
+PHY-3002 : Step(7): len = 445745, overlap = 981.406
+PHY-3002 : Step(8): len = 405493, overlap = 1019.38
+PHY-3002 : Step(9): len = 363117, overlap = 1091.91
+PHY-3002 : Step(10): len = 329304, overlap = 1121.38
+PHY-3002 : Step(11): len = 303188, overlap = 1163.59
+PHY-3002 : Step(12): len = 272148, overlap = 1217.34
+PHY-3002 : Step(13): len = 248433, overlap = 1257.53
+PHY-3002 : Step(14): len = 227908, overlap = 1301.97
+PHY-3002 : Step(15): len = 207003, overlap = 1343.69
+PHY-3002 : Step(16): len = 193622, overlap = 1379.62
+PHY-3002 : Step(17): len = 180002, overlap = 1401
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.01622e-06
+PHY-3002 : Step(18): len = 182123, overlap = 1383.91
+PHY-3002 : Step(19): len = 215230, overlap = 1282.84
+PHY-3002 : Step(20): len = 213239, overlap = 1212.84
+PHY-3002 : Step(21): len = 214006, overlap = 1148.56
+PHY-3002 : Step(22): len = 208086, overlap = 1113.41
+PHY-3002 : Step(23): len = 205609, overlap = 1106.66
+PHY-3002 : Step(24): len = 198673, overlap = 1133.22
+PHY-3002 : Step(25): len = 198088, overlap = 1150.72
+PHY-3002 : Step(26): len = 191867, overlap = 1174.03
+PHY-3002 : Step(27): len = 191372, overlap = 1164.56
+PHY-3002 : Step(28): len = 185205, overlap = 1167.16
+PHY-3002 : Step(29): len = 183794, overlap = 1153.84
+PHY-3002 : Step(30): len = 179516, overlap = 1161.16
+PHY-3002 : Step(31): len = 179972, overlap = 1168.62
+PHY-3002 : Step(32): len = 177866, overlap = 1180.72
+PHY-3002 : Step(33): len = 177665, overlap = 1172.19
+PHY-3002 : Step(34): len = 176471, overlap = 1150.62
+PHY-3002 : Step(35): len = 177086, overlap = 1141.09
+PHY-3002 : Step(36): len = 174891, overlap = 1137.72
+PHY-3002 : Step(37): len = 174895, overlap = 1142.38
+PHY-3002 : Step(38): len = 173254, overlap = 1160.41
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.03243e-06
+PHY-3002 : Step(39): len = 176582, overlap = 1136.91
+PHY-3002 : Step(40): len = 187650, overlap = 1113.09
+PHY-3002 : Step(41): len = 192783, overlap = 1090.03
+PHY-3002 : Step(42): len = 197628, overlap = 1048.94
+PHY-3002 : Step(43): len = 200604, overlap = 1020.94
+PHY-3002 : Step(44): len = 203361, overlap = 1007.66
+PHY-3002 : Step(45): len = 204008, overlap = 1005.91
+PHY-3002 : Step(46): len = 204597, overlap = 996.969
+PHY-3002 : Step(47): len = 203418, overlap = 981.406
+PHY-3002 : Step(48): len = 203197, overlap = 991.688
+PHY-3002 : Step(49): len = 200899, overlap = 1001.72
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.06487e-06
+PHY-3002 : Step(50): len = 207065, overlap = 989.688
+PHY-3002 : Step(51): len = 219903, overlap = 990.594
+PHY-3002 : Step(52): len = 224752, overlap = 957.875
+PHY-3002 : Step(53): len = 233321, overlap = 881.219
+PHY-3002 : Step(54): len = 238408, overlap = 869.781
+PHY-3002 : Step(55): len = 242097, overlap = 861
+PHY-3002 : Step(56): len = 244616, overlap = 860.625
+PHY-3002 : Step(57): len = 245490, overlap = 849.469
+PHY-3002 : Step(58): len = 245546, overlap = 838.688
+PHY-3002 : Step(59): len = 244641, overlap = 849.625
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.12974e-06
+PHY-3002 : Step(60): len = 257236, overlap = 815.781
+PHY-3002 : Step(61): len = 276206, overlap = 735.906
+PHY-3002 : Step(62): len = 284785, overlap = 649.562
+PHY-3002 : Step(63): len = 290937, overlap = 608.375
+PHY-3002 : Step(64): len = 292232, overlap = 599.312
+PHY-3002 : Step(65): len = 293835, overlap = 586.625
+PHY-3002 : Step(66): len = 293272, overlap = 587.031
+PHY-3002 : Step(67): len = 294183, overlap = 575.75
+PHY-3002 : Step(68): len = 293786, overlap = 564.062
+PHY-3002 : Step(69): len = 294159, overlap = 569.812
+PHY-3002 : Step(70): len = 292371, overlap = 572.062
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.62595e-05
+PHY-3002 : Step(71): len = 308152, overlap = 529.469
+PHY-3002 : Step(72): len = 324083, overlap = 474.219
+PHY-3002 : Step(73): len = 330239, overlap = 428.875
+PHY-3002 : Step(74): len = 332632, overlap = 417.375
+PHY-3002 : Step(75): len = 331827, overlap = 398.438
+PHY-3002 : Step(76): len = 333036, overlap = 415.344
+PHY-3002 : Step(77): len = 333241, overlap = 415.375
+PHY-3002 : Step(78): len = 334598, overlap = 392.188
+PHY-3002 : Step(79): len = 335117, overlap = 396.188
+PHY-3002 : Step(80): len = 335973, overlap = 370.812
+PHY-3002 : Step(81): len = 336666, overlap = 368.406
+PHY-3002 : Step(82): len = 337453, overlap = 366.969
+PHY-3002 : Step(83): len = 337352, overlap = 364.5
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.2519e-05
+PHY-3002 : Step(84): len = 353737, overlap = 332.438
+PHY-3002 : Step(85): len = 368321, overlap = 322.156
+PHY-3002 : Step(86): len = 372663, overlap = 315.469
+PHY-3002 : Step(87): len = 376855, overlap = 323.125
+PHY-3002 : Step(88): len = 375407, overlap = 323.094
+PHY-3002 : Step(89): len = 377631, overlap = 325.906
+PHY-3002 : Step(90): len = 377836, overlap = 319.875
+PHY-3002 : Step(91): len = 379162, overlap = 321.25
+PHY-3002 : Step(92): len = 378277, overlap = 329.656
+PHY-3002 : Step(93): len = 378834, overlap = 331.25
+PHY-3002 : Step(94): len = 378077, overlap = 316.281
+PHY-3002 : Step(95): len = 378669, overlap = 318
+PHY-3002 : Step(96): len = 378190, overlap = 323.812
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.50379e-05
+PHY-3002 : Step(97): len = 393412, overlap = 301.406
+PHY-3002 : Step(98): len = 405320, overlap = 269.969
+PHY-3002 : Step(99): len = 406795, overlap = 259.125
+PHY-3002 : Step(100): len = 406852, overlap = 268.406
+PHY-3002 : Step(101): len = 408509, overlap = 257.281
+PHY-3002 : Step(102): len = 410743, overlap = 259.875
+PHY-3002 : Step(103): len = 410466, overlap = 254.844
+PHY-3002 : Step(104): len = 412300, overlap = 251.438
+PHY-3002 : Step(105): len = 413900, overlap = 249.656
+PHY-3002 : Step(106): len = 416003, overlap = 233.906
+PHY-3002 : Step(107): len = 415469, overlap = 241.875
+PHY-3002 : Step(108): len = 416695, overlap = 243
+PHY-3002 : Step(109): len = 415844, overlap = 245.438
+PHY-3002 : Step(110): len = 416275, overlap = 248.188
+PHY-3002 : Step(111): len = 414899, overlap = 248.094
+PHY-3002 : Step(112): len = 415219, overlap = 252.594
+PHY-3002 : Step(113): len = 416520, overlap = 246.625
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000130076
+PHY-3002 : Step(114): len = 428910, overlap = 239.75
+PHY-3002 : Step(115): len = 438462, overlap = 228.188
+PHY-3002 : Step(116): len = 437215, overlap = 221.719
+PHY-3002 : Step(117): len = 438682, overlap = 220.844
+PHY-3002 : Step(118): len = 441592, overlap = 212.094
+PHY-3002 : Step(119): len = 443717, overlap = 204.562
+PHY-3002 : Step(120): len = 441387, overlap = 212.625
+PHY-3002 : Step(121): len = 441784, overlap = 205.375
+PHY-3002 : Step(122): len = 443545, overlap = 197.031
+PHY-3002 : Step(123): len = 445907, overlap = 190.031
+PHY-3002 : Step(124): len = 443828, overlap = 195.719
+PHY-3002 : Step(125): len = 443543, overlap = 199.312
+PHY-3002 : Step(126): len = 445067, overlap = 188.656
+PHY-3002 : Step(127): len = 447541, overlap = 188.094
+PHY-3002 : Step(128): len = 445886, overlap = 181.125
+PHY-3002 : Step(129): len = 445614, overlap = 183.562
+PHY-3002 : Step(130): len = 446731, overlap = 180.125
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000260152
+PHY-3002 : Step(131): len = 454313, overlap = 179
+PHY-3002 : Step(132): len = 464242, overlap = 187.344
+PHY-3002 : Step(133): len = 466413, overlap = 172.094
+PHY-3002 : Step(134): len = 468003, overlap = 174.281
+PHY-3002 : Step(135): len = 469917, overlap = 166.219
+PHY-3002 : Step(136): len = 471784, overlap = 162.812
+PHY-3002 : Step(137): len = 470447, overlap = 164.906
+PHY-3002 : Step(138): len = 470947, overlap = 158.594
+PHY-3002 : Step(139): len = 473691, overlap = 158.125
+PHY-3002 : Step(140): len = 475465, overlap = 156.281
+PHY-3002 : Step(141): len = 473479, overlap = 158.812
+PHY-3002 : Step(142): len = 473249, overlap = 158.875
+PHY-3002 : Step(143): len = 475915, overlap = 156.438
+PHY-3002 : Step(144): len = 478350, overlap = 160
+PHY-3002 : Step(145): len = 475911, overlap = 159.688
+PHY-3002 : Step(146): len = 475266, overlap = 157.969
+PHY-3002 : Step(147): len = 476320, overlap = 158.312
+PHY-3002 : Step(148): len = 477685, overlap = 168.75
+PHY-3002 : Step(149): len = 476374, overlap = 164.125
+PHY-3002 : Step(150): len = 476534, overlap = 157.875
+PHY-3002 : Step(151): len = 477767, overlap = 166.375
+PHY-3002 : Step(152): len = 478268, overlap = 167.906
+PHY-3002 : Step(153): len = 477116, overlap = 168.625
+PHY-3002 : Step(154): len = 477032, overlap = 168.906
+PHY-3002 : Step(155): len = 478102, overlap = 167.562
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000508611
+PHY-3002 : Step(156): len = 484627, overlap = 159.656
+PHY-3002 : Step(157): len = 491655, overlap = 150.875
+PHY-3002 : Step(158): len = 492113, overlap = 156.875
+PHY-3002 : Step(159): len = 492847, overlap = 157.562
+PHY-3002 : Step(160): len = 494864, overlap = 158.5
+PHY-3002 : Step(161): len = 496276, overlap = 156.312
+PHY-3002 : Step(162): len = 496447, overlap = 145.906
+PHY-3002 : Step(163): len = 496616, overlap = 150.062
+PHY-3002 : Step(164): len = 497328, overlap = 154.25
+PHY-3002 : Step(165): len = 497891, overlap = 153.938
+PHY-3002 : Step(166): len = 497881, overlap = 160.406
+PHY-3002 : Step(167): len = 498217, overlap = 155.781
+PHY-3002 : Step(168): len = 499724, overlap = 157.188
+PHY-3002 : Step(169): len = 500745, overlap = 160.719
+PHY-3002 : Step(170): len = 499938, overlap = 160.406
+PHY-3002 : Step(171): len = 499824, overlap = 160.094
+PHY-3002 : Step(172): len = 499733, overlap = 156.938
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000916394
+PHY-3002 : Step(173): len = 503790, overlap = 157.219
+PHY-3002 : Step(174): len = 509995, overlap = 151.281
+PHY-3002 : Step(175): len = 511465, overlap = 152.688
+PHY-3002 : Step(176): len = 512336, overlap = 152.656
+PHY-3002 : Step(177): len = 513141, overlap = 151.344
+PHY-3002 : Step(178): len = 513594, overlap = 151.406
+PHY-3002 : Step(179): len = 514035, overlap = 148.406
+PHY-3002 : Step(180): len = 514863, overlap = 149.594
+PHY-3002 : Step(181): len = 515914, overlap = 151.781
+PHY-3002 : Step(182): len = 516409, overlap = 157.781
+PHY-3002 : Step(183): len = 516533, overlap = 156.438
+PHY-3002 : Step(184): len = 516784, overlap = 157
+PHY-3002 : Step(185): len = 517366, overlap = 155.375
+PHY-3002 : Step(186): len = 517825, overlap = 155
+PHY-3002 : Step(187): len = 517802, overlap = 155.688
+PHY-3002 : Step(188): len = 517765, overlap = 151.812
+PHY-3002 : Step(189): len = 517513, overlap = 154.312
+PHY-3002 : Step(190): len = 517781, overlap = 149.719
+PHY-3002 : Step(191): len = 518451, overlap = 154.156
+PHY-3002 : Step(192): len = 518451, overlap = 154.156
+PHY-3002 : Step(193): len = 518408, overlap = 152.531
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.013607s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (114.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20347.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 682472, over cnt = 1568(4%), over = 7348, worst = 60
+PHY-1001 : End global iterations; 0.701971s wall, 0.984375s user + 0.093750s system = 1.078125s CPU (153.6%)
+
+PHY-1001 : Congestion index: top1 = 79.31, top5 = 61.39, top10 = 52.06, top15 = 46.55.
+PHY-3001 : End congestion estimation; 0.935869s wall, 1.203125s user + 0.109375s system = 1.312500s CPU (140.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20169 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.884244s wall, 0.859375s user + 0.031250s system = 0.890625s CPU (100.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00012332
+PHY-3002 : Step(194): len = 623999, overlap = 94.5312
+PHY-3002 : Step(195): len = 626420, overlap = 92.8125
+PHY-3002 : Step(196): len = 619917, overlap = 87.4688
+PHY-3002 : Step(197): len = 613919, overlap = 88.3125
+PHY-3002 : Step(198): len = 612227, overlap = 77.625
+PHY-3002 : Step(199): len = 612245, overlap = 68.3438
+PHY-3002 : Step(200): len = 610809, overlap = 62.6562
+PHY-3002 : Step(201): len = 609693, overlap = 61.125
+PHY-3002 : Step(202): len = 609501, overlap = 60.7188
+PHY-3002 : Step(203): len = 610090, overlap = 58.7188
+PHY-3002 : Step(204): len = 609053, overlap = 55.9375
+PHY-3002 : Step(205): len = 608203, overlap = 54
+PHY-3002 : Step(206): len = 608024, overlap = 50.2812
+PHY-3002 : Step(207): len = 607896, overlap = 46.375
+PHY-3002 : Step(208): len = 607617, overlap = 41.9688
+PHY-3002 : Step(209): len = 608120, overlap = 34.3125
+PHY-3002 : Step(210): len = 608539, overlap = 27.875
+PHY-3002 : Step(211): len = 608209, overlap = 30.875
+PHY-3002 : Step(212): len = 607981, overlap = 29.1875
+PHY-3002 : Step(213): len = 607724, overlap = 30.5
+PHY-3002 : Step(214): len = 607431, overlap = 30.3125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000246641
+PHY-3002 : Step(215): len = 608700, overlap = 29.4688
+PHY-3002 : Step(216): len = 611354, overlap = 30.1562
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 147/20347.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 693304, over cnt = 2596(7%), over = 11544, worst = 74
+PHY-1001 : End global iterations; 1.610721s wall, 2.140625s user + 0.031250s system = 2.171875s CPU (134.8%)
+
+PHY-1001 : Congestion index: top1 = 83.19, top5 = 65.81, top10 = 57.01, top15 = 51.64.
+PHY-3001 : End congestion estimation; 1.873180s wall, 2.406250s user + 0.031250s system = 2.437500s CPU (130.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20169 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.901494s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.21639e-05
+PHY-3002 : Step(217): len = 611065, overlap = 291.625
+PHY-3002 : Step(218): len = 617614, overlap = 232.812
+PHY-3002 : Step(219): len = 615889, overlap = 218.75
+PHY-3002 : Step(220): len = 612069, overlap = 208.562
+PHY-3002 : Step(221): len = 611948, overlap = 190.719
+PHY-3002 : Step(222): len = 612999, overlap = 188.062
+PHY-3002 : Step(223): len = 609435, overlap = 183.031
+PHY-3002 : Step(224): len = 607576, overlap = 179.281
+PHY-3002 : Step(225): len = 605266, overlap = 167.25
+PHY-3002 : Step(226): len = 603976, overlap = 167.938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000184328
+PHY-3002 : Step(227): len = 604636, overlap = 160.531
+PHY-3002 : Step(228): len = 607725, overlap = 151.688
+PHY-3002 : Step(229): len = 610005, overlap = 144.938
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000368656
+PHY-3002 : Step(230): len = 615061, overlap = 135.406
+PHY-3002 : Step(231): len = 624467, overlap = 114.781
+PHY-3002 : Step(232): len = 629080, overlap = 107.719
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84881, tnet num: 20169, tinst num: 17767, tnode num: 115265, tedge num: 136154.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.482142s wall, 1.437500s user + 0.046875s system = 1.484375s CPU (100.2%)
+
+RUN-1004 : used memory is 573 MB, reserved memory is 563 MB, peak memory is 708 MB
+OPT-1001 : Total overflow 445.22 peak overflow 3.72
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1476/20347.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 727144, over cnt = 3002(8%), over = 11122, worst = 33
+PHY-1001 : End global iterations; 1.160257s wall, 1.703125s user + 0.015625s system = 1.718750s CPU (148.1%)
+
+PHY-1001 : Congestion index: top1 = 71.51, top5 = 57.60, top10 = 51.43, top15 = 47.67.
+PHY-1001 : End incremental global routing; 1.500849s wall, 2.046875s user + 0.015625s system = 2.062500s CPU (137.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20169 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.939978s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (99.7%)
+
+OPT-1001 : 52 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17630 has valid locations, 342 needs to be replaced
+PHY-3001 : design contains 18057 instances, 7507 luts, 9329 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 6075 pins
+PHY-3001 : Found 1242 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 652248
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16683/20637.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 739360, over cnt = 3019(8%), over = 11163, worst = 32
+PHY-1001 : End global iterations; 0.253944s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (153.8%)
+
+PHY-1001 : Congestion index: top1 = 72.13, top5 = 58.10, top10 = 51.76, top15 = 47.97.
+PHY-3001 : End congestion estimation; 0.517312s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (123.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86051, tnet num: 20459, tinst num: 18057, tnode num: 117015, tedge num: 137914.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.522231s wall, 1.515625s user + 0.000000s system = 1.515625s CPU (99.6%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 619 MB, peak memory is 712 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20459 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.524332s wall, 2.500000s user + 0.015625s system = 2.515625s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(233): len = 651090, overlap = 0.875
+PHY-3002 : Step(234): len = 650852, overlap = 0.8125
+PHY-3002 : Step(235): len = 650797, overlap = 0.9375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16798/20637.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 737136, over cnt = 3035(8%), over = 11247, worst = 33
+PHY-1001 : End global iterations; 0.207665s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (127.9%)
+
+PHY-1001 : Congestion index: top1 = 71.92, top5 = 58.26, top10 = 51.91, top15 = 48.13.
+PHY-3001 : End congestion estimation; 0.486185s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (112.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20459 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.955874s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000343529
+PHY-3002 : Step(236): len = 650596, overlap = 110.062
+PHY-3002 : Step(237): len = 650728, overlap = 110.062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000687057
+PHY-3002 : Step(238): len = 650800, overlap = 110.375
+PHY-3002 : Step(239): len = 651471, overlap = 110.562
+PHY-3001 : Final: Len = 651471, Over = 110.562
+PHY-3001 : End incremental placement; 5.196510s wall, 5.453125s user + 0.171875s system = 5.625000s CPU (108.2%)
+
+OPT-1001 : Total overflow 451.06 peak overflow 3.72
+OPT-1001 : End high-fanout net optimization; 8.193999s wall, 9.015625s user + 0.218750s system = 9.234375s CPU (112.7%)
+
+OPT-1001 : Current memory(MB): used = 716, reserve = 710, peak = 732.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16748/20637.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 740304, over cnt = 2976(8%), over = 10280, worst = 31
+PHY-1002 : len = 797744, over cnt = 2050(5%), over = 4998, worst = 28
+PHY-1002 : len = 833368, over cnt = 1040(2%), over = 2255, worst = 20
+PHY-1002 : len = 860352, over cnt = 318(0%), over = 652, worst = 14
+PHY-1002 : len = 871312, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.797807s wall, 2.687500s user + 0.000000s system = 2.687500s CPU (149.5%)
+
+PHY-1001 : Congestion index: top1 = 58.23, top5 = 50.65, top10 = 47.13, top15 = 44.75.
+OPT-1001 : End congestion update; 2.077715s wall, 2.953125s user + 0.015625s system = 2.968750s CPU (142.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20459 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.864294s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.4%)
+
+OPT-0007 : Start: WNS -1068 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 64 cells processed and 6700 slack improved
+OPT-0007 : Iter 2: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 13 cells processed and 1300 slack improved
+OPT-0007 : Iter 3: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 13 cells processed and 616 slack improved
+OPT-1001 : End global optimization; 2.994388s wall, 3.875000s user + 0.015625s system = 3.890625s CPU (129.9%)
+
+OPT-1001 : Current memory(MB): used = 691, reserve = 690, peak = 732.
+OPT-1001 : End physical optimization; 13.356336s wall, 15.093750s user + 0.281250s system = 15.375000s CPU (115.1%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7507 LUT to BLE ...
+SYN-4008 : Packed 7507 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6196 remaining SEQ's ...
+SYN-4005 : Packed 3622 SEQ with LUT/SLICE
+SYN-4006 : 1057 single LUT's are left
+SYN-4006 : 2574 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10081/13812 primitive instances ...
+PHY-3001 : End packing; 1.760930s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (100.3%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6931 instances
+RUN-1001 : 3392 mslices, 3391 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17634 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9975 nets have 2 pins
+RUN-1001 : 5997 nets have [3 - 5] pins
+RUN-1001 : 971 nets have [6 - 10] pins
+RUN-1001 : 311 nets have [11 - 20] pins
+RUN-1001 : 348 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6929 instances, 6783 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3567 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 661265, Over = 294.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7588/17634.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 816704, over cnt = 1966(5%), over = 3356, worst = 9
+PHY-1002 : len = 825624, over cnt = 1383(3%), over = 2102, worst = 8
+PHY-1002 : len = 843408, over cnt = 388(1%), over = 548, worst = 8
+PHY-1002 : len = 851880, over cnt = 41(0%), over = 44, worst = 2
+PHY-1002 : len = 853664, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.636704s wall, 2.406250s user + 0.046875s system = 2.453125s CPU (149.9%)
+
+PHY-1001 : Congestion index: top1 = 60.06, top5 = 51.85, top10 = 47.44, top15 = 44.70.
+PHY-3001 : End congestion estimation; 2.049110s wall, 2.812500s user + 0.046875s system = 2.859375s CPU (139.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73753, tnet num: 17456, tinst num: 6929, tnode num: 96323, tedge num: 123805.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.657844s wall, 1.640625s user + 0.015625s system = 1.656250s CPU (99.9%)
+
+RUN-1004 : used memory is 610 MB, reserved memory is 613 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17456 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.543230s wall, 2.531250s user + 0.015625s system = 2.546875s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.56714e-05
+PHY-3002 : Step(240): len = 649477, overlap = 291.5
+PHY-3002 : Step(241): len = 642662, overlap = 286.5
+PHY-3002 : Step(242): len = 638039, overlap = 278.25
+PHY-3002 : Step(243): len = 634973, overlap = 290
+PHY-3002 : Step(244): len = 633321, overlap = 295.75
+PHY-3002 : Step(245): len = 631879, overlap = 299.5
+PHY-3002 : Step(246): len = 631044, overlap = 301.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.13427e-05
+PHY-3002 : Step(247): len = 634717, overlap = 285.5
+PHY-3002 : Step(248): len = 638741, overlap = 273.75
+PHY-3002 : Step(249): len = 638599, overlap = 268
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000182685
+PHY-3002 : Step(250): len = 648101, overlap = 263.25
+PHY-3002 : Step(251): len = 658542, overlap = 248.5
+PHY-3002 : Step(252): len = 657720, overlap = 247.25
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000365371
+PHY-3002 : Step(253): len = 664776, overlap = 238.75
+PHY-3002 : Step(254): len = 679743, overlap = 231.5
+PHY-3002 : Step(255): len = 680538, overlap = 218.5
+PHY-3002 : Step(256): len = 679051, overlap = 211.75
+PHY-3002 : Step(257): len = 679003, overlap = 208.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.420178s wall, 0.250000s user + 0.625000s system = 0.875000s CPU (208.2%)
+
+PHY-3001 : Trial Legalized: Len = 756387
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 756/17634.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 876544, over cnt = 2698(7%), over = 4584, worst = 8
+PHY-1002 : len = 893224, over cnt = 1620(4%), over = 2408, worst = 7
+PHY-1002 : len = 912488, over cnt = 602(1%), over = 875, worst = 6
+PHY-1002 : len = 923440, over cnt = 127(0%), over = 189, worst = 5
+PHY-1002 : len = 926264, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations; 2.644778s wall, 3.875000s user + 0.046875s system = 3.921875s CPU (148.3%)
+
+PHY-1001 : Congestion index: top1 = 55.09, top5 = 49.67, top10 = 46.80, top15 = 44.91.
+PHY-3001 : End congestion estimation; 3.114647s wall, 4.343750s user + 0.046875s system = 4.390625s CPU (141.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17456 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.897327s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (101.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000167586
+PHY-3002 : Step(258): len = 729049, overlap = 40.75
+PHY-3002 : Step(259): len = 712627, overlap = 61.25
+PHY-3002 : Step(260): len = 698364, overlap = 92
+PHY-3002 : Step(261): len = 688041, overlap = 120
+PHY-3002 : Step(262): len = 681416, overlap = 143.75
+PHY-3002 : Step(263): len = 676841, overlap = 171.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000335172
+PHY-3002 : Step(264): len = 681856, overlap = 161
+PHY-3002 : Step(265): len = 685823, overlap = 154.5
+PHY-3002 : Step(266): len = 686234, overlap = 151.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000625275
+PHY-3002 : Step(267): len = 689985, overlap = 152
+PHY-3002 : Step(268): len = 697033, overlap = 142.25
+PHY-3002 : Step(269): len = 704808, overlap = 137.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.037143s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (126.2%)
+
+PHY-3001 : Legalized: Len = 734778, Over = 0
+PHY-3001 : Spreading special nets. 426 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.111343s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (98.2%)
+
+PHY-3001 : 621 instances has been re-located, deltaX = 223, deltaY = 383, maxDist = 7.
+PHY-3001 : Final: Len = 745354, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73753, tnet num: 17456, tinst num: 6932, tnode num: 96323, tedge num: 123805.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.906035s wall, 1.906250s user + 0.000000s system = 1.906250s CPU (100.0%)
+
+RUN-1004 : used memory is 625 MB, reserved memory is 639 MB, peak memory is 732 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4554/17634.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 880784, over cnt = 2574(7%), over = 4090, worst = 7
+PHY-1002 : len = 894376, over cnt = 1488(4%), over = 2117, worst = 7
+PHY-1002 : len = 908568, over cnt = 669(1%), over = 908, worst = 7
+PHY-1002 : len = 919736, over cnt = 197(0%), over = 238, worst = 4
+PHY-1002 : len = 923504, over cnt = 9(0%), over = 10, worst = 2
+PHY-1001 : End global iterations; 1.872689s wall, 2.875000s user + 0.000000s system = 2.875000s CPU (153.5%)
+
+PHY-1001 : Congestion index: top1 = 54.55, top5 = 49.49, top10 = 46.55, top15 = 44.59.
+PHY-1001 : End incremental global routing; 2.259403s wall, 3.250000s user + 0.015625s system = 3.265625s CPU (144.5%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17456 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.915060s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (97.3%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6841 has valid locations, 13 needs to be replaced
+PHY-3001 : design contains 6942 instances, 6793 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3630 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 746167
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16081/17645.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 924104, over cnt = 57(0%), over = 61, worst = 3
+PHY-1002 : len = 924240, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 924264, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 924344, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 924376, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.844524s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.9%)
+
+PHY-1001 : Congestion index: top1 = 54.55, top5 = 49.47, top10 = 46.55, top15 = 44.60.
+PHY-3001 : End congestion estimation; 1.174961s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (99.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73816, tnet num: 17467, tinst num: 6942, tnode num: 96403, tedge num: 123883.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.886447s wall, 1.875000s user + 0.015625s system = 1.890625s CPU (100.2%)
+
+RUN-1004 : used memory is 654 MB, reserved memory is 655 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17467 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.787838s wall, 2.750000s user + 0.031250s system = 2.781250s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(270): len = 746171, overlap = 0
+PHY-3002 : Step(271): len = 746171, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16077/17645.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 924256, over cnt = 30(0%), over = 30, worst = 1
+PHY-1002 : len = 924296, over cnt = 16(0%), over = 16, worst = 1
+PHY-1002 : len = 924376, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 924456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.585764s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (109.4%)
+
+PHY-1001 : Congestion index: top1 = 54.55, top5 = 49.47, top10 = 46.54, top15 = 44.58.
+PHY-3001 : End congestion estimation; 0.910585s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (106.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17467 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.890223s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000577723
+PHY-3002 : Step(272): len = 746097, overlap = 0.75
+PHY-3002 : Step(273): len = 746097, overlap = 0.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005979s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 746095, Over = 0
+PHY-3001 : End spreading; 0.064090s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.5%)
+
+PHY-3001 : Final: Len = 746095, Over = 0
+PHY-3001 : End incremental placement; 6.298301s wall, 6.390625s user + 0.093750s system = 6.484375s CPU (103.0%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.989633s wall, 11.078125s user + 0.109375s system = 11.187500s CPU (112.0%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 738, peak = 739.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16078/17645.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 924232, over cnt = 25(0%), over = 28, worst = 2
+PHY-1002 : len = 924216, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 924320, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 924320, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 924320, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.765406s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (104.1%)
+
+PHY-1001 : Congestion index: top1 = 54.55, top5 = 49.46, top10 = 46.54, top15 = 44.58.
+OPT-1001 : End congestion update; 1.093792s wall, 1.109375s user + 0.015625s system = 1.125000s CPU (102.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17467 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.745631s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.5%)
+
+OPT-0007 : Start: WNS -1083 TNS -1668 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6854 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6942 instances, 6793 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3630 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 752163, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066062s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.6%)
+
+PHY-3001 : 16 instances has been re-located, deltaX = 20, deltaY = 3, maxDist = 3.
+PHY-3001 : Final: Len = 752299, Over = 0
+PHY-3001 : End incremental legalization; 0.418193s wall, 0.484375s user + 0.015625s system = 0.500000s CPU (119.6%)
+
+OPT-0007 : Iter 1: improved WNS -1033 TNS -1568 NUM_FEPS 2 with 26 cells processed and 9750 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6854 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6942 instances, 6793 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3630 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 752327, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062120s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.6%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 5, deltaY = 1, maxDist = 2.
+PHY-3001 : Final: Len = 752367, Over = 0
+PHY-3001 : End incremental legalization; 0.418101s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.9%)
+
+OPT-0007 : Iter 2: improved WNS -1033 TNS -1568 NUM_FEPS 2 with 8 cells processed and 650 slack improved
+OPT-1001 : End path based optimization; 2.944102s wall, 3.000000s user + 0.046875s system = 3.046875s CPU (103.5%)
+
+OPT-1001 : Current memory(MB): used = 737, reserve = 738, peak = 740.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17467 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.909630s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.6%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15962/17645.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 929896, over cnt = 88(0%), over = 100, worst = 3
+PHY-1002 : len = 929736, over cnt = 56(0%), over = 59, worst = 3
+PHY-1002 : len = 929896, over cnt = 40(0%), over = 41, worst = 2
+PHY-1002 : len = 930288, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 930576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.851852s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (111.9%)
+
+PHY-1001 : Congestion index: top1 = 55.47, top5 = 49.60, top10 = 46.55, top15 = 44.55.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17467 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.748712s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.1%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -1083 TNS -1668 NUM_FEPS 2
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 55.137931
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -1083ps with logic level 2
+RUN-1001 : #2 path slack -1047ps with logic level 2
+RUN-1001 : 0 HFN exist on timing critical paths out of 17645 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 17645 nets
+OPT-1001 : End physical optimization; 18.074323s wall, 19.296875s user + 0.156250s system = 19.453125s CPU (107.6%)
+
+RUN-1003 : finish command "place" in 61.317853s wall, 86.234375s user + 6.156250s system = 92.390625s CPU (150.7%)
+
+RUN-1004 : used memory is 643 MB, reserved memory is 647 MB, peak memory is 740 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.735178s wall, 2.953125s user + 0.015625s system = 2.968750s CPU (171.1%)
+
+RUN-1004 : used memory is 643 MB, reserved memory is 649 MB, peak memory is 740 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6944 instances
+RUN-1001 : 3395 mslices, 3398 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17645 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9978 nets have 2 pins
+RUN-1001 : 5997 nets have [3 - 5] pins
+RUN-1001 : 970 nets have [6 - 10] pins
+RUN-1001 : 314 nets have [11 - 20] pins
+RUN-1001 : 356 nets have [21 - 99] pins
+RUN-1001 : 10 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73816, tnet num: 17467, tinst num: 6942, tnode num: 96403, tedge num: 123883.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.698216s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (100.3%)
+
+RUN-1004 : used memory is 625 MB, reserved memory is 620 MB, peak memory is 740 MB
+PHY-1001 : 3395 mslices, 3398 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17467 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 860472, over cnt = 2755(7%), over = 4598, worst = 9
+PHY-1002 : len = 880168, over cnt = 1588(4%), over = 2277, worst = 7
+PHY-1002 : len = 898880, over cnt = 682(1%), over = 918, worst = 5
+PHY-1002 : len = 911264, over cnt = 67(0%), over = 85, worst = 4
+PHY-1002 : len = 912808, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.007620s wall, 4.140625s user + 0.000000s system = 4.140625s CPU (137.7%)
+
+PHY-1001 : Congestion index: top1 = 54.70, top5 = 49.15, top10 = 46.11, top15 = 44.16.
+PHY-1001 : End global routing; 3.353105s wall, 4.468750s user + 0.031250s system = 4.500000s CPU (134.2%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 710, reserve = 714, peak = 740.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 985, reserve = 990, peak = 985.
+PHY-1001 : End build detailed router design. 4.110705s wall, 4.031250s user + 0.078125s system = 4.109375s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 265192, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.821144s wall, 5.812500s user + 0.015625s system = 5.828125s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 265248, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.533845s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1022, reserve = 1027, peak = 1022.
+PHY-1001 : End phase 1; 6.371412s wall, 6.359375s user + 0.015625s system = 6.375000s CPU (100.1%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.32329e+06, over cnt = 1821(0%), over = 1832, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1039, reserve = 1043, peak = 1039.
+PHY-1001 : End initial routed; 32.101044s wall, 64.265625s user + 0.437500s system = 64.703125s CPU (201.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16568(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.845 | -4.166 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.355172s wall, 3.343750s user + 0.000000s system = 3.343750s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1051, reserve = 1054, peak = 1051.
+PHY-1001 : End phase 2; 35.456283s wall, 67.609375s user + 0.437500s system = 68.046875s CPU (191.9%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -1.801ns STNS -4.118ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.149971s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (104.2%)
+
+PHY-1022 : len = 2.32329e+06, over cnt = 1824(0%), over = 1835, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.441714s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2904e+06, over cnt = 745(0%), over = 748, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.868912s wall, 3.125000s user + 0.000000s system = 3.125000s CPU (167.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.28829e+06, over cnt = 168(0%), over = 168, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.965154s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (148.9%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.28979e+06, over cnt = 15(0%), over = 15, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.503561s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (121.0%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.28989e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.256122s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (97.6%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.28994e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.404608s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (96.5%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.28998e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.677796s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (99.1%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.28998e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.828214s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (100.0%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.28998e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.182386s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (102.8%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.28994e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.175431s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (106.9%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.28994e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.188795s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.28994e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.263506s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.28994e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.417357s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (101.1%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.28995e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.182084s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (94.4%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.28998e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.169188s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16568(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.801 | -4.118 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.392721s wall, 3.390625s user + 0.000000s system = 3.390625s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 521 feed throughs used by 383 nets
+PHY-1001 : End commit to database; 2.257866s wall, 2.250000s user + 0.000000s system = 2.250000s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1154, reserve = 1161, peak = 1154.
+PHY-1001 : End phase 3; 13.617305s wall, 15.453125s user + 0.015625s system = 15.468750s CPU (113.6%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.801ns STNS -4.118ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.147466s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (106.0%)
+
+PHY-1022 : len = 2.28998e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.409964s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.1%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.801ns, -4.118ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16568(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.801 | -4.118 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.376743s wall, 3.375000s user + 0.000000s system = 3.375000s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 521 feed throughs used by 383 nets
+PHY-1001 : End commit to database; 2.368787s wall, 2.359375s user + 0.000000s system = 2.359375s CPU (99.6%)
+
+PHY-1001 : Current memory(MB): used = 1163, reserve = 1170, peak = 1163.
+PHY-1001 : End phase 4; 6.185321s wall, 6.171875s user + 0.000000s system = 6.171875s CPU (99.8%)
+
+PHY-1003 : Routed, final wirelength = 2.28998e+06
+PHY-1001 : Current memory(MB): used = 1165, reserve = 1172, peak = 1165.
+PHY-1001 : End export database. 0.067537s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (92.5%)
+
+PHY-1001 : End detail routing; 66.248719s wall, 100.156250s user + 0.546875s system = 100.703125s CPU (152.0%)
+
+RUN-1003 : finish command "route" in 72.418450s wall, 107.390625s user + 0.625000s system = 108.015625s CPU (149.2%)
+
+RUN-1004 : used memory is 1088 MB, reserved memory is 1096 MB, peak memory is 1165 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10226 out of 19600 52.17%
+#reg 9465 out of 19600 48.29%
+#le 12733
+ #lut only 3268 out of 12733 25.67%
+ #reg only 2507 out of 12733 19.69%
+ #lut® 6958 out of 12733 54.65%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1848
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1403
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1315
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 948
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice a_frame_pad_d0_reg_syn_17.q0 140
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 68
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 25
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/reg9_syn_157.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg39_syn_205.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P143 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P17 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P133 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P16 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P109 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P88 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P32 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P35 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12733 |9199 |1027 |9497 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |555 |445 |23 |441 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |101 |82 |4 |89 |4 |0 |
+| U_crc16_24b |crc16_24b |29 |29 |0 |19 |0 |0 |
+| U_ecc_gen |ecc_gen |12 |12 |0 |7 |0 |0 |
+| exdev_ctl_a |exdev_ctl |792 |378 |96 |592 |0 |0 |
+| u_ADconfig |AD_config |199 |139 |25 |144 |0 |0 |
+| u_gen_sp |gen_sp |264 |156 |71 |119 |0 |0 |
+| exdev_ctl_b |exdev_ctl |743 |408 |96 |555 |0 |0 |
+| u_ADconfig |AD_config |176 |136 |25 |126 |0 |0 |
+| u_gen_sp |gen_sp |255 |167 |71 |117 |0 |0 |
+| sampling_fe_a |sampling_fe |3215 |2525 |306 |2112 |25 |0 |
+| u0_soft_n |cdc_sync |9 |9 |0 |9 |0 |0 |
+| u_ad_sampling |ad_sampling |175 |95 |17 |140 |0 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_sort |sort |3001 |2418 |289 |1933 |25 |0 |
+| rddpram_ctl |rddpram_ctl |5 |5 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |2 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |6 |3 |0 |6 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2515 |2087 |253 |1544 |22 |0 |
+| channelPart |channel_part_8478 |158 |155 |3 |140 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |42 |0 |0 |
+| ram_switch |ram_switch |1965 |1595 |197 |1128 |0 |0 |
+| adc_addr_gen |adc_addr_gen |211 |182 |27 |121 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |8 |3 |3 |4 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |21 |18 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |23 |20 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |10 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |15 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |28 |25 |3 |13 |0 |0 |
+| insert |insert |933 |592 |170 |634 |0 |0 |
+| ram_switch_state |ram_switch_state |821 |821 |0 |373 |0 |0 |
+| read_ram_i |read_ram |310 |265 |44 |210 |0 |0 |
+| read_ram_addr |read_ram_addr |218 |178 |40 |152 |0 |0 |
+| read_ram_data |read_ram_data |90 |86 |4 |56 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |346 |221 |36 |277 |3 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3347 |2619 |349 |2141 |25 |1 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_ad_sampling |ad_sampling |171 |125 |17 |133 |0 |0 |
+| u0_soft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_sort |sort_rev |3143 |2473 |332 |1975 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |3 |1 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |2 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2694 |2157 |290 |1591 |22 |1 |
+| channelPart |channel_part_8478 |240 |236 |3 |144 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
+| ram_switch |ram_switch |1940 |1524 |197 |1143 |0 |0 |
+| adc_addr_gen |adc_addr_gen |232 |205 |27 |112 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |8 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |9 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 |
+| insert |insert |995 |613 |170 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |713 |706 |0 |339 |0 |0 |
+| read_ram_i |read_ram_rev |431 |330 |81 |236 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |312 |229 |73 |168 |0 |0 |
+| read_ram_data |read_ram_data_rev |119 |101 |8 |68 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9916
+ #2 2 3864
+ #3 3 1477
+ #4 4 653
+ #5 5-10 1025
+ #6 11-50 591
+ #7 51-100 22
+ #8 101-500 1
+ #9 >500 1
+ Average 2.89
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.147680s wall, 3.687500s user + 0.015625s system = 3.703125s CPU (172.4%)
+
+RUN-1004 : used memory is 1089 MB, reserved memory is 1097 MB, peak memory is 1165 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73816, tnet num: 17467, tinst num: 6942, tnode num: 96403, tedge num: 123883.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.781531s wall, 1.781250s user + 0.000000s system = 1.781250s CPU (100.0%)
+
+RUN-1004 : used memory is 1094 MB, reserved memory is 1101 MB, peak memory is 1165 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17467 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.634929s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (99.4%)
+
+RUN-1004 : used memory is 1096 MB, reserved memory is 1103 MB, peak memory is 1165 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6942
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17645, pip num: 171568
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 521
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3247 valid insts, and 477628 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 11.822072s wall, 59.328125s user + 0.765625s system = 60.093750s CPU (508.3%)
+
+RUN-1004 : used memory is 1263 MB, reserved memory is 1266 MB, peak memory is 1379 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240219_101011.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240219_102207.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240219_102207.log
new file mode 100644
index 0000000..0cd64e5
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240219_102207.log
@@ -0,0 +1,1994 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Feb 19 10:22:07 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.184460s wall, 2.062500s user + 0.125000s system = 2.187500s CPU (100.1%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 315 MB, peak memory is 341 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (3047 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2214 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2053 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17769 instances
+RUN-0007 : 7403 luts, 9143 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20347 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13281 nets have 2 pins
+RUN-1001 : 5798 nets have [3 - 5] pins
+RUN-1001 : 853 nets have [6 - 10] pins
+RUN-1001 : 158 nets have [11 - 20] pins
+RUN-1001 : 183 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 1968
+RUN-1001 : No | Yes | No | 3573
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17767 instances, 7403 luts, 9143 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 5948 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84883, tnet num: 20169, tinst num: 17767, tnode num: 115270, tedge num: 136158.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.187414s wall, 1.140625s user + 0.046875s system = 1.187500s CPU (100.0%)
+
+RUN-1004 : used memory is 531 MB, reserved memory is 515 MB, peak memory is 531 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20169 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.994819s wall, 1.937500s user + 0.046875s system = 1.984375s CPU (99.5%)
+
+PHY-3001 : Found 1230 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.16247e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17767.
+PHY-3001 : Level 1 #clusters 2054.
+PHY-3001 : End clustering; 0.137854s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (147.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28561e+06, overlap = 497.375
+PHY-3002 : Step(2): len = 1.23327e+06, overlap = 469.531
+PHY-3002 : Step(3): len = 861536, overlap = 555.656
+PHY-3002 : Step(4): len = 720499, overlap = 659.562
+PHY-3002 : Step(5): len = 583306, overlap = 809.188
+PHY-3002 : Step(6): len = 547395, overlap = 899.75
+PHY-3002 : Step(7): len = 445727, overlap = 979
+PHY-3002 : Step(8): len = 405418, overlap = 1020.12
+PHY-3002 : Step(9): len = 363415, overlap = 1093.28
+PHY-3002 : Step(10): len = 330069, overlap = 1120.62
+PHY-3002 : Step(11): len = 303527, overlap = 1159.88
+PHY-3002 : Step(12): len = 272698, overlap = 1217.34
+PHY-3002 : Step(13): len = 248511, overlap = 1260
+PHY-3002 : Step(14): len = 228372, overlap = 1298.69
+PHY-3002 : Step(15): len = 207395, overlap = 1349.38
+PHY-3002 : Step(16): len = 194456, overlap = 1382.97
+PHY-3002 : Step(17): len = 181738, overlap = 1403.59
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.04808e-06
+PHY-3002 : Step(18): len = 183303, overlap = 1383.56
+PHY-3002 : Step(19): len = 217847, overlap = 1278.53
+PHY-3002 : Step(20): len = 216276, overlap = 1211.22
+PHY-3002 : Step(21): len = 216965, overlap = 1136.31
+PHY-3002 : Step(22): len = 212507, overlap = 1105.25
+PHY-3002 : Step(23): len = 210728, overlap = 1109.12
+PHY-3002 : Step(24): len = 202948, overlap = 1122.66
+PHY-3002 : Step(25): len = 201910, overlap = 1136.22
+PHY-3002 : Step(26): len = 195006, overlap = 1138.22
+PHY-3002 : Step(27): len = 194595, overlap = 1124.5
+PHY-3002 : Step(28): len = 190388, overlap = 1132
+PHY-3002 : Step(29): len = 188436, overlap = 1142.88
+PHY-3002 : Step(30): len = 183917, overlap = 1126.66
+PHY-3002 : Step(31): len = 183260, overlap = 1120.88
+PHY-3002 : Step(32): len = 180872, overlap = 1132.91
+PHY-3002 : Step(33): len = 181029, overlap = 1149.38
+PHY-3002 : Step(34): len = 179793, overlap = 1148.47
+PHY-3002 : Step(35): len = 178185, overlap = 1151.56
+PHY-3002 : Step(36): len = 177219, overlap = 1145.72
+PHY-3002 : Step(37): len = 176610, overlap = 1144.38
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.09615e-06
+PHY-3002 : Step(38): len = 179745, overlap = 1137.78
+PHY-3002 : Step(39): len = 190236, overlap = 1111.22
+PHY-3002 : Step(40): len = 193926, overlap = 1090.09
+PHY-3002 : Step(41): len = 199468, overlap = 1045.53
+PHY-3002 : Step(42): len = 201778, overlap = 1024.16
+PHY-3002 : Step(43): len = 204158, overlap = 1006.41
+PHY-3002 : Step(44): len = 204011, overlap = 998.812
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.1923e-06
+PHY-3002 : Step(45): len = 210155, overlap = 971.844
+PHY-3002 : Step(46): len = 224935, overlap = 944.344
+PHY-3002 : Step(47): len = 231963, overlap = 890.094
+PHY-3002 : Step(48): len = 237889, overlap = 856.844
+PHY-3002 : Step(49): len = 241978, overlap = 852.625
+PHY-3002 : Step(50): len = 245742, overlap = 856
+PHY-3002 : Step(51): len = 247799, overlap = 825.062
+PHY-3002 : Step(52): len = 250012, overlap = 846.281
+PHY-3002 : Step(53): len = 249829, overlap = 850.625
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.3846e-06
+PHY-3002 : Step(54): len = 262406, overlap = 818.25
+PHY-3002 : Step(55): len = 282607, overlap = 711.312
+PHY-3002 : Step(56): len = 291231, overlap = 604.875
+PHY-3002 : Step(57): len = 296008, overlap = 591.406
+PHY-3002 : Step(58): len = 297804, overlap = 584.969
+PHY-3002 : Step(59): len = 298748, overlap = 598.25
+PHY-3002 : Step(60): len = 298064, overlap = 580.5
+PHY-3002 : Step(61): len = 298544, overlap = 569.344
+PHY-3002 : Step(62): len = 299115, overlap = 568.562
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.67692e-05
+PHY-3002 : Step(63): len = 313516, overlap = 537.656
+PHY-3002 : Step(64): len = 327822, overlap = 487.562
+PHY-3002 : Step(65): len = 333509, overlap = 456.594
+PHY-3002 : Step(66): len = 337766, overlap = 436.656
+PHY-3002 : Step(67): len = 338890, overlap = 409.438
+PHY-3002 : Step(68): len = 340164, overlap = 396.938
+PHY-3002 : Step(69): len = 338819, overlap = 400.281
+PHY-3002 : Step(70): len = 338164, overlap = 381.594
+PHY-3002 : Step(71): len = 338648, overlap = 394.969
+PHY-3002 : Step(72): len = 339435, overlap = 385.156
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.35384e-05
+PHY-3002 : Step(73): len = 356760, overlap = 388.719
+PHY-3002 : Step(74): len = 371638, overlap = 386.312
+PHY-3002 : Step(75): len = 375470, overlap = 374.906
+PHY-3002 : Step(76): len = 378349, overlap = 360.438
+PHY-3002 : Step(77): len = 379121, overlap = 358.844
+PHY-3002 : Step(78): len = 382114, overlap = 334.312
+PHY-3002 : Step(79): len = 380107, overlap = 347.5
+PHY-3002 : Step(80): len = 381502, overlap = 344.656
+PHY-3002 : Step(81): len = 381740, overlap = 335.969
+PHY-3002 : Step(82): len = 383167, overlap = 329.219
+PHY-3002 : Step(83): len = 381248, overlap = 330.562
+PHY-3002 : Step(84): len = 381262, overlap = 323.25
+PHY-3002 : Step(85): len = 380617, overlap = 306.938
+PHY-3002 : Step(86): len = 381204, overlap = 303.531
+PHY-3002 : Step(87): len = 379711, overlap = 310.969
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.70768e-05
+PHY-3002 : Step(88): len = 395593, overlap = 285
+PHY-3002 : Step(89): len = 405007, overlap = 268.188
+PHY-3002 : Step(90): len = 406128, overlap = 265.5
+PHY-3002 : Step(91): len = 408899, overlap = 269.438
+PHY-3002 : Step(92): len = 411888, overlap = 263.469
+PHY-3002 : Step(93): len = 415779, overlap = 259.969
+PHY-3002 : Step(94): len = 412650, overlap = 260.125
+PHY-3002 : Step(95): len = 413898, overlap = 246.438
+PHY-3002 : Step(96): len = 416898, overlap = 239.812
+PHY-3002 : Step(97): len = 419176, overlap = 240.062
+PHY-3002 : Step(98): len = 415426, overlap = 238.469
+PHY-3002 : Step(99): len = 416274, overlap = 235.406
+PHY-3002 : Step(100): len = 417517, overlap = 236.812
+PHY-3002 : Step(101): len = 419044, overlap = 239.375
+PHY-3002 : Step(102): len = 416791, overlap = 244.75
+PHY-3002 : Step(103): len = 417189, overlap = 245.188
+PHY-3002 : Step(104): len = 418923, overlap = 254.781
+PHY-3002 : Step(105): len = 421078, overlap = 257.438
+PHY-3002 : Step(106): len = 419013, overlap = 255.562
+PHY-3002 : Step(107): len = 418639, overlap = 259.906
+PHY-3002 : Step(108): len = 419146, overlap = 266.062
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000134154
+PHY-3002 : Step(109): len = 431505, overlap = 257.469
+PHY-3002 : Step(110): len = 440879, overlap = 250.688
+PHY-3002 : Step(111): len = 441298, overlap = 229.875
+PHY-3002 : Step(112): len = 442293, overlap = 235.375
+PHY-3002 : Step(113): len = 445370, overlap = 229.219
+PHY-3002 : Step(114): len = 449179, overlap = 226.5
+PHY-3002 : Step(115): len = 446668, overlap = 221
+PHY-3002 : Step(116): len = 447556, overlap = 211.156
+PHY-3002 : Step(117): len = 449418, overlap = 222.781
+PHY-3002 : Step(118): len = 450558, overlap = 220.906
+PHY-3002 : Step(119): len = 448911, overlap = 211.75
+PHY-3002 : Step(120): len = 449284, overlap = 201.781
+PHY-3002 : Step(121): len = 450400, overlap = 214.188
+PHY-3002 : Step(122): len = 451364, overlap = 217.312
+PHY-3002 : Step(123): len = 449440, overlap = 215.844
+PHY-3002 : Step(124): len = 448916, overlap = 219.594
+PHY-3002 : Step(125): len = 450069, overlap = 219.938
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000268307
+PHY-3002 : Step(126): len = 459821, overlap = 207.125
+PHY-3002 : Step(127): len = 466379, overlap = 202.312
+PHY-3002 : Step(128): len = 466999, overlap = 197.594
+PHY-3002 : Step(129): len = 468577, overlap = 184.438
+PHY-3002 : Step(130): len = 472633, overlap = 196.438
+PHY-3002 : Step(131): len = 475447, overlap = 191.312
+PHY-3002 : Step(132): len = 473546, overlap = 187.438
+PHY-3002 : Step(133): len = 473765, overlap = 184.75
+PHY-3002 : Step(134): len = 476581, overlap = 184.406
+PHY-3002 : Step(135): len = 478333, overlap = 184.25
+PHY-3002 : Step(136): len = 476631, overlap = 181.281
+PHY-3002 : Step(137): len = 476799, overlap = 180.969
+PHY-3002 : Step(138): len = 478690, overlap = 178.625
+PHY-3002 : Step(139): len = 479723, overlap = 178
+PHY-3002 : Step(140): len = 478314, overlap = 176.281
+PHY-3002 : Step(141): len = 478313, overlap = 179.719
+PHY-3002 : Step(142): len = 479310, overlap = 174.844
+PHY-3002 : Step(143): len = 480156, overlap = 170.531
+PHY-3002 : Step(144): len = 479474, overlap = 163.188
+PHY-3002 : Step(145): len = 480088, overlap = 163.312
+PHY-3002 : Step(146): len = 480953, overlap = 164.375
+PHY-3002 : Step(147): len = 481413, overlap = 162.312
+PHY-3002 : Step(148): len = 480206, overlap = 160.969
+PHY-3002 : Step(149): len = 480354, overlap = 159.594
+PHY-3002 : Step(150): len = 481008, overlap = 155.75
+PHY-3002 : Step(151): len = 481603, overlap = 157
+PHY-3002 : Step(152): len = 481404, overlap = 152.969
+PHY-3002 : Step(153): len = 482179, overlap = 154.031
+PHY-3002 : Step(154): len = 483416, overlap = 151.406
+PHY-3002 : Step(155): len = 484103, overlap = 156.531
+PHY-3002 : Step(156): len = 482501, overlap = 154.531
+PHY-3002 : Step(157): len = 482088, overlap = 156.062
+PHY-3002 : Step(158): len = 482780, overlap = 154.031
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000531942
+PHY-3002 : Step(159): len = 489167, overlap = 154.906
+PHY-3002 : Step(160): len = 495990, overlap = 147.812
+PHY-3002 : Step(161): len = 497319, overlap = 146.094
+PHY-3002 : Step(162): len = 498304, overlap = 145.688
+PHY-3002 : Step(163): len = 499636, overlap = 136.219
+PHY-3002 : Step(164): len = 500474, overlap = 134.469
+PHY-3002 : Step(165): len = 500036, overlap = 136.562
+PHY-3002 : Step(166): len = 500088, overlap = 135.438
+PHY-3002 : Step(167): len = 500934, overlap = 138.5
+PHY-3002 : Step(168): len = 501913, overlap = 139.188
+PHY-3002 : Step(169): len = 501647, overlap = 135.188
+PHY-3002 : Step(170): len = 501651, overlap = 134.031
+PHY-3002 : Step(171): len = 501873, overlap = 132.188
+PHY-3002 : Step(172): len = 502077, overlap = 131.062
+PHY-3002 : Step(173): len = 501924, overlap = 127.188
+PHY-3002 : Step(174): len = 501991, overlap = 126.375
+PHY-3002 : Step(175): len = 502190, overlap = 127.156
+PHY-3002 : Step(176): len = 502327, overlap = 125.688
+PHY-3002 : Step(177): len = 502241, overlap = 124.844
+PHY-3002 : Step(178): len = 502253, overlap = 124.531
+PHY-3002 : Step(179): len = 502377, overlap = 121.5
+PHY-3002 : Step(180): len = 502401, overlap = 121.438
+PHY-3002 : Step(181): len = 502240, overlap = 119.25
+PHY-3002 : Step(182): len = 502285, overlap = 117.375
+PHY-3002 : Step(183): len = 502265, overlap = 115.375
+PHY-3002 : Step(184): len = 502421, overlap = 112.625
+PHY-3002 : Step(185): len = 502482, overlap = 113.969
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00097135
+PHY-3002 : Step(186): len = 505377, overlap = 110.469
+PHY-3002 : Step(187): len = 509966, overlap = 106.719
+PHY-3002 : Step(188): len = 511931, overlap = 108.125
+PHY-3002 : Step(189): len = 513463, overlap = 109.531
+PHY-3002 : Step(190): len = 514556, overlap = 104.812
+PHY-3002 : Step(191): len = 515019, overlap = 103.594
+PHY-3002 : Step(192): len = 514642, overlap = 106.938
+PHY-3002 : Step(193): len = 514631, overlap = 106.938
+PHY-3002 : Step(194): len = 515080, overlap = 106.781
+PHY-3002 : Step(195): len = 515205, overlap = 106.688
+PHY-3002 : Step(196): len = 515438, overlap = 105.781
+PHY-3002 : Step(197): len = 516032, overlap = 104.781
+PHY-3002 : Step(198): len = 516282, overlap = 106.188
+PHY-3002 : Step(199): len = 516333, overlap = 107.25
+PHY-3002 : Step(200): len = 516356, overlap = 106.188
+PHY-3002 : Step(201): len = 516726, overlap = 104.094
+PHY-3002 : Step(202): len = 516942, overlap = 106.281
+PHY-3002 : Step(203): len = 517051, overlap = 106.656
+PHY-3002 : Step(204): len = 517420, overlap = 107.188
+PHY-3002 : Step(205): len = 518358, overlap = 103.625
+PHY-3002 : Step(206): len = 519124, overlap = 104.469
+PHY-3002 : Step(207): len = 519656, overlap = 105
+PHY-3002 : Step(208): len = 519434, overlap = 106.5
+PHY-3002 : Step(209): len = 519329, overlap = 106.5
+PHY-3002 : Step(210): len = 519181, overlap = 106.5
+PHY-3002 : Step(211): len = 519341, overlap = 104.75
+PHY-3002 : Step(212): len = 519819, overlap = 106.5
+PHY-3002 : Step(213): len = 520433, overlap = 111
+PHY-3002 : Step(214): len = 520862, overlap = 110.25
+PHY-3002 : Step(215): len = 521069, overlap = 110.25
+PHY-3002 : Step(216): len = 521123, overlap = 105.969
+PHY-3002 : Step(217): len = 521264, overlap = 105.969
+PHY-3002 : Step(218): len = 521347, overlap = 109.406
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00179389
+PHY-3002 : Step(219): len = 523386, overlap = 111.25
+PHY-3002 : Step(220): len = 526149, overlap = 112.312
+PHY-3002 : Step(221): len = 527026, overlap = 111.312
+PHY-3002 : Step(222): len = 527690, overlap = 110.406
+PHY-3002 : Step(223): len = 528598, overlap = 111.812
+PHY-3002 : Step(224): len = 529005, overlap = 111.812
+PHY-3002 : Step(225): len = 529392, overlap = 111.688
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.015871s wall, 0.015625s user + 0.046875s system = 0.062500s CPU (393.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20347.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 687512, over cnt = 1570(4%), over = 7433, worst = 68
+PHY-1001 : End global iterations; 0.726460s wall, 0.984375s user + 0.062500s system = 1.046875s CPU (144.1%)
+
+PHY-1001 : Congestion index: top1 = 75.80, top5 = 58.73, top10 = 50.53, top15 = 45.59.
+PHY-3001 : End congestion estimation; 0.942976s wall, 1.218750s user + 0.062500s system = 1.281250s CPU (135.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20169 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.891716s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000118846
+PHY-3002 : Step(226): len = 615390, overlap = 76.25
+PHY-3002 : Step(227): len = 613815, overlap = 73.2188
+PHY-3002 : Step(228): len = 612471, overlap = 67.3125
+PHY-3002 : Step(229): len = 614040, overlap = 58.8125
+PHY-3002 : Step(230): len = 614806, overlap = 57.9375
+PHY-3002 : Step(231): len = 614714, overlap = 51.0938
+PHY-3002 : Step(232): len = 611198, overlap = 49.25
+PHY-3002 : Step(233): len = 610134, overlap = 45.3125
+PHY-3002 : Step(234): len = 608955, overlap = 46.5312
+PHY-3002 : Step(235): len = 607653, overlap = 48.0938
+PHY-3002 : Step(236): len = 605839, overlap = 48.5625
+PHY-3002 : Step(237): len = 605024, overlap = 45.2812
+PHY-3002 : Step(238): len = 603510, overlap = 44.75
+PHY-3002 : Step(239): len = 602235, overlap = 40.9062
+PHY-3002 : Step(240): len = 602702, overlap = 40.8125
+PHY-3002 : Step(241): len = 601022, overlap = 40.7812
+PHY-3002 : Step(242): len = 600156, overlap = 40.8125
+PHY-3002 : Step(243): len = 599931, overlap = 40.7188
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000237692
+PHY-3002 : Step(244): len = 603069, overlap = 41.6562
+PHY-3002 : Step(245): len = 604697, overlap = 42.125
+PHY-3002 : Step(246): len = 607120, overlap = 42.7812
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000397734
+PHY-3002 : Step(247): len = 614259, overlap = 44.8438
+PHY-3002 : Step(248): len = 621126, overlap = 45.9375
+PHY-3002 : Step(249): len = 625511, overlap = 43.5312
+PHY-3002 : Step(250): len = 632105, overlap = 41.8438
+PHY-3002 : Step(251): len = 637683, overlap = 40.4375
+PHY-3002 : Step(252): len = 637128, overlap = 39.2188
+PHY-3002 : Step(253): len = 637357, overlap = 38.4062
+PHY-3002 : Step(254): len = 635494, overlap = 38.0625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 99/20347.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 723864, over cnt = 2683(7%), over = 12208, worst = 79
+PHY-1001 : End global iterations; 1.703307s wall, 2.296875s user + 0.046875s system = 2.343750s CPU (137.6%)
+
+PHY-1001 : Congestion index: top1 = 83.12, top5 = 65.38, top10 = 57.15, top15 = 52.23.
+PHY-3001 : End congestion estimation; 1.973220s wall, 2.546875s user + 0.062500s system = 2.609375s CPU (132.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20169 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.907065s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000105055
+PHY-3002 : Step(255): len = 629859, overlap = 253.375
+PHY-3002 : Step(256): len = 632699, overlap = 220.062
+PHY-3002 : Step(257): len = 623828, overlap = 208.688
+PHY-3002 : Step(258): len = 619657, overlap = 191.5
+PHY-3002 : Step(259): len = 615953, overlap = 168.562
+PHY-3002 : Step(260): len = 613731, overlap = 156.125
+PHY-3002 : Step(261): len = 609379, overlap = 149.844
+PHY-3002 : Step(262): len = 607673, overlap = 146.219
+PHY-3002 : Step(263): len = 604368, overlap = 148.344
+PHY-3002 : Step(264): len = 602640, overlap = 143.688
+PHY-3002 : Step(265): len = 601333, overlap = 137.531
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00021011
+PHY-3002 : Step(266): len = 601502, overlap = 136.281
+PHY-3002 : Step(267): len = 604337, overlap = 131.062
+PHY-3002 : Step(268): len = 608517, overlap = 123.656
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00042022
+PHY-3002 : Step(269): len = 613597, overlap = 117.219
+PHY-3002 : Step(270): len = 617608, overlap = 111.625
+PHY-3002 : Step(271): len = 621477, overlap = 105.938
+PHY-3002 : Step(272): len = 623507, overlap = 101.469
+PHY-3002 : Step(273): len = 624983, overlap = 97.25
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84883, tnet num: 20169, tinst num: 17767, tnode num: 115270, tedge num: 136158.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.510592s wall, 1.453125s user + 0.046875s system = 1.500000s CPU (99.3%)
+
+RUN-1004 : used memory is 574 MB, reserved memory is 564 MB, peak memory is 710 MB
+OPT-1001 : Total overflow 438.38 peak overflow 6.28
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1058/20347.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 721992, over cnt = 2936(8%), over = 10548, worst = 23
+PHY-1001 : End global iterations; 1.292151s wall, 1.843750s user + 0.031250s system = 1.875000s CPU (145.1%)
+
+PHY-1001 : Congestion index: top1 = 64.74, top5 = 54.94, top10 = 49.30, top15 = 45.84.
+PHY-1001 : End incremental global routing; 1.640313s wall, 2.203125s user + 0.031250s system = 2.234375s CPU (136.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20169 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.951778s wall, 0.906250s user + 0.046875s system = 0.953125s CPU (100.1%)
+
+OPT-1001 : 53 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17629 has valid locations, 338 needs to be replaced
+PHY-3001 : design contains 18052 instances, 7512 luts, 9319 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 6074 pins
+PHY-3001 : Found 1241 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 648852
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16516/20632.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 736920, over cnt = 3020(8%), over = 10641, worst = 23
+PHY-1001 : End global iterations; 0.267916s wall, 0.375000s user + 0.015625s system = 0.390625s CPU (145.8%)
+
+PHY-1001 : Congestion index: top1 = 65.28, top5 = 55.36, top10 = 49.91, top15 = 46.48.
+PHY-3001 : End congestion estimation; 0.548798s wall, 0.625000s user + 0.046875s system = 0.671875s CPU (122.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86041, tnet num: 20454, tinst num: 18052, tnode num: 116985, tedge num: 137904.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.484621s wall, 1.468750s user + 0.015625s system = 1.484375s CPU (100.0%)
+
+RUN-1004 : used memory is 620 MB, reserved memory is 623 MB, peak memory is 714 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20454 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.473220s wall, 2.453125s user + 0.031250s system = 2.484375s CPU (100.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(274): len = 648114, overlap = 0
+PHY-3002 : Step(275): len = 647860, overlap = 0
+PHY-3002 : Step(276): len = 647677, overlap = 0
+PHY-3002 : Step(277): len = 647393, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16633/20632.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 734456, over cnt = 3000(8%), over = 10682, worst = 23
+PHY-1001 : End global iterations; 0.201312s wall, 0.312500s user + 0.031250s system = 0.343750s CPU (170.8%)
+
+PHY-1001 : Congestion index: top1 = 65.50, top5 = 55.64, top10 = 50.04, top15 = 46.63.
+PHY-3001 : End congestion estimation; 0.470321s wall, 0.578125s user + 0.031250s system = 0.609375s CPU (129.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20454 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.955798s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000292668
+PHY-3002 : Step(278): len = 647326, overlap = 98.8125
+PHY-3002 : Step(279): len = 647435, overlap = 98.2188
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000585336
+PHY-3002 : Step(280): len = 647697, overlap = 98.5938
+PHY-3002 : Step(281): len = 647980, overlap = 99.125
+PHY-3001 : Final: Len = 647980, Over = 99.125
+PHY-3001 : End incremental placement; 5.245051s wall, 5.640625s user + 0.390625s system = 6.031250s CPU (115.0%)
+
+OPT-1001 : Total overflow 443.84 peak overflow 6.28
+OPT-1001 : End high-fanout net optimization; 8.582002s wall, 9.609375s user + 0.468750s system = 10.078125s CPU (117.4%)
+
+OPT-1001 : Current memory(MB): used = 716, reserve = 710, peak = 733.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16576/20632.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 737864, over cnt = 2933(8%), over = 9656, worst = 23
+PHY-1002 : len = 780288, over cnt = 2058(5%), over = 5310, worst = 19
+PHY-1002 : len = 817928, over cnt = 927(2%), over = 2329, worst = 19
+PHY-1002 : len = 843024, over cnt = 312(0%), over = 687, worst = 11
+PHY-1002 : len = 854264, over cnt = 15(0%), over = 23, worst = 4
+PHY-1001 : End global iterations; 1.536054s wall, 2.312500s user + 0.000000s system = 2.312500s CPU (150.5%)
+
+PHY-1001 : Congestion index: top1 = 55.80, top5 = 49.54, top10 = 45.94, top15 = 43.66.
+OPT-1001 : End congestion update; 1.822368s wall, 2.609375s user + 0.000000s system = 2.609375s CPU (143.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20454 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.819039s wall, 0.796875s user + 0.015625s system = 0.812500s CPU (99.2%)
+
+OPT-0007 : Start: WNS -1068 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 54 cells processed and 6400 slack improved
+OPT-0007 : Iter 2: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 21 cells processed and 758 slack improved
+OPT-0007 : Iter 3: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 7 cells processed and 618 slack improved
+OPT-1001 : End global optimization; 2.686894s wall, 3.453125s user + 0.015625s system = 3.468750s CPU (129.1%)
+
+OPT-1001 : Current memory(MB): used = 694, reserve = 693, peak = 733.
+OPT-1001 : End physical optimization; 13.427292s wall, 15.265625s user + 0.546875s system = 15.812500s CPU (117.8%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7512 LUT to BLE ...
+SYN-4008 : Packed 7512 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6186 remaining SEQ's ...
+SYN-4005 : Packed 3744 SEQ with LUT/SLICE
+SYN-4006 : 942 single LUT's are left
+SYN-4006 : 2442 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9954/13685 primitive instances ...
+PHY-3001 : End packing; 1.734578s wall, 1.703125s user + 0.015625s system = 1.718750s CPU (99.1%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6875 instances
+RUN-1001 : 3363 mslices, 3364 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17630 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9960 nets have 2 pins
+RUN-1001 : 6009 nets have [3 - 5] pins
+RUN-1001 : 969 nets have [6 - 10] pins
+RUN-1001 : 312 nets have [11 - 20] pins
+RUN-1001 : 348 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6873 instances, 6727 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3602 pins
+PHY-3001 : Found 481 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 659659, Over = 278.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7396/17630.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 805864, over cnt = 1931(5%), over = 3205, worst = 9
+PHY-1002 : len = 813904, over cnt = 1308(3%), over = 1921, worst = 6
+PHY-1002 : len = 827712, over cnt = 552(1%), over = 781, worst = 6
+PHY-1002 : len = 833824, over cnt = 304(0%), over = 442, worst = 6
+PHY-1002 : len = 841384, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.637626s wall, 2.359375s user + 0.031250s system = 2.390625s CPU (146.0%)
+
+PHY-1001 : Congestion index: top1 = 57.63, top5 = 50.02, top10 = 46.13, top15 = 43.65.
+PHY-3001 : End congestion estimation; 2.060763s wall, 2.765625s user + 0.046875s system = 2.812500s CPU (136.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73874, tnet num: 17452, tinst num: 6873, tnode num: 96518, tedge num: 124043.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.672651s wall, 1.640625s user + 0.031250s system = 1.671875s CPU (100.0%)
+
+RUN-1004 : used memory is 613 MB, reserved memory is 613 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.574749s wall, 2.531250s user + 0.046875s system = 2.578125s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.44519e-05
+PHY-3002 : Step(282): len = 647892, overlap = 277
+PHY-3002 : Step(283): len = 641203, overlap = 267.75
+PHY-3002 : Step(284): len = 637835, overlap = 278
+PHY-3002 : Step(285): len = 635472, overlap = 278
+PHY-3002 : Step(286): len = 633367, overlap = 285.75
+PHY-3002 : Step(287): len = 631446, overlap = 289
+PHY-3002 : Step(288): len = 629493, overlap = 285.25
+PHY-3002 : Step(289): len = 628133, overlap = 285.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.89037e-05
+PHY-3002 : Step(290): len = 631759, overlap = 273
+PHY-3002 : Step(291): len = 635801, overlap = 265.25
+PHY-3002 : Step(292): len = 635922, overlap = 267.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000177807
+PHY-3002 : Step(293): len = 644928, overlap = 264
+PHY-3002 : Step(294): len = 654305, overlap = 254.5
+PHY-3002 : Step(295): len = 653237, overlap = 252.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.404895s wall, 0.437500s user + 0.578125s system = 1.015625s CPU (250.8%)
+
+PHY-3001 : Trial Legalized: Len = 746215
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 696/17630.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862256, over cnt = 2756(7%), over = 4823, worst = 8
+PHY-1002 : len = 879112, over cnt = 1767(5%), over = 2751, worst = 7
+PHY-1002 : len = 898928, over cnt = 760(2%), over = 1215, worst = 7
+PHY-1002 : len = 916048, over cnt = 148(0%), over = 248, worst = 6
+PHY-1002 : len = 920112, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.687253s wall, 3.718750s user + 0.015625s system = 3.734375s CPU (139.0%)
+
+PHY-1001 : Congestion index: top1 = 55.73, top5 = 50.24, top10 = 47.40, top15 = 45.39.
+PHY-3001 : End congestion estimation; 3.174915s wall, 4.218750s user + 0.015625s system = 4.234375s CPU (133.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.953084s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000152443
+PHY-3002 : Step(296): len = 716726, overlap = 43.25
+PHY-3002 : Step(297): len = 701246, overlap = 71.75
+PHY-3002 : Step(298): len = 687462, overlap = 102.5
+PHY-3002 : Step(299): len = 678901, overlap = 121.75
+PHY-3002 : Step(300): len = 673061, overlap = 135.75
+PHY-3002 : Step(301): len = 669780, overlap = 155
+PHY-3002 : Step(302): len = 668113, overlap = 158
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000304886
+PHY-3002 : Step(303): len = 673790, overlap = 154.25
+PHY-3002 : Step(304): len = 680571, overlap = 156
+PHY-3002 : Step(305): len = 682411, overlap = 158
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000609772
+PHY-3002 : Step(306): len = 687713, overlap = 154
+PHY-3002 : Step(307): len = 699954, overlap = 148.5
+PHY-3002 : Step(308): len = 701108, overlap = 143.25
+PHY-3002 : Step(309): len = 701234, overlap = 150.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.041409s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (113.2%)
+
+PHY-3001 : Legalized: Len = 732439, Over = 0
+PHY-3001 : Spreading special nets. 425 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.109806s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (99.6%)
+
+PHY-3001 : 631 instances has been re-located, deltaX = 236, deltaY = 358, maxDist = 3.
+PHY-3001 : Final: Len = 743019, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73874, tnet num: 17452, tinst num: 6876, tnode num: 96518, tedge num: 124043.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.932828s wall, 1.921875s user + 0.015625s system = 1.937500s CPU (100.2%)
+
+RUN-1004 : used memory is 628 MB, reserved memory is 650 MB, peak memory is 733 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3333/17630.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874176, over cnt = 2554(7%), over = 4283, worst = 9
+PHY-1002 : len = 891928, over cnt = 1426(4%), over = 1980, worst = 7
+PHY-1002 : len = 904768, over cnt = 698(1%), over = 931, worst = 7
+PHY-1002 : len = 912904, over cnt = 293(0%), over = 381, worst = 5
+PHY-1002 : len = 919680, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.146403s wall, 3.234375s user + 0.062500s system = 3.296875s CPU (153.6%)
+
+PHY-1001 : Congestion index: top1 = 53.28, top5 = 49.04, top10 = 46.24, top15 = 44.32.
+PHY-1001 : End incremental global routing; 2.548851s wall, 3.625000s user + 0.062500s system = 3.687500s CPU (144.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.911472s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (101.1%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6783 has valid locations, 23 needs to be replaced
+PHY-3001 : design contains 6894 instances, 6745 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3664 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 746415
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16025/17648.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 923288, over cnt = 90(0%), over = 104, worst = 5
+PHY-1002 : len = 923312, over cnt = 67(0%), over = 71, worst = 2
+PHY-1002 : len = 923736, over cnt = 16(0%), over = 16, worst = 1
+PHY-1002 : len = 923920, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 924048, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.804087s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (104.9%)
+
+PHY-1001 : Congestion index: top1 = 53.36, top5 = 49.04, top10 = 46.29, top15 = 44.40.
+PHY-3001 : End congestion estimation; 1.137480s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (103.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74041, tnet num: 17470, tinst num: 6894, tnode num: 96705, tedge num: 124247.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.963190s wall, 1.953125s user + 0.015625s system = 1.968750s CPU (100.3%)
+
+RUN-1004 : used memory is 657 MB, reserved memory is 663 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17470 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.921349s wall, 2.875000s user + 0.046875s system = 2.921875s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(310): len = 745893, overlap = 0
+PHY-3002 : Step(311): len = 745299, overlap = 0
+PHY-3002 : Step(312): len = 745147, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16016/17648.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 921880, over cnt = 84(0%), over = 104, worst = 6
+PHY-1002 : len = 922008, over cnt = 37(0%), over = 44, worst = 5
+PHY-1002 : len = 922552, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 922664, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.653780s wall, 0.687500s user + 0.015625s system = 0.703125s CPU (107.5%)
+
+PHY-1001 : Congestion index: top1 = 53.34, top5 = 49.02, top10 = 46.22, top15 = 44.35.
+PHY-3001 : End congestion estimation; 0.983475s wall, 1.015625s user + 0.015625s system = 1.031250s CPU (104.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17470 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.909621s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000894785
+PHY-3002 : Step(313): len = 745462, overlap = 1
+PHY-3002 : Step(314): len = 745459, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005932s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (263.4%)
+
+PHY-3001 : Legalized: Len = 745629, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065276s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.7%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 0, deltaY = 3, maxDist = 1.
+PHY-3001 : Final: Len = 745657, Over = 0
+PHY-3001 : End incremental placement; 6.508761s wall, 6.562500s user + 0.187500s system = 6.750000s CPU (103.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.501334s wall, 11.625000s user + 0.265625s system = 11.890625s CPU (113.2%)
+
+OPT-1001 : Current memory(MB): used = 735, reserve = 737, peak = 738.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16006/17648.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 922704, over cnt = 69(0%), over = 98, worst = 5
+PHY-1002 : len = 922904, over cnt = 40(0%), over = 49, worst = 3
+PHY-1002 : len = 923136, over cnt = 21(0%), over = 22, worst = 2
+PHY-1002 : len = 923304, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.625394s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (104.9%)
+
+PHY-1001 : Congestion index: top1 = 53.34, top5 = 49.03, top10 = 46.24, top15 = 44.36.
+OPT-1001 : End congestion update; 0.962340s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (103.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17470 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.743195s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.8%)
+
+OPT-0007 : Start: WNS -997 TNS -1532 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6806 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6894 instances, 6745 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3664 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 750477, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063978s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.7%)
+
+PHY-3001 : 18 instances has been re-located, deltaX = 9, deltaY = 11, maxDist = 3.
+PHY-3001 : Final: Len = 750505, Over = 0
+PHY-3001 : End incremental legalization; 0.413340s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (98.3%)
+
+OPT-0007 : Iter 1: improved WNS -997 TNS -1532 NUM_FEPS 2 with 22 cells processed and 8095 slack improved
+OPT-0007 : Iter 2: improved WNS -997 TNS -1532 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.257973s wall, 2.343750s user + 0.000000s system = 2.343750s CPU (103.8%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 737, peak = 739.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17470 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.746555s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.4%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15922/17648.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928008, over cnt = 58(0%), over = 67, worst = 3
+PHY-1002 : len = 927984, over cnt = 29(0%), over = 29, worst = 1
+PHY-1002 : len = 928192, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 928256, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 928272, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.892479s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (103.3%)
+
+PHY-1001 : Congestion index: top1 = 53.45, top5 = 48.98, top10 = 46.14, top15 = 44.32.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17470 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.745703s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.5%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -997 TNS -1532 NUM_FEPS 2
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 52.965517
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -997ps with logic level 2
+RUN-1001 : extra opt step will be enabled to improve QoR
+RUN-1001 : 0 HFN exist on timing critical paths out of 17648 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 17648 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6806 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6894 instances, 6745 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3664 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 750505, Over = 0
+PHY-3001 : End spreading; 0.062045s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.7%)
+
+PHY-3001 : Final: Len = 750505, Over = 0
+PHY-3001 : End incremental legalization; 0.410441s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17470 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.773696s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (101.0%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16045/17648.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928272, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.136732s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.8%)
+
+PHY-1001 : Congestion index: top1 = 53.45, top5 = 48.98, top10 = 46.14, top15 = 44.32.
+OPT-1001 : End congestion update; 0.482507s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (100.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17470 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.744952s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.6%)
+
+OPT-0007 : Start: WNS -997 TNS -1532 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6806 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6894 instances, 6745 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3664 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 750509, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063451s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.5%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 750505, Over = 0
+PHY-3001 : End incremental legalization; 0.411696s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (102.5%)
+
+OPT-0007 : Iter 1: improved WNS -947 TNS -1432 NUM_FEPS 2 with 1 cells processed and 50 slack improved
+OPT-0007 : Iter 2: improved WNS -947 TNS -1432 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.764416s wall, 1.796875s user + 0.000000s system = 1.796875s CPU (101.8%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 737, peak = 739.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16045/17648.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928272, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.139397s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.9%)
+
+PHY-1001 : Congestion index: top1 = 53.45, top5 = 48.98, top10 = 46.14, top15 = 44.32.
+OPT-1001 : End congestion update; 0.471700s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (99.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17470 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.744527s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.7%)
+
+OPT-0007 : Start: WNS -997 TNS -1532 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -997 TNS -1532 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 2: improved WNS -997 TNS -1532 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 1.383618s wall, 1.375000s user + 0.000000s system = 1.375000s CPU (99.4%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 737, peak = 739.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17470 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.743538s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.9%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 736, reserve = 737, peak = 739.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17470 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.743916s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.7%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16045/17648.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928272, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.140829s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.9%)
+
+PHY-1001 : Congestion index: top1 = 53.45, top5 = 48.98, top10 = 46.14, top15 = 44.32.
+RUN-1001 : End congestion update; 0.478077s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (98.0%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.225744s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (99.4%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 737, peak = 739.
+OPT-1001 : End physical optimization; 24.242899s wall, 25.468750s user + 0.312500s system = 25.781250s CPU (106.3%)
+
+RUN-1003 : finish command "place" in 70.069894s wall, 100.734375s user + 7.375000s system = 108.109375s CPU (154.3%)
+
+RUN-1004 : used memory is 643 MB, reserved memory is 638 MB, peak memory is 739 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.727563s wall, 2.968750s user + 0.031250s system = 3.000000s CPU (173.7%)
+
+RUN-1004 : used memory is 643 MB, reserved memory is 639 MB, peak memory is 739 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6896 instances
+RUN-1001 : 3374 mslices, 3371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17648 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9958 nets have 2 pins
+RUN-1001 : 6005 nets have [3 - 5] pins
+RUN-1001 : 974 nets have [6 - 10] pins
+RUN-1001 : 322 nets have [11 - 20] pins
+RUN-1001 : 360 nets have [21 - 99] pins
+RUN-1001 : 9 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74041, tnet num: 17470, tinst num: 6894, tnode num: 96705, tedge num: 124247.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.639220s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (100.1%)
+
+RUN-1004 : used memory is 653 MB, reserved memory is 662 MB, peak memory is 739 MB
+PHY-1001 : 3374 mslices, 3371 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17470 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 859984, over cnt = 2773(7%), over = 4629, worst = 8
+PHY-1002 : len = 877552, over cnt = 1702(4%), over = 2561, worst = 8
+PHY-1002 : len = 893576, over cnt = 902(2%), over = 1365, worst = 8
+PHY-1002 : len = 914232, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 914632, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.123860s wall, 4.203125s user + 0.031250s system = 4.234375s CPU (135.5%)
+
+PHY-1001 : Congestion index: top1 = 53.25, top5 = 48.47, top10 = 45.67, top15 = 43.83.
+PHY-1001 : End global routing; 3.492832s wall, 4.578125s user + 0.031250s system = 4.609375s CPU (132.0%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 712, reserve = 716, peak = 739.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 988, reserve = 989, peak = 988.
+PHY-1001 : End build detailed router design. 4.035019s wall, 4.000000s user + 0.046875s system = 4.046875s CPU (100.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 263792, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 6.277392s wall, 6.250000s user + 0.015625s system = 6.265625s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 263848, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.487244s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (102.6%)
+
+PHY-1001 : Current memory(MB): used = 1023, reserve = 1025, peak = 1023.
+PHY-1001 : End phase 1; 6.777770s wall, 6.750000s user + 0.015625s system = 6.765625s CPU (99.8%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.33118e+06, over cnt = 1873(0%), over = 1887, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1039, reserve = 1041, peak = 1039.
+PHY-1001 : End initial routed; 33.324667s wall, 69.953125s user + 0.593750s system = 70.546875s CPU (211.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16571(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.923 | -3.946 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.407293s wall, 3.390625s user + 0.000000s system = 3.390625s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1053, reserve = 1056, peak = 1054.
+PHY-1001 : End phase 2; 36.732029s wall, 73.343750s user + 0.593750s system = 73.937500s CPU (201.3%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.921ns STNS -3.805ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.141532s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.4%)
+
+PHY-1022 : len = 2.3312e+06, over cnt = 1876(0%), over = 1890, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.426241s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (102.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.29872e+06, over cnt = 642(0%), over = 642, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.804310s wall, 3.578125s user + 0.000000s system = 3.578125s CPU (198.3%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.29651e+06, over cnt = 189(0%), over = 189, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.594998s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (154.9%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.29745e+06, over cnt = 16(0%), over = 16, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.508360s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (116.8%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.29761e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.225773s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (96.9%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.29774e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.208200s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (97.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16571(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.921 | -3.805 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.360221s wall, 3.359375s user + 0.000000s system = 3.359375s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 561 feed throughs used by 414 nets
+PHY-1001 : End commit to database; 2.300262s wall, 2.296875s user + 0.015625s system = 2.312500s CPU (100.5%)
+
+PHY-1001 : Current memory(MB): used = 1154, reserve = 1159, peak = 1154.
+PHY-1001 : End phase 3; 9.824432s wall, 12.000000s user + 0.015625s system = 12.015625s CPU (122.3%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.802ns STNS -3.686ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.146398s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (106.7%)
+
+PHY-1022 : len = 2.29774e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.409615s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.2%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.802ns, -3.686ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16571(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.802 | -3.686 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.351138s wall, 3.343750s user + 0.000000s system = 3.343750s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 562 feed throughs used by 415 nets
+PHY-1001 : End commit to database; 2.367618s wall, 2.375000s user + 0.000000s system = 2.375000s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1163, reserve = 1169, peak = 1163.
+PHY-1001 : End phase 4; 6.156385s wall, 6.156250s user + 0.000000s system = 6.156250s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.29774e+06
+PHY-1001 : Current memory(MB): used = 1164, reserve = 1171, peak = 1164.
+PHY-1001 : End export database. 0.064374s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (121.4%)
+
+PHY-1001 : End detail routing; 64.000398s wall, 102.718750s user + 0.671875s system = 103.390625s CPU (161.5%)
+
+RUN-1003 : finish command "route" in 70.244243s wall, 110.015625s user + 0.718750s system = 110.734375s CPU (157.6%)
+
+RUN-1004 : used memory is 1090 MB, reserved memory is 1099 MB, peak memory is 1165 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10265 out of 19600 52.37%
+#reg 9457 out of 19600 48.25%
+#le 12633
+ #lut only 3176 out of 12633 25.14%
+ #reg only 2368 out of 12633 18.74%
+ #lut® 7089 out of 12633 56.11%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 20
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1866
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1405
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1338
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 934
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 140
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 71
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 67
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 25
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/reg9_syn_131.f0 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg63_syn_222.f0 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P141 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P17 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P25 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P16 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P109 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P91 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P32 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P35 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12633 |9238 |1027 |9490 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |555 |468 |23 |443 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |95 |85 |4 |88 |4 |0 |
+| U_ecc_gen |ecc_gen |14 |14 |0 |8 |0 |0 |
+| U_crc16_24b |crc16_24b |31 |31 |0 |20 |0 |0 |
+| exdev_ctl_a |exdev_ctl |786 |407 |96 |590 |0 |0 |
+| u_ADconfig |AD_config |191 |119 |25 |142 |0 |0 |
+| u_gen_sp |gen_sp |265 |173 |71 |118 |0 |0 |
+| exdev_ctl_b |exdev_ctl |740 |439 |96 |553 |0 |0 |
+| u_ADconfig |AD_config |177 |121 |25 |128 |0 |0 |
+| u_gen_sp |gen_sp |255 |164 |71 |117 |0 |0 |
+| sampling_fe_a |sampling_fe |3166 |2478 |306 |2112 |25 |0 |
+| u0_soft_n |cdc_sync |6 |4 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |177 |86 |17 |142 |0 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_sort |sort |2953 |2383 |289 |1934 |25 |0 |
+| rddpram_ctl |rddpram_ctl |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |0 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |7 |6 |0 |7 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2453 |2033 |253 |1535 |22 |0 |
+| channelPart |channel_part_8478 |158 |154 |3 |140 |0 |0 |
+| fifo_adc |fifo_adc |59 |50 |9 |43 |0 |0 |
+| ram_switch |ram_switch |1896 |1537 |197 |1115 |0 |0 |
+| adc_addr_gen |adc_addr_gen |230 |202 |27 |116 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |14 |10 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 |
+| insert |insert |940 |611 |170 |644 |0 |0 |
+| ram_switch_state |ram_switch_state |726 |724 |0 |355 |0 |0 |
+| read_ram_i |read_ram |309 |263 |44 |208 |0 |0 |
+| read_ram_addr |read_ram_addr |210 |170 |40 |146 |0 |0 |
+| read_ram_data |read_ram_data |97 |91 |4 |60 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |344 |222 |36 |278 |3 |0 |
+| u0_soft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3312 |2604 |349 |2133 |25 |1 |
+| u0_soft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |167 |117 |17 |132 |0 |0 |
+| u0_soft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u_sort |sort_rev |3111 |2472 |332 |1967 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |2 |1 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2626 |2121 |290 |1582 |22 |1 |
+| channelPart |channel_part_8478 |262 |257 |3 |140 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
+| ram_switch |ram_switch |1889 |1501 |197 |1150 |0 |0 |
+| adc_addr_gen |adc_addr_gen |225 |198 |27 |122 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |11 |8 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |21 |18 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |24 |21 |3 |15 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |28 |25 |3 |17 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |10 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| insert |insert |977 |621 |170 |671 |0 |0 |
+| ram_switch_state |ram_switch_state |687 |682 |0 |357 |0 |0 |
+| read_ram_i |read_ram_rev |397 |298 |81 |229 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |307 |225 |73 |171 |0 |0 |
+| read_ram_data |read_ram_data_rev |90 |73 |8 |58 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9896
+ #2 2 3874
+ #3 3 1475
+ #4 4 653
+ #5 5-10 1043
+ #6 11-50 589
+ #7 51-100 21
+ #8 101-500 1
+ #9 >500 1
+ Average 2.90
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.111604s wall, 3.593750s user + 0.015625s system = 3.609375s CPU (170.9%)
+
+RUN-1004 : used memory is 1092 MB, reserved memory is 1099 MB, peak memory is 1165 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74041, tnet num: 17470, tinst num: 6894, tnode num: 96705, tedge num: 124247.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.658702s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (99.9%)
+
+RUN-1004 : used memory is 1096 MB, reserved memory is 1103 MB, peak memory is 1165 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17470 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.525495s wall, 1.531250s user + 0.000000s system = 1.531250s CPU (100.4%)
+
+RUN-1004 : used memory is 1098 MB, reserved memory is 1105 MB, peak memory is 1165 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6894
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17648, pip num: 172208
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 562
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3247 valid insts, and 479506 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 10.784939s wall, 57.046875s user + 0.718750s system = 57.765625s CPU (535.6%)
+
+RUN-1004 : used memory is 1262 MB, reserved memory is 1266 MB, peak memory is 1377 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240219_102207.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240219_103630.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240219_103630.log
new file mode 100644
index 0000000..684f00f
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240219_103630.log
@@ -0,0 +1,2082 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Feb 19 10:36:30 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.171089s wall, 2.109375s user + 0.062500s system = 2.171875s CPU (100.0%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 315 MB, peak memory is 341 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17822 instances
+RUN-0007 : 7556 luts, 9043 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20400 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13420 nets have 2 pins
+RUN-1001 : 5507 nets have [3 - 5] pins
+RUN-1001 : 1060 nets have [6 - 10] pins
+RUN-1001 : 163 nets have [11 - 20] pins
+RUN-1001 : 176 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 807
+RUN-1001 : No | No | Yes | 1968
+RUN-1001 : No | Yes | No | 3459
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 55
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 140
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17820 instances, 7556 luts, 9043 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 5947 pins
+PHY-0007 : Cell area utilization is 49%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85233, tnet num: 20222, tinst num: 17820, tnode num: 115303, tedge num: 136752.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.223958s wall, 1.218750s user + 0.015625s system = 1.234375s CPU (100.9%)
+
+RUN-1004 : used memory is 530 MB, reserved memory is 514 MB, peak memory is 530 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20222 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.034780s wall, 2.000000s user + 0.015625s system = 2.015625s CPU (99.1%)
+
+PHY-3001 : Found 1223 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.10079e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17820.
+PHY-3001 : Level 1 #clusters 2009.
+PHY-3001 : End clustering; 0.139123s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (146.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 49%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.27417e+06, overlap = 469.75
+PHY-3002 : Step(2): len = 1.19275e+06, overlap = 528
+PHY-3002 : Step(3): len = 816963, overlap = 610
+PHY-3002 : Step(4): len = 770549, overlap = 634.688
+PHY-3002 : Step(5): len = 598753, overlap = 768.719
+PHY-3002 : Step(6): len = 516198, overlap = 794.031
+PHY-3002 : Step(7): len = 452307, overlap = 901.344
+PHY-3002 : Step(8): len = 419274, overlap = 986.719
+PHY-3002 : Step(9): len = 376905, overlap = 1047.19
+PHY-3002 : Step(10): len = 349665, overlap = 1083.59
+PHY-3002 : Step(11): len = 317414, overlap = 1137.91
+PHY-3002 : Step(12): len = 294297, overlap = 1175
+PHY-3002 : Step(13): len = 268750, overlap = 1192.06
+PHY-3002 : Step(14): len = 251191, overlap = 1274.72
+PHY-3002 : Step(15): len = 239493, overlap = 1338.53
+PHY-3002 : Step(16): len = 219855, overlap = 1377.34
+PHY-3002 : Step(17): len = 203892, overlap = 1392.09
+PHY-3002 : Step(18): len = 184139, overlap = 1411.03
+PHY-3002 : Step(19): len = 172411, overlap = 1426.75
+PHY-3002 : Step(20): len = 153975, overlap = 1442.41
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.04751e-06
+PHY-3002 : Step(21): len = 155571, overlap = 1420.66
+PHY-3002 : Step(22): len = 183474, overlap = 1332.53
+PHY-3002 : Step(23): len = 188592, overlap = 1267.38
+PHY-3002 : Step(24): len = 193755, overlap = 1166.53
+PHY-3002 : Step(25): len = 193374, overlap = 1154.38
+PHY-3002 : Step(26): len = 194165, overlap = 1125.5
+PHY-3002 : Step(27): len = 193285, overlap = 1113
+PHY-3002 : Step(28): len = 190906, overlap = 1152.03
+PHY-3002 : Step(29): len = 188212, overlap = 1157.5
+PHY-3002 : Step(30): len = 186963, overlap = 1149.5
+PHY-3002 : Step(31): len = 185251, overlap = 1138.75
+PHY-3002 : Step(32): len = 184695, overlap = 1133.44
+PHY-3002 : Step(33): len = 183126, overlap = 1133.75
+PHY-3002 : Step(34): len = 182443, overlap = 1133.69
+PHY-3002 : Step(35): len = 180334, overlap = 1158.09
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.09502e-06
+PHY-3002 : Step(36): len = 184151, overlap = 1158.66
+PHY-3002 : Step(37): len = 197166, overlap = 1132.91
+PHY-3002 : Step(38): len = 202021, overlap = 1103.31
+PHY-3002 : Step(39): len = 204975, overlap = 1088.12
+PHY-3002 : Step(40): len = 204946, overlap = 1080.97
+PHY-3002 : Step(41): len = 204924, overlap = 1088.5
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.19004e-06
+PHY-3002 : Step(42): len = 211550, overlap = 1061.69
+PHY-3002 : Step(43): len = 230737, overlap = 916.188
+PHY-3002 : Step(44): len = 241387, overlap = 874.781
+PHY-3002 : Step(45): len = 250673, overlap = 845.219
+PHY-3002 : Step(46): len = 254477, overlap = 806.188
+PHY-3002 : Step(47): len = 255384, overlap = 789
+PHY-3002 : Step(48): len = 255253, overlap = 780.188
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.38007e-06
+PHY-3002 : Step(49): len = 267857, overlap = 742.344
+PHY-3002 : Step(50): len = 289952, overlap = 660.75
+PHY-3002 : Step(51): len = 300057, overlap = 600.594
+PHY-3002 : Step(52): len = 308196, overlap = 563.75
+PHY-3002 : Step(53): len = 309950, overlap = 542.25
+PHY-3002 : Step(54): len = 311050, overlap = 552.25
+PHY-3002 : Step(55): len = 307769, overlap = 560.031
+PHY-3002 : Step(56): len = 307410, overlap = 571.75
+PHY-3002 : Step(57): len = 306686, overlap = 557.719
+PHY-3002 : Step(58): len = 306233, overlap = 543.344
+PHY-3002 : Step(59): len = 304448, overlap = 536.469
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.67601e-05
+PHY-3002 : Step(60): len = 321484, overlap = 507.875
+PHY-3002 : Step(61): len = 334293, overlap = 451.562
+PHY-3002 : Step(62): len = 338632, overlap = 414.156
+PHY-3002 : Step(63): len = 341519, overlap = 393.656
+PHY-3002 : Step(64): len = 341076, overlap = 379.094
+PHY-3002 : Step(65): len = 344106, overlap = 385.938
+PHY-3002 : Step(66): len = 346154, overlap = 378.688
+PHY-3002 : Step(67): len = 348320, overlap = 370.938
+PHY-3002 : Step(68): len = 347568, overlap = 382.688
+PHY-3002 : Step(69): len = 348532, overlap = 386.906
+PHY-3002 : Step(70): len = 348386, overlap = 391.406
+PHY-3002 : Step(71): len = 349105, overlap = 383.344
+PHY-3002 : Step(72): len = 348043, overlap = 365.844
+PHY-3002 : Step(73): len = 348266, overlap = 357.688
+PHY-3002 : Step(74): len = 348440, overlap = 371.812
+PHY-3002 : Step(75): len = 348610, overlap = 366.906
+PHY-3002 : Step(76): len = 348146, overlap = 371.812
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.35203e-05
+PHY-3002 : Step(77): len = 366239, overlap = 340.844
+PHY-3002 : Step(78): len = 379163, overlap = 294.656
+PHY-3002 : Step(79): len = 381645, overlap = 291.594
+PHY-3002 : Step(80): len = 384723, overlap = 288.75
+PHY-3002 : Step(81): len = 385140, overlap = 288.812
+PHY-3002 : Step(82): len = 388313, overlap = 282.75
+PHY-3002 : Step(83): len = 386387, overlap = 305.281
+PHY-3002 : Step(84): len = 387500, overlap = 302.625
+PHY-3002 : Step(85): len = 389301, overlap = 302.625
+PHY-3002 : Step(86): len = 391925, overlap = 297.594
+PHY-3002 : Step(87): len = 388743, overlap = 277.469
+PHY-3002 : Step(88): len = 389053, overlap = 281.781
+PHY-3002 : Step(89): len = 389253, overlap = 270.781
+PHY-3002 : Step(90): len = 390275, overlap = 274.25
+PHY-3002 : Step(91): len = 387164, overlap = 276
+PHY-3002 : Step(92): len = 386753, overlap = 282.125
+PHY-3002 : Step(93): len = 388256, overlap = 277.938
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.70406e-05
+PHY-3002 : Step(94): len = 407497, overlap = 256.281
+PHY-3002 : Step(95): len = 417174, overlap = 249.812
+PHY-3002 : Step(96): len = 414063, overlap = 238.281
+PHY-3002 : Step(97): len = 414365, overlap = 236
+PHY-3002 : Step(98): len = 418527, overlap = 253.625
+PHY-3002 : Step(99): len = 422160, overlap = 259.281
+PHY-3002 : Step(100): len = 418041, overlap = 250.75
+PHY-3002 : Step(101): len = 418631, overlap = 254.906
+PHY-3002 : Step(102): len = 421368, overlap = 255.125
+PHY-3002 : Step(103): len = 423358, overlap = 258.719
+PHY-3002 : Step(104): len = 420625, overlap = 264.312
+PHY-3002 : Step(105): len = 420875, overlap = 267.25
+PHY-3002 : Step(106): len = 422796, overlap = 262.344
+PHY-3002 : Step(107): len = 424154, overlap = 251.062
+PHY-3002 : Step(108): len = 422062, overlap = 255.344
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000131184
+PHY-3002 : Step(109): len = 435745, overlap = 218.469
+PHY-3002 : Step(110): len = 444718, overlap = 212.281
+PHY-3002 : Step(111): len = 443836, overlap = 204.219
+PHY-3002 : Step(112): len = 443902, overlap = 212.438
+PHY-3002 : Step(113): len = 447135, overlap = 189.438
+PHY-3002 : Step(114): len = 450749, overlap = 177.812
+PHY-3002 : Step(115): len = 449994, overlap = 178.906
+PHY-3002 : Step(116): len = 451038, overlap = 179.688
+PHY-3002 : Step(117): len = 452571, overlap = 177.438
+PHY-3002 : Step(118): len = 453293, overlap = 177.438
+PHY-3002 : Step(119): len = 451665, overlap = 183.75
+PHY-3002 : Step(120): len = 451747, overlap = 189.156
+PHY-3002 : Step(121): len = 453181, overlap = 171.531
+PHY-3002 : Step(122): len = 454578, overlap = 179
+PHY-3002 : Step(123): len = 453047, overlap = 181.188
+PHY-3002 : Step(124): len = 452826, overlap = 182.281
+PHY-3002 : Step(125): len = 453923, overlap = 184.312
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000262368
+PHY-3002 : Step(126): len = 466478, overlap = 183.312
+PHY-3002 : Step(127): len = 473763, overlap = 175.438
+PHY-3002 : Step(128): len = 473376, overlap = 163
+PHY-3002 : Step(129): len = 474193, overlap = 157.844
+PHY-3002 : Step(130): len = 477397, overlap = 168.406
+PHY-3002 : Step(131): len = 481558, overlap = 176.75
+PHY-3002 : Step(132): len = 481933, overlap = 179.094
+PHY-3002 : Step(133): len = 484421, overlap = 181.969
+PHY-3002 : Step(134): len = 486763, overlap = 184.344
+PHY-3002 : Step(135): len = 488626, overlap = 187.844
+PHY-3002 : Step(136): len = 487441, overlap = 181
+PHY-3002 : Step(137): len = 487590, overlap = 175.219
+PHY-3002 : Step(138): len = 488706, overlap = 181.344
+PHY-3002 : Step(139): len = 489229, overlap = 182.625
+PHY-3002 : Step(140): len = 487874, overlap = 181.156
+PHY-3002 : Step(141): len = 487918, overlap = 185.625
+PHY-3002 : Step(142): len = 488987, overlap = 186.438
+PHY-3002 : Step(143): len = 490306, overlap = 192.219
+PHY-3002 : Step(144): len = 489797, overlap = 193.844
+PHY-3002 : Step(145): len = 490057, overlap = 190.656
+PHY-3002 : Step(146): len = 490753, overlap = 195.812
+PHY-3002 : Step(147): len = 490858, overlap = 196.781
+PHY-3002 : Step(148): len = 490198, overlap = 192.688
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000488858
+PHY-3002 : Step(149): len = 496658, overlap = 194.969
+PHY-3002 : Step(150): len = 502533, overlap = 197.625
+PHY-3002 : Step(151): len = 504322, overlap = 182.406
+PHY-3002 : Step(152): len = 505896, overlap = 182.656
+PHY-3002 : Step(153): len = 508205, overlap = 188.125
+PHY-3002 : Step(154): len = 509964, overlap = 178.906
+PHY-3002 : Step(155): len = 510353, overlap = 171.562
+PHY-3002 : Step(156): len = 511386, overlap = 171.625
+PHY-3002 : Step(157): len = 512710, overlap = 171.688
+PHY-3002 : Step(158): len = 513589, overlap = 169.125
+PHY-3002 : Step(159): len = 513302, overlap = 161.375
+PHY-3002 : Step(160): len = 513523, overlap = 160
+PHY-3002 : Step(161): len = 513918, overlap = 164.906
+PHY-3002 : Step(162): len = 514058, overlap = 167.531
+PHY-3002 : Step(163): len = 514133, overlap = 152.594
+PHY-3002 : Step(164): len = 516225, overlap = 136.469
+PHY-3002 : Step(165): len = 516883, overlap = 140.938
+PHY-3002 : Step(166): len = 517193, overlap = 142.312
+PHY-3002 : Step(167): len = 516318, overlap = 132.812
+PHY-3002 : Step(168): len = 516183, overlap = 131.125
+PHY-3002 : Step(169): len = 516390, overlap = 134
+PHY-3002 : Step(170): len = 516513, overlap = 136.281
+PHY-3002 : Step(171): len = 516072, overlap = 136.375
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000886298
+PHY-3002 : Step(172): len = 520702, overlap = 124.125
+PHY-3002 : Step(173): len = 526372, overlap = 129.969
+PHY-3002 : Step(174): len = 527347, overlap = 134.688
+PHY-3002 : Step(175): len = 527951, overlap = 128.469
+PHY-3002 : Step(176): len = 529428, overlap = 130.188
+PHY-3002 : Step(177): len = 530572, overlap = 133.406
+PHY-3002 : Step(178): len = 530924, overlap = 133.938
+PHY-3002 : Step(179): len = 531455, overlap = 136
+PHY-3002 : Step(180): len = 532285, overlap = 128.688
+PHY-3002 : Step(181): len = 532617, overlap = 126.75
+PHY-3002 : Step(182): len = 532202, overlap = 129.031
+PHY-3002 : Step(183): len = 532147, overlap = 131.219
+PHY-3002 : Step(184): len = 532636, overlap = 131.719
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.0016247
+PHY-3002 : Step(185): len = 535445, overlap = 131.531
+PHY-3002 : Step(186): len = 539093, overlap = 126.062
+PHY-3002 : Step(187): len = 540275, overlap = 126.156
+PHY-3002 : Step(188): len = 540774, overlap = 126.031
+PHY-3002 : Step(189): len = 541348, overlap = 123.188
+PHY-3002 : Step(190): len = 542350, overlap = 125.188
+PHY-3002 : Step(191): len = 543304, overlap = 125.156
+PHY-3002 : Step(192): len = 543880, overlap = 125.188
+PHY-3002 : Step(193): len = 544332, overlap = 123.031
+PHY-3002 : Step(194): len = 544555, overlap = 122.812
+PHY-3002 : Step(195): len = 544747, overlap = 121.281
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00272808
+PHY-3002 : Step(196): len = 546871, overlap = 119.469
+PHY-3002 : Step(197): len = 551057, overlap = 106.188
+PHY-3002 : Step(198): len = 551851, overlap = 107.469
+PHY-3002 : Step(199): len = 552659, overlap = 108.906
+PHY-3002 : Step(200): len = 553471, overlap = 108.281
+PHY-3002 : Step(201): len = 553955, overlap = 107.156
+PHY-3002 : Step(202): len = 554214, overlap = 107.094
+PHY-3002 : Step(203): len = 554515, overlap = 112.969
+PHY-3002 : Step(204): len = 554670, overlap = 116.125
+PHY-3002 : Step(205): len = 554943, overlap = 117.656
+PHY-3002 : Step(206): len = 555296, overlap = 115.219
+PHY-3002 : Step(207): len = 555506, overlap = 115.219
+PHY-3002 : Step(208): len = 555781, overlap = 115.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.017356s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (90.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20400.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 745568, over cnt = 1604(4%), over = 7785, worst = 65
+PHY-1001 : End global iterations; 0.757725s wall, 0.984375s user + 0.015625s system = 1.000000s CPU (132.0%)
+
+PHY-1001 : Congestion index: top1 = 80.04, top5 = 61.43, top10 = 52.50, top15 = 47.17.
+PHY-3001 : End congestion estimation; 1.011857s wall, 1.203125s user + 0.046875s system = 1.250000s CPU (123.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20222 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.889209s wall, 0.859375s user + 0.031250s system = 0.890625s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000144935
+PHY-3002 : Step(209): len = 676337, overlap = 83.5625
+PHY-3002 : Step(210): len = 677757, overlap = 77.375
+PHY-3002 : Step(211): len = 668468, overlap = 78.75
+PHY-3002 : Step(212): len = 663435, overlap = 74.7812
+PHY-3002 : Step(213): len = 662575, overlap = 68.8125
+PHY-3002 : Step(214): len = 662957, overlap = 64.125
+PHY-3002 : Step(215): len = 660965, overlap = 61.5
+PHY-3002 : Step(216): len = 658935, overlap = 60.1562
+PHY-3002 : Step(217): len = 657050, overlap = 60.75
+PHY-3002 : Step(218): len = 654354, overlap = 56.375
+PHY-3002 : Step(219): len = 652009, overlap = 50.4688
+PHY-3002 : Step(220): len = 649818, overlap = 49.5312
+PHY-3002 : Step(221): len = 648004, overlap = 49.9688
+PHY-3002 : Step(222): len = 646756, overlap = 48.625
+PHY-3002 : Step(223): len = 644699, overlap = 48.0625
+PHY-3002 : Step(224): len = 643572, overlap = 45.1562
+PHY-3002 : Step(225): len = 641357, overlap = 45.9375
+PHY-3002 : Step(226): len = 639912, overlap = 50.0312
+PHY-3002 : Step(227): len = 636884, overlap = 48.4375
+PHY-3002 : Step(228): len = 635511, overlap = 46.4062
+PHY-3002 : Step(229): len = 633178, overlap = 43.6562
+PHY-3002 : Step(230): len = 631087, overlap = 42.9062
+PHY-3002 : Step(231): len = 629948, overlap = 41.6875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00028987
+PHY-3002 : Step(232): len = 631414, overlap = 40.5312
+PHY-3002 : Step(233): len = 633318, overlap = 38.5625
+PHY-3002 : Step(234): len = 637918, overlap = 37.1562
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000578032
+PHY-3002 : Step(235): len = 645619, overlap = 35.3125
+PHY-3002 : Step(236): len = 654994, overlap = 32.375
+PHY-3002 : Step(237): len = 664023, overlap = 27.5
+PHY-3002 : Step(238): len = 664624, overlap = 26.5625
+PHY-3002 : Step(239): len = 665050, overlap = 26.25
+PHY-3002 : Step(240): len = 664890, overlap = 27.6562
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 108/20400.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 758424, over cnt = 2804(7%), over = 12341, worst = 48
+PHY-1001 : End global iterations; 1.815079s wall, 2.406250s user + 0.000000s system = 2.406250s CPU (132.6%)
+
+PHY-1001 : Congestion index: top1 = 84.94, top5 = 66.55, top10 = 58.21, top15 = 53.19.
+PHY-3001 : End congestion estimation; 2.145938s wall, 2.750000s user + 0.000000s system = 2.750000s CPU (128.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20222 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.922111s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000128221
+PHY-3002 : Step(241): len = 658426, overlap = 227.531
+PHY-3002 : Step(242): len = 656698, overlap = 191.062
+PHY-3002 : Step(243): len = 652194, overlap = 159.438
+PHY-3002 : Step(244): len = 648387, overlap = 140.875
+PHY-3002 : Step(245): len = 643795, overlap = 135.062
+PHY-3002 : Step(246): len = 640069, overlap = 122.5
+PHY-3002 : Step(247): len = 636904, overlap = 118.531
+PHY-3002 : Step(248): len = 634130, overlap = 111.469
+PHY-3002 : Step(249): len = 631091, overlap = 116.625
+PHY-3002 : Step(250): len = 628827, overlap = 115.281
+PHY-3002 : Step(251): len = 625443, overlap = 112.969
+PHY-3002 : Step(252): len = 622280, overlap = 111.312
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000256443
+PHY-3002 : Step(253): len = 623700, overlap = 104.75
+PHY-3002 : Step(254): len = 625791, overlap = 100.188
+PHY-3002 : Step(255): len = 628358, overlap = 95.1562
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000512886
+PHY-3002 : Step(256): len = 630773, overlap = 88
+PHY-3002 : Step(257): len = 636512, overlap = 85.125
+PHY-3002 : Step(258): len = 639094, overlap = 80.3125
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00102577
+PHY-3002 : Step(259): len = 644344, overlap = 74.6875
+PHY-3002 : Step(260): len = 652038, overlap = 68.2188
+PHY-3002 : Step(261): len = 655607, overlap = 65.2188
+PHY-3002 : Step(262): len = 655816, overlap = 64.2188
+PHY-3002 : Step(263): len = 655865, overlap = 66.4375
+PHY-3002 : Step(264): len = 656451, overlap = 65.1562
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85233, tnet num: 20222, tinst num: 17820, tnode num: 115303, tedge num: 136752.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.477489s wall, 1.437500s user + 0.046875s system = 1.484375s CPU (100.5%)
+
+RUN-1004 : used memory is 576 MB, reserved memory is 566 MB, peak memory is 711 MB
+OPT-1001 : Total overflow 371.69 peak overflow 2.69
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 913/20400.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 764120, over cnt = 3097(8%), over = 10783, worst = 26
+PHY-1001 : End global iterations; 1.360884s wall, 2.000000s user + 0.015625s system = 2.015625s CPU (148.1%)
+
+PHY-1001 : Congestion index: top1 = 71.85, top5 = 57.07, top10 = 51.02, top15 = 47.47.
+PHY-1001 : End incremental global routing; 1.728329s wall, 2.359375s user + 0.031250s system = 2.390625s CPU (138.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20222 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.945037s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (99.2%)
+
+OPT-1001 : 49 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17686 has valid locations, 322 needs to be replaced
+PHY-3001 : design contains 18093 instances, 7653 luts, 9219 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 6054 pins
+PHY-3001 : Found 1235 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 682948
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16853/20673.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 780544, over cnt = 3144(8%), over = 10791, worst = 26
+PHY-1001 : End global iterations; 0.247063s wall, 0.343750s user + 0.078125s system = 0.421875s CPU (170.8%)
+
+PHY-1001 : Congestion index: top1 = 71.90, top5 = 57.16, top10 = 51.29, top15 = 47.82.
+PHY-3001 : End congestion estimation; 0.519509s wall, 0.640625s user + 0.078125s system = 0.718750s CPU (138.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86311, tnet num: 20495, tinst num: 18093, tnode num: 116904, tedge num: 138362.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.515779s wall, 1.500000s user + 0.015625s system = 1.515625s CPU (100.0%)
+
+RUN-1004 : used memory is 619 MB, reserved memory is 617 MB, peak memory is 716 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20495 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.557253s wall, 2.531250s user + 0.015625s system = 2.546875s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(265): len = 681538, overlap = 0
+PHY-3002 : Step(266): len = 681177, overlap = 0
+PHY-3002 : Step(267): len = 680857, overlap = 0
+PHY-3002 : Step(268): len = 680499, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16941/20673.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 777840, over cnt = 3164(8%), over = 10961, worst = 26
+PHY-1001 : End global iterations; 0.214499s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (123.8%)
+
+PHY-1001 : Congestion index: top1 = 72.82, top5 = 57.96, top10 = 51.93, top15 = 48.30.
+PHY-3001 : End congestion estimation; 0.491831s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (111.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20495 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.955767s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000509045
+PHY-3002 : Step(269): len = 680264, overlap = 67.0625
+PHY-3002 : Step(270): len = 680300, overlap = 66.7812
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00101809
+PHY-3002 : Step(271): len = 680535, overlap = 66.3125
+PHY-3002 : Step(272): len = 681007, overlap = 66.4688
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00199859
+PHY-3002 : Step(273): len = 681133, overlap = 66.8125
+PHY-3002 : Step(274): len = 681553, overlap = 66.9688
+PHY-3001 : Final: Len = 681553, Over = 66.9688
+PHY-3001 : End incremental placement; 5.370176s wall, 5.625000s user + 0.265625s system = 5.890625s CPU (109.7%)
+
+OPT-1001 : Total overflow 376.66 peak overflow 2.69
+OPT-1001 : End high-fanout net optimization; 8.771458s wall, 9.718750s user + 0.328125s system = 10.046875s CPU (114.5%)
+
+OPT-1001 : Current memory(MB): used = 718, reserve = 713, peak = 734.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16882/20673.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 780440, over cnt = 3097(8%), over = 9661, worst = 26
+PHY-1002 : len = 826384, over cnt = 2058(5%), over = 4871, worst = 20
+PHY-1002 : len = 865120, over cnt = 792(2%), over = 1780, worst = 15
+PHY-1002 : len = 882888, over cnt = 245(0%), over = 516, worst = 15
+PHY-1002 : len = 891968, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.007274s wall, 2.796875s user + 0.000000s system = 2.796875s CPU (139.3%)
+
+PHY-1001 : Congestion index: top1 = 58.34, top5 = 50.90, top10 = 46.96, top15 = 44.56.
+OPT-1001 : End congestion update; 2.293182s wall, 3.062500s user + 0.000000s system = 3.062500s CPU (133.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20495 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.839944s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (100.5%)
+
+OPT-0007 : Start: WNS -968 TNS -1428 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -968 TNS -1428 NUM_FEPS 2 with 53 cells processed and 5287 slack improved
+OPT-0007 : Iter 2: improved WNS -968 TNS -1428 NUM_FEPS 2 with 30 cells processed and 1434 slack improved
+OPT-0007 : Iter 3: improved WNS -968 TNS -1428 NUM_FEPS 2 with 10 cells processed and 550 slack improved
+OPT-1001 : End global optimization; 3.178910s wall, 3.937500s user + 0.015625s system = 3.953125s CPU (124.4%)
+
+OPT-1001 : Current memory(MB): used = 696, reserve = 695, peak = 734.
+OPT-1001 : End physical optimization; 14.084246s wall, 15.828125s user + 0.390625s system = 16.218750s CPU (115.2%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7653 LUT to BLE ...
+SYN-4008 : Packed 7653 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6072 remaining SEQ's ...
+SYN-4005 : Packed 4104 SEQ with LUT/SLICE
+SYN-4006 : 711 single LUT's are left
+SYN-4006 : 1968 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9621/13352 primitive instances ...
+PHY-3001 : End packing; 1.661584s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (99.7%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6734 instances
+RUN-1001 : 3293 mslices, 3293 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17660 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10092 nets have 2 pins
+RUN-1001 : 5730 nets have [3 - 5] pins
+RUN-1001 : 1161 nets have [6 - 10] pins
+RUN-1001 : 303 nets have [11 - 20] pins
+RUN-1001 : 342 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6732 instances, 6586 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3585 pins
+PHY-3001 : Found 504 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 692649, Over = 221.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7243/17660.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 844736, over cnt = 2047(5%), over = 3298, worst = 8
+PHY-1002 : len = 853824, over cnt = 1260(3%), over = 1837, worst = 8
+PHY-1002 : len = 866152, over cnt = 562(1%), over = 783, worst = 8
+PHY-1002 : len = 876368, over cnt = 51(0%), over = 64, worst = 4
+PHY-1002 : len = 877712, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.690437s wall, 2.453125s user + 0.015625s system = 2.468750s CPU (146.0%)
+
+PHY-1001 : Congestion index: top1 = 57.44, top5 = 50.43, top10 = 46.58, top15 = 44.15.
+PHY-3001 : End congestion estimation; 2.113789s wall, 2.875000s user + 0.015625s system = 2.890625s CPU (136.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74121, tnet num: 17482, tinst num: 6732, tnode num: 96516, tedge num: 124320.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.656726s wall, 1.625000s user + 0.031250s system = 1.656250s CPU (100.0%)
+
+RUN-1004 : used memory is 615 MB, reserved memory is 617 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17482 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.558151s wall, 2.484375s user + 0.078125s system = 2.562500s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.35145e-05
+PHY-3002 : Step(275): len = 680432, overlap = 222
+PHY-3002 : Step(276): len = 673592, overlap = 219.5
+PHY-3002 : Step(277): len = 669274, overlap = 223.25
+PHY-3002 : Step(278): len = 666299, overlap = 227
+PHY-3002 : Step(279): len = 664700, overlap = 229.5
+PHY-3002 : Step(280): len = 662863, overlap = 228
+PHY-3002 : Step(281): len = 660477, overlap = 232.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000107029
+PHY-3002 : Step(282): len = 662464, overlap = 228.5
+PHY-3002 : Step(283): len = 666379, overlap = 216.75
+PHY-3002 : Step(284): len = 666944, overlap = 211
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000214058
+PHY-3002 : Step(285): len = 672789, overlap = 206.25
+PHY-3002 : Step(286): len = 683226, overlap = 195
+PHY-3002 : Step(287): len = 684678, overlap = 194.5
+PHY-3002 : Step(288): len = 684974, overlap = 195.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.427850s wall, 0.484375s user + 0.703125s system = 1.187500s CPU (277.6%)
+
+PHY-3001 : Trial Legalized: Len = 760360
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 677/17660.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 882632, over cnt = 2795(7%), over = 4768, worst = 8
+PHY-1002 : len = 900784, over cnt = 1770(5%), over = 2645, worst = 7
+PHY-1002 : len = 915304, over cnt = 1057(3%), over = 1566, worst = 7
+PHY-1002 : len = 935688, over cnt = 247(0%), over = 389, worst = 5
+PHY-1002 : len = 942224, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.682846s wall, 3.843750s user + 0.015625s system = 3.859375s CPU (143.9%)
+
+PHY-1001 : Congestion index: top1 = 56.79, top5 = 51.46, top10 = 48.44, top15 = 46.42.
+PHY-3001 : End congestion estimation; 3.187339s wall, 4.328125s user + 0.031250s system = 4.359375s CPU (136.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17482 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.184123s wall, 1.171875s user + 0.015625s system = 1.187500s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000148073
+PHY-3002 : Step(289): len = 733443, overlap = 41.75
+PHY-3002 : Step(290): len = 718112, overlap = 62.25
+PHY-3002 : Step(291): len = 704313, overlap = 88
+PHY-3002 : Step(292): len = 696939, overlap = 110
+PHY-3002 : Step(293): len = 691424, overlap = 131.25
+PHY-3002 : Step(294): len = 688014, overlap = 148
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000296145
+PHY-3002 : Step(295): len = 692833, overlap = 144.75
+PHY-3002 : Step(296): len = 698104, overlap = 139.5
+PHY-3002 : Step(297): len = 702042, overlap = 137.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00059229
+PHY-3002 : Step(298): len = 706273, overlap = 135.75
+PHY-3002 : Step(299): len = 717722, overlap = 133.25
+PHY-3002 : Step(300): len = 724669, overlap = 129.25
+PHY-3002 : Step(301): len = 724930, overlap = 134.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.034524s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (90.5%)
+
+PHY-3001 : Legalized: Len = 750600, Over = 0
+PHY-3001 : Spreading special nets. 422 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.102668s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (106.5%)
+
+PHY-3001 : 622 instances has been re-located, deltaX = 183, deltaY = 378, maxDist = 3.
+PHY-3001 : Final: Len = 760986, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74121, tnet num: 17482, tinst num: 6735, tnode num: 96516, tedge num: 124320.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.894870s wall, 1.875000s user + 0.015625s system = 1.890625s CPU (99.8%)
+
+RUN-1004 : used memory is 629 MB, reserved memory is 645 MB, peak memory is 734 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3709/17660.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 903456, over cnt = 2681(7%), over = 4286, worst = 7
+PHY-1002 : len = 916872, over cnt = 1595(4%), over = 2318, worst = 7
+PHY-1002 : len = 936352, over cnt = 545(1%), over = 775, worst = 6
+PHY-1002 : len = 948384, over cnt = 31(0%), over = 34, worst = 2
+PHY-1002 : len = 949040, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.183342s wall, 3.312500s user + 0.015625s system = 3.328125s CPU (152.4%)
+
+PHY-1001 : Congestion index: top1 = 53.88, top5 = 49.37, top10 = 46.84, top15 = 45.04.
+PHY-1001 : End incremental global routing; 2.600766s wall, 3.734375s user + 0.015625s system = 3.750000s CPU (144.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17482 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.024808s wall, 1.000000s user + 0.015625s system = 1.015625s CPU (99.1%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6643 has valid locations, 21 needs to be replaced
+PHY-3001 : design contains 6752 instances, 6603 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3648 pins
+PHY-3001 : Found 509 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 763282
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16162/17681.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 951264, over cnt = 71(0%), over = 81, worst = 4
+PHY-1002 : len = 951456, over cnt = 30(0%), over = 31, worst = 2
+PHY-1002 : len = 951712, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 951744, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.622055s wall, 0.625000s user + 0.015625s system = 0.640625s CPU (103.0%)
+
+PHY-1001 : Congestion index: top1 = 53.88, top5 = 49.42, top10 = 46.91, top15 = 45.13.
+PHY-3001 : End congestion estimation; 0.966173s wall, 0.953125s user + 0.031250s system = 0.984375s CPU (101.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74263, tnet num: 17503, tinst num: 6752, tnode num: 96706, tedge num: 124505.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.888239s wall, 1.875000s user + 0.015625s system = 1.890625s CPU (100.1%)
+
+RUN-1004 : used memory is 661 MB, reserved memory is 670 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.807181s wall, 2.796875s user + 0.015625s system = 2.812500s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(302): len = 762484, overlap = 0
+PHY-3002 : Step(303): len = 762123, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16150/17681.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 950272, over cnt = 63(0%), over = 75, worst = 3
+PHY-1002 : len = 950408, over cnt = 32(0%), over = 32, worst = 1
+PHY-1002 : len = 950600, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 950808, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.627703s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (112.0%)
+
+PHY-1001 : Congestion index: top1 = 53.88, top5 = 49.40, top10 = 46.87, top15 = 45.07.
+PHY-3001 : End congestion estimation; 0.961397s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (107.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.906101s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000232842
+PHY-3002 : Step(304): len = 762198, overlap = 0.5
+PHY-3002 : Step(305): len = 762198, overlap = 0.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005684s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (274.9%)
+
+PHY-3001 : Legalized: Len = 762260, Over = 0
+PHY-3001 : End spreading; 0.061437s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.7%)
+
+PHY-3001 : Final: Len = 762260, Over = 0
+PHY-3001 : End incremental placement; 6.137406s wall, 6.203125s user + 0.093750s system = 6.296875s CPU (102.6%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.284536s wall, 11.468750s user + 0.140625s system = 11.609375s CPU (112.9%)
+
+OPT-1001 : Current memory(MB): used = 743, reserve = 743, peak = 746.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16152/17681.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 950784, over cnt = 33(0%), over = 43, worst = 4
+PHY-1002 : len = 950904, over cnt = 16(0%), over = 18, worst = 2
+PHY-1002 : len = 951072, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 951104, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.623483s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (100.2%)
+
+PHY-1001 : Congestion index: top1 = 53.88, top5 = 49.39, top10 = 46.87, top15 = 45.08.
+OPT-1001 : End congestion update; 0.961632s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (99.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.740566s wall, 0.734375s user + 0.015625s system = 0.750000s CPU (101.3%)
+
+OPT-0007 : Start: WNS -1136 TNS -1821 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6664 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6752 instances, 6603 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3648 pins
+PHY-3001 : Found 509 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 767458, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062928s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.3%)
+
+PHY-3001 : 16 instances has been re-located, deltaX = 10, deltaY = 6, maxDist = 2.
+PHY-3001 : Final: Len = 767780, Over = 0
+PHY-3001 : End incremental legalization; 0.408918s wall, 0.453125s user + 0.031250s system = 0.484375s CPU (118.5%)
+
+OPT-0007 : Iter 1: improved WNS -886 TNS -1421 NUM_FEPS 2 with 27 cells processed and 8950 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6664 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6752 instances, 6603 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3648 pins
+PHY-3001 : Found 509 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 768728, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065363s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.6%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 11, deltaY = 12, maxDist = 4.
+PHY-3001 : Final: Len = 768978, Over = 0
+PHY-3001 : End incremental legalization; 0.444279s wall, 0.437500s user + 0.015625s system = 0.453125s CPU (102.0%)
+
+OPT-0007 : Iter 2: improved WNS -886 TNS -1421 NUM_FEPS 2 with 17 cells processed and 2594 slack improved
+OPT-0007 : Iter 3: improved WNS -886 TNS -1421 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.842127s wall, 2.843750s user + 0.062500s system = 2.906250s CPU (102.3%)
+
+OPT-1001 : Current memory(MB): used = 743, reserve = 743, peak = 746.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.765192s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.1%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15990/17681.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 957432, over cnt = 131(0%), over = 152, worst = 4
+PHY-1002 : len = 957224, over cnt = 63(0%), over = 66, worst = 2
+PHY-1002 : len = 957680, over cnt = 15(0%), over = 16, worst = 2
+PHY-1002 : len = 957888, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 957976, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.885161s wall, 0.921875s user + 0.031250s system = 0.953125s CPU (107.7%)
+
+PHY-1001 : Congestion index: top1 = 53.60, top5 = 49.34, top10 = 46.86, top15 = 45.08.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.746806s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.3%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -986 TNS -1521 NUM_FEPS 2
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 53.172414
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -986ps with logic level 2
+RUN-1001 : #2 path slack -940ps with logic level 2
+RUN-1001 : extra opt step will be enabled to improve QoR
+RUN-1001 : 0 HFN exist on timing critical paths out of 17681 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 17681 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6664 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6752 instances, 6603 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3648 pins
+PHY-3001 : Found 509 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 768978, Over = 0
+PHY-3001 : End spreading; 0.064204s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.3%)
+
+PHY-3001 : Final: Len = 768978, Over = 0
+PHY-3001 : End incremental legalization; 0.413364s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (102.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.779190s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.3%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16178/17681.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 957976, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.140288s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.2%)
+
+PHY-1001 : Congestion index: top1 = 53.60, top5 = 49.34, top10 = 46.86, top15 = 45.08.
+OPT-1001 : End congestion update; 0.483114s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (100.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.750608s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.9%)
+
+OPT-0007 : Start: WNS -986 TNS -1521 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6664 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6752 instances, 6603 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3648 pins
+PHY-3001 : Found 509 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 768928, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063379s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.6%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 768978, Over = 0
+PHY-3001 : End incremental legalization; 0.405752s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.1%)
+
+OPT-0007 : Iter 1: improved WNS -886 TNS -1421 NUM_FEPS 2 with 1 cells processed and 100 slack improved
+OPT-0007 : Iter 2: improved WNS -886 TNS -1421 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.797600s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (101.7%)
+
+OPT-1001 : Current memory(MB): used = 743, reserve = 744, peak = 746.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16178/17681.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 957976, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.137721s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.1%)
+
+PHY-1001 : Congestion index: top1 = 53.60, top5 = 49.34, top10 = 46.86, top15 = 45.08.
+OPT-1001 : End congestion update; 0.485271s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (99.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.747793s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.3%)
+
+OPT-0007 : Start: WNS -986 TNS -1521 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6664 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6752 instances, 6603 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3648 pins
+PHY-3001 : Found 509 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 768928, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061035s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.4%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 768978, Over = 0
+PHY-3001 : End incremental legalization; 0.407490s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.7%)
+
+OPT-0007 : Iter 1: improved WNS -886 TNS -1421 NUM_FEPS 2 with 1 cells processed and 100 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6664 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6752 instances, 6603 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1263 with 3648 pins
+PHY-3001 : Found 509 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 768928, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063747s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.0%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 768978, Over = 0
+PHY-3001 : End incremental legalization; 0.422187s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (122.1%)
+
+OPT-0007 : Iter 2: improved WNS -886 TNS -1421 NUM_FEPS 2 with 1 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS -986 TNS -1521 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 2.389077s wall, 2.531250s user + 0.000000s system = 2.531250s CPU (106.0%)
+
+OPT-1001 : Current memory(MB): used = 743, reserve = 744, peak = 746.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.752383s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.7%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 743, reserve = 744, peak = 746.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.761426s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.6%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16178/17681.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 957976, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.152704s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (92.1%)
+
+PHY-1001 : Congestion index: top1 = 53.60, top5 = 49.34, top10 = 46.86, top15 = 45.08.
+RUN-1001 : End congestion update; 0.530883s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (100.1%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.296094s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (100.1%)
+
+OPT-1001 : Current memory(MB): used = 743, reserve = 744, peak = 746.
+OPT-1001 : End physical optimization; 25.729640s wall, 27.093750s user + 0.250000s system = 27.343750s CPU (106.3%)
+
+RUN-1003 : finish command "place" in 72.356790s wall, 101.468750s user + 6.703125s system = 108.171875s CPU (149.5%)
+
+RUN-1004 : used memory is 650 MB, reserved memory is 653 MB, peak memory is 746 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.719237s wall, 2.984375s user + 0.000000s system = 2.984375s CPU (173.6%)
+
+RUN-1004 : used memory is 650 MB, reserved memory is 654 MB, peak memory is 746 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6754 instances
+RUN-1001 : 3301 mslices, 3302 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17681 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10092 nets have 2 pins
+RUN-1001 : 5733 nets have [3 - 5] pins
+RUN-1001 : 1166 nets have [6 - 10] pins
+RUN-1001 : 305 nets have [11 - 20] pins
+RUN-1001 : 357 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74263, tnet num: 17503, tinst num: 6752, tnode num: 96706, tedge num: 124505.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.694031s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (99.6%)
+
+RUN-1004 : used memory is 659 MB, reserved memory is 669 MB, peak memory is 746 MB
+PHY-1001 : 3301 mslices, 3302 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 888576, over cnt = 2758(7%), over = 4615, worst = 7
+PHY-1002 : len = 905616, over cnt = 1731(4%), over = 2584, worst = 7
+PHY-1002 : len = 924536, over cnt = 740(2%), over = 1102, worst = 6
+PHY-1002 : len = 942968, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 943016, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.354656s wall, 4.546875s user + 0.015625s system = 4.562500s CPU (136.0%)
+
+PHY-1001 : Congestion index: top1 = 54.01, top5 = 49.06, top10 = 46.60, top15 = 44.81.
+PHY-1001 : End global routing; 3.712378s wall, 4.906250s user + 0.015625s system = 4.921875s CPU (132.6%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 720, reserve = 726, peak = 746.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 989, reserve = 994, peak = 989.
+PHY-1001 : End build detailed router design. 4.060079s wall, 4.000000s user + 0.062500s system = 4.062500s CPU (100.1%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 271800, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.922154s wall, 5.906250s user + 0.015625s system = 5.921875s CPU (100.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 271856, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.520720s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (99.0%)
+
+PHY-1001 : Current memory(MB): used = 1025, reserve = 1030, peak = 1025.
+PHY-1001 : End phase 1; 6.456937s wall, 6.437500s user + 0.015625s system = 6.453125s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.44049e+06, over cnt = 1948(0%), over = 1956, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1040, reserve = 1041, peak = 1040.
+PHY-1001 : End initial routed; 42.191716s wall, 75.921875s user + 0.875000s system = 76.796875s CPU (182.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16604(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -2.068 | -3.932 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.359570s wall, 3.343750s user + 0.015625s system = 3.359375s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1052, reserve = 1055, peak = 1052.
+PHY-1001 : End phase 2; 45.551352s wall, 79.265625s user + 0.890625s system = 80.156250s CPU (176.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.068ns STNS -3.809ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.148108s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (105.5%)
+
+PHY-1022 : len = 2.44049e+06, over cnt = 1949(0%), over = 1957, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.451077s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.40416e+06, over cnt = 741(0%), over = 741, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.869909s wall, 3.437500s user + 0.015625s system = 3.453125s CPU (184.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.40045e+06, over cnt = 137(0%), over = 137, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.179348s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (131.2%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.4007e+06, over cnt = 32(0%), over = 32, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.446172s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (126.1%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.4008e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.382777s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (118.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.4008e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.287793s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (92.3%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.4008e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.436255s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.3%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.4008e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.782088s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.9%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.4008e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.189726s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (98.8%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.4008e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.189103s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.4008e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.228096s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.8%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.4008e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.329184s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.4008e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.664325s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (98.8%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.40082e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.191806s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (105.9%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.40086e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.174305s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16604(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -2.068 | -3.809 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.352525s wall, 3.343750s user + 0.015625s system = 3.359375s CPU (100.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 596 feed throughs used by 418 nets
+PHY-1001 : End commit to database; 2.325971s wall, 2.312500s user + 0.015625s system = 2.328125s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1157, reserve = 1164, peak = 1157.
+PHY-1001 : End phase 3; 13.924064s wall, 15.968750s user + 0.046875s system = 16.015625s CPU (115.0%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.942ns STNS -3.683ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.142786s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.5%)
+
+PHY-1022 : len = 2.40086e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.413404s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (102.0%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.942ns, -3.683ns, 3}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.40086e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.175617s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (97.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16604(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.942 | -3.683 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.387204s wall, 3.390625s user + 0.000000s system = 3.390625s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 597 feed throughs used by 419 nets
+PHY-1001 : End commit to database; 2.434509s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1166, reserve = 1173, peak = 1166.
+PHY-1001 : End phase 4; 6.466763s wall, 6.468750s user + 0.000000s system = 6.468750s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.40086e+06
+PHY-1001 : Current memory(MB): used = 1169, reserve = 1176, peak = 1169.
+PHY-1001 : End export database. 0.167293s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (93.4%)
+
+PHY-1001 : End detail routing; 77.041954s wall, 112.734375s user + 1.015625s system = 113.750000s CPU (147.6%)
+
+RUN-1003 : finish command "route" in 83.638530s wall, 120.484375s user + 1.046875s system = 121.531250s CPU (145.3%)
+
+RUN-1004 : used memory is 1092 MB, reserved memory is 1105 MB, peak memory is 1169 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10364 out of 19600 52.88%
+#reg 9361 out of 19600 47.76%
+#le 12265
+ #lut only 2904 out of 12265 23.68%
+ #reg only 1901 out of 12265 15.50%
+ #lut® 7460 out of 12265 60.82%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1805
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1430
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1326
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 935
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/reg6_syn_49.q0 135
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 71
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 23
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg45_syn_210.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg42_syn_239.f0 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P139 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P17 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P19 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P16 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P109 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P104 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P71 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P35 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12265 |9337 |1027 |9393 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |541 |443 |23 |440 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |102 |93 |4 |89 |4 |0 |
+| U_crc16_24b |crc16_24b |30 |30 |0 |20 |0 |0 |
+| U_ecc_gen |ecc_gen |6 |6 |0 |5 |0 |0 |
+| exdev_ctl_a |exdev_ctl |784 |407 |96 |590 |0 |0 |
+| u_ADconfig |AD_config |192 |127 |25 |143 |0 |0 |
+| u_gen_sp |gen_sp |267 |167 |71 |122 |0 |0 |
+| exdev_ctl_b |exdev_ctl |744 |435 |96 |552 |0 |0 |
+| u_ADconfig |AD_config |178 |132 |25 |128 |0 |0 |
+| u_gen_sp |gen_sp |262 |165 |71 |120 |0 |0 |
+| sampling_fe_a |sampling_fe |3077 |2470 |306 |2069 |25 |0 |
+| u0_soft_n |cdc_sync |6 |4 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |191 |94 |17 |153 |0 |0 |
+| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u_sort |sort |2850 |2365 |289 |1880 |25 |0 |
+| rddpram_ctl |rddpram_ctl |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2419 |2019 |253 |1525 |22 |0 |
+| channelPart |channel_part_8478 |162 |159 |3 |133 |0 |0 |
+| fifo_adc |fifo_adc |62 |53 |9 |43 |0 |0 |
+| ram_switch |ram_switch |1890 |1559 |197 |1128 |0 |0 |
+| adc_addr_gen |adc_addr_gen |260 |232 |27 |117 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |14 |10 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |25 |22 |3 |14 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |28 |25 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |28 |25 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |28 |25 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |21 |18 |3 |8 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |28 |25 |3 |10 |0 |0 |
+| insert |insert |960 |657 |170 |655 |0 |0 |
+| ram_switch_state |ram_switch_state |670 |670 |0 |356 |0 |0 |
+| read_ram_i |read_ram |282 |229 |44 |198 |0 |0 |
+| read_ram_addr |read_ram_addr |226 |186 |40 |156 |0 |0 |
+| read_ram_data |read_ram_data |51 |38 |4 |37 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |335 |269 |36 |279 |3 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3079 |2445 |349 |2109 |25 |1 |
+| u0_soft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |168 |121 |17 |135 |0 |0 |
+| u0_soft_n |cdc_sync |3 |0 |0 |3 |0 |0 |
+| u_sort |sort_rev |2876 |2302 |332 |1939 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |6 |3 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |3 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2449 |1980 |290 |1584 |22 |1 |
+| channelPart |channel_part_8478 |232 |220 |3 |142 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |42 |0 |1 |
+| ram_switch |ram_switch |1766 |1423 |197 |1155 |0 |0 |
+| adc_addr_gen |adc_addr_gen |196 |163 |27 |128 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |16 |8 |3 |12 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |13 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |21 |18 |3 |14 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |25 |22 |3 |18 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |18 |15 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |21 |18 |3 |13 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |10 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| insert |insert |993 |688 |170 |681 |0 |0 |
+| ram_switch_state |ram_switch_state |577 |572 |0 |346 |0 |0 |
+| read_ram_i |read_ram_rev |363 |264 |81 |215 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |292 |210 |73 |163 |0 |0 |
+| read_ram_data |read_ram_data_rev |71 |54 |8 |52 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 10030
+ #2 2 3788
+ #3 3 1404
+ #4 4 538
+ #5 5-10 1220
+ #6 11-50 580
+ #7 51-100 25
+ #8 >500 1
+ Average 2.91
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.099238s wall, 3.625000s user + 0.015625s system = 3.640625s CPU (173.4%)
+
+RUN-1004 : used memory is 1093 MB, reserved memory is 1105 MB, peak memory is 1169 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74263, tnet num: 17503, tinst num: 6752, tnode num: 96706, tedge num: 124505.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.637319s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (99.2%)
+
+RUN-1004 : used memory is 1098 MB, reserved memory is 1109 MB, peak memory is 1169 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.542396s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (100.3%)
+
+RUN-1004 : used memory is 1100 MB, reserved memory is 1112 MB, peak memory is 1169 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6752
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17681, pip num: 176069
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 597
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3239 valid insts, and 485886 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 10.937697s wall, 60.343750s user + 0.734375s system = 61.078125s CPU (558.4%)
+
+RUN-1004 : used memory is 1268 MB, reserved memory is 1272 MB, peak memory is 1384 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240219_103630.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240219_104251.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240219_104251.log
new file mode 100644
index 0000000..e878b4f
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240219_104251.log
@@ -0,0 +1,1874 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Feb 19 10:42:51 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.162706s wall, 2.062500s user + 0.093750s system = 2.156250s CPU (99.7%)
+
+RUN-1004 : used memory is 336 MB, reserved memory is 314 MB, peak memory is 340 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17673 instances
+RUN-0007 : 7407 luts, 9043 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20251 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13316 nets have 2 pins
+RUN-1001 : 5518 nets have [3 - 5] pins
+RUN-1001 : 1004 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 177 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 1968
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17671 instances, 7407 luts, 9043 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5897 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.185000s wall, 1.171875s user + 0.015625s system = 1.187500s CPU (100.2%)
+
+RUN-1004 : used memory is 528 MB, reserved memory is 513 MB, peak memory is 528 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.985457s wall, 1.968750s user + 0.015625s system = 1.984375s CPU (99.9%)
+
+PHY-3001 : Found 1227 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.10018e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17671.
+PHY-3001 : Level 1 #clusters 2000.
+PHY-3001 : End clustering; 0.135912s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (149.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28781e+06, overlap = 486.375
+PHY-3002 : Step(2): len = 1.18448e+06, overlap = 556.844
+PHY-3002 : Step(3): len = 844678, overlap = 603.438
+PHY-3002 : Step(4): len = 790961, overlap = 620.656
+PHY-3002 : Step(5): len = 610845, overlap = 760.312
+PHY-3002 : Step(6): len = 529733, overlap = 802.5
+PHY-3002 : Step(7): len = 455969, overlap = 922.25
+PHY-3002 : Step(8): len = 422838, overlap = 992.312
+PHY-3002 : Step(9): len = 375139, overlap = 1058.94
+PHY-3002 : Step(10): len = 342398, overlap = 1103.94
+PHY-3002 : Step(11): len = 296960, overlap = 1184.03
+PHY-3002 : Step(12): len = 276772, overlap = 1211.03
+PHY-3002 : Step(13): len = 250769, overlap = 1258.16
+PHY-3002 : Step(14): len = 233429, overlap = 1298.5
+PHY-3002 : Step(15): len = 209104, overlap = 1316.44
+PHY-3002 : Step(16): len = 195508, overlap = 1353.78
+PHY-3002 : Step(17): len = 173537, overlap = 1395.03
+PHY-3002 : Step(18): len = 165216, overlap = 1428.59
+PHY-3002 : Step(19): len = 151805, overlap = 1456.56
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.24217e-06
+PHY-3002 : Step(20): len = 151437, overlap = 1418.41
+PHY-3002 : Step(21): len = 188587, overlap = 1309.94
+PHY-3002 : Step(22): len = 197958, overlap = 1227.19
+PHY-3002 : Step(23): len = 205610, overlap = 1187.41
+PHY-3002 : Step(24): len = 205191, overlap = 1195.41
+PHY-3002 : Step(25): len = 202779, overlap = 1176.06
+PHY-3002 : Step(26): len = 200981, overlap = 1137.22
+PHY-3002 : Step(27): len = 198313, overlap = 1101.44
+PHY-3002 : Step(28): len = 196474, overlap = 1116.75
+PHY-3002 : Step(29): len = 191917, overlap = 1110.5
+PHY-3002 : Step(30): len = 190072, overlap = 1119.06
+PHY-3002 : Step(31): len = 187276, overlap = 1106.41
+PHY-3002 : Step(32): len = 186973, overlap = 1109.91
+PHY-3002 : Step(33): len = 184645, overlap = 1093.56
+PHY-3002 : Step(34): len = 184203, overlap = 1075.03
+PHY-3002 : Step(35): len = 182768, overlap = 1078.69
+PHY-3002 : Step(36): len = 182773, overlap = 1088.78
+PHY-3002 : Step(37): len = 180469, overlap = 1096.28
+PHY-3002 : Step(38): len = 180227, overlap = 1107.56
+PHY-3002 : Step(39): len = 179831, overlap = 1122.91
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.48434e-06
+PHY-3002 : Step(40): len = 184347, overlap = 1116.06
+PHY-3002 : Step(41): len = 196346, overlap = 1101.75
+PHY-3002 : Step(42): len = 200234, overlap = 1079.22
+PHY-3002 : Step(43): len = 205439, overlap = 1058.78
+PHY-3002 : Step(44): len = 206361, overlap = 1036.47
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.96868e-06
+PHY-3002 : Step(45): len = 213151, overlap = 971.906
+PHY-3002 : Step(46): len = 239505, overlap = 832.062
+PHY-3002 : Step(47): len = 257962, overlap = 789.656
+PHY-3002 : Step(48): len = 266574, overlap = 756.438
+PHY-3002 : Step(49): len = 268831, overlap = 758.562
+PHY-3002 : Step(50): len = 268292, overlap = 756.375
+PHY-3002 : Step(51): len = 266038, overlap = 737.531
+PHY-3002 : Step(52): len = 264557, overlap = 717.156
+PHY-3002 : Step(53): len = 263477, overlap = 723
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.93736e-06
+PHY-3002 : Step(54): len = 278369, overlap = 691.906
+PHY-3002 : Step(55): len = 294870, overlap = 627.406
+PHY-3002 : Step(56): len = 301298, overlap = 548.594
+PHY-3002 : Step(57): len = 305620, overlap = 511.812
+PHY-3002 : Step(58): len = 306591, overlap = 495.281
+PHY-3002 : Step(59): len = 308768, overlap = 482.594
+PHY-3002 : Step(60): len = 309666, overlap = 466.719
+PHY-3002 : Step(61): len = 311359, overlap = 474.188
+PHY-3002 : Step(62): len = 311931, overlap = 486.5
+PHY-3002 : Step(63): len = 311951, overlap = 491.531
+PHY-3002 : Step(64): len = 309893, overlap = 485.719
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.98747e-05
+PHY-3002 : Step(65): len = 329539, overlap = 425.188
+PHY-3002 : Step(66): len = 341239, overlap = 395.719
+PHY-3002 : Step(67): len = 345570, overlap = 398.531
+PHY-3002 : Step(68): len = 347409, overlap = 384.094
+PHY-3002 : Step(69): len = 347399, overlap = 372.75
+PHY-3002 : Step(70): len = 349137, overlap = 368.781
+PHY-3002 : Step(71): len = 349251, overlap = 372.906
+PHY-3002 : Step(72): len = 349953, overlap = 389.281
+PHY-3002 : Step(73): len = 348477, overlap = 396.344
+PHY-3002 : Step(74): len = 349143, overlap = 406.156
+PHY-3002 : Step(75): len = 348303, overlap = 377.344
+PHY-3002 : Step(76): len = 350330, overlap = 385.344
+PHY-3002 : Step(77): len = 350009, overlap = 425.031
+PHY-3002 : Step(78): len = 351198, overlap = 434.438
+PHY-3002 : Step(79): len = 350475, overlap = 438.812
+PHY-3002 : Step(80): len = 351449, overlap = 442.938
+PHY-3002 : Step(81): len = 349456, overlap = 435.969
+PHY-3002 : Step(82): len = 349832, overlap = 435.562
+PHY-3002 : Step(83): len = 349223, overlap = 433.812
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.97494e-05
+PHY-3002 : Step(84): len = 366176, overlap = 434.25
+PHY-3002 : Step(85): len = 376303, overlap = 414.312
+PHY-3002 : Step(86): len = 378212, overlap = 387.281
+PHY-3002 : Step(87): len = 379689, overlap = 368.469
+PHY-3002 : Step(88): len = 379612, overlap = 345.812
+PHY-3002 : Step(89): len = 382828, overlap = 349.906
+PHY-3002 : Step(90): len = 383711, overlap = 345.031
+PHY-3002 : Step(91): len = 385704, overlap = 340.906
+PHY-3002 : Step(92): len = 387202, overlap = 329.344
+PHY-3002 : Step(93): len = 387674, overlap = 329.719
+PHY-3002 : Step(94): len = 385757, overlap = 331.625
+PHY-3002 : Step(95): len = 385855, overlap = 328.094
+PHY-3002 : Step(96): len = 385901, overlap = 323.594
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.94989e-05
+PHY-3002 : Step(97): len = 401052, overlap = 305.781
+PHY-3002 : Step(98): len = 408769, overlap = 287.625
+PHY-3002 : Step(99): len = 408389, overlap = 274.5
+PHY-3002 : Step(100): len = 413114, overlap = 274.844
+PHY-3002 : Step(101): len = 420867, overlap = 264.125
+PHY-3002 : Step(102): len = 426831, overlap = 270.594
+PHY-3002 : Step(103): len = 422580, overlap = 272.688
+PHY-3002 : Step(104): len = 422370, overlap = 270.625
+PHY-3002 : Step(105): len = 424675, overlap = 278.719
+PHY-3002 : Step(106): len = 428122, overlap = 265.875
+PHY-3002 : Step(107): len = 424377, overlap = 265.219
+PHY-3002 : Step(108): len = 424166, overlap = 282.656
+PHY-3002 : Step(109): len = 425463, overlap = 272.906
+PHY-3002 : Step(110): len = 426483, overlap = 272.375
+PHY-3002 : Step(111): len = 424168, overlap = 268.125
+PHY-3002 : Step(112): len = 424061, overlap = 269.938
+PHY-3002 : Step(113): len = 424585, overlap = 268.875
+PHY-3002 : Step(114): len = 425603, overlap = 264.688
+PHY-3002 : Step(115): len = 423824, overlap = 272.125
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000154571
+PHY-3002 : Step(116): len = 435750, overlap = 266
+PHY-3002 : Step(117): len = 444478, overlap = 249.938
+PHY-3002 : Step(118): len = 443643, overlap = 246.438
+PHY-3002 : Step(119): len = 444343, overlap = 240.562
+PHY-3002 : Step(120): len = 445827, overlap = 246.781
+PHY-3002 : Step(121): len = 447671, overlap = 250.281
+PHY-3002 : Step(122): len = 448017, overlap = 242.969
+PHY-3002 : Step(123): len = 451540, overlap = 245.594
+PHY-3002 : Step(124): len = 453609, overlap = 235.25
+PHY-3002 : Step(125): len = 457122, overlap = 227.281
+PHY-3002 : Step(126): len = 456222, overlap = 220.469
+PHY-3002 : Step(127): len = 457383, overlap = 218.719
+PHY-3002 : Step(128): len = 458854, overlap = 221.562
+PHY-3002 : Step(129): len = 460199, overlap = 211.031
+PHY-3002 : Step(130): len = 457613, overlap = 225.25
+PHY-3002 : Step(131): len = 457697, overlap = 219.781
+PHY-3002 : Step(132): len = 458652, overlap = 213.281
+PHY-3002 : Step(133): len = 459321, overlap = 206.656
+PHY-3002 : Step(134): len = 458020, overlap = 208.031
+PHY-3002 : Step(135): len = 457933, overlap = 209.719
+PHY-3002 : Step(136): len = 458338, overlap = 207.312
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000309141
+PHY-3002 : Step(137): len = 469252, overlap = 191
+PHY-3002 : Step(138): len = 477052, overlap = 187.562
+PHY-3002 : Step(139): len = 478275, overlap = 176.625
+PHY-3002 : Step(140): len = 480066, overlap = 169.312
+PHY-3002 : Step(141): len = 483575, overlap = 175.031
+PHY-3002 : Step(142): len = 486202, overlap = 172.031
+PHY-3002 : Step(143): len = 483842, overlap = 165.375
+PHY-3002 : Step(144): len = 483879, overlap = 166.531
+PHY-3002 : Step(145): len = 486041, overlap = 166.469
+PHY-3002 : Step(146): len = 488298, overlap = 166.656
+PHY-3002 : Step(147): len = 486479, overlap = 163.094
+PHY-3002 : Step(148): len = 486905, overlap = 162.219
+PHY-3002 : Step(149): len = 488174, overlap = 162.656
+PHY-3002 : Step(150): len = 488730, overlap = 162.844
+PHY-3002 : Step(151): len = 486252, overlap = 161.875
+PHY-3002 : Step(152): len = 485862, overlap = 157
+PHY-3002 : Step(153): len = 487128, overlap = 153.688
+PHY-3002 : Step(154): len = 487393, overlap = 153.594
+PHY-3002 : Step(155): len = 485752, overlap = 156.062
+PHY-3002 : Step(156): len = 485436, overlap = 155.719
+PHY-3002 : Step(157): len = 486010, overlap = 156.094
+PHY-3002 : Step(158): len = 486570, overlap = 152.5
+PHY-3002 : Step(159): len = 485723, overlap = 151.969
+PHY-3002 : Step(160): len = 485692, overlap = 152.656
+PHY-3002 : Step(161): len = 486390, overlap = 153.062
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000596435
+PHY-3002 : Step(162): len = 494074, overlap = 149.719
+PHY-3002 : Step(163): len = 501251, overlap = 149.844
+PHY-3002 : Step(164): len = 503214, overlap = 142.188
+PHY-3002 : Step(165): len = 504242, overlap = 139.531
+PHY-3002 : Step(166): len = 505752, overlap = 140.688
+PHY-3002 : Step(167): len = 506547, overlap = 138.562
+PHY-3002 : Step(168): len = 505427, overlap = 138.312
+PHY-3002 : Step(169): len = 505227, overlap = 138.438
+PHY-3002 : Step(170): len = 506840, overlap = 142.25
+PHY-3002 : Step(171): len = 508132, overlap = 146.5
+PHY-3002 : Step(172): len = 508171, overlap = 143.219
+PHY-3002 : Step(173): len = 508607, overlap = 150.531
+PHY-3002 : Step(174): len = 509279, overlap = 147.094
+PHY-3002 : Step(175): len = 509519, overlap = 153.406
+PHY-3002 : Step(176): len = 508818, overlap = 152.312
+PHY-3002 : Step(177): len = 508720, overlap = 148.344
+PHY-3002 : Step(178): len = 509186, overlap = 144.531
+PHY-3002 : Step(179): len = 509390, overlap = 144.781
+PHY-3002 : Step(180): len = 508812, overlap = 145.438
+PHY-3002 : Step(181): len = 508799, overlap = 142.688
+PHY-3002 : Step(182): len = 509197, overlap = 144.781
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00117073
+PHY-3002 : Step(183): len = 513354, overlap = 144.219
+PHY-3002 : Step(184): len = 518436, overlap = 141.688
+PHY-3002 : Step(185): len = 519282, overlap = 142.031
+PHY-3002 : Step(186): len = 519675, overlap = 139.125
+PHY-3002 : Step(187): len = 520105, overlap = 145
+PHY-3002 : Step(188): len = 520475, overlap = 143.125
+PHY-3002 : Step(189): len = 520741, overlap = 142.625
+PHY-3002 : Step(190): len = 521094, overlap = 140.719
+PHY-3002 : Step(191): len = 521700, overlap = 139.281
+PHY-3002 : Step(192): len = 521958, overlap = 139.469
+PHY-3002 : Step(193): len = 522005, overlap = 136.531
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00203107
+PHY-3002 : Step(194): len = 525335, overlap = 134.281
+PHY-3002 : Step(195): len = 530178, overlap = 138.375
+PHY-3002 : Step(196): len = 530436, overlap = 137.5
+PHY-3002 : Step(197): len = 530556, overlap = 137.438
+PHY-3002 : Step(198): len = 531236, overlap = 136.062
+PHY-3002 : Step(199): len = 531595, overlap = 133.969
+PHY-3002 : Step(200): len = 531906, overlap = 131.75
+PHY-3002 : Step(201): len = 533381, overlap = 127.75
+PHY-3002 : Step(202): len = 534736, overlap = 134.094
+PHY-3002 : Step(203): len = 535295, overlap = 131.5
+PHY-3002 : Step(204): len = 535513, overlap = 128.469
+PHY-3002 : Step(205): len = 535702, overlap = 126.5
+PHY-3002 : Step(206): len = 536093, overlap = 128.656
+PHY-3002 : Step(207): len = 536326, overlap = 128.969
+PHY-3002 : Step(208): len = 536675, overlap = 124.875
+PHY-3002 : Step(209): len = 537320, overlap = 124.031
+PHY-3002 : Step(210): len = 537725, overlap = 124.5
+PHY-3002 : Step(211): len = 537725, overlap = 124.5
+PHY-3002 : Step(212): len = 537416, overlap = 124.094
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.013690s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (114.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 701832, over cnt = 1570(4%), over = 7561, worst = 40
+PHY-1001 : End global iterations; 0.713909s wall, 1.000000s user + 0.046875s system = 1.046875s CPU (146.6%)
+
+PHY-1001 : Congestion index: top1 = 81.10, top5 = 63.34, top10 = 53.27, top15 = 47.20.
+PHY-3001 : End congestion estimation; 0.941284s wall, 1.234375s user + 0.046875s system = 1.281250s CPU (136.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.881454s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000140147
+PHY-3002 : Step(213): len = 635592, overlap = 72.25
+PHY-3002 : Step(214): len = 635873, overlap = 68.8125
+PHY-3002 : Step(215): len = 632277, overlap = 59.9688
+PHY-3002 : Step(216): len = 630694, overlap = 50.6562
+PHY-3002 : Step(217): len = 631226, overlap = 53.9375
+PHY-3002 : Step(218): len = 630758, overlap = 48.125
+PHY-3002 : Step(219): len = 629636, overlap = 36.2188
+PHY-3002 : Step(220): len = 628040, overlap = 30.0625
+PHY-3002 : Step(221): len = 627086, overlap = 31.875
+PHY-3002 : Step(222): len = 625052, overlap = 32.5
+PHY-3002 : Step(223): len = 624146, overlap = 31.25
+PHY-3002 : Step(224): len = 623374, overlap = 31.2812
+PHY-3002 : Step(225): len = 622676, overlap = 31.2812
+PHY-3002 : Step(226): len = 621484, overlap = 30.5
+PHY-3002 : Step(227): len = 621724, overlap = 29.9375
+PHY-3002 : Step(228): len = 620428, overlap = 30.25
+PHY-3002 : Step(229): len = 619923, overlap = 31.2812
+PHY-3002 : Step(230): len = 618778, overlap = 33.9375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000280295
+PHY-3002 : Step(231): len = 620156, overlap = 31.875
+PHY-3002 : Step(232): len = 622640, overlap = 31.3438
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 110/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 709952, over cnt = 2556(7%), over = 11181, worst = 47
+PHY-1001 : End global iterations; 1.670820s wall, 2.203125s user + 0.140625s system = 2.343750s CPU (140.3%)
+
+PHY-1001 : Congestion index: top1 = 83.06, top5 = 65.23, top10 = 56.92, top15 = 51.70.
+PHY-3001 : End congestion estimation; 1.995197s wall, 2.531250s user + 0.140625s system = 2.671875s CPU (133.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.090075s wall, 1.062500s user + 0.031250s system = 1.093750s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.52533e-05
+PHY-3002 : Step(233): len = 621125, overlap = 281.969
+PHY-3002 : Step(234): len = 625546, overlap = 230.031
+PHY-3002 : Step(235): len = 623192, overlap = 209.562
+PHY-3002 : Step(236): len = 619391, overlap = 205.375
+PHY-3002 : Step(237): len = 617967, overlap = 193.25
+PHY-3002 : Step(238): len = 615999, overlap = 178.531
+PHY-3002 : Step(239): len = 613834, overlap = 165.125
+PHY-3002 : Step(240): len = 614092, overlap = 162.625
+PHY-3002 : Step(241): len = 610918, overlap = 158.625
+PHY-3002 : Step(242): len = 608718, overlap = 152.406
+PHY-3002 : Step(243): len = 607826, overlap = 147.906
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000190507
+PHY-3002 : Step(244): len = 608104, overlap = 146.5
+PHY-3002 : Step(245): len = 609952, overlap = 144.406
+PHY-3002 : Step(246): len = 613212, overlap = 135.438
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000381013
+PHY-3002 : Step(247): len = 619115, overlap = 127.594
+PHY-3002 : Step(248): len = 628239, overlap = 120.031
+PHY-3002 : Step(249): len = 634393, overlap = 109.594
+PHY-3002 : Step(250): len = 632138, overlap = 110.938
+PHY-3002 : Step(251): len = 631285, overlap = 111.781
+PHY-3002 : Step(252): len = 629904, overlap = 105.25
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000762026
+PHY-3002 : Step(253): len = 636003, overlap = 99.5312
+PHY-3002 : Step(254): len = 640928, overlap = 90.8125
+PHY-3002 : Step(255): len = 643791, overlap = 86.125
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.489666s wall, 1.437500s user + 0.062500s system = 1.500000s CPU (100.7%)
+
+RUN-1004 : used memory is 572 MB, reserved memory is 561 MB, peak memory is 707 MB
+OPT-1001 : Total overflow 410.41 peak overflow 4.03
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1303/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 742520, over cnt = 2941(8%), over = 10698, worst = 26
+PHY-1001 : End global iterations; 1.214371s wall, 1.828125s user + 0.031250s system = 1.859375s CPU (153.1%)
+
+PHY-1001 : Congestion index: top1 = 76.31, top5 = 58.18, top10 = 51.24, top15 = 47.26.
+PHY-1001 : End incremental global routing; 1.562729s wall, 2.187500s user + 0.031250s system = 2.218750s CPU (142.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.946410s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (99.1%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17535 has valid locations, 334 needs to be replaced
+PHY-3001 : design contains 17954 instances, 7508 luts, 9225 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6026 pins
+PHY-3001 : Found 1238 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 667213
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16511/20534.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 756704, over cnt = 3016(8%), over = 10803, worst = 26
+PHY-1001 : End global iterations; 0.248043s wall, 0.375000s user + 0.015625s system = 0.390625s CPU (157.5%)
+
+PHY-1001 : Congestion index: top1 = 75.88, top5 = 58.07, top10 = 51.34, top15 = 47.46.
+PHY-3001 : End congestion estimation; 0.510985s wall, 0.625000s user + 0.031250s system = 0.656250s CPU (128.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85764, tnet num: 20356, tinst num: 17954, tnode num: 116421, tedge num: 137546.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.545929s wall, 1.468750s user + 0.015625s system = 1.484375s CPU (96.0%)
+
+RUN-1004 : used memory is 616 MB, reserved memory is 615 MB, peak memory is 711 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20356 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.523984s wall, 2.421875s user + 0.046875s system = 2.468750s CPU (97.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(256): len = 666107, overlap = 0.4375
+PHY-3002 : Step(257): len = 665569, overlap = 0.4375
+PHY-3002 : Step(258): len = 665297, overlap = 0.4375
+PHY-3002 : Step(259): len = 664993, overlap = 0.4375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16606/20534.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 753976, over cnt = 3007(8%), over = 10860, worst = 26
+PHY-1001 : End global iterations; 0.199657s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (164.3%)
+
+PHY-1001 : Congestion index: top1 = 76.12, top5 = 58.52, top10 = 51.63, top15 = 47.67.
+PHY-3001 : End congestion estimation; 0.468040s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (126.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20356 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.955925s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (101.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000417609
+PHY-3002 : Step(260): len = 664892, overlap = 89.125
+PHY-3002 : Step(261): len = 664872, overlap = 88.2188
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000835219
+PHY-3002 : Step(262): len = 665255, overlap = 88.0625
+PHY-3002 : Step(263): len = 665903, overlap = 87.9688
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00167044
+PHY-3002 : Step(264): len = 666030, overlap = 87.625
+PHY-3002 : Step(265): len = 666619, overlap = 87.5625
+PHY-3001 : Final: Len = 666619, Over = 87.5625
+PHY-3001 : End incremental placement; 5.295196s wall, 5.625000s user + 0.281250s system = 5.906250s CPU (111.5%)
+
+OPT-1001 : Total overflow 415.34 peak overflow 4.03
+OPT-1001 : End high-fanout net optimization; 8.459238s wall, 9.453125s user + 0.343750s system = 9.796875s CPU (115.8%)
+
+OPT-1001 : Current memory(MB): used = 712, reserve = 707, peak = 729.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16540/20534.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 758632, over cnt = 2948(8%), over = 9791, worst = 26
+PHY-1002 : len = 805064, over cnt = 2025(5%), over = 5115, worst = 20
+PHY-1002 : len = 850104, over cnt = 769(2%), over = 1589, worst = 15
+PHY-1002 : len = 857912, over cnt = 421(1%), over = 966, worst = 11
+PHY-1002 : len = 876416, over cnt = 13(0%), over = 40, worst = 7
+PHY-1001 : End global iterations; 1.923722s wall, 2.531250s user + 0.000000s system = 2.531250s CPU (131.6%)
+
+PHY-1001 : Congestion index: top1 = 60.82, top5 = 50.96, top10 = 46.89, top15 = 44.44.
+OPT-1001 : End congestion update; 2.197968s wall, 2.812500s user + 0.000000s system = 2.812500s CPU (128.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20356 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.845996s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.7%)
+
+OPT-0007 : Start: WNS -1018 TNS -1478 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 66 cells processed and 5800 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 30 cells processed and 100 slack improved
+OPT-1001 : End global optimization; 3.093924s wall, 3.703125s user + 0.000000s system = 3.703125s CPU (119.7%)
+
+OPT-1001 : Current memory(MB): used = 690, reserve = 687, peak = 729.
+OPT-1001 : End physical optimization; 13.581223s wall, 15.140625s user + 0.421875s system = 15.562500s CPU (114.6%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7508 LUT to BLE ...
+SYN-4008 : Packed 7508 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6092 remaining SEQ's ...
+SYN-4005 : Packed 3709 SEQ with LUT/SLICE
+SYN-4006 : 966 single LUT's are left
+SYN-4006 : 2383 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9891/13622 primitive instances ...
+PHY-3001 : End packing; 1.675539s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (100.7%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6872 instances
+RUN-1001 : 3362 mslices, 3362 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17532 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9993 nets have 2 pins
+RUN-1001 : 5747 nets have [3 - 5] pins
+RUN-1001 : 1112 nets have [6 - 10] pins
+RUN-1001 : 311 nets have [11 - 20] pins
+RUN-1001 : 338 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6870 instances, 6724 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3568 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 675132, Over = 277.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7346/17532.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 823800, over cnt = 1978(5%), over = 3290, worst = 9
+PHY-1002 : len = 831992, over cnt = 1371(3%), over = 2005, worst = 8
+PHY-1002 : len = 849696, over cnt = 409(1%), over = 560, worst = 6
+PHY-1002 : len = 857880, over cnt = 62(0%), over = 73, worst = 3
+PHY-1002 : len = 859416, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.729054s wall, 2.312500s user + 0.062500s system = 2.375000s CPU (137.4%)
+
+PHY-1001 : Congestion index: top1 = 59.83, top5 = 51.76, top10 = 47.35, top15 = 44.70.
+PHY-3001 : End congestion estimation; 2.137786s wall, 2.703125s user + 0.062500s system = 2.765625s CPU (129.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73632, tnet num: 17354, tinst num: 6870, tnode num: 96080, tedge num: 123596.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.661902s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (100.6%)
+
+RUN-1004 : used memory is 609 MB, reserved memory is 606 MB, peak memory is 729 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17354 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.552662s wall, 2.562500s user + 0.000000s system = 2.562500s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.88523e-05
+PHY-3002 : Step(266): len = 661140, overlap = 274.25
+PHY-3002 : Step(267): len = 653710, overlap = 280
+PHY-3002 : Step(268): len = 649655, overlap = 284.25
+PHY-3002 : Step(269): len = 647083, overlap = 292.5
+PHY-3002 : Step(270): len = 645043, overlap = 282.75
+PHY-3002 : Step(271): len = 643105, overlap = 279.25
+PHY-3002 : Step(272): len = 640639, overlap = 278.5
+PHY-3002 : Step(273): len = 638693, overlap = 276.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.77045e-05
+PHY-3002 : Step(274): len = 642361, overlap = 269.75
+PHY-3002 : Step(275): len = 647414, overlap = 256
+PHY-3002 : Step(276): len = 649658, overlap = 249.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000195409
+PHY-3002 : Step(277): len = 659283, overlap = 239.5
+PHY-3002 : Step(278): len = 672226, overlap = 223.25
+PHY-3002 : Step(279): len = 671704, overlap = 225.25
+PHY-3002 : Step(280): len = 670549, overlap = 232.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.406492s wall, 0.390625s user + 0.640625s system = 1.031250s CPU (253.7%)
+
+PHY-3001 : Trial Legalized: Len = 753636
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 792/17532.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 873560, over cnt = 2719(7%), over = 4582, worst = 7
+PHY-1002 : len = 892248, over cnt = 1535(4%), over = 2192, worst = 7
+PHY-1002 : len = 909088, over cnt = 599(1%), over = 843, worst = 6
+PHY-1002 : len = 917312, over cnt = 278(0%), over = 396, worst = 5
+PHY-1002 : len = 924208, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.806487s wall, 3.859375s user + 0.031250s system = 3.890625s CPU (138.6%)
+
+PHY-1001 : Congestion index: top1 = 55.11, top5 = 50.19, top10 = 47.25, top15 = 45.22.
+PHY-3001 : End congestion estimation; 3.284635s wall, 4.328125s user + 0.031250s system = 4.359375s CPU (132.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17354 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.884476s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (100.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000155931
+PHY-3002 : Step(281): len = 726546, overlap = 44.25
+PHY-3002 : Step(282): len = 710785, overlap = 72
+PHY-3002 : Step(283): len = 697535, overlap = 98.25
+PHY-3002 : Step(284): len = 689212, overlap = 117.75
+PHY-3002 : Step(285): len = 683437, overlap = 139.25
+PHY-3002 : Step(286): len = 679754, overlap = 156.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000311862
+PHY-3002 : Step(287): len = 686158, overlap = 154.25
+PHY-3002 : Step(288): len = 692183, overlap = 151
+PHY-3002 : Step(289): len = 693370, overlap = 149
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000604753
+PHY-3002 : Step(290): len = 698355, overlap = 149
+PHY-3002 : Step(291): len = 710746, overlap = 144.5
+PHY-3002 : Step(292): len = 718540, overlap = 143
+PHY-3002 : Step(293): len = 716475, overlap = 141
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.037230s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (83.9%)
+
+PHY-3001 : Legalized: Len = 744379, Over = 0
+PHY-3001 : Spreading special nets. 412 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.110275s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (99.2%)
+
+PHY-3001 : 616 instances has been re-located, deltaX = 245, deltaY = 355, maxDist = 3.
+PHY-3001 : Final: Len = 754347, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73632, tnet num: 17354, tinst num: 6873, tnode num: 96080, tedge num: 123596.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.902117s wall, 1.906250s user + 0.000000s system = 1.906250s CPU (100.2%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 636 MB, peak memory is 729 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3399/17532.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 887920, over cnt = 2525(7%), over = 4096, worst = 8
+PHY-1002 : len = 900752, over cnt = 1641(4%), over = 2359, worst = 6
+PHY-1002 : len = 916560, over cnt = 803(2%), over = 1143, worst = 6
+PHY-1002 : len = 930360, over cnt = 214(0%), over = 302, worst = 5
+PHY-1002 : len = 935080, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.122175s wall, 2.937500s user + 0.015625s system = 2.953125s CPU (139.2%)
+
+PHY-1001 : Congestion index: top1 = 56.83, top5 = 50.39, top10 = 47.27, top15 = 45.14.
+PHY-1001 : End incremental global routing; 2.509273s wall, 3.343750s user + 0.015625s system = 3.359375s CPU (133.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17354 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.890845s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.0%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6781 has valid locations, 21 needs to be replaced
+PHY-3001 : design contains 6890 instances, 6741 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3650 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 756870
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15971/17549.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 938192, over cnt = 73(0%), over = 81, worst = 3
+PHY-1002 : len = 938320, over cnt = 37(0%), over = 43, worst = 2
+PHY-1002 : len = 938408, over cnt = 20(0%), over = 24, worst = 2
+PHY-1002 : len = 938632, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.629294s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (101.8%)
+
+PHY-1001 : Congestion index: top1 = 56.83, top5 = 50.39, top10 = 47.27, top15 = 45.18.
+PHY-3001 : End congestion estimation; 0.974600s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (101.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73796, tnet num: 17371, tinst num: 6890, tnode num: 96281, tedge num: 123807.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.890183s wall, 1.890625s user + 0.000000s system = 1.890625s CPU (100.0%)
+
+RUN-1004 : used memory is 653 MB, reserved memory is 651 MB, peak memory is 729 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17371 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.811155s wall, 2.812500s user + 0.000000s system = 2.812500s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(294): len = 756027, overlap = 0
+PHY-3002 : Step(295): len = 755617, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 15954/17549.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 936448, over cnt = 57(0%), over = 80, worst = 5
+PHY-1002 : len = 936800, over cnt = 26(0%), over = 26, worst = 1
+PHY-1002 : len = 937048, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 937232, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.661335s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (101.6%)
+
+PHY-1001 : Congestion index: top1 = 56.83, top5 = 50.39, top10 = 47.27, top15 = 45.18.
+PHY-3001 : End congestion estimation; 0.990875s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (100.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17371 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.890243s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000188517
+PHY-3002 : Step(296): len = 755760, overlap = 2
+PHY-3002 : Step(297): len = 755760, overlap = 2
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005778s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (270.4%)
+
+PHY-3001 : Legalized: Len = 755879, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065326s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.7%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 11, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 756055, Over = 0
+PHY-3001 : End incremental placement; 6.208253s wall, 6.328125s user + 0.062500s system = 6.390625s CPU (102.9%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.108771s wall, 11.140625s user + 0.078125s system = 11.218750s CPU (111.0%)
+
+OPT-1001 : Current memory(MB): used = 737, reserve = 739, peak = 740.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15931/17549.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 937272, over cnt = 55(0%), over = 68, worst = 3
+PHY-1002 : len = 937360, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 937488, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 937616, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.632911s wall, 0.671875s user + 0.031250s system = 0.703125s CPU (111.1%)
+
+PHY-1001 : Congestion index: top1 = 56.83, top5 = 50.43, top10 = 47.28, top15 = 45.15.
+OPT-1001 : End congestion update; 0.967274s wall, 1.000000s user + 0.031250s system = 1.031250s CPU (106.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17371 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.739577s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.3%)
+
+OPT-0007 : Start: WNS -1136 TNS -1771 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6802 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6890 instances, 6741 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3650 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 760972, Over = 0
+PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063863s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.9%)
+
+PHY-3001 : 29 instances has been re-located, deltaX = 16, deltaY = 21, maxDist = 4.
+PHY-3001 : Final: Len = 761562, Over = 0
+PHY-3001 : End incremental legalization; 0.411792s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (121.4%)
+
+OPT-0007 : Iter 1: improved WNS -986 TNS -1471 NUM_FEPS 2 with 31 cells processed and 9350 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6802 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6890 instances, 6741 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3650 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 762460, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064032s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.6%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 6, deltaY = 9, maxDist = 2.
+PHY-3001 : Final: Len = 762624, Over = 0
+PHY-3001 : End incremental legalization; 0.407157s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (119.0%)
+
+OPT-0007 : Iter 2: improved WNS -1036 TNS -1521 NUM_FEPS 2 with 16 cells processed and 3200 slack improved
+OPT-1001 : End path based optimization; 2.807663s wall, 3.015625s user + 0.031250s system = 3.046875s CPU (108.5%)
+
+OPT-1001 : Current memory(MB): used = 738, reserve = 739, peak = 741.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17371 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.742451s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.9%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15794/17549.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 943616, over cnt = 100(0%), over = 128, worst = 5
+PHY-1002 : len = 943664, over cnt = 55(0%), over = 63, worst = 3
+PHY-1002 : len = 943944, over cnt = 30(0%), over = 33, worst = 2
+PHY-1002 : len = 944384, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 944400, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.898450s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (106.1%)
+
+PHY-1001 : Congestion index: top1 = 56.98, top5 = 50.41, top10 = 47.26, top15 = 45.18.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17371 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.867027s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.9%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -1036 TNS -1571 NUM_FEPS 2
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 56.655172
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -1036ps with logic level 2
+RUN-1001 : #2 path slack -990ps with logic level 2
+RUN-1001 : 0 HFN exist on timing critical paths out of 17549 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 17549 nets
+OPT-1001 : End physical optimization; 18.038364s wall, 19.328125s user + 0.109375s system = 19.437500s CPU (107.8%)
+
+RUN-1003 : finish command "place" in 63.048054s wall, 88.109375s user + 6.921875s system = 95.031250s CPU (150.7%)
+
+RUN-1004 : used memory is 644 MB, reserved memory is 636 MB, peak memory is 741 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.708805s wall, 2.984375s user + 0.015625s system = 3.000000s CPU (175.6%)
+
+RUN-1004 : used memory is 645 MB, reserved memory is 638 MB, peak memory is 741 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6892 instances
+RUN-1001 : 3379 mslices, 3362 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17549 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9991 nets have 2 pins
+RUN-1001 : 5747 nets have [3 - 5] pins
+RUN-1001 : 1115 nets have [6 - 10] pins
+RUN-1001 : 316 nets have [11 - 20] pins
+RUN-1001 : 352 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73796, tnet num: 17371, tinst num: 6890, tnode num: 96281, tedge num: 123807.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.615637s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (100.6%)
+
+RUN-1004 : used memory is 655 MB, reserved memory is 655 MB, peak memory is 741 MB
+PHY-1001 : 3379 mslices, 3362 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17371 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 875584, over cnt = 2745(7%), over = 4514, worst = 8
+PHY-1002 : len = 892552, over cnt = 1601(4%), over = 2358, worst = 8
+PHY-1002 : len = 911144, over cnt = 687(1%), over = 998, worst = 6
+PHY-1002 : len = 926056, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 926376, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.139281s wall, 4.140625s user + 0.031250s system = 4.171875s CPU (132.9%)
+
+PHY-1001 : Congestion index: top1 = 56.70, top5 = 50.20, top10 = 46.90, top15 = 44.74.
+PHY-1001 : End global routing; 3.484323s wall, 4.468750s user + 0.046875s system = 4.515625s CPU (129.6%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 716, reserve = 716, peak = 741.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 991, reserve = 992, peak = 991.
+PHY-1001 : End build detailed router design. 4.161704s wall, 4.140625s user + 0.015625s system = 4.156250s CPU (99.9%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 259504, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.786790s wall, 5.781250s user + 0.000000s system = 5.781250s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 259560, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.594768s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1027, reserve = 1028, peak = 1027.
+PHY-1001 : End phase 1; 6.394878s wall, 6.390625s user + 0.000000s system = 6.390625s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.36846e+06, over cnt = 1702(0%), over = 1715, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1044, reserve = 1045, peak = 1044.
+PHY-1001 : End initial routed; 36.419863s wall, 74.796875s user + 0.593750s system = 75.390625s CPU (207.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16472(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.951 | -4.087 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.356024s wall, 3.359375s user + 0.000000s system = 3.359375s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1058, reserve = 1059, peak = 1058.
+PHY-1001 : End phase 2; 39.775964s wall, 78.156250s user + 0.593750s system = 78.750000s CPU (198.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.951ns STNS -3.964ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.144892s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (107.8%)
+
+PHY-1022 : len = 2.36846e+06, over cnt = 1702(0%), over = 1715, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.452483s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.33651e+06, over cnt = 608(0%), over = 608, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.540139s wall, 2.921875s user + 0.000000s system = 2.921875s CPU (189.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.33466e+06, over cnt = 155(0%), over = 155, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.766827s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (136.5%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.3354e+06, over cnt = 18(0%), over = 18, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.508741s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (119.8%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.33566e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.365646s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (115.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.33569e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.228490s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.6%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.33569e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.284221s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (99.0%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.33569e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.466286s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (100.5%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.33572e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.195158s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (96.1%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.33575e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.169786s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16472(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.951 | -3.964 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.352285s wall, 3.343750s user + 0.000000s system = 3.343750s CPU (99.7%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 526 feed throughs used by 380 nets
+PHY-1001 : End commit to database; 2.326229s wall, 2.312500s user + 0.015625s system = 2.328125s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1159, reserve = 1164, peak = 1159.
+PHY-1001 : End phase 3; 11.098147s wall, 12.890625s user + 0.015625s system = 12.906250s CPU (116.3%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.951ns STNS -3.964ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.154634s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (101.0%)
+
+PHY-1022 : len = 2.33575e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.416099s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (97.6%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.951ns, -3.964ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16472(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.951 | -3.964 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.314091s wall, 3.312500s user + 0.000000s system = 3.312500s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 526 feed throughs used by 380 nets
+PHY-1001 : End commit to database; 2.394286s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1167, reserve = 1173, peak = 1167.
+PHY-1001 : End phase 4; 6.151829s wall, 6.156250s user + 0.000000s system = 6.156250s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.33575e+06
+PHY-1001 : Current memory(MB): used = 1170, reserve = 1176, peak = 1170.
+PHY-1001 : End export database. 0.063245s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.8%)
+
+PHY-1001 : End detail routing; 68.062780s wall, 108.218750s user + 0.625000s system = 108.843750s CPU (159.9%)
+
+RUN-1003 : finish command "route" in 74.250306s wall, 115.390625s user + 0.671875s system = 116.062500s CPU (156.3%)
+
+RUN-1004 : used memory is 1093 MB, reserved memory is 1107 MB, peak memory is 1170 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10245 out of 19600 52.27%
+#reg 9361 out of 19600 47.76%
+#le 12551
+ #lut only 3190 out of 12551 25.42%
+ #reg only 2306 out of 12551 18.37%
+ #lut® 7055 out of 12551 56.21%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1809
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1417
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1346
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 941
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 131
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 68
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 68
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg48_syn_210.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/reg3_syn_169.f0 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P140 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P17 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P19 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P16 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P111 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P104 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P83 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P35 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12551 |9218 |1027 |9393 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |550 |445 |23 |441 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |99 |81 |4 |88 |4 |0 |
+| U_ecc_gen |ecc_gen |12 |12 |0 |8 |0 |0 |
+| U_crc16_24b |crc16_24b |22 |22 |0 |17 |0 |0 |
+| exdev_ctl_a |exdev_ctl |767 |404 |96 |579 |0 |0 |
+| u_ADconfig |AD_config |187 |131 |25 |143 |0 |0 |
+| u_gen_sp |gen_sp |264 |157 |71 |120 |0 |0 |
+| exdev_ctl_b |exdev_ctl |745 |410 |96 |555 |0 |0 |
+| u_ADconfig |AD_config |175 |129 |25 |129 |0 |0 |
+| u_gen_sp |gen_sp |262 |166 |71 |118 |0 |0 |
+| sampling_fe_a |sampling_fe |3099 |2430 |306 |2051 |25 |0 |
+| u0_soft_n |cdc_sync |7 |1 |0 |7 |0 |0 |
+| u_ad_sampling |ad_sampling |176 |102 |17 |140 |0 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_sort |sort |2886 |2324 |289 |1874 |25 |0 |
+| rddpram_ctl |rddpram_ctl |4 |3 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u0_wrsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2449 |2003 |253 |1517 |22 |0 |
+| channelPart |channel_part_8478 |136 |131 |3 |122 |0 |0 |
+| fifo_adc |fifo_adc |62 |53 |9 |45 |0 |0 |
+| ram_switch |ram_switch |1950 |1570 |197 |1135 |0 |0 |
+| adc_addr_gen |adc_addr_gen |254 |225 |27 |121 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |15 |10 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |27 |24 |3 |16 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |27 |24 |3 |12 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |25 |22 |3 |14 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |21 |18 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
+| insert |insert |953 |602 |170 |658 |0 |0 |
+| ram_switch_state |ram_switch_state |743 |743 |0 |356 |0 |0 |
+| read_ram_i |read_ram |272 |222 |44 |190 |0 |0 |
+| read_ram_addr |read_ram_addr |217 |177 |40 |149 |0 |0 |
+| read_ram_data |read_ram_data |52 |45 |4 |38 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |0 |0 |3 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |336 |236 |36 |280 |3 |0 |
+| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3300 |2574 |349 |2072 |25 |1 |
+| u0_soft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |174 |140 |17 |136 |0 |0 |
+| u0_soft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_sort |sort_rev |3092 |2419 |332 |1902 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |3 |3 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2657 |2102 |290 |1551 |22 |1 |
+| channelPart |channel_part_8478 |220 |204 |3 |133 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |44 |0 |1 |
+| ram_switch |ram_switch |1984 |1567 |197 |1133 |0 |0 |
+| adc_addr_gen |adc_addr_gen |221 |194 |27 |108 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |11 |8 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |16 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 |
+| insert |insert |992 |603 |170 |678 |0 |0 |
+| ram_switch_state |ram_switch_state |771 |770 |0 |347 |0 |0 |
+| read_ram_i |read_ram_rev |367 |259 |81 |215 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |297 |214 |73 |165 |0 |0 |
+| read_ram_data |read_ram_data_rev |70 |45 |8 |50 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9929
+ #2 2 3788
+ #3 3 1383
+ #4 4 573
+ #5 5-10 1174
+ #6 11-50 584
+ #7 51-100 22
+ #8 >500 1
+ Average 2.91
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.111414s wall, 3.609375s user + 0.062500s system = 3.671875s CPU (173.9%)
+
+RUN-1004 : used memory is 1094 MB, reserved memory is 1108 MB, peak memory is 1170 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73796, tnet num: 17371, tinst num: 6890, tnode num: 96281, tedge num: 123807.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.649555s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.5%)
+
+RUN-1004 : used memory is 1098 MB, reserved memory is 1111 MB, peak memory is 1170 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17371 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.507022s wall, 1.500000s user + 0.015625s system = 1.515625s CPU (100.6%)
+
+RUN-1004 : used memory is 1100 MB, reserved memory is 1113 MB, peak memory is 1170 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6890
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17549, pip num: 173091
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 526
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3258 valid insts, and 479736 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 10.588263s wall, 55.640625s user + 0.796875s system = 56.437500s CPU (533.0%)
+
+RUN-1004 : used memory is 1263 MB, reserved memory is 1266 MB, peak memory is 1379 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240219_104251.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240219_105751.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240219_105751.log
new file mode 100644
index 0000000..52d96d2
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240219_105751.log
@@ -0,0 +1,1854 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Feb 19 10:57:51 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.171020s wall, 2.093750s user + 0.078125s system = 2.171875s CPU (100.0%)
+
+RUN-1004 : used memory is 336 MB, reserved memory is 314 MB, peak memory is 340 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17673 instances
+RUN-0007 : 7407 luts, 9043 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20251 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13316 nets have 2 pins
+RUN-1001 : 5518 nets have [3 - 5] pins
+RUN-1001 : 1004 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 177 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 1968
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17671 instances, 7407 luts, 9043 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5897 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.161753s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (100.9%)
+
+RUN-1004 : used memory is 528 MB, reserved memory is 512 MB, peak memory is 528 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.976174s wall, 1.968750s user + 0.015625s system = 1.984375s CPU (100.4%)
+
+PHY-3001 : Found 1227 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.09967e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17671.
+PHY-3001 : Level 1 #clusters 2000.
+PHY-3001 : End clustering; 0.125609s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (136.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28668e+06, overlap = 484.094
+PHY-3002 : Step(2): len = 1.18318e+06, overlap = 557.375
+PHY-3002 : Step(3): len = 843931, overlap = 601.625
+PHY-3002 : Step(4): len = 791874, overlap = 624.344
+PHY-3002 : Step(5): len = 609615, overlap = 754.969
+PHY-3002 : Step(6): len = 529112, overlap = 805.719
+PHY-3002 : Step(7): len = 456874, overlap = 912.031
+PHY-3002 : Step(8): len = 425331, overlap = 995.844
+PHY-3002 : Step(9): len = 378282, overlap = 1057.66
+PHY-3002 : Step(10): len = 340965, overlap = 1115.97
+PHY-3002 : Step(11): len = 297218, overlap = 1185.28
+PHY-3002 : Step(12): len = 272422, overlap = 1214.28
+PHY-3002 : Step(13): len = 251103, overlap = 1252.66
+PHY-3002 : Step(14): len = 233830, overlap = 1297.31
+PHY-3002 : Step(15): len = 207240, overlap = 1327.09
+PHY-3002 : Step(16): len = 192315, overlap = 1358.84
+PHY-3002 : Step(17): len = 174239, overlap = 1404.44
+PHY-3002 : Step(18): len = 162009, overlap = 1423.03
+PHY-3002 : Step(19): len = 147685, overlap = 1465.97
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.2036e-06
+PHY-3002 : Step(20): len = 148424, overlap = 1423.66
+PHY-3002 : Step(21): len = 179191, overlap = 1304.53
+PHY-3002 : Step(22): len = 190294, overlap = 1232.22
+PHY-3002 : Step(23): len = 199319, overlap = 1189.78
+PHY-3002 : Step(24): len = 198566, overlap = 1179.34
+PHY-3002 : Step(25): len = 198247, overlap = 1163.12
+PHY-3002 : Step(26): len = 195020, overlap = 1157.25
+PHY-3002 : Step(27): len = 194648, overlap = 1158.09
+PHY-3002 : Step(28): len = 193918, overlap = 1142.66
+PHY-3002 : Step(29): len = 192851, overlap = 1149.03
+PHY-3002 : Step(30): len = 191764, overlap = 1148.06
+PHY-3002 : Step(31): len = 190566, overlap = 1168.28
+PHY-3002 : Step(32): len = 188829, overlap = 1145.56
+PHY-3002 : Step(33): len = 188125, overlap = 1149.47
+PHY-3002 : Step(34): len = 187128, overlap = 1136
+PHY-3002 : Step(35): len = 186806, overlap = 1099.56
+PHY-3002 : Step(36): len = 184419, overlap = 1073.5
+PHY-3002 : Step(37): len = 183688, overlap = 1074.06
+PHY-3002 : Step(38): len = 181963, overlap = 1075.84
+PHY-3002 : Step(39): len = 180821, overlap = 1100.16
+PHY-3002 : Step(40): len = 180049, overlap = 1107.62
+PHY-3002 : Step(41): len = 178563, overlap = 1115.78
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.40721e-06
+PHY-3002 : Step(42): len = 182212, overlap = 1088.72
+PHY-3002 : Step(43): len = 192003, overlap = 1041.94
+PHY-3002 : Step(44): len = 195313, overlap = 996.5
+PHY-3002 : Step(45): len = 200502, overlap = 971.938
+PHY-3002 : Step(46): len = 203704, overlap = 964.062
+PHY-3002 : Step(47): len = 207043, overlap = 946.125
+PHY-3002 : Step(48): len = 207363, overlap = 916.281
+PHY-3002 : Step(49): len = 207868, overlap = 907.031
+PHY-3002 : Step(50): len = 206820, overlap = 918.844
+PHY-3002 : Step(51): len = 206254, overlap = 931.125
+PHY-3002 : Step(52): len = 204603, overlap = 938.312
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.81441e-06
+PHY-3002 : Step(53): len = 211487, overlap = 931
+PHY-3002 : Step(54): len = 228174, overlap = 895.562
+PHY-3002 : Step(55): len = 237150, overlap = 803.812
+PHY-3002 : Step(56): len = 242854, overlap = 767.344
+PHY-3002 : Step(57): len = 244809, overlap = 750.625
+PHY-3002 : Step(58): len = 247200, overlap = 746.219
+PHY-3002 : Step(59): len = 246762, overlap = 749.906
+PHY-3002 : Step(60): len = 246476, overlap = 758.188
+PHY-3002 : Step(61): len = 245504, overlap = 776.312
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.62883e-06
+PHY-3002 : Step(62): len = 259270, overlap = 736.844
+PHY-3002 : Step(63): len = 280310, overlap = 622.125
+PHY-3002 : Step(64): len = 289452, overlap = 594.688
+PHY-3002 : Step(65): len = 292950, overlap = 596.625
+PHY-3002 : Step(66): len = 291834, overlap = 562.719
+PHY-3002 : Step(67): len = 289272, overlap = 547.375
+PHY-3002 : Step(68): len = 287091, overlap = 546.344
+PHY-3002 : Step(69): len = 287110, overlap = 528.281
+PHY-3002 : Step(70): len = 287591, overlap = 509.438
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.92577e-05
+PHY-3002 : Step(71): len = 306070, overlap = 487.531
+PHY-3002 : Step(72): len = 321535, overlap = 471.406
+PHY-3002 : Step(73): len = 327807, overlap = 437.219
+PHY-3002 : Step(74): len = 332649, overlap = 431.281
+PHY-3002 : Step(75): len = 331947, overlap = 424.094
+PHY-3002 : Step(76): len = 332519, overlap = 428.656
+PHY-3002 : Step(77): len = 332226, overlap = 415.594
+PHY-3002 : Step(78): len = 331189, overlap = 397.969
+PHY-3002 : Step(79): len = 330580, overlap = 386.438
+PHY-3002 : Step(80): len = 331430, overlap = 383.438
+PHY-3002 : Step(81): len = 332546, overlap = 365.906
+PHY-3002 : Step(82): len = 332833, overlap = 367.281
+PHY-3002 : Step(83): len = 331822, overlap = 367.219
+PHY-3002 : Step(84): len = 332233, overlap = 356.375
+PHY-3002 : Step(85): len = 331344, overlap = 344.094
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.85153e-05
+PHY-3002 : Step(86): len = 350518, overlap = 322.5
+PHY-3002 : Step(87): len = 360328, overlap = 306.594
+PHY-3002 : Step(88): len = 357880, overlap = 317.406
+PHY-3002 : Step(89): len = 358822, overlap = 305.344
+PHY-3002 : Step(90): len = 363911, overlap = 302.406
+PHY-3002 : Step(91): len = 367835, overlap = 304.938
+PHY-3002 : Step(92): len = 363522, overlap = 317.188
+PHY-3002 : Step(93): len = 365018, overlap = 310.875
+PHY-3002 : Step(94): len = 367761, overlap = 310.25
+PHY-3002 : Step(95): len = 369860, overlap = 319.094
+PHY-3002 : Step(96): len = 365177, overlap = 314.25
+PHY-3002 : Step(97): len = 363436, overlap = 316.188
+PHY-3002 : Step(98): len = 364963, overlap = 322.094
+PHY-3002 : Step(99): len = 366885, overlap = 314
+PHY-3002 : Step(100): len = 363632, overlap = 313.844
+PHY-3002 : Step(101): len = 363549, overlap = 310.25
+PHY-3002 : Step(102): len = 364192, overlap = 304.562
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.70306e-05
+PHY-3002 : Step(103): len = 382186, overlap = 300.719
+PHY-3002 : Step(104): len = 393320, overlap = 290.438
+PHY-3002 : Step(105): len = 390061, overlap = 265.469
+PHY-3002 : Step(106): len = 389428, overlap = 253.938
+PHY-3002 : Step(107): len = 394384, overlap = 237.344
+PHY-3002 : Step(108): len = 399627, overlap = 227.5
+PHY-3002 : Step(109): len = 397812, overlap = 236.219
+PHY-3002 : Step(110): len = 399415, overlap = 243.656
+PHY-3002 : Step(111): len = 402607, overlap = 242.125
+PHY-3002 : Step(112): len = 404322, overlap = 239.312
+PHY-3002 : Step(113): len = 400761, overlap = 240.844
+PHY-3002 : Step(114): len = 399368, overlap = 243.125
+PHY-3002 : Step(115): len = 401595, overlap = 233.938
+PHY-3002 : Step(116): len = 404676, overlap = 239.812
+PHY-3002 : Step(117): len = 400962, overlap = 247.219
+PHY-3002 : Step(118): len = 400739, overlap = 247.281
+PHY-3002 : Step(119): len = 402377, overlap = 239.938
+PHY-3002 : Step(120): len = 404242, overlap = 244.781
+PHY-3002 : Step(121): len = 401723, overlap = 248.594
+PHY-3002 : Step(122): len = 401871, overlap = 252.375
+PHY-3002 : Step(123): len = 404195, overlap = 251.375
+PHY-3002 : Step(124): len = 406140, overlap = 257.312
+PHY-3002 : Step(125): len = 403540, overlap = 259.656
+PHY-3002 : Step(126): len = 403245, overlap = 259.188
+PHY-3002 : Step(127): len = 403984, overlap = 258
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000154061
+PHY-3002 : Step(128): len = 419164, overlap = 244.906
+PHY-3002 : Step(129): len = 428463, overlap = 233.125
+PHY-3002 : Step(130): len = 426829, overlap = 217.812
+PHY-3002 : Step(131): len = 427102, overlap = 211.844
+PHY-3002 : Step(132): len = 429947, overlap = 210.938
+PHY-3002 : Step(133): len = 431921, overlap = 206.281
+PHY-3002 : Step(134): len = 429822, overlap = 204.156
+PHY-3002 : Step(135): len = 430225, overlap = 212.344
+PHY-3002 : Step(136): len = 432285, overlap = 210.5
+PHY-3002 : Step(137): len = 434226, overlap = 207.281
+PHY-3002 : Step(138): len = 433644, overlap = 199.531
+PHY-3002 : Step(139): len = 434785, overlap = 208.406
+PHY-3002 : Step(140): len = 436011, overlap = 203.75
+PHY-3002 : Step(141): len = 437222, overlap = 200.469
+PHY-3002 : Step(142): len = 436221, overlap = 201.188
+PHY-3002 : Step(143): len = 436724, overlap = 207.406
+PHY-3002 : Step(144): len = 437985, overlap = 207.875
+PHY-3002 : Step(145): len = 439045, overlap = 207.375
+PHY-3002 : Step(146): len = 437923, overlap = 207.281
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000297449
+PHY-3002 : Step(147): len = 447213, overlap = 201.406
+PHY-3002 : Step(148): len = 454452, overlap = 203.656
+PHY-3002 : Step(149): len = 454959, overlap = 198.281
+PHY-3002 : Step(150): len = 455780, overlap = 191
+PHY-3002 : Step(151): len = 458270, overlap = 186.562
+PHY-3002 : Step(152): len = 459849, overlap = 184
+PHY-3002 : Step(153): len = 458838, overlap = 186.688
+PHY-3002 : Step(154): len = 459485, overlap = 181.969
+PHY-3002 : Step(155): len = 461789, overlap = 184.562
+PHY-3002 : Step(156): len = 463496, overlap = 173.094
+PHY-3002 : Step(157): len = 462326, overlap = 171.438
+PHY-3002 : Step(158): len = 462656, overlap = 170.656
+PHY-3002 : Step(159): len = 464690, overlap = 167.469
+PHY-3002 : Step(160): len = 466201, overlap = 171.656
+PHY-3002 : Step(161): len = 465166, overlap = 165.188
+PHY-3002 : Step(162): len = 465218, overlap = 167.594
+PHY-3002 : Step(163): len = 466623, overlap = 165.719
+PHY-3002 : Step(164): len = 467287, overlap = 162.25
+PHY-3002 : Step(165): len = 466412, overlap = 161.688
+PHY-3002 : Step(166): len = 466327, overlap = 158.469
+PHY-3002 : Step(167): len = 467295, overlap = 161.75
+PHY-3002 : Step(168): len = 468354, overlap = 160.594
+PHY-3002 : Step(169): len = 468124, overlap = 155.656
+PHY-3002 : Step(170): len = 468614, overlap = 159.062
+PHY-3002 : Step(171): len = 469394, overlap = 153.281
+PHY-3002 : Step(172): len = 469789, overlap = 151.75
+PHY-3002 : Step(173): len = 470169, overlap = 135.656
+PHY-3002 : Step(174): len = 471663, overlap = 137.594
+PHY-3002 : Step(175): len = 472466, overlap = 133.844
+PHY-3002 : Step(176): len = 473025, overlap = 132.812
+PHY-3002 : Step(177): len = 472951, overlap = 135.25
+PHY-3002 : Step(178): len = 473084, overlap = 136.938
+PHY-3002 : Step(179): len = 473356, overlap = 135.25
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000566962
+PHY-3002 : Step(180): len = 479949, overlap = 132.312
+PHY-3002 : Step(181): len = 485650, overlap = 134
+PHY-3002 : Step(182): len = 486958, overlap = 125.781
+PHY-3002 : Step(183): len = 488201, overlap = 126
+PHY-3002 : Step(184): len = 490404, overlap = 126.844
+PHY-3002 : Step(185): len = 492125, overlap = 131.5
+PHY-3002 : Step(186): len = 492854, overlap = 128.094
+PHY-3002 : Step(187): len = 494116, overlap = 125.406
+PHY-3002 : Step(188): len = 496340, overlap = 126.312
+PHY-3002 : Step(189): len = 497988, overlap = 123.688
+PHY-3002 : Step(190): len = 498041, overlap = 122.812
+PHY-3002 : Step(191): len = 498102, overlap = 120.5
+PHY-3002 : Step(192): len = 498689, overlap = 124.594
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00109183
+PHY-3002 : Step(193): len = 502699, overlap = 120.406
+PHY-3002 : Step(194): len = 508726, overlap = 117.844
+PHY-3002 : Step(195): len = 511069, overlap = 114.281
+PHY-3002 : Step(196): len = 512644, overlap = 114.906
+PHY-3002 : Step(197): len = 513979, overlap = 114.875
+PHY-3002 : Step(198): len = 515197, overlap = 112.781
+PHY-3002 : Step(199): len = 515367, overlap = 112.906
+PHY-3002 : Step(200): len = 515820, overlap = 108.875
+PHY-3002 : Step(201): len = 516704, overlap = 111.188
+PHY-3002 : Step(202): len = 517142, overlap = 112.75
+PHY-3002 : Step(203): len = 517073, overlap = 107.688
+PHY-3002 : Step(204): len = 517115, overlap = 107.688
+PHY-3002 : Step(205): len = 517492, overlap = 112
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00191502
+PHY-3002 : Step(206): len = 520575, overlap = 107.125
+PHY-3002 : Step(207): len = 525493, overlap = 102.531
+PHY-3002 : Step(208): len = 526615, overlap = 100.969
+PHY-3002 : Step(209): len = 527208, overlap = 101.75
+PHY-3002 : Step(210): len = 528067, overlap = 102.562
+PHY-3002 : Step(211): len = 529197, overlap = 104.125
+PHY-3002 : Step(212): len = 530271, overlap = 102.125
+PHY-3002 : Step(213): len = 532302, overlap = 102.125
+PHY-3002 : Step(214): len = 533399, overlap = 103.219
+PHY-3002 : Step(215): len = 533896, overlap = 100.969
+PHY-3002 : Step(216): len = 534380, overlap = 98.9375
+PHY-3002 : Step(217): len = 534814, overlap = 96.5
+PHY-3002 : Step(218): len = 535308, overlap = 96.6875
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.014083s wall, 0.031250s user + 0.015625s system = 0.046875s CPU (332.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 705016, over cnt = 1536(4%), over = 7270, worst = 58
+PHY-1001 : End global iterations; 0.697043s wall, 1.015625s user + 0.046875s system = 1.062500s CPU (152.4%)
+
+PHY-1001 : Congestion index: top1 = 78.64, top5 = 60.55, top10 = 51.46, top15 = 45.82.
+PHY-3001 : End congestion estimation; 0.923953s wall, 1.265625s user + 0.046875s system = 1.312500s CPU (142.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.844461s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000143207
+PHY-3002 : Step(219): len = 646213, overlap = 36.1875
+PHY-3002 : Step(220): len = 644319, overlap = 34.0938
+PHY-3002 : Step(221): len = 639708, overlap = 39.3438
+PHY-3002 : Step(222): len = 639697, overlap = 46.5312
+PHY-3002 : Step(223): len = 642009, overlap = 48.0312
+PHY-3002 : Step(224): len = 641422, overlap = 47.8125
+PHY-3002 : Step(225): len = 640251, overlap = 44.2188
+PHY-3002 : Step(226): len = 638069, overlap = 35.5625
+PHY-3002 : Step(227): len = 635262, overlap = 23.5
+PHY-3002 : Step(228): len = 631544, overlap = 27.6875
+PHY-3002 : Step(229): len = 628555, overlap = 28.2812
+PHY-3002 : Step(230): len = 626551, overlap = 29.0312
+PHY-3002 : Step(231): len = 624331, overlap = 32.0312
+PHY-3002 : Step(232): len = 622629, overlap = 37.5625
+PHY-3002 : Step(233): len = 620279, overlap = 34.2812
+PHY-3002 : Step(234): len = 620152, overlap = 34.7812
+PHY-3002 : Step(235): len = 617309, overlap = 36.5625
+PHY-3002 : Step(236): len = 615563, overlap = 38.2188
+PHY-3002 : Step(237): len = 614250, overlap = 37.7812
+PHY-3002 : Step(238): len = 613568, overlap = 37.75
+PHY-3002 : Step(239): len = 611804, overlap = 36.5
+PHY-3002 : Step(240): len = 610938, overlap = 38.875
+PHY-3002 : Step(241): len = 609379, overlap = 39.9062
+PHY-3002 : Step(242): len = 608310, overlap = 39.2812
+PHY-3002 : Step(243): len = 607656, overlap = 40.0312
+PHY-3002 : Step(244): len = 605710, overlap = 41.8438
+PHY-3002 : Step(245): len = 605011, overlap = 44.0625
+PHY-3002 : Step(246): len = 603058, overlap = 43.3438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000286414
+PHY-3002 : Step(247): len = 605841, overlap = 43.4688
+PHY-3002 : Step(248): len = 609140, overlap = 42.8438
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000469768
+PHY-3002 : Step(249): len = 613099, overlap = 42.2188
+PHY-3002 : Step(250): len = 620558, overlap = 41.125
+PHY-3002 : Step(251): len = 635556, overlap = 34.5938
+PHY-3002 : Step(252): len = 638311, overlap = 33.125
+PHY-3002 : Step(253): len = 640895, overlap = 31.9375
+PHY-3002 : Step(254): len = 642045, overlap = 32.5625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 40/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 731656, over cnt = 2654(7%), over = 12250, worst = 64
+PHY-1001 : End global iterations; 1.758166s wall, 2.359375s user + 0.046875s system = 2.406250s CPU (136.9%)
+
+PHY-1001 : Congestion index: top1 = 85.02, top5 = 66.04, top10 = 57.79, top15 = 52.68.
+PHY-3001 : End congestion estimation; 2.028716s wall, 2.640625s user + 0.046875s system = 2.687500s CPU (132.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.066492s wall, 1.031250s user + 0.031250s system = 1.062500s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00012412
+PHY-3002 : Step(255): len = 634493, overlap = 218.594
+PHY-3002 : Step(256): len = 633945, overlap = 186.656
+PHY-3002 : Step(257): len = 624281, overlap = 182.938
+PHY-3002 : Step(258): len = 620956, overlap = 176.469
+PHY-3002 : Step(259): len = 616979, overlap = 157.156
+PHY-3002 : Step(260): len = 613520, overlap = 135.344
+PHY-3002 : Step(261): len = 609779, overlap = 127.906
+PHY-3002 : Step(262): len = 608368, overlap = 127.469
+PHY-3002 : Step(263): len = 603987, overlap = 124.812
+PHY-3002 : Step(264): len = 601816, overlap = 126.906
+PHY-3002 : Step(265): len = 599563, overlap = 125.969
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00024824
+PHY-3002 : Step(266): len = 599695, overlap = 121.312
+PHY-3002 : Step(267): len = 601392, overlap = 118.5
+PHY-3002 : Step(268): len = 603887, overlap = 117.031
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000496481
+PHY-3002 : Step(269): len = 610653, overlap = 103.031
+PHY-3002 : Step(270): len = 617658, overlap = 96.375
+PHY-3002 : Step(271): len = 621957, overlap = 93.625
+PHY-3002 : Step(272): len = 624159, overlap = 89.5625
+PHY-3002 : Step(273): len = 623537, overlap = 89.2188
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.458795s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (100.7%)
+
+RUN-1004 : used memory is 572 MB, reserved memory is 561 MB, peak memory is 708 MB
+OPT-1001 : Total overflow 402.84 peak overflow 2.69
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 966/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 725272, over cnt = 2983(8%), over = 10954, worst = 26
+PHY-1001 : End global iterations; 1.163434s wall, 1.734375s user + 0.015625s system = 1.750000s CPU (150.4%)
+
+PHY-1001 : Congestion index: top1 = 65.78, top5 = 55.57, top10 = 50.32, top15 = 46.98.
+PHY-1001 : End incremental global routing; 1.485633s wall, 2.062500s user + 0.015625s system = 2.078125s CPU (139.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.906483s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (100.0%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17535 has valid locations, 332 needs to be replaced
+PHY-3001 : design contains 17952 instances, 7503 luts, 9228 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6004 pins
+PHY-3001 : Found 1238 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 648311
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16555/20532.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 741400, over cnt = 3040(8%), over = 11005, worst = 23
+PHY-1001 : End global iterations; 0.250345s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (156.0%)
+
+PHY-1001 : Congestion index: top1 = 66.03, top5 = 56.05, top10 = 50.69, top15 = 47.27.
+PHY-3001 : End congestion estimation; 0.525617s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (124.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85749, tnet num: 20354, tinst num: 17952, tnode num: 116398, tedge num: 137520.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.456048s wall, 1.421875s user + 0.031250s system = 1.453125s CPU (99.8%)
+
+RUN-1004 : used memory is 616 MB, reserved memory is 619 MB, peak memory is 710 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20354 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.402078s wall, 2.343750s user + 0.062500s system = 2.406250s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(274): len = 647207, overlap = 0.4375
+PHY-3002 : Step(275): len = 646813, overlap = 0.4375
+PHY-3002 : Step(276): len = 646562, overlap = 0.4375
+PHY-3002 : Step(277): len = 646329, overlap = 0.4375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16669/20532.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 738224, over cnt = 3040(8%), over = 11020, worst = 23
+PHY-1001 : End global iterations; 0.232955s wall, 0.296875s user + 0.015625s system = 0.312500s CPU (134.1%)
+
+PHY-1001 : Congestion index: top1 = 66.44, top5 = 56.30, top10 = 50.96, top15 = 47.56.
+PHY-3001 : End congestion estimation; 0.494469s wall, 0.546875s user + 0.015625s system = 0.562500s CPU (113.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20354 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.000311s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000327438
+PHY-3002 : Step(278): len = 646336, overlap = 91.7812
+PHY-3002 : Step(279): len = 646431, overlap = 91.4062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000654876
+PHY-3002 : Step(280): len = 646360, overlap = 90.7812
+PHY-3002 : Step(281): len = 646751, overlap = 91.4375
+PHY-3001 : Final: Len = 646751, Over = 91.4375
+PHY-3001 : End incremental placement; 5.153788s wall, 5.734375s user + 0.234375s system = 5.968750s CPU (115.8%)
+
+OPT-1001 : Total overflow 409.66 peak overflow 2.69
+OPT-1001 : End high-fanout net optimization; 8.186217s wall, 9.406250s user + 0.265625s system = 9.671875s CPU (118.1%)
+
+OPT-1001 : Current memory(MB): used = 715, reserve = 709, peak = 732.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16602/20532.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 740224, over cnt = 2991(8%), over = 9937, worst = 20
+PHY-1002 : len = 794184, over cnt = 2008(5%), over = 4860, worst = 18
+PHY-1002 : len = 828048, over cnt = 869(2%), over = 1996, worst = 17
+PHY-1002 : len = 852104, over cnt = 293(0%), over = 560, worst = 11
+PHY-1002 : len = 861664, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.010204s wall, 2.765625s user + 0.015625s system = 2.781250s CPU (138.4%)
+
+PHY-1001 : Congestion index: top1 = 55.04, top5 = 49.28, top10 = 45.86, top15 = 43.68.
+OPT-1001 : End congestion update; 2.319261s wall, 3.093750s user + 0.015625s system = 3.109375s CPU (134.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20354 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.814386s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.8%)
+
+OPT-0007 : Start: WNS -1018 TNS -1565 NUM_FEPS 3
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1565 NUM_FEPS 3 with 96 cells processed and 6778 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1565 NUM_FEPS 3 with 7 cells processed and 350 slack improved
+OPT-1001 : End global optimization; 3.178466s wall, 3.953125s user + 0.015625s system = 3.968750s CPU (124.9%)
+
+OPT-1001 : Current memory(MB): used = 695, reserve = 693, peak = 732.
+OPT-1001 : End physical optimization; 13.329156s wall, 15.296875s user + 0.296875s system = 15.593750s CPU (117.0%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7503 LUT to BLE ...
+SYN-4008 : Packed 7503 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6095 remaining SEQ's ...
+SYN-4005 : Packed 3693 SEQ with LUT/SLICE
+SYN-4006 : 969 single LUT's are left
+SYN-4006 : 2402 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9905/13636 primitive instances ...
+PHY-3001 : End packing; 1.652991s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (100.2%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6890 instances
+RUN-1001 : 3371 mslices, 3371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17530 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9969 nets have 2 pins
+RUN-1001 : 5758 nets have [3 - 5] pins
+RUN-1001 : 1123 nets have [6 - 10] pins
+RUN-1001 : 308 nets have [11 - 20] pins
+RUN-1001 : 340 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6888 instances, 6742 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3560 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 657912, Over = 251
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7593/17530.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 813888, over cnt = 1952(5%), over = 3148, worst = 7
+PHY-1002 : len = 821784, over cnt = 1230(3%), over = 1767, worst = 6
+PHY-1002 : len = 830520, over cnt = 722(2%), over = 1019, worst = 6
+PHY-1002 : len = 837008, over cnt = 475(1%), over = 681, worst = 6
+PHY-1002 : len = 845584, over cnt = 109(0%), over = 150, worst = 6
+PHY-1001 : End global iterations; 1.493644s wall, 2.187500s user + 0.000000s system = 2.187500s CPU (146.5%)
+
+PHY-1001 : Congestion index: top1 = 57.65, top5 = 50.04, top10 = 45.96, top15 = 43.38.
+PHY-3001 : End congestion estimation; 1.895549s wall, 2.578125s user + 0.000000s system = 2.578125s CPU (136.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73751, tnet num: 17352, tinst num: 6888, tnode num: 96233, tedge num: 123821.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.663680s wall, 1.656250s user + 0.015625s system = 1.671875s CPU (100.5%)
+
+RUN-1004 : used memory is 608 MB, reserved memory is 603 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17352 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.524608s wall, 2.500000s user + 0.031250s system = 2.531250s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.75783e-05
+PHY-3002 : Step(282): len = 645888, overlap = 249.75
+PHY-3002 : Step(283): len = 639979, overlap = 245.5
+PHY-3002 : Step(284): len = 636462, overlap = 252.5
+PHY-3002 : Step(285): len = 633658, overlap = 252.5
+PHY-3002 : Step(286): len = 630887, overlap = 260.75
+PHY-3002 : Step(287): len = 627447, overlap = 264
+PHY-3002 : Step(288): len = 624149, overlap = 268
+PHY-3002 : Step(289): len = 621609, overlap = 270.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.51567e-05
+PHY-3002 : Step(290): len = 624770, overlap = 262
+PHY-3002 : Step(291): len = 629314, overlap = 250.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000190313
+PHY-3002 : Step(292): len = 633723, overlap = 244
+PHY-3002 : Step(293): len = 645927, overlap = 215.75
+PHY-3002 : Step(294): len = 648474, overlap = 213.5
+PHY-3002 : Step(295): len = 649771, overlap = 210.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.398554s wall, 0.328125s user + 0.453125s system = 0.781250s CPU (196.0%)
+
+PHY-3001 : Trial Legalized: Len = 725964
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 759/17530.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 840944, over cnt = 2673(7%), over = 4537, worst = 8
+PHY-1002 : len = 859824, over cnt = 1524(4%), over = 2187, worst = 7
+PHY-1002 : len = 878400, over cnt = 481(1%), over = 720, worst = 7
+PHY-1002 : len = 886200, over cnt = 114(0%), over = 174, worst = 7
+PHY-1002 : len = 888632, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.310098s wall, 3.468750s user + 0.031250s system = 3.500000s CPU (151.5%)
+
+PHY-1001 : Congestion index: top1 = 53.23, top5 = 48.36, top10 = 45.74, top15 = 43.97.
+PHY-3001 : End congestion estimation; 2.768120s wall, 3.921875s user + 0.031250s system = 3.953125s CPU (142.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17352 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.857966s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (98.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000160038
+PHY-3002 : Step(296): len = 699842, overlap = 38.5
+PHY-3002 : Step(297): len = 685178, overlap = 66.25
+PHY-3002 : Step(298): len = 673051, overlap = 91.75
+PHY-3002 : Step(299): len = 666043, overlap = 117.25
+PHY-3002 : Step(300): len = 661142, overlap = 139.5
+PHY-3002 : Step(301): len = 658978, overlap = 146.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000320077
+PHY-3002 : Step(302): len = 665134, overlap = 141.75
+PHY-3002 : Step(303): len = 670968, overlap = 139.75
+PHY-3002 : Step(304): len = 671541, overlap = 147.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00063987
+PHY-3002 : Step(305): len = 676138, overlap = 148.5
+PHY-3002 : Step(306): len = 686491, overlap = 145
+PHY-3002 : Step(307): len = 691560, overlap = 146.25
+PHY-3002 : Step(308): len = 692892, overlap = 151.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.035092s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (89.1%)
+
+PHY-3001 : Legalized: Len = 721430, Over = 0
+PHY-3001 : Spreading special nets. 418 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.110096s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (99.3%)
+
+PHY-3001 : 612 instances has been re-located, deltaX = 269, deltaY = 342, maxDist = 3.
+PHY-3001 : Final: Len = 732202, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73751, tnet num: 17352, tinst num: 6891, tnode num: 96233, tedge num: 123821.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.874554s wall, 1.859375s user + 0.015625s system = 1.875000s CPU (100.0%)
+
+RUN-1004 : used memory is 612 MB, reserved memory is 607 MB, peak memory is 732 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3456/17530.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 859832, over cnt = 2564(7%), over = 4193, worst = 8
+PHY-1002 : len = 875568, over cnt = 1522(4%), over = 2156, worst = 6
+PHY-1002 : len = 887848, over cnt = 801(2%), over = 1128, worst = 6
+PHY-1002 : len = 899448, over cnt = 263(0%), over = 372, worst = 5
+PHY-1002 : len = 905456, over cnt = 12(0%), over = 15, worst = 2
+PHY-1001 : End global iterations; 1.903423s wall, 2.906250s user + 0.031250s system = 2.937500s CPU (154.3%)
+
+PHY-1001 : Congestion index: top1 = 53.38, top5 = 48.42, top10 = 45.65, top15 = 43.88.
+PHY-1001 : End incremental global routing; 2.274139s wall, 3.281250s user + 0.046875s system = 3.328125s CPU (146.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17352 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.862982s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.6%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6798 has valid locations, 27 needs to be replaced
+PHY-3001 : design contains 6913 instances, 6764 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3639 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 735387
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15975/17552.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 909520, over cnt = 90(0%), over = 105, worst = 5
+PHY-1002 : len = 909704, over cnt = 43(0%), over = 44, worst = 2
+PHY-1002 : len = 910104, over cnt = 19(0%), over = 19, worst = 1
+PHY-1002 : len = 910456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.622373s wall, 0.656250s user + 0.015625s system = 0.671875s CPU (108.0%)
+
+PHY-1001 : Congestion index: top1 = 53.36, top5 = 48.44, top10 = 45.71, top15 = 43.96.
+PHY-3001 : End congestion estimation; 0.931666s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (105.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73989, tnet num: 17374, tinst num: 6913, tnode num: 96516, tedge num: 124127.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.842906s wall, 1.812500s user + 0.031250s system = 1.843750s CPU (100.0%)
+
+RUN-1004 : used memory is 661 MB, reserved memory is 665 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.732448s wall, 2.671875s user + 0.062500s system = 2.734375s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(309): len = 734474, overlap = 0
+PHY-3002 : Step(310): len = 734081, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 15963/17552.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 908160, over cnt = 75(0%), over = 95, worst = 4
+PHY-1002 : len = 908296, over cnt = 39(0%), over = 42, worst = 2
+PHY-1002 : len = 908824, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 908920, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.653769s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (112.3%)
+
+PHY-1001 : Congestion index: top1 = 53.30, top5 = 48.44, top10 = 45.71, top15 = 43.95.
+PHY-3001 : End congestion estimation; 0.987356s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (107.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.862313s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000333503
+PHY-3002 : Step(311): len = 734109, overlap = 1.5
+PHY-3002 : Step(312): len = 734482, overlap = 1.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005911s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 734542, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059822s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (78.4%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 13, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 734724, Over = 0
+PHY-3001 : End incremental placement; 5.993245s wall, 6.046875s user + 0.171875s system = 6.218750s CPU (103.8%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.612886s wall, 10.796875s user + 0.218750s system = 11.015625s CPU (114.6%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 736, peak = 742.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15926/17552.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 909344, over cnt = 69(0%), over = 91, worst = 7
+PHY-1002 : len = 909360, over cnt = 28(0%), over = 28, worst = 1
+PHY-1002 : len = 909488, over cnt = 18(0%), over = 18, worst = 1
+PHY-1002 : len = 909728, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 909752, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.805598s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (106.7%)
+
+PHY-1001 : Congestion index: top1 = 53.19, top5 = 48.37, top10 = 45.65, top15 = 43.90.
+OPT-1001 : End congestion update; 1.116446s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (103.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.721944s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.6%)
+
+OPT-0007 : Start: WNS -1040 TNS -1754 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6825 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6913 instances, 6764 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3639 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 739128, Over = 0
+PHY-3001 : Spreading special nets. 19 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063330s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.7%)
+
+PHY-3001 : 29 instances has been re-located, deltaX = 25, deltaY = 15, maxDist = 3.
+PHY-3001 : Final: Len = 739360, Over = 0
+PHY-3001 : End incremental legalization; 0.392123s wall, 0.375000s user + 0.031250s system = 0.406250s CPU (103.6%)
+
+OPT-0007 : Iter 1: improved WNS -990 TNS -1625 NUM_FEPS 2 with 35 cells processed and 11554 slack improved
+OPT-0007 : Iter 2: improved WNS -990 TNS -1625 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.369147s wall, 2.390625s user + 0.031250s system = 2.421875s CPU (102.2%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 736, peak = 742.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.726593s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (101.1%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15842/17552.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 913768, over cnt = 81(0%), over = 92, worst = 4
+PHY-1002 : len = 913880, over cnt = 38(0%), over = 40, worst = 2
+PHY-1002 : len = 914048, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 914240, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 914256, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.816002s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (109.1%)
+
+PHY-1001 : Congestion index: top1 = 53.56, top5 = 48.50, top10 = 45.71, top15 = 43.94.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.719422s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.9%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -1040 TNS -1725 NUM_FEPS 2
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 53.103448
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -1040ps with logic level 2
+RUN-1001 : 0 HFN exist on timing critical paths out of 17552 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 17552 nets
+OPT-1001 : End physical optimization; 16.807141s wall, 18.046875s user + 0.281250s system = 18.328125s CPU (109.0%)
+
+RUN-1003 : finish command "place" in 59.234187s wall, 88.281250s user + 5.921875s system = 94.203125s CPU (159.0%)
+
+RUN-1004 : used memory is 604 MB, reserved memory is 617 MB, peak memory is 742 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.701880s wall, 2.968750s user + 0.015625s system = 2.984375s CPU (175.4%)
+
+RUN-1004 : used memory is 605 MB, reserved memory is 618 MB, peak memory is 742 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6915 instances
+RUN-1001 : 3380 mslices, 3384 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17552 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9969 nets have 2 pins
+RUN-1001 : 5757 nets have [3 - 5] pins
+RUN-1001 : 1125 nets have [6 - 10] pins
+RUN-1001 : 318 nets have [11 - 20] pins
+RUN-1001 : 355 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73989, tnet num: 17374, tinst num: 6913, tnode num: 96516, tedge num: 124127.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.725273s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (99.6%)
+
+RUN-1004 : used memory is 601 MB, reserved memory is 611 MB, peak memory is 742 MB
+PHY-1001 : 3380 mslices, 3384 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 847752, over cnt = 2759(7%), over = 4572, worst = 8
+PHY-1002 : len = 866784, over cnt = 1589(4%), over = 2268, worst = 8
+PHY-1002 : len = 884376, over cnt = 660(1%), over = 927, worst = 6
+PHY-1002 : len = 898472, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 898536, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.878729s wall, 3.984375s user + 0.078125s system = 4.062500s CPU (141.1%)
+
+PHY-1001 : Congestion index: top1 = 53.28, top5 = 48.37, top10 = 45.59, top15 = 43.67.
+PHY-1001 : End global routing; 3.212755s wall, 4.296875s user + 0.093750s system = 4.390625s CPU (136.7%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 711, reserve = 715, peak = 742.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 988, reserve = 993, peak = 988.
+PHY-1001 : End build detailed router design. 3.992463s wall, 3.984375s user + 0.015625s system = 4.000000s CPU (100.2%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267120, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.309327s wall, 5.281250s user + 0.015625s system = 5.296875s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267176, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.431956s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.3%)
+
+PHY-1001 : Current memory(MB): used = 1024, reserve = 1030, peak = 1024.
+PHY-1001 : End phase 1; 5.753878s wall, 5.734375s user + 0.015625s system = 5.750000s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.31459e+06, over cnt = 1958(0%), over = 1962, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1042, reserve = 1047, peak = 1042.
+PHY-1001 : End initial routed; 22.886717s wall, 57.109375s user + 0.343750s system = 57.453125s CPU (251.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16475(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -2.084 | -4.275 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.376894s wall, 3.359375s user + 0.015625s system = 3.375000s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1045, reserve = 1047, peak = 1045.
+PHY-1001 : End phase 2; 26.263678s wall, 60.468750s user + 0.359375s system = 60.828125s CPU (231.6%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -1.945ns STNS -4.090ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.147381s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (106.0%)
+
+PHY-1022 : len = 2.31459e+06, over cnt = 1960(0%), over = 1964, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.412433s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (98.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.28119e+06, over cnt = 722(0%), over = 722, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.359431s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (183.9%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.27972e+06, over cnt = 191(0%), over = 191, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.616469s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (167.3%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.28086e+06, over cnt = 22(0%), over = 22, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.482993s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (119.7%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.28087e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.237032s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (105.5%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.28094e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.207754s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (105.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16475(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.945 | -4.090 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.278177s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 589 feed throughs used by 429 nets
+PHY-1001 : End commit to database; 2.281274s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1153, reserve = 1160, peak = 1153.
+PHY-1001 : End phase 3; 9.283671s wall, 10.937500s user + 0.000000s system = 10.937500s CPU (117.8%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.945ns STNS -4.090ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.157822s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.0%)
+
+PHY-1022 : len = 2.28094e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.431752s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.7%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.945ns, -4.090ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16475(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.945 | -4.090 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.367672s wall, 3.359375s user + 0.000000s system = 3.359375s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 589 feed throughs used by 429 nets
+PHY-1001 : End commit to database; 2.325026s wall, 2.328125s user + 0.000000s system = 2.328125s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1162, reserve = 1169, peak = 1162.
+PHY-1001 : End phase 4; 6.151986s wall, 6.156250s user + 0.000000s system = 6.156250s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.28094e+06
+PHY-1001 : Current memory(MB): used = 1165, reserve = 1172, peak = 1165.
+PHY-1001 : End export database. 0.144027s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.6%)
+
+PHY-1001 : End detail routing; 51.989670s wall, 87.828125s user + 0.390625s system = 88.218750s CPU (169.7%)
+
+RUN-1003 : finish command "route" in 57.995979s wall, 94.890625s user + 0.484375s system = 95.375000s CPU (164.5%)
+
+RUN-1004 : used memory is 1093 MB, reserved memory is 1105 MB, peak memory is 1165 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10273 out of 19600 52.41%
+#reg 9368 out of 19600 47.80%
+#le 12618
+ #lut only 3250 out of 12618 25.76%
+ #reg only 2345 out of 12618 18.58%
+ #lut® 7023 out of 12618 55.66%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1810
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1425
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1358
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 942
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 143
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_277.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/reg10_syn_122.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P148 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P106 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P25 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P139 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P107 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P169 LVCMOS33 8 N/A NONE
+ paper_out OUTPUT P91 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P66 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P39 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12618 |9246 |1027 |9400 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |561 |454 |23 |449 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |110 |93 |4 |93 |4 |0 |
+| U_crc16_24b |crc16_24b |32 |32 |0 |22 |0 |0 |
+| U_ecc_gen |ecc_gen |12 |12 |0 |9 |0 |0 |
+| exdev_ctl_a |exdev_ctl |781 |337 |96 |583 |0 |0 |
+| u_ADconfig |AD_config |191 |118 |25 |142 |0 |0 |
+| u_gen_sp |gen_sp |269 |158 |71 |120 |0 |0 |
+| exdev_ctl_b |exdev_ctl |743 |379 |96 |554 |0 |0 |
+| u_ADconfig |AD_config |177 |129 |25 |125 |0 |0 |
+| u_gen_sp |gen_sp |259 |144 |71 |122 |0 |0 |
+| sampling_fe_a |sampling_fe |3071 |2501 |306 |2076 |25 |0 |
+| u0_soft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |180 |137 |17 |133 |0 |0 |
+| u0_soft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_sort |sort |2855 |2346 |289 |1907 |25 |0 |
+| rddpram_ctl |rddpram_ctl |2 |1 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |9 |4 |0 |9 |0 |0 |
+| u0_wrsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2407 |1999 |253 |1544 |22 |0 |
+| channelPart |channel_part_8478 |143 |136 |3 |126 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |41 |0 |0 |
+| ram_switch |ram_switch |1870 |1532 |197 |1149 |0 |0 |
+| adc_addr_gen |adc_addr_gen |247 |220 |27 |123 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |5 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |29 |26 |3 |15 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |31 |28 |3 |17 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |27 |24 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |25 |22 |3 |10 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| insert |insert |965 |654 |170 |661 |0 |0 |
+| ram_switch_state |ram_switch_state |658 |658 |0 |365 |0 |0 |
+| read_ram_i |read_ram |300 |255 |44 |195 |0 |0 |
+| read_ram_addr |read_ram_addr |240 |200 |40 |155 |0 |0 |
+| read_ram_data |read_ram_data |56 |51 |4 |36 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |337 |245 |36 |283 |3 |0 |
+| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3397 |2743 |349 |2088 |25 |1 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_ad_sampling |ad_sampling |189 |127 |17 |147 |0 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_sort |sort_rev |3178 |2597 |332 |1911 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2741 |2251 |290 |1561 |22 |1 |
+| channelPart |channel_part_8478 |243 |238 |3 |137 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |43 |0 |1 |
+| ram_switch |ram_switch |2023 |1671 |197 |1132 |0 |0 |
+| adc_addr_gen |adc_addr_gen |219 |192 |27 |98 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |19 |16 |3 |6 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| insert |insert |982 |658 |170 |674 |0 |0 |
+| ram_switch_state |ram_switch_state |822 |821 |0 |360 |0 |0 |
+| read_ram_i |read_ram_rev |378 |263 |81 |214 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |311 |226 |73 |165 |0 |0 |
+| read_ram_data |read_ram_data_rev |67 |37 |8 |49 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9907
+ #2 2 3801
+ #3 3 1374
+ #4 4 579
+ #5 5-10 1189
+ #6 11-50 584
+ #7 51-100 22
+ #8 >500 1
+ Average 2.92
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.104425s wall, 3.593750s user + 0.000000s system = 3.593750s CPU (170.8%)
+
+RUN-1004 : used memory is 1094 MB, reserved memory is 1106 MB, peak memory is 1165 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73989, tnet num: 17374, tinst num: 6913, tnode num: 96516, tedge num: 124127.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.643211s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (100.8%)
+
+RUN-1004 : used memory is 1098 MB, reserved memory is 1110 MB, peak memory is 1165 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.458982s wall, 1.437500s user + 0.015625s system = 1.453125s CPU (99.6%)
+
+RUN-1004 : used memory is 1102 MB, reserved memory is 1114 MB, peak memory is 1165 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6913
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17552, pip num: 172527
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 589
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3249 valid insts, and 479670 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 10.263146s wall, 65.328125s user + 0.125000s system = 65.453125s CPU (637.7%)
+
+RUN-1004 : used memory is 1265 MB, reserved memory is 1268 MB, peak memory is 1380 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240219_105751.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240218_174459.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240218_174459.log
new file mode 100644
index 0000000..a2905f4
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240218_174459.log
@@ -0,0 +1,1875 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sun Feb 18 17:44:59 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(344)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(344)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(344)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(344)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(344)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(344)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(194)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.139704s wall, 1.109375s user + 0.031250s system = 1.140625s CPU (100.1%)
+
+RUN-1004 : used memory is 193 MB, reserved memory is 171 MB, peak memory is 233 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 20 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_out has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54204/19013 useful/useless nets, 20711/1803 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42745/8971 useful/useless nets, 11003/4738 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(285) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40418/363 useful/useless nets, 37615/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3953 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6205 instances.
+SYN-1015 : Optimize round 1, 30031 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25981/1547 useful/useless nets, 23270/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25732/80 useful/useless nets, 23053/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25637/95 useful/useless nets, 22969/7 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 4 instances.
+SYN-1015 : Optimize round 1, 280 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25358/20 useful/useless nets, 22706/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 18.907330s wall, 17.109375s user + 1.781250s system = 18.890625s CPU (99.9%)
+
+RUN-1004 : used memory is 331 MB, reserved memory is 303 MB, peak memory is 350 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 14010
+ #and 2484
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 204
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 571
+ #FADD 0
+ #DFF 9193
+ #LATCH 6
+#MACRO_ADD 497
+#MACRO_EQ 224
+#MACRO_MULT 4
+#MACRO_MUX 4957
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4811 |9199 |798 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1824 |1969 |269 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |10 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1780 |1787 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1548 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |121 |164 |32 |
+| read_ram_addr |read_ram_addr |69 |127 |22 |
+| read_ram_data |read_ram_data |50 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1790 |1986 |267 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1748 |1804 |257 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1516 |1408 |118 |
+| channelPart |channel_part_8478 |870 |144 |7 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |90 |181 |33 |
+| read_ram_addr |read_ram_addr_rev |56 |139 |23 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.069280s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (165.1%)
+
+RUN-1004 : used memory is 326 MB, reserved memory is 300 MB, peak memory is 399 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | low | medium | *
+RUN-1001 : opt_timing | high | auto | *
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25392/24 useful/useless nets, 22755/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25710/670 useful/useless nets, 23089/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29140/338 useful/useless nets, 26520/38 useful/useless insts
+SYN-1016 : Merged 393 instances.
+SYN-2501 : Optimize round 1, 1765 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36687/296 useful/useless nets, 33961/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122436, tnet num: 36689, tinst num: 33961, tnode num: 156700, tedge num: 180252.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 1.341604s wall, 1.328125s user + 0.015625s system = 1.343750s CPU (100.2%)
+
+RUN-1004 : used memory is 519 MB, reserved memory is 496 MB, peak memory is 519 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36689 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7533 (3.86), #lev = 9 (3.09)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7355 (3.94), #lev = 7 (3.00)
+SYN-3001 : Logic optimization runtime opt = 1.31 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 19016 instances into 7383 LUTs, name keeping = 60%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 9958
+ #lut4 5104
+ #lut5 2299
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2555
+
+Utilization Statistics
+#lut 9958 out of 19600 50.81%
+#reg 9273 out of 19600 47.31%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |7403 |2555 |9305 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |339 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |287 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |101 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |128 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |274 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |90 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |126 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2294 |738 |1969 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |2224 |691 |1787 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2044 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
+| ram_switch |ram_switch |1439 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1045 |0 |216 |0 |0 |
+| read_ram_i |read_ram |371 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |159 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |211 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |126 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2336 |751 |1986 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2266 |704 |1804 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2084 |628 |1408 |22 |1 |
+| channelPart |channel_part_8478 |148 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1446 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1052 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |402 |171 |181 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |181 |145 |139 |0 |0 |
+| read_ram_data |read_ram_data_rev |221 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9273 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 64.442333s wall, 64.187500s user + 0.250000s system = 64.437500s CPU (100.0%)
+
+RUN-1004 : used memory is 394 MB, reserved memory is 378 MB, peak memory is 703 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.568997s wall, 2.750000s user + 0.000000s system = 2.750000s CPU (175.3%)
+
+RUN-1004 : used memory is 431 MB, reserved memory is 418 MB, peak memory is 703 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240218_174459.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_100829.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_100829.log
new file mode 100644
index 0000000..24bbffb
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_100829.log
@@ -0,0 +1,1875 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Feb 19 10:08:30 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(344)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(344)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(344)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(344)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(344)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(344)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(194)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.116777s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.7%)
+
+RUN-1004 : used memory is 193 MB, reserved memory is 171 MB, peak memory is 234 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 20 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_out has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54204/19013 useful/useless nets, 20711/1803 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42745/8971 useful/useless nets, 11003/4738 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(285) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40418/363 useful/useless nets, 37615/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3953 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6205 instances.
+SYN-1015 : Optimize round 1, 30031 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25981/1547 useful/useless nets, 23270/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25732/80 useful/useless nets, 23053/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25637/95 useful/useless nets, 22969/7 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 4 instances.
+SYN-1015 : Optimize round 1, 280 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25358/20 useful/useless nets, 22706/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 19.247675s wall, 17.921875s user + 1.312500s system = 19.234375s CPU (99.9%)
+
+RUN-1004 : used memory is 331 MB, reserved memory is 303 MB, peak memory is 351 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 14010
+ #and 2484
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 204
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 571
+ #FADD 0
+ #DFF 9193
+ #LATCH 6
+#MACRO_ADD 497
+#MACRO_EQ 224
+#MACRO_MULT 4
+#MACRO_MUX 4957
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4811 |9199 |798 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1824 |1969 |269 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |10 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1780 |1787 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1548 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |121 |164 |32 |
+| read_ram_addr |read_ram_addr |69 |127 |22 |
+| read_ram_data |read_ram_data |50 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1790 |1986 |267 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1748 |1804 |257 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1516 |1408 |118 |
+| channelPart |channel_part_8478 |870 |144 |7 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |90 |181 |33 |
+| read_ram_addr |read_ram_addr_rev |56 |139 |23 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.117198s wall, 1.703125s user + 0.015625s system = 1.718750s CPU (153.8%)
+
+RUN-1004 : used memory is 341 MB, reserved memory is 313 MB, peak memory is 400 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | low | medium | *
+RUN-1001 : opt_timing | high | auto | *
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25392/24 useful/useless nets, 22755/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25710/670 useful/useless nets, 23089/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29140/338 useful/useless nets, 26520/38 useful/useless insts
+SYN-1016 : Merged 393 instances.
+SYN-2501 : Optimize round 1, 1765 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36687/296 useful/useless nets, 33961/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122436, tnet num: 36689, tinst num: 33961, tnode num: 156700, tedge num: 180252.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 1.335533s wall, 1.328125s user + 0.015625s system = 1.343750s CPU (100.6%)
+
+RUN-1004 : used memory is 520 MB, reserved memory is 497 MB, peak memory is 520 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36689 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7533 (3.86), #lev = 9 (3.09)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7355 (3.94), #lev = 7 (3.00)
+SYN-3001 : Logic optimization runtime opt = 1.43 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 19016 instances into 7383 LUTs, name keeping = 60%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 9958
+ #lut4 5104
+ #lut5 2299
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2555
+
+Utilization Statistics
+#lut 9958 out of 19600 50.81%
+#reg 9273 out of 19600 47.31%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |7403 |2555 |9305 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |339 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |287 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |101 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |128 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |274 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |90 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |126 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2294 |738 |1969 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |2224 |691 |1787 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2044 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
+| ram_switch |ram_switch |1439 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1045 |0 |216 |0 |0 |
+| read_ram_i |read_ram |371 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |159 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |211 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |126 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2336 |751 |1986 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2266 |704 |1804 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2084 |628 |1408 |22 |1 |
+| channelPart |channel_part_8478 |148 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1446 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1052 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |402 |171 |181 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |181 |145 |139 |0 |0 |
+| read_ram_data |read_ram_data_rev |221 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9273 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 75.063786s wall, 74.562500s user + 0.406250s system = 74.968750s CPU (99.9%)
+
+RUN-1004 : used memory is 396 MB, reserved memory is 387 MB, peak memory is 704 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.586733s wall, 2.718750s user + 0.015625s system = 2.734375s CPU (172.3%)
+
+RUN-1004 : used memory is 404 MB, reserved memory is 386 MB, peak memory is 704 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240219_100829.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_102025.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_102025.log
new file mode 100644
index 0000000..cb6c3f9
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_102025.log
@@ -0,0 +1,1875 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Feb 19 10:20:26 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(344)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(344)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(344)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(344)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(344)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(344)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(194)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.148558s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (99.3%)
+
+RUN-1004 : used memory is 193 MB, reserved memory is 171 MB, peak memory is 233 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 20 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_out has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54204/19013 useful/useless nets, 20711/1803 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42745/8971 useful/useless nets, 11003/4738 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(285) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40418/363 useful/useless nets, 37615/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3953 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6205 instances.
+SYN-1015 : Optimize round 1, 30031 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25981/1547 useful/useless nets, 23270/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25732/80 useful/useless nets, 23053/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25637/95 useful/useless nets, 22969/7 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 4 instances.
+SYN-1015 : Optimize round 1, 280 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25358/20 useful/useless nets, 22706/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 19.771068s wall, 17.750000s user + 1.703125s system = 19.453125s CPU (98.4%)
+
+RUN-1004 : used memory is 331 MB, reserved memory is 303 MB, peak memory is 351 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 14010
+ #and 2484
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 204
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 571
+ #FADD 0
+ #DFF 9193
+ #LATCH 6
+#MACRO_ADD 497
+#MACRO_EQ 224
+#MACRO_MULT 4
+#MACRO_MUX 4957
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4811 |9199 |798 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1823 |1969 |269 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |10 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1780 |1787 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1548 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |121 |164 |32 |
+| read_ram_addr |read_ram_addr |69 |127 |22 |
+| read_ram_data |read_ram_data |50 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1790 |1986 |267 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1748 |1804 |257 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1516 |1408 |118 |
+| channelPart |channel_part_8478 |870 |144 |7 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |90 |181 |33 |
+| read_ram_addr |read_ram_addr_rev |56 |139 |23 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.073932s wall, 1.750000s user + 0.031250s system = 1.781250s CPU (165.9%)
+
+RUN-1004 : used memory is 326 MB, reserved memory is 300 MB, peak memory is 399 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | low | medium | *
+RUN-1001 : opt_timing | high | auto | *
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25392/24 useful/useless nets, 22755/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25710/670 useful/useless nets, 23089/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29140/338 useful/useless nets, 26520/38 useful/useless insts
+SYN-1016 : Merged 393 instances.
+SYN-2501 : Optimize round 1, 1765 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36687/296 useful/useless nets, 33961/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122438, tnet num: 36689, tinst num: 33961, tnode num: 156705, tedge num: 180256.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 1.341669s wall, 1.203125s user + 0.125000s system = 1.328125s CPU (99.0%)
+
+RUN-1004 : used memory is 519 MB, reserved memory is 497 MB, peak memory is 519 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36689 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7533 (3.86), #lev = 9 (3.09)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7355 (3.94), #lev = 7 (3.00)
+SYN-3001 : Logic optimization runtime opt = 1.33 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 19016 instances into 7383 LUTs, name keeping = 60%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 9958
+ #lut4 5104
+ #lut5 2299
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2555
+
+Utilization Statistics
+#lut 9958 out of 19600 50.81%
+#reg 9273 out of 19600 47.31%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 20
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |7403 |2555 |9306 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |339 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |287 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |101 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |128 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |274 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |90 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |126 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2294 |738 |1969 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |2224 |691 |1787 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2044 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
+| ram_switch |ram_switch |1439 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1045 |0 |216 |0 |0 |
+| read_ram_i |read_ram |371 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |159 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |211 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |126 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2336 |751 |1986 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2266 |704 |1804 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2084 |628 |1408 |22 |1 |
+| channelPart |channel_part_8478 |148 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1446 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1052 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |402 |171 |181 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |181 |145 |139 |0 |0 |
+| read_ram_data |read_ram_data_rev |221 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9273 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 75.239434s wall, 74.781250s user + 0.375000s system = 75.156250s CPU (99.9%)
+
+RUN-1004 : used memory is 397 MB, reserved memory is 388 MB, peak memory is 703 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.595960s wall, 2.781250s user + 0.000000s system = 2.781250s CPU (174.3%)
+
+RUN-1004 : used memory is 405 MB, reserved memory is 388 MB, peak memory is 703 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240219_102025.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_103046.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_103046.log
new file mode 100644
index 0000000..88c3384
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_103046.log
@@ -0,0 +1,422 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Feb 19 10:30:46 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 60 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-7007 CRITICAL-WARNING: instantiate unknown module read_ram in ../../../../hg_mp/fe/prebuffer.v(373)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-5007 WARNING: actual bit length 6 differs from formal bit length 4 for port 'debug' in ../../../../hg_mp/fe/sampling_fe.v(140)
+HDL-5007 WARNING: actual bit length 4 differs from formal bit length 6 for port 'debug' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(963)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-8007 ERROR: read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) is a black box in ../../../../hg_mp/fe/prebuffer.v(373)
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240219_103046.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_103102.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_103102.log
new file mode 100644
index 0000000..088da21
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_103102.log
@@ -0,0 +1,422 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Feb 19 10:31:02 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 60 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-7007 CRITICAL-WARNING: instantiate unknown module read_ram in ../../../../hg_mp/fe/prebuffer.v(373)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-5007 WARNING: actual bit length 6 differs from formal bit length 4 for port 'debug' in ../../../../hg_mp/fe/sampling_fe.v(140)
+HDL-5007 WARNING: actual bit length 4 differs from formal bit length 6 for port 'debug' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(963)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-8007 ERROR: read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) is a black box in ../../../../hg_mp/fe/prebuffer.v(373)
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240219_103102.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_103120.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_103120.log
new file mode 100644
index 0000000..dcd4585
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_103120.log
@@ -0,0 +1,424 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Feb 19 10:31:20 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-8007 ERROR: index 4 is out of range [3:0] for 'debug' in ../../../../hg_mp/fe/read_ram_data.v(77)
+HDL-1007 : module 'read_ram_data' remains a black box due to errors in its contents in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-5007 WARNING: actual bit length 6 differs from formal bit length 4 for port 'debug' in ../../../../hg_mp/fe/sampling_fe.v(140)
+HDL-5007 WARNING: actual bit length 4 differs from formal bit length 6 for port 'debug' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(963)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240219_103120.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_103451.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_103451.log
new file mode 100644
index 0000000..d07fb93
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_103451.log
@@ -0,0 +1,1874 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Feb 19 10:34:51 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.136841s wall, 1.078125s user + 0.046875s system = 1.125000s CPU (99.0%)
+
+RUN-1004 : used memory is 193 MB, reserved memory is 170 MB, peak memory is 233 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 20 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_out has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53909/19157 useful/useless nets, 20692/1822 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42440/8976 useful/useless nets, 10974/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40113/363 useful/useless nets, 37310/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3853 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6107 instances.
+SYN-1015 : Optimize round 1, 29633 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25874/1547 useful/useless nets, 23163/7483 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9327 better
+SYN-1032 : 25625/80 useful/useless nets, 22946/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25532/93 useful/useless nets, 22864/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25254/20 useful/useless nets, 22602/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 19.257652s wall, 17.421875s user + 1.828125s system = 19.250000s CPU (100.0%)
+
+RUN-1004 : used memory is 330 MB, reserved memory is 302 MB, peak memory is 350 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 13905
+ #and 2479
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 204
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 571
+ #FADD 0
+ #DFF 9093
+ #LATCH 6
+#MACRO_ADD 497
+#MACRO_EQ 225
+#MACRO_MULT 4
+#MACRO_MUX 4957
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4806 |9099 |799 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1824 |1919 |269 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |10 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1780 |1737 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1548 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |121 |164 |32 |
+| read_ram_addr |read_ram_addr |69 |127 |22 |
+| read_ram_data |read_ram_data |50 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1785 |1936 |268 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1743 |1754 |258 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |90 |181 |33 |
+| read_ram_addr |read_ram_addr_rev |56 |139 |23 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.064791s wall, 1.687500s user + 0.031250s system = 1.718750s CPU (161.4%)
+
+RUN-1004 : used memory is 325 MB, reserved memory is 299 MB, peak memory is 398 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | low | medium | *
+RUN-1001 : opt_timing | high | auto | *
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25288/24 useful/useless nets, 22651/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25606/670 useful/useless nets, 22985/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 331 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29056/338 useful/useless nets, 26436/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36600/296 useful/useless nets, 33874/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122060, tnet num: 36602, tinst num: 33874, tnode num: 156010, tedge num: 179674.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 1.336961s wall, 1.328125s user + 0.015625s system = 1.343750s CPU (100.5%)
+
+RUN-1004 : used memory is 518 MB, reserved memory is 496 MB, peak memory is 518 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36602 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7566 (3.85), #lev = 10 (3.12)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7508 (3.95), #lev = 7 (3.09)
+SYN-3001 : Logic optimization runtime opt = 1.34 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 19029 instances into 7536 LUTs, name keeping = 57%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 10111
+ #lut4 5345
+ #lut5 2211
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2555
+
+Utilization Statistics
+#lut 10111 out of 19600 51.59%
+#reg 9173 out of 19600 46.80%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |7556 |2555 |9205 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |339 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |285 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |99 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |128 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |273 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |90 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |125 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2400 |738 |1919 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |2330 |691 |1737 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |1927 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |147 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
+| ram_switch |ram_switch |1484 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1090 |0 |216 |0 |0 |
+| read_ram_i |read_ram |208 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |170 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |37 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2399 |751 |1936 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2329 |704 |1754 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1931 |628 |1408 |22 |1 |
+| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1483 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1089 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |214 |171 |181 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |183 |145 |139 |0 |0 |
+| read_ram_data |read_ram_data_rev |31 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9173 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 74.049544s wall, 73.671875s user + 0.312500s system = 73.984375s CPU (99.9%)
+
+RUN-1004 : used memory is 394 MB, reserved memory is 381 MB, peak memory is 702 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.581109s wall, 2.718750s user + 0.015625s system = 2.734375s CPU (172.9%)
+
+RUN-1004 : used memory is 430 MB, reserved memory is 420 MB, peak memory is 702 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240219_103451.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_104111.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_104111.log
new file mode 100644
index 0000000..958066d
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_104111.log
@@ -0,0 +1,1874 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Feb 19 10:41:12 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.111810s wall, 1.078125s user + 0.031250s system = 1.109375s CPU (99.8%)
+
+RUN-1004 : used memory is 193 MB, reserved memory is 169 MB, peak memory is 234 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 20 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_out has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53909/19207 useful/useless nets, 20692/1826 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42440/8976 useful/useless nets, 10974/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40113/363 useful/useless nets, 37310/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29880 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25775/1547 useful/useless nets, 23064/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25526/80 useful/useless nets, 22847/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25433/93 useful/useless nets, 22765/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25155/20 useful/useless nets, 22503/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 19.338845s wall, 17.250000s user + 2.093750s system = 19.343750s CPU (100.0%)
+
+RUN-1004 : used memory is 332 MB, reserved memory is 304 MB, peak memory is 350 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 13950
+ #and 2480
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 204
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 615
+ #FADD 0
+ #DFF 9093
+ #LATCH 6
+#MACRO_ADD 497
+#MACRO_EQ 225
+#MACRO_MULT 4
+#MACRO_MUX 4813
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4851 |9099 |799 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1847 |1919 |269 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |10 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1803 |1737 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1548 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |121 |164 |32 |
+| read_ram_addr |read_ram_addr |69 |127 |22 |
+| read_ram_data |read_ram_data |50 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1765 |1754 |258 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |90 |181 |33 |
+| read_ram_addr |read_ram_addr_rev |56 |139 |23 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.054675s wall, 1.734375s user + 0.015625s system = 1.750000s CPU (165.9%)
+
+RUN-1004 : used memory is 327 MB, reserved memory is 300 MB, peak memory is 400 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | low | medium | *
+RUN-1001 : opt_timing | high | auto | *
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25189/24 useful/useless nets, 22552/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25507/670 useful/useless nets, 22886/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28943/338 useful/useless nets, 26323/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36487/296 useful/useless nets, 33761/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121685, tnet num: 36489, tinst num: 33761, tnode num: 155649, tedge num: 179150.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 1.328516s wall, 1.281250s user + 0.046875s system = 1.328125s CPU (100.0%)
+
+RUN-1004 : used memory is 518 MB, reserved memory is 496 MB, peak memory is 518 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36489 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7497 (3.86), #lev = 10 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7359 (3.96), #lev = 7 (3.05)
+SYN-3001 : Logic optimization runtime opt = 1.27 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 18916 instances into 7387 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 9962
+ #lut4 5231
+ #lut5 2176
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2555
+
+Utilization Statistics
+#lut 9962 out of 19600 50.83%
+#reg 9173 out of 19600 46.80%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |7407 |2555 |9205 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |342 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |282 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |99 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |125 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |274 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |91 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |125 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2317 |738 |1919 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |2247 |691 |1737 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |1906 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
+| ram_switch |ram_switch |1466 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1072 |0 |216 |0 |0 |
+| read_ram_i |read_ram |207 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |177 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |29 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2335 |751 |1936 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2265 |704 |1754 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1924 |628 |1408 |22 |1 |
+| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1479 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1085 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |210 |171 |181 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |181 |145 |139 |0 |0 |
+| read_ram_data |read_ram_data_rev |29 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9173 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 74.159196s wall, 73.734375s user + 0.375000s system = 74.109375s CPU (99.9%)
+
+RUN-1004 : used memory is 396 MB, reserved memory is 387 MB, peak memory is 702 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.578551s wall, 2.750000s user + 0.000000s system = 2.750000s CPU (174.2%)
+
+RUN-1004 : used memory is 403 MB, reserved memory is 387 MB, peak memory is 702 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240219_104111.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_105625.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_105625.log
new file mode 100644
index 0000000..f455ff1
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240219_105625.log
@@ -0,0 +1,1874 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Feb 19 10:56:25 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.112400s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.7%)
+
+RUN-1004 : used memory is 193 MB, reserved memory is 171 MB, peak memory is 234 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 20 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53909/19207 useful/useless nets, 20692/1826 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42440/8976 useful/useless nets, 10974/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40113/363 useful/useless nets, 37310/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29880 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25775/1547 useful/useless nets, 23064/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25526/80 useful/useless nets, 22847/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25433/93 useful/useless nets, 22765/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25155/20 useful/useless nets, 22503/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 18.908404s wall, 16.984375s user + 1.906250s system = 18.890625s CPU (99.9%)
+
+RUN-1004 : used memory is 331 MB, reserved memory is 303 MB, peak memory is 349 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 13950
+ #and 2480
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 204
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 615
+ #FADD 0
+ #DFF 9093
+ #LATCH 6
+#MACRO_ADD 497
+#MACRO_EQ 225
+#MACRO_MULT 4
+#MACRO_MUX 4813
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4851 |9099 |799 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1847 |1919 |269 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |10 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1803 |1737 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1548 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |121 |164 |32 |
+| read_ram_addr |read_ram_addr |69 |127 |22 |
+| read_ram_data |read_ram_data |50 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1765 |1754 |258 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |90 |181 |33 |
+| read_ram_addr |read_ram_addr_rev |56 |139 |23 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.053069s wall, 1.656250s user + 0.078125s system = 1.734375s CPU (164.7%)
+
+RUN-1004 : used memory is 326 MB, reserved memory is 301 MB, peak memory is 399 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | low | medium | *
+RUN-1001 : opt_timing | high | auto | *
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25189/24 useful/useless nets, 22552/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25507/670 useful/useless nets, 22886/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28943/338 useful/useless nets, 26323/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36487/296 useful/useless nets, 33761/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121685, tnet num: 36489, tinst num: 33761, tnode num: 155649, tedge num: 179150.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 1.303515s wall, 1.281250s user + 0.031250s system = 1.312500s CPU (100.7%)
+
+RUN-1004 : used memory is 517 MB, reserved memory is 495 MB, peak memory is 517 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36489 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7497 (3.86), #lev = 10 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7359 (3.96), #lev = 7 (3.05)
+SYN-3001 : Logic optimization runtime opt = 1.20 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 18916 instances into 7387 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 9962
+ #lut4 5231
+ #lut5 2176
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2555
+
+Utilization Statistics
+#lut 9962 out of 19600 50.83%
+#reg 9173 out of 19600 46.80%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |7407 |2555 |9205 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |342 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |282 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |99 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |125 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |274 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |91 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |125 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2317 |738 |1919 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |2247 |691 |1737 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |1906 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
+| ram_switch |ram_switch |1466 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1072 |0 |216 |0 |0 |
+| read_ram_i |read_ram |207 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |177 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |29 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2335 |751 |1936 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2265 |704 |1754 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1924 |628 |1408 |22 |1 |
+| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1479 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1085 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |210 |171 |181 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |181 |145 |139 |0 |0 |
+| read_ram_data |read_ram_data_rev |29 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9173 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 61.071613s wall, 60.671875s user + 0.375000s system = 61.046875s CPU (100.0%)
+
+RUN-1004 : used memory is 394 MB, reserved memory is 379 MB, peak memory is 699 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.555646s wall, 2.687500s user + 0.031250s system = 2.718750s CPU (174.8%)
+
+RUN-1004 : used memory is 403 MB, reserved memory is 384 MB, peak memory is 699 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240219_105625.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/.bitgen.begin.f b/src/prj/td_project/hg_anlogic_Runs/phy_1/.bitgen.begin.f
index e65be6c..5b91233 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/.bitgen.begin.f
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/.bitgen.begin.f
@@ -1,5 +1,5 @@
-
+
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_place.begin.f b/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_place.begin.f
index e65be6c..5b91233 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_place.begin.f
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_place.begin.f
@@ -1,5 +1,5 @@
-
+
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_route.begin.f b/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_route.begin.f
index e65be6c..5b91233 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_route.begin.f
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_route.begin.f
@@ -1,5 +1,5 @@
-
+
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit
index f579b29..85c7fca 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit and b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.prj b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.prj
index 203766c..3ebb862 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.prj
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.prj
@@ -1,5 +1,5 @@
-
+
UTF-8
5.6.71036
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.rbf b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.rbf
index 9be9f4e..4105502 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.rbf and b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.rbf differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_20240218_a002_1615_soft_reset.bin b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_20240218_a002_1615_soft_reset.bin
deleted file mode 100644
index 907f1f9..0000000
Binary files a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_20240218_a002_1615_soft_reset.bin and /dev/null differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_2024021_1108_soft_reset.bin b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_2024021_1108_soft_reset.bin
new file mode 100644
index 0000000..2482c96
Binary files /dev/null and b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_2024021_1108_soft_reset.bin differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.area b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.area
index 532e8aa..4e86c9c 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.area
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.area
@@ -8,12 +8,12 @@ IO Statistics
#inout 0
Utilization Statistics
-#lut 10320 out of 19600 52.65%
-#reg 9363 out of 19600 47.77%
-#le 12661
- #lut only 3298 out of 12661 26.05%
- #reg only 2341 out of 12661 18.49%
- #lut® 7022 out of 12661 55.46%
+#lut 10273 out of 19600 52.41%
+#reg 9368 out of 19600 47.80%
+#le 12618
+ #lut only 3250 out of 12618 25.76%
+ #reg only 2345 out of 12618 18.58%
+ #lut® 7023 out of 12618 55.66%
#dsp 3 out of 29 10.34%
#bram 54 out of 64 84.38%
#bram9k 50
@@ -21,24 +21,24 @@ Utilization Statistics
#bram32k 4 out of 16 25.00%
#pad 75 out of 130 57.69%
#ireg 13
- #oreg 18
+ #oreg 19
#treg 0
#pll 3 out of 4 75.00%
#gclk 6 out of 16 37.50%
Clock Resource Statistics
Index ClockNet Type DriverType Driver Fanout
-#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1795
-#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1417
-#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1355
-#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 967
-#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 139
-#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70
-#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
-#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1810
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1425
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1358
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 942
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 143
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
-#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg42_syn_219.f1 3
-#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_b/u_ADconfig/reg1_syn_191.f0 2
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_277.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/reg10_syn_122.f1 3
#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
@@ -48,36 +48,36 @@ Index ClockNet Type
Detailed IO Report
Name Direction Location IOStandard DriveStrength PullType PackReg
- a_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
- a_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
- a_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
- b_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
- b_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
- b_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
- onoff_in INPUT P133 LVCMOS33 N/A N/A NONE
- paper_in INPUT P4 LVCMOS25 N/A N/A NONE
+ onoff_in INPUT P148 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P106 LVCMOS25 N/A N/A NONE
rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
@@ -99,85 +99,85 @@ Detailed IO Report
O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
- a_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
- a_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
- a_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
- a_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
- a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
- b_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
- b_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
- b_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
- b_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P25 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
- debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
- debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
- debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
- fan_pwm OUTPUT P138 LVCMOS33 8 N/A NONE
- frame_indicator OUTPUT P16 LVCMOS25 8 N/A OREG
- onoff_out OUTPUT P152 LVCMOS33 8 N/A NONE
- paper_out OUTPUT P17 LVCMOS25 8 N/A NONE
- scan_out OUTPUT P15 LVCMOS25 8 N/A NONE
- sys_initial_done OUTPUT P104 LVCMOS25 8 N/A NONE
+ fan_pwm OUTPUT P139 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P107 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P169 LVCMOS33 8 N/A NONE
+ paper_out OUTPUT P91 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P66 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P39 LVCMOS25 8 N/A NONE
txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
Report Hierarchy Area:
+---------------------------------------------------------------------------------------------------------+
|Instance |Module |le |lut |ripple |seq |bram |dsp |
+---------------------------------------------------------------------------------------------------------+
-|top |huagao_mipi_top |12661 |9293 |1027 |9394 |58 |3 |
-| U_rgb_to_csi_pakage |rgb_to_csi_pakage |545 |451 |23 |442 |4 |1 |
-| U_fifo_w32_d8192 |fifo_w32_d8192 |98 |83 |4 |90 |4 |0 |
-| U_crc16_24b |crc16_24b |29 |29 |0 |19 |0 |0 |
-| U_ecc_gen |ecc_gen |14 |14 |0 |10 |0 |0 |
-| exdev_ctl_a |exdev_ctl |767 |373 |96 |581 |0 |0 |
-| u_ADconfig |AD_config |188 |139 |25 |142 |0 |0 |
-| u_gen_sp |gen_sp |263 |160 |71 |123 |0 |0 |
-| exdev_ctl_b |exdev_ctl |752 |423 |96 |556 |0 |0 |
-| u_ADconfig |AD_config |178 |140 |25 |126 |0 |0 |
-| u_gen_sp |gen_sp |262 |168 |71 |118 |0 |0 |
-| sampling_fe_a |sampling_fe |3094 |2433 |306 |2032 |25 |0 |
+|top |huagao_mipi_top |12618 |9246 |1027 |9400 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |561 |454 |23 |449 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |110 |93 |4 |93 |4 |0 |
+| U_crc16_24b |crc16_24b |32 |32 |0 |22 |0 |0 |
+| U_ecc_gen |ecc_gen |12 |12 |0 |9 |0 |0 |
+| exdev_ctl_a |exdev_ctl |781 |337 |96 |583 |0 |0 |
+| u_ADconfig |AD_config |191 |118 |25 |142 |0 |0 |
+| u_gen_sp |gen_sp |269 |158 |71 |120 |0 |0 |
+| exdev_ctl_b |exdev_ctl |743 |379 |96 |554 |0 |0 |
+| u_ADconfig |AD_config |177 |129 |25 |125 |0 |0 |
+| u_gen_sp |gen_sp |259 |144 |71 |122 |0 |0 |
+| sampling_fe_a |sampling_fe |3071 |2501 |306 |2076 |25 |0 |
| u0_soft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
-| u_ad_sampling |ad_sampling |183 |97 |17 |141 |0 |0 |
-| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
-| u_sort |sort |2875 |2311 |289 |1855 |25 |0 |
-| rddpram_ctl |rddpram_ctl |5 |5 |0 |5 |0 |0 |
-| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
-| u0_rdsoft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
-| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
-| u_data_prebuffer |data_prebuffer |2499 |2063 |253 |1538 |22 |0 |
-| channelPart |channel_part_8478 |133 |130 |3 |122 |0 |0 |
-| fifo_adc |fifo_adc |62 |53 |9 |44 |0 |0 |
-| ram_switch |ram_switch |1994 |1633 |197 |1144 |0 |0 |
-| adc_addr_gen |adc_addr_gen |244 |217 |27 |114 |0 |0 |
-| [0]$ch_addr_gen |ch_addr_gen |8 |5 |3 |4 |0 |0 |
-| [1]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
-| [2]$ch_addr_gen |ch_addr_gen |29 |26 |3 |14 |0 |0 |
-| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
-| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
-| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
-| [6]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
-| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
-| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |9 |0 |0 |
-| insert |insert |953 |620 |170 |654 |0 |0 |
-| ram_switch_state |ram_switch_state |797 |796 |0 |376 |0 |0 |
-| read_ram_i |read_ram |265 |209 |44 |186 |0 |0 |
-| read_ram_addr |read_ram_addr |213 |173 |40 |147 |0 |0 |
-| read_ram_data |read_ram_data |51 |35 |4 |38 |0 |0 |
-| u0_rdsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u_ad_sampling |ad_sampling |180 |137 |17 |133 |0 |0 |
+| u0_soft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_sort |sort |2855 |2346 |289 |1907 |25 |0 |
+| rddpram_ctl |rddpram_ctl |2 |1 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |9 |4 |0 |9 |0 |0 |
+| u0_wrsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2407 |1999 |253 |1544 |22 |0 |
+| channelPart |channel_part_8478 |143 |136 |3 |126 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |41 |0 |0 |
+| ram_switch |ram_switch |1870 |1532 |197 |1149 |0 |0 |
+| adc_addr_gen |adc_addr_gen |247 |220 |27 |123 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |5 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |29 |26 |3 |15 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |31 |28 |3 |17 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |27 |24 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |25 |22 |3 |10 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| insert |insert |965 |654 |170 |661 |0 |0 |
+| ram_switch_state |ram_switch_state |658 |658 |0 |365 |0 |0 |
+| read_ram_i |read_ram |300 |255 |44 |195 |0 |0 |
+| read_ram_addr |read_ram_addr |240 |200 |40 |155 |0 |0 |
+| read_ram_data |read_ram_data |56 |51 |4 |36 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
@@ -185,42 +185,41 @@ Report Hierarchy Area:
| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_b_5 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u_transfer_300_to_200 |transfer_300_to_200 |339 |233 |36 |280 |3 |0 |
-| u0_soft_n |cdc_sync |7 |7 |0 |7 |0 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |337 |245 |36 |283 |3 |0 |
+| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
-| sampling_fe_b |sampling_fe_rev |3367 |2648 |349 |2114 |25 |1 |
-| u0_soft_n |cdc_sync |6 |1 |0 |6 |0 |0 |
-| u_ad_sampling |ad_sampling |166 |113 |17 |130 |0 |0 |
-| u0_soft_n |cdc_sync |6 |1 |0 |6 |0 |0 |
-| u_sort |sort_rev |3165 |2522 |332 |1948 |25 |1 |
-| rddpram_ctl |rddpram_ctl_rev |4 |3 |0 |4 |0 |0 |
-| u0_rdsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
-| u0_rdsoft_n |cdc_sync |7 |2 |0 |7 |0 |0 |
-| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
-| u_data_prebuffer_rev |data_prebuffer_rev |2731 |2228 |290 |1587 |22 |1 |
-| channelPart |channel_part_8478 |238 |235 |3 |135 |0 |0 |
-| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
-| ram_switch |ram_switch |1983 |1621 |197 |1142 |0 |0 |
-| adc_addr_gen |adc_addr_gen |221 |194 |27 |105 |0 |0 |
-| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |6 |0 |0 |
-| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
-| [2]$ch_addr_gen |ch_addr_gen |30 |27 |3 |18 |0 |0 |
-| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
-| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
-| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |8 |0 |0 |
-| [6]$ch_addr_gen |ch_addr_gen |21 |18 |3 |10 |0 |0 |
-| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
-| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
-| insert |insert |974 |641 |170 |669 |0 |0 |
-| ram_switch_state |ram_switch_state |788 |786 |0 |368 |0 |0 |
-| read_ram_i |read_ram_rev |424 |303 |81 |240 |0 |0 |
-| read_ram_addr |read_ram_addr_rev |291 |206 |73 |159 |0 |0 |
-| read_ram_data |read_ram_data_rev |133 |97 |8 |81 |0 |0 |
+| sampling_fe_b |sampling_fe_rev |3397 |2743 |349 |2088 |25 |1 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_ad_sampling |ad_sampling |189 |127 |17 |147 |0 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_sort |sort_rev |3178 |2597 |332 |1911 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2741 |2251 |290 |1561 |22 |1 |
+| channelPart |channel_part_8478 |243 |238 |3 |137 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |43 |0 |1 |
+| ram_switch |ram_switch |2023 |1671 |197 |1132 |0 |0 |
+| adc_addr_gen |adc_addr_gen |219 |192 |27 |98 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |19 |16 |3 |6 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| insert |insert |982 |658 |170 |674 |0 |0 |
+| ram_switch_state |ram_switch_state |822 |821 |0 |360 |0 |0 |
+| read_ram_i |read_ram_rev |378 |263 |81 |214 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |311 |226 |73 |165 |0 |0 |
+| read_ram_data |read_ram_data_rev |67 |37 |8 |49 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
@@ -243,66 +242,66 @@ Report Hierarchy Area:
| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u_transfer_300_to_200 |transfer_300_to_200 |327 |215 |42 |273 |3 |0 |
-| u0_soft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |342 |260 |42 |277 |3 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
-| scan_start_diff |scan_start_diff |23 |23 |0 |15 |0 |0 |
-| u0_test_en |cdc_sync |4 |2 |0 |4 |0 |0 |
-| u1_test_en |cdc_sync |4 |4 |0 |4 |0 |0 |
-| u2_test_en |cdc_sync |3 |3 |0 |3 |0 |0 |
-| u_a_pclk |cdc_sync |5 |5 |0 |5 |0 |0 |
-| u_a_sp_sampling |cdc_sync |4 |4 |0 |4 |0 |0 |
-| u_a_sp_sampling_cam |cdc_sync |5 |1 |0 |5 |0 |0 |
-| u_a_sp_sampling_last |cdc_sync |5 |4 |0 |5 |0 |0 |
-| u_b_pclk |cdc_sync |4 |3 |0 |4 |0 |0 |
-| u_b_sp_sampling |cdc_sync |6 |2 |0 |6 |0 |0 |
-| u_b_sp_sampling_cam |cdc_sync |6 |4 |0 |6 |0 |0 |
-| u_b_sp_sampling_last |cdc_sync |2 |2 |0 |2 |0 |0 |
-| u_bus_top |ubus_top |1297 |1117 |22 |1208 |0 |0 |
-| u_local_bus_slve_cis |local_bus_slve_cis |800 |724 |22 |711 |0 |0 |
-| u_uart_2dsp |uart_2dsp |98 |86 |12 |61 |0 |0 |
-| u_dpi_mode |cdc_sync |4 |4 |0 |4 |0 |0 |
-| u_eot |cdc_sync |3 |3 |0 |3 |0 |0 |
+| scan_start_diff |scan_start_diff |29 |29 |0 |18 |0 |0 |
+| u0_test_en |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u1_test_en |cdc_sync |5 |2 |0 |5 |0 |0 |
+| u2_test_en |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u_a_pclk |cdc_sync |1 |0 |0 |1 |0 |0 |
+| u_a_sp_sampling |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_a_sp_sampling_cam |cdc_sync |6 |4 |0 |6 |0 |0 |
+| u_a_sp_sampling_last |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_b_pclk |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_b_sp_sampling |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_b_sp_sampling_cam |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_b_sp_sampling_last |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_bus_top |ubus_top |1333 |944 |22 |1243 |0 |0 |
+| u_local_bus_slve_cis |local_bus_slve_cis |821 |667 |22 |731 |0 |0 |
+| u_uart_2dsp |uart_2dsp |103 |87 |12 |64 |0 |0 |
+| u_dpi_mode |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_eot |cdc_sync |5 |4 |0 |5 |0 |0 |
| u_lv_en_flag |cdc_sync |5 |5 |0 |5 |0 |0 |
-| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |275 |237 |20 |213 |4 |0 |
-| u_hs_tx_wrapper |hs_tx_wrapper |227 |189 |20 |185 |4 |0 |
-| [0]$u_data_lane_wrapper |data_lane_wrapper |112 |89 |15 |86 |1 |0 |
-| u_data_hs_generate |data_hs_generate |107 |84 |15 |81 |1 |0 |
+| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |262 |213 |20 |209 |4 |0 |
+| u_hs_tx_wrapper |hs_tx_wrapper |220 |171 |20 |184 |4 |0 |
+| [0]$u_data_lane_wrapper |data_lane_wrapper |110 |76 |15 |85 |1 |0 |
+| u_data_hs_generate |data_hs_generate |105 |72 |15 |80 |1 |0 |
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
-| u_data_lp_generate |data_lp_generate |5 |5 |0 |5 |0 |0 |
-| [1]$u_data_lane_wrapper |data_lane_wrapper |27 |17 |0 |27 |1 |0 |
-| u_data_hs_generate |data_hs_generate |27 |17 |0 |27 |1 |0 |
+| u_data_lp_generate |data_lp_generate |5 |4 |0 |5 |0 |0 |
+| [1]$u_data_lane_wrapper |data_lane_wrapper |28 |27 |0 |28 |1 |0 |
+| u_data_hs_generate |data_hs_generate |28 |27 |0 |28 |1 |0 |
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
-| [2]$u_data_lane_wrapper |data_lane_wrapper |22 |22 |0 |22 |1 |0 |
-| u_data_hs_generate |data_hs_generate |22 |22 |0 |22 |1 |0 |
+| [2]$u_data_lane_wrapper |data_lane_wrapper |31 |27 |0 |31 |1 |0 |
+| u_data_hs_generate |data_hs_generate |31 |27 |0 |31 |1 |0 |
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
-| [3]$u_data_lane_wrapper |data_lane_wrapper |24 |24 |0 |24 |1 |0 |
-| u_data_hs_generate |data_hs_generate |24 |24 |0 |24 |1 |0 |
+| [3]$u_data_lane_wrapper |data_lane_wrapper |19 |14 |0 |19 |1 |0 |
+| u_data_hs_generate |data_hs_generate |19 |14 |0 |19 |1 |0 |
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
-| u_hs_tx_controler |hs_tx_controler |34 |29 |5 |18 |0 |0 |
-| u_clk_lane_wrapper |clk_lane_wrapper |8 |8 |0 |8 |0 |0 |
-| u_clk_lp_generate |clk_lp_generate |4 |4 |0 |4 |0 |0 |
+| u_hs_tx_controler |hs_tx_controler |26 |21 |5 |15 |0 |0 |
+| u_clk_lane_wrapper |clk_lane_wrapper |6 |6 |0 |6 |0 |0 |
+| u_clk_lp_generate |clk_lp_generate |2 |2 |0 |2 |0 |0 |
| u_clk_hs_generate |clk_hs_generate |4 |4 |0 |4 |0 |0 |
-| u_mipi_eot_min |cdc_sync |58 |58 |0 |58 |0 |0 |
-| u_mipi_sot_min |cdc_sync |66 |65 |0 |66 |0 |0 |
-| u_pic_cnt |cdc_sync |117 |40 |0 |117 |0 |0 |
-| u_pixel_cdc |pixel_cdc |688 |412 |0 |688 |0 |1 |
-| u_clk_cis_frame_num |cdc_sync |75 |65 |0 |75 |0 |0 |
-| u_clk_cis_pixel_y |cdc_sync |74 |47 |0 |74 |0 |0 |
-| u_clk_mipi_pixel_y |cdc_sync |67 |45 |0 |67 |0 |0 |
-| u_clka_cis_total_num |cdc_sync |108 |33 |0 |108 |0 |0 |
-| u_clka_mipi_total_num |cdc_sync |108 |58 |0 |108 |0 |0 |
-| u_clkb_cis_total_num |cdc_sync |104 |65 |0 |104 |0 |0 |
-| u_clkb_mipi_total_num |cdc_sync |89 |58 |0 |89 |0 |0 |
+| u_mipi_eot_min |cdc_sync |64 |39 |0 |64 |0 |0 |
+| u_mipi_sot_min |cdc_sync |58 |46 |0 |58 |0 |0 |
+| u_pic_cnt |cdc_sync |108 |58 |0 |108 |0 |0 |
+| u_pixel_cdc |pixel_cdc |676 |577 |0 |676 |0 |1 |
+| u_clk_cis_frame_num |cdc_sync |77 |77 |0 |77 |0 |0 |
+| u_clk_cis_pixel_y |cdc_sync |71 |65 |0 |71 |0 |0 |
+| u_clk_mipi_pixel_y |cdc_sync |73 |71 |0 |73 |0 |0 |
+| u_clka_cis_total_num |cdc_sync |90 |76 |0 |90 |0 |0 |
+| u_clka_mipi_total_num |cdc_sync |102 |87 |0 |102 |0 |0 |
+| u_clkb_cis_total_num |cdc_sync |105 |92 |0 |105 |0 |0 |
+| u_clkb_mipi_total_num |cdc_sync |95 |77 |0 |95 |0 |0 |
| u_pll |pll |0 |0 |0 |0 |0 |0 |
| u_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |0 |
-| u_softrst_done |cdc_sync |2 |0 |0 |2 |0 |0 |
-| ua_lvds_rx |lvds_rx |286 |192 |19 |206 |0 |0 |
-| ub_lvds_rx |lvds_rx |287 |185 |19 |207 |0 |0 |
+| u_softrst_done |cdc_sync |4 |4 |0 |4 |0 |0 |
+| ua_lvds_rx |lvds_rx |284 |208 |19 |203 |0 |0 |
+| ub_lvds_rx |lvds_rx |290 |191 |19 |211 |0 |0 |
| uu_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |0 |
+---------------------------------------------------------------------------------------------------------+
@@ -310,12 +309,12 @@ Report Hierarchy Area:
DataNet Average Fanout:
Index Fanout Nets
- #1 1 9824
- #2 2 3937
- #3 3 1458
- #4 4 642
- #5 5-10 1062
- #6 11-50 587
- #7 51-100 24
+ #1 1 9907
+ #2 2 3801
+ #3 3 1374
+ #4 4 579
+ #5 5-10 1189
+ #6 11-50 584
+ #7 51-100 22
#8 >500 1
- Average 2.91
+ Average 2.92
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.timing b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.timing
index 66632a8..d187ea2 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.timing
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.timing
@@ -1,7 +1,7 @@
=========================================================================================================
Auto created by Tang Dynasty v5.6.71036
Copyright (c) 2012-2023 Anlogic Inc.
-Sun Feb 18 16:14:56 2024
+Mon Feb 19 10:59:58 2024
=========================================================================================================
@@ -25,20 +25,20 @@ Minimum period is 0ns
Timing constraint: clock: a_pclk
Clock = a_pclk, period 20.833ns, rising at 0ns, falling at 10.417ns
-6230 endpoints analyzed totally, and 105934 paths analyzed
+6218 endpoints analyzed totally, and 103438 paths analyzed
0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 13.964ns
+Minimum period is 12.299ns
---------------------------------------------------------------------------------------------------------
Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 (691 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 6.869 ns
+ Slack (setup check): 8.534 ns
Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (rising edge triggered by clock a_pclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 13.712ns (logic 6.927ns, net 6.785ns, 50% logic)
- Logic Levels: 7 ( LUT5=3 ADDER=2 LUT2=1 MULT18=1 )
+ Data Path Delay: 12.047ns (logic 6.702ns, net 5.345ns, 55% logic)
+ Logic Levels: 7 ( LUT5=3 ADDER=2 LUT4=1 MULT18=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -49,26 +49,22 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 (
sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[0] clk2q 0.146 r 2.422
- U_rgb_to_csi_pakage/mult0_syn_4.a[12] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net (fanout = 4) 1.971 r 4.393 ../../../../hg_mp/fe/prebuffer.v(105)
- U_rgb_to_csi_pakage/mult0_syn_4.p[19] cell (MULT18) 3.563 r 7.956
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 1.345 r 9.301
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 10.007
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 10.007
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 10.080
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 10.080
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 10.153
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 10.153
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.508
- u_pixel_cdc/reg6_syn_65.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.794 r 11.302
- u_pixel_cdc/reg6_syn_65.f[0] cell (LUT5) 0.424 r 11.726
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.738 r 12.464 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.f[1] cell (LUT2) 0.424 r 12.888
- u_pixel_cdc/reg6_syn_67.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.468 r 13.356 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/reg6_syn_67.f[0] cell (LUT5) 0.431 r 13.787
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 1.469 r 15.256 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 15.988
- Arrival time 15.988 (7 lvl)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[1] clk2q 0.146 r 2.422
+ U_rgb_to_csi_pakage/mult0_syn_4.a[14] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net (fanout = 4) 1.622 r 4.044 ../../../../hg_mp/fe/prebuffer.v(109)
+ U_rgb_to_csi_pakage/mult0_syn_4.p[18] cell (MULT18) 3.563 r 7.607
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.705 r 9.312
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 9.939
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 9.939
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.f[1] cell (ADDER) 0.355 r 10.294
+ sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6]) net (fanout = 1) 0.468 r 10.762
+ sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.f[0] cell (LUT4) 0.431 r 11.193
+ u_pic_cnt/reg1_syn_396.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net (fanout = 1) 0.309 r 11.502 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_396.f[0] cell (LUT5) 0.424 r 11.926
+ u_pic_cnt/reg1_syn_384.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239) net (fanout = 1) 0.738 r 12.664 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_384.f[0] cell (LUT5) 0.424 r 13.088
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 0.503 r 13.591 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 14.323
+ Arrival time 14.323 (7 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
@@ -82,17 +78,67 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 (
clock recovergence pessimism 0.095 22.857
Required time 22.857
---------------------------------------------------------------------------------------------------------
- Slack 6.869ns
+ Slack 8.534ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 6.869 ns
+ Slack (setup check): 8.534 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (rising edge triggered by clock a_pclk)
+ Clock group: a_lvds_clk_p
+ Process: Slow
+ Data Path Delay: 12.047ns (logic 6.702ns, net 5.345ns, 55% logic)
+ Logic Levels: 7 ( LUT5=3 ADDER=2 LUT4=1 MULT18=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 2.276
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[0] clk2q 0.146 r 2.422
+ U_rgb_to_csi_pakage/mult0_syn_4.a[12] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net (fanout = 4) 1.622 r 4.044 ../../../../hg_mp/fe/prebuffer.v(109)
+ U_rgb_to_csi_pakage/mult0_syn_4.p[18] cell (MULT18) 3.563 r 7.607
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.705 r 9.312
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 9.939
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 9.939
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.f[1] cell (ADDER) 0.355 r 10.294
+ sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6]) net (fanout = 1) 0.468 r 10.762
+ sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.f[0] cell (LUT4) 0.431 r 11.193
+ u_pic_cnt/reg1_syn_396.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net (fanout = 1) 0.309 r 11.502 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_396.f[0] cell (LUT5) 0.424 r 11.926
+ u_pic_cnt/reg1_syn_384.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239) net (fanout = 1) 0.738 r 12.664 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_384.f[0] cell (LUT5) 0.424 r 13.088
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 0.503 r 13.591 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 14.323
+ Arrival time 14.323 (7 lvl)
+
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 20.833 22.878
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.116 22.762
+ clock uncertainty -0.000 22.762
+ clock recovergence pessimism 0.095 22.857
+ Required time 22.857
+---------------------------------------------------------------------------------------------------------
+ Slack 8.534ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check): 8.534 ns
Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[0] (rising edge triggered by clock a_pclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 13.712ns (logic 6.927ns, net 6.785ns, 50% logic)
- Logic Levels: 7 ( LUT5=3 ADDER=2 LUT2=1 MULT18=1 )
+ Data Path Delay: 12.047ns (logic 6.702ns, net 5.345ns, 55% logic)
+ Logic Levels: 7 ( LUT5=3 ADDER=2 LUT4=1 MULT18=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -103,26 +149,22 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 (
sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[0] clk2q 0.146 r 2.422
- U_rgb_to_csi_pakage/mult0_syn_4.a[12] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net (fanout = 4) 1.971 r 4.393 ../../../../hg_mp/fe/prebuffer.v(105)
- U_rgb_to_csi_pakage/mult0_syn_4.p[19] cell (MULT18) 3.563 r 7.956
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 1.345 r 9.301
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 10.007
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 10.007
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 10.080
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 10.080
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 10.153
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 10.153
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.508
- u_pixel_cdc/reg6_syn_65.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.794 r 11.302
- u_pixel_cdc/reg6_syn_65.f[0] cell (LUT5) 0.424 r 11.726
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.738 r 12.464 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.f[1] cell (LUT2) 0.424 r 12.888
- u_pixel_cdc/reg6_syn_67.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.468 r 13.356 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/reg6_syn_67.f[0] cell (LUT5) 0.431 r 13.787
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 1.469 r 15.256 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 15.988
- Arrival time 15.988 (7 lvl)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[1] clk2q 0.146 r 2.422
+ U_rgb_to_csi_pakage/mult0_syn_4.a[14] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net (fanout = 4) 1.622 r 4.044 ../../../../hg_mp/fe/prebuffer.v(109)
+ U_rgb_to_csi_pakage/mult0_syn_4.p[18] cell (MULT18) 3.563 r 7.607
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.705 r 9.312
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 9.939
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 9.939
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.f[1] cell (ADDER) 0.355 r 10.294
+ sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6]) net (fanout = 1) 0.468 r 10.762
+ sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.f[0] cell (LUT4) 0.431 r 11.193
+ u_pic_cnt/reg1_syn_396.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net (fanout = 1) 0.309 r 11.502 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_396.f[0] cell (LUT5) 0.424 r 11.926
+ u_pic_cnt/reg1_syn_384.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239) net (fanout = 1) 0.738 r 12.664 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_384.f[0] cell (LUT5) 0.424 r 13.088
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 0.503 r 13.591 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 14.323
+ Arrival time 14.323 (7 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
@@ -136,75 +178,69 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 (
clock recovergence pessimism 0.095 22.857
Required time 22.857
---------------------------------------------------------------------------------------------------------
- Slack 6.869ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check): 6.875 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (rising edge triggered by clock a_pclk)
- Clock group: a_lvds_clk_p
- Process: Slow
- Data Path Delay: 13.706ns (logic 6.921ns, net 6.785ns, 50% logic)
- Logic Levels: 7 ( LUT5=3 ADDER=2 LUT2=1 MULT18=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 2.276
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[0] clk2q 0.146 r 2.422
- U_rgb_to_csi_pakage/mult0_syn_4.a[12] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net (fanout = 4) 1.971 r 4.393 ../../../../hg_mp/fe/prebuffer.v(105)
- U_rgb_to_csi_pakage/mult0_syn_4.p[18] cell (MULT18) 3.563 r 7.956
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.345 r 9.301
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 9.928
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 9.928
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 10.001
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 10.001
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 10.074
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 10.074
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 10.147
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 10.147
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.502
- u_pixel_cdc/reg6_syn_65.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.794 r 11.296
- u_pixel_cdc/reg6_syn_65.f[0] cell (LUT5) 0.424 r 11.720
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.738 r 12.458 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.f[1] cell (LUT2) 0.424 r 12.882
- u_pixel_cdc/reg6_syn_67.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.468 r 13.350 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/reg6_syn_67.f[0] cell (LUT5) 0.431 r 13.781
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 1.469 r 15.250 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 15.982
- Arrival time 15.982 (7 lvl)
-
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 20.833 22.878
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 22.762
- clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.095 22.857
- Required time 22.857
----------------------------------------------------------------------------------------------------------
- Slack 6.875ns
+ Slack 8.534ns
---------------------------------------------------------------------------------------------------------
Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 (659 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 7.164 ns
+ Slack (setup check): 8.641 ns
Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1] (rising edge triggered by clock a_pclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 13.417ns (logic 6.927ns, net 6.490ns, 51% logic)
- Logic Levels: 7 ( LUT5=3 ADDER=2 LUT2=1 MULT18=1 )
+ Data Path Delay: 12.012ns (logic 6.702ns, net 5.310ns, 55% logic)
+ Logic Levels: 7 ( LUT5=3 ADDER=2 LUT4=1 MULT18=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 2.276
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[1] clk2q 0.146 r 2.422
+ U_rgb_to_csi_pakage/mult0_syn_4.a[14] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net (fanout = 4) 1.622 r 4.044 ../../../../hg_mp/fe/prebuffer.v(109)
+ U_rgb_to_csi_pakage/mult0_syn_4.p[18] cell (MULT18) 3.563 r 7.607
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.705 r 9.312
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 9.939
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 9.939
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.f[1] cell (ADDER) 0.355 r 10.294
+ sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6]) net (fanout = 1) 0.468 r 10.762
+ sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.f[0] cell (LUT4) 0.431 r 11.193
+ u_pic_cnt/reg1_syn_396.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net (fanout = 1) 0.309 r 11.502 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_396.f[0] cell (LUT5) 0.424 r 11.926
+ u_pic_cnt/reg1_syn_384.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239) net (fanout = 1) 0.738 r 12.664 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_384.f[0] cell (LUT5) 0.424 r 13.088
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 0.468 r 13.556 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.732 14.288
+ Arrival time 14.288 (7 lvl)
+
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 20.833 22.878
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.116 22.762
+ clock uncertainty -0.000 22.762
+ clock recovergence pessimism 0.167 22.929
+ Required time 22.929
+---------------------------------------------------------------------------------------------------------
+ Slack 8.641ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check): 8.641 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1] (rising edge triggered by clock a_pclk)
+ Clock group: a_lvds_clk_p
+ Process: Slow
+ Data Path Delay: 12.012ns (logic 6.702ns, net 5.310ns, 55% logic)
+ Logic Levels: 7 ( LUT5=3 ADDER=2 LUT4=1 MULT18=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -216,25 +252,21 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 (
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[0] clk2q 0.146 r 2.422
- U_rgb_to_csi_pakage/mult0_syn_4.a[12] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net (fanout = 4) 1.971 r 4.393 ../../../../hg_mp/fe/prebuffer.v(105)
- U_rgb_to_csi_pakage/mult0_syn_4.p[19] cell (MULT18) 3.563 r 7.956
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 1.345 r 9.301
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 10.007
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 10.007
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 10.080
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 10.080
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 10.153
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 10.153
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.508
- u_pixel_cdc/reg6_syn_65.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.794 r 11.302
- u_pixel_cdc/reg6_syn_65.f[0] cell (LUT5) 0.424 r 11.726
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.738 r 12.464 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.f[1] cell (LUT2) 0.424 r 12.888
- u_pixel_cdc/reg6_syn_67.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.468 r 13.356 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/reg6_syn_67.f[0] cell (LUT5) 0.431 r 13.787
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 1.174 r 14.961 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.732 15.693
- Arrival time 15.693 (7 lvl)
+ U_rgb_to_csi_pakage/mult0_syn_4.a[12] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net (fanout = 4) 1.622 r 4.044 ../../../../hg_mp/fe/prebuffer.v(109)
+ U_rgb_to_csi_pakage/mult0_syn_4.p[18] cell (MULT18) 3.563 r 7.607
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.705 r 9.312
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 9.939
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 9.939
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.f[1] cell (ADDER) 0.355 r 10.294
+ sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6]) net (fanout = 1) 0.468 r 10.762
+ sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.f[0] cell (LUT4) 0.431 r 11.193
+ u_pic_cnt/reg1_syn_396.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net (fanout = 1) 0.309 r 11.502 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_396.f[0] cell (LUT5) 0.424 r 11.926
+ u_pic_cnt/reg1_syn_384.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239) net (fanout = 1) 0.738 r 12.664 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_384.f[0] cell (LUT5) 0.424 r 13.088
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 0.468 r 13.556 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.732 14.288
+ Arrival time 14.288 (7 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
@@ -245,20 +277,20 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 (
---------------------------------------------------------------------------------------------------------
cell setup -0.116 22.762
clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.095 22.857
- Required time 22.857
+ clock recovergence pessimism 0.167 22.929
+ Required time 22.929
---------------------------------------------------------------------------------------------------------
- Slack 7.164ns
+ Slack 8.641ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 7.164 ns
+ Slack (setup check): 8.641 ns
Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[0] (rising edge triggered by clock a_pclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 13.417ns (logic 6.927ns, net 6.490ns, 51% logic)
- Logic Levels: 7 ( LUT5=3 ADDER=2 LUT2=1 MULT18=1 )
+ Data Path Delay: 12.012ns (logic 6.702ns, net 5.310ns, 55% logic)
+ Logic Levels: 7 ( LUT5=3 ADDER=2 LUT4=1 MULT18=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -269,26 +301,22 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 (
sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[0] clk2q 0.146 r 2.422
- U_rgb_to_csi_pakage/mult0_syn_4.a[12] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net (fanout = 4) 1.971 r 4.393 ../../../../hg_mp/fe/prebuffer.v(105)
- U_rgb_to_csi_pakage/mult0_syn_4.p[19] cell (MULT18) 3.563 r 7.956
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 1.345 r 9.301
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 10.007
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 10.007
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 10.080
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 10.080
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 10.153
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 10.153
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.508
- u_pixel_cdc/reg6_syn_65.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.794 r 11.302
- u_pixel_cdc/reg6_syn_65.f[0] cell (LUT5) 0.424 r 11.726
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.738 r 12.464 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.f[1] cell (LUT2) 0.424 r 12.888
- u_pixel_cdc/reg6_syn_67.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.468 r 13.356 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/reg6_syn_67.f[0] cell (LUT5) 0.431 r 13.787
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 1.174 r 14.961 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.732 15.693
- Arrival time 15.693 (7 lvl)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[1] clk2q 0.146 r 2.422
+ U_rgb_to_csi_pakage/mult0_syn_4.a[14] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net (fanout = 4) 1.622 r 4.044 ../../../../hg_mp/fe/prebuffer.v(109)
+ U_rgb_to_csi_pakage/mult0_syn_4.p[18] cell (MULT18) 3.563 r 7.607
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.705 r 9.312
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 9.939
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 9.939
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.f[1] cell (ADDER) 0.355 r 10.294
+ sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6]) net (fanout = 1) 0.468 r 10.762
+ sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.f[0] cell (LUT4) 0.431 r 11.193
+ u_pic_cnt/reg1_syn_396.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net (fanout = 1) 0.309 r 11.502 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_396.f[0] cell (LUT5) 0.424 r 11.926
+ u_pic_cnt/reg1_syn_384.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239) net (fanout = 1) 0.738 r 12.664 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_384.f[0] cell (LUT5) 0.424 r 13.088
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 0.468 r 13.556 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.732 14.288
+ Arrival time 14.288 (7 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
@@ -299,20 +327,22 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 (
---------------------------------------------------------------------------------------------------------
cell setup -0.116 22.762
clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.095 22.857
- Required time 22.857
+ clock recovergence pessimism 0.167 22.929
+ Required time 22.929
---------------------------------------------------------------------------------------------------------
- Slack 7.164ns
+ Slack 8.641ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 7.170 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1] (rising edge triggered by clock a_pclk)
+Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14 (85 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check): 12.509 ns
+ Start Point: scan_start_diff/trigger_syn_7099.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.c[0] (rising edge triggered by clock a_pclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 13.411ns (logic 6.921ns, net 6.490ns, 51% logic)
- Logic Levels: 7 ( LUT5=3 ADDER=2 LUT2=1 MULT18=1 )
+ Data Path Delay: 8.144ns (logic 2.383ns, net 5.761ns, 29% logic)
+ Logic Levels: 6 ( LUT4=6 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -320,57 +350,47 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 (
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ scan_start_diff/trigger_syn_7099.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[0] clk2q 0.146 r 2.422
- U_rgb_to_csi_pakage/mult0_syn_4.a[12] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net (fanout = 4) 1.971 r 4.393 ../../../../hg_mp/fe/prebuffer.v(105)
- U_rgb_to_csi_pakage/mult0_syn_4.p[18] cell (MULT18) 3.563 r 7.956
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.345 r 9.301
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 9.928
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 9.928
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 10.001
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 10.001
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 10.074
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 10.074
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 10.147
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 10.147
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.502
- u_pixel_cdc/reg6_syn_65.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.794 r 11.296
- u_pixel_cdc/reg6_syn_65.f[0] cell (LUT5) 0.424 r 11.720
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.738 r 12.458 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.f[1] cell (LUT2) 0.424 r 12.882
- u_pixel_cdc/reg6_syn_67.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.468 r 13.350 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/reg6_syn_67.f[0] cell (LUT5) 0.431 r 13.781
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 1.174 r 14.955 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.732 15.687
- Arrival time 15.687 (7 lvl)
+ scan_start_diff/trigger_syn_7099.q[0] clk2q 0.146 r 2.422
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_244.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[1]) net (fanout = 94) 1.817 r 4.239 ../../../../hg_mp/fe/ram_switch.v(33)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_244.f[1] cell (LUT4) 0.348 r 4.587
+ sampling_fe_a/u_sort/reg2_syn_54.b[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_39) net (fanout = 61) 1.327 r 5.914 ../../../../hg_mp/fe/ram_switch_state.v(64)
+ sampling_fe_a/u_sort/reg2_syn_54.f[1] cell (LUT4) 0.431 r 6.345
+ sampling_fe_a/u_sort/reg0_syn_58.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_3656) net (fanout = 5) 0.685 r 7.030 ../../../../hg_mp/fe/mux_e.v(24)
+ sampling_fe_a/u_sort/reg0_syn_58.f[0] cell (LUT4) 0.333 r 7.363
+ sampling_fe_a/u_sort/reg0_syn_58.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_2) net (fanout = 1) 0.593 r 7.956 ../../../../hg_mp/fe/ram_switch_state.v(47)
+ sampling_fe_a/u_sort/reg0_syn_58.f[1] cell (LUT4) 0.251 r 8.207
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_712.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_4) net (fanout = 3) 0.601 r 8.808 ../../../../hg_mp/fe/ram_switch_state.v(47)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_712.f[0] cell (LUT4) 0.408 r 9.216
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.c[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[24]_syn_2) net (fanout = 1) 0.738 r 9.954 ../../../../hg_mp/fe/ram_switch_state.v(47)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14 path2reg0 (LUT4) 0.466 10.420
+ Arrival time 10.420 (6 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 20.833 22.878
---------------------------------------------------------------------------------------------------------
cell setup -0.116 22.762
clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.095 22.857
- Required time 22.857
+ clock recovergence pessimism 0.167 22.929
+ Required time 22.929
---------------------------------------------------------------------------------------------------------
- Slack 7.170ns
+ Slack 12.509ns
---------------------------------------------------------------------------------------------------------
-Paths for end point exdev_ctl_a/u_gen_sp/reg0_syn_81 (217 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check): 12.294 ns
- Start Point: exdev_ctl_a/u_gen_sp/reg9_syn_103.clk (rising edge triggered by clock a_pclk)
- End Point: exdev_ctl_a/u_gen_sp/reg0_syn_81.sr (rising edge triggered by clock a_pclk)
+ Slack (setup check): 12.523 ns
+ Start Point: scan_start_diff/trigger_syn_7101.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.c[0] (rising edge triggered by clock a_pclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 8.216ns (logic 3.713ns, net 4.503ns, 45% logic)
- Logic Levels: 7 ( LUT5=5 ADDER=2 )
+ Data Path Delay: 8.130ns (logic 2.297ns, net 5.833ns, 28% logic)
+ Logic Levels: 6 ( LUT4=6 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -378,53 +398,47 @@ Paths for end point exdev_ctl_a/u_gen_sp/reg0_syn_81 (217 paths)
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- exdev_ctl_a/u_gen_sp/reg9_syn_103.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ scan_start_diff/trigger_syn_7101.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- exdev_ctl_a/u_gen_sp/reg9_syn_103.q[0] clk2q 0.146 r 2.422
- exdev_ctl_a/u_gen_sp/sub1_syn_103.a[0] (exdev_ctl_a/u_gen_sp/sp_t_d1[3]) net (fanout = 1) 0.803 r 3.225 ../../../../hg_mp/fe/gen_sp.v(87)
- exdev_ctl_a/u_gen_sp/sub1_syn_103.fco cell (ADDER) 0.947 r 4.172
- exdev_ctl_a/u_gen_sp/sub1_syn_104.fci (exdev_ctl_a/u_gen_sp/sub1_syn_91) net (fanout = 1) 0.000 f 4.172 ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_a/u_gen_sp/sub1_syn_104.fco cell (ADDER) 0.132 r 4.304
- exdev_ctl_a/u_gen_sp/sub1_syn_105.fci (exdev_ctl_a/u_gen_sp/sub1_syn_95) net (fanout = 1) 0.000 f 4.304 ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_a/u_gen_sp/sub1_syn_105.fx[0] cell (ADDER) 0.387 r 4.691
- exdev_ctl_a/reg8_syn_103.a[1] (exdev_ctl_a/u_gen_sp/cnt_one_line_b5[12]) net (fanout = 1) 0.591 r 5.282
- exdev_ctl_a/reg8_syn_103.f[1] cell (LUT5) 0.424 r 5.706
- exdev_ctl_b/reg6_syn_103.a[1] (exdev_ctl_a/u_gen_sp/mux31_syn_140) net (fanout = 1) 0.738 r 6.444 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/reg6_syn_103.f[1] cell (LUT5) 0.424 r 6.868
- u_bus_top/reg5_syn_196.a[0] (exdev_ctl_a/u_gen_sp/mux31_syn_142) net (fanout = 1) 0.307 r 7.175 ../../../../hg_mp/fe/gen_sp.v(137)
- u_bus_top/reg5_syn_196.f[0] cell (LUT5) 0.424 r 7.599
- exdev_ctl_a/reg8_syn_103.a[0] (exdev_ctl_a/u_gen_sp/mux31_syn_150) net (fanout = 1) 0.456 r 8.055 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_a/reg8_syn_103.f[0] cell (LUT5) 0.424 r 8.479
- exdev_ctl_a/reg8_syn_109.d[1] (exdev_ctl_a/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.612 r 9.091
- exdev_ctl_a/reg8_syn_109.f[1] cell (LUT5) 0.262 r 9.353
- exdev_ctl_a/u_gen_sp/reg0_syn_81.sr (exdev_ctl_a/u_gen_sp/mux31_syn_19) net (fanout = 8) 0.996 r 10.349 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_a/u_gen_sp/reg0_syn_81 path2reg 0.143 10.492
- Arrival time 10.492 (7 lvl)
+ scan_start_diff/trigger_syn_7101.q[0] clk2q 0.146 r 2.422
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_244.d[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[0]) net (fanout = 90) 1.889 r 4.311 ../../../../hg_mp/fe/ram_switch.v(33)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_244.f[1] cell (LUT4) 0.262 r 4.573
+ sampling_fe_a/u_sort/reg2_syn_54.b[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_39) net (fanout = 61) 1.327 r 5.900 ../../../../hg_mp/fe/ram_switch_state.v(64)
+ sampling_fe_a/u_sort/reg2_syn_54.f[1] cell (LUT4) 0.431 r 6.331
+ sampling_fe_a/u_sort/reg0_syn_58.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_3656) net (fanout = 5) 0.685 r 7.016 ../../../../hg_mp/fe/mux_e.v(24)
+ sampling_fe_a/u_sort/reg0_syn_58.f[0] cell (LUT4) 0.333 r 7.349
+ sampling_fe_a/u_sort/reg0_syn_58.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_2) net (fanout = 1) 0.593 r 7.942 ../../../../hg_mp/fe/ram_switch_state.v(47)
+ sampling_fe_a/u_sort/reg0_syn_58.f[1] cell (LUT4) 0.251 r 8.193
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_712.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_4) net (fanout = 3) 0.601 r 8.794 ../../../../hg_mp/fe/ram_switch_state.v(47)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_712.f[0] cell (LUT4) 0.408 r 9.202
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.c[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[24]_syn_2) net (fanout = 1) 0.738 r 9.940 ../../../../hg_mp/fe/ram_switch_state.v(47)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14 path2reg0 (LUT4) 0.466 10.406
+ Arrival time 10.406 (6 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- exdev_ctl_a/u_gen_sp/reg0_syn_81.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 20.833 22.878
---------------------------------------------------------------------------------------------------------
- cell setup -0.187 22.691
- clock uncertainty -0.000 22.691
- clock recovergence pessimism 0.095 22.786
- Required time 22.786
+ cell setup -0.116 22.762
+ clock uncertainty -0.000 22.762
+ clock recovergence pessimism 0.167 22.929
+ Required time 22.929
---------------------------------------------------------------------------------------------------------
- Slack 12.294ns
+ Slack 12.523ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 12.405 ns
- Start Point: exdev_ctl_a/u_gen_sp/reg9_syn_100.clk (rising edge triggered by clock a_pclk)
- End Point: exdev_ctl_a/u_gen_sp/reg0_syn_81.sr (rising edge triggered by clock a_pclk)
+ Slack (setup check): 12.660 ns
+ Start Point: scan_start_diff/trigger_syn_7099.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.c[0] (rising edge triggered by clock a_pclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 8.105ns (logic 3.602ns, net 4.503ns, 44% logic)
- Logic Levels: 7 ( LUT5=5 ADDER=2 )
+ Data Path Delay: 7.993ns (logic 2.360ns, net 5.633ns, 29% logic)
+ Logic Levels: 6 ( LUT4=6 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -432,105 +446,163 @@ Paths for end point exdev_ctl_a/u_gen_sp/reg0_syn_81 (217 paths)
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- exdev_ctl_a/u_gen_sp/reg9_syn_100.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ scan_start_diff/trigger_syn_7099.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- exdev_ctl_a/u_gen_sp/reg9_syn_100.q[0] clk2q 0.146 r 2.422
- exdev_ctl_a/u_gen_sp/sub1_syn_103.b[0] (exdev_ctl_a/u_gen_sp/sp_t_d1[4]) net (fanout = 1) 0.803 r 3.225 ../../../../hg_mp/fe/gen_sp.v(87)
- exdev_ctl_a/u_gen_sp/sub1_syn_103.fco cell (ADDER) 0.836 r 4.061
- exdev_ctl_a/u_gen_sp/sub1_syn_104.fci (exdev_ctl_a/u_gen_sp/sub1_syn_91) net (fanout = 1) 0.000 f 4.061 ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_a/u_gen_sp/sub1_syn_104.fco cell (ADDER) 0.132 r 4.193
- exdev_ctl_a/u_gen_sp/sub1_syn_105.fci (exdev_ctl_a/u_gen_sp/sub1_syn_95) net (fanout = 1) 0.000 f 4.193 ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_a/u_gen_sp/sub1_syn_105.fx[0] cell (ADDER) 0.387 r 4.580
- exdev_ctl_a/reg8_syn_103.a[1] (exdev_ctl_a/u_gen_sp/cnt_one_line_b5[12]) net (fanout = 1) 0.591 r 5.171
- exdev_ctl_a/reg8_syn_103.f[1] cell (LUT5) 0.424 r 5.595
- exdev_ctl_b/reg6_syn_103.a[1] (exdev_ctl_a/u_gen_sp/mux31_syn_140) net (fanout = 1) 0.738 r 6.333 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/reg6_syn_103.f[1] cell (LUT5) 0.424 r 6.757
- u_bus_top/reg5_syn_196.a[0] (exdev_ctl_a/u_gen_sp/mux31_syn_142) net (fanout = 1) 0.307 r 7.064 ../../../../hg_mp/fe/gen_sp.v(137)
- u_bus_top/reg5_syn_196.f[0] cell (LUT5) 0.424 r 7.488
- exdev_ctl_a/reg8_syn_103.a[0] (exdev_ctl_a/u_gen_sp/mux31_syn_150) net (fanout = 1) 0.456 r 7.944 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_a/reg8_syn_103.f[0] cell (LUT5) 0.424 r 8.368
- exdev_ctl_a/reg8_syn_109.d[1] (exdev_ctl_a/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.612 r 8.980
- exdev_ctl_a/reg8_syn_109.f[1] cell (LUT5) 0.262 r 9.242
- exdev_ctl_a/u_gen_sp/reg0_syn_81.sr (exdev_ctl_a/u_gen_sp/mux31_syn_19) net (fanout = 8) 0.996 r 10.238 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_a/u_gen_sp/reg0_syn_81 path2reg 0.143 10.381
- Arrival time 10.381 (7 lvl)
+ scan_start_diff/trigger_syn_7099.q[0] clk2q 0.146 r 2.422
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_244.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[1]) net (fanout = 94) 1.817 r 4.239 ../../../../hg_mp/fe/ram_switch.v(33)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_244.f[1] cell (LUT4) 0.348 r 4.587
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[84]_syn_62.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_39) net (fanout = 61) 1.218 r 5.805 ../../../../hg_mp/fe/ram_switch_state.v(64)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[84]_syn_62.f[0] cell (LUT4) 0.333 r 6.138
+ sampling_fe_a/u_sort/reg0_syn_58.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_4756) net (fanout = 5) 0.666 r 6.804 ../../../../hg_mp/fe/mux_e.v(24)
+ sampling_fe_a/u_sort/reg0_syn_58.f[0] cell (LUT4) 0.408 r 7.212
+ sampling_fe_a/u_sort/reg0_syn_58.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_2) net (fanout = 1) 0.593 r 7.805 ../../../../hg_mp/fe/ram_switch_state.v(47)
+ sampling_fe_a/u_sort/reg0_syn_58.f[1] cell (LUT4) 0.251 r 8.056
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_712.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_4) net (fanout = 3) 0.601 r 8.657 ../../../../hg_mp/fe/ram_switch_state.v(47)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_712.f[0] cell (LUT4) 0.408 r 9.065
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.c[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[24]_syn_2) net (fanout = 1) 0.738 r 9.803 ../../../../hg_mp/fe/ram_switch_state.v(47)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14 path2reg0 (LUT4) 0.466 10.269
+ Arrival time 10.269 (6 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- exdev_ctl_a/u_gen_sp/reg0_syn_81.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 20.833 22.878
---------------------------------------------------------------------------------------------------------
- cell setup -0.187 22.691
- clock uncertainty -0.000 22.691
- clock recovergence pessimism 0.095 22.786
- Required time 22.786
+ cell setup -0.116 22.762
+ clock uncertainty -0.000 22.762
+ clock recovergence pessimism 0.167 22.929
+ Required time 22.929
---------------------------------------------------------------------------------------------------------
- Slack 12.405ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check): 12.598 ns
- Start Point: exdev_ctl_a/u_gen_sp/reg9_syn_100.clk (rising edge triggered by clock a_pclk)
- End Point: exdev_ctl_a/u_gen_sp/reg0_syn_81.sr (rising edge triggered by clock a_pclk)
- Clock group: a_lvds_clk_p
- Process: Slow
- Data Path Delay: 7.912ns (logic 3.581ns, net 4.331ns, 45% logic)
- Logic Levels: 7 ( LUT5=5 ADDER=2 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- exdev_ctl_a/u_gen_sp/reg9_syn_100.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 2.276
----------------------------------------------------------------------------------------------------------
- exdev_ctl_a/u_gen_sp/reg9_syn_100.q[1] clk2q 0.146 r 2.422
- exdev_ctl_a/u_gen_sp/sub1_syn_104.a[0] (exdev_ctl_a/u_gen_sp/sp_t_d1[7]) net (fanout = 1) 0.631 r 3.053 ../../../../hg_mp/fe/gen_sp.v(87)
- exdev_ctl_a/u_gen_sp/sub1_syn_104.fco cell (ADDER) 0.947 r 4.000
- exdev_ctl_a/u_gen_sp/sub1_syn_105.fci (exdev_ctl_a/u_gen_sp/sub1_syn_95) net (fanout = 1) 0.000 f 4.000 ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_a/u_gen_sp/sub1_syn_105.fx[0] cell (ADDER) 0.387 r 4.387
- exdev_ctl_a/reg8_syn_103.a[1] (exdev_ctl_a/u_gen_sp/cnt_one_line_b5[12]) net (fanout = 1) 0.591 r 4.978
- exdev_ctl_a/reg8_syn_103.f[1] cell (LUT5) 0.424 r 5.402
- exdev_ctl_b/reg6_syn_103.a[1] (exdev_ctl_a/u_gen_sp/mux31_syn_140) net (fanout = 1) 0.738 r 6.140 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/reg6_syn_103.f[1] cell (LUT5) 0.424 r 6.564
- u_bus_top/reg5_syn_196.a[0] (exdev_ctl_a/u_gen_sp/mux31_syn_142) net (fanout = 1) 0.307 r 6.871 ../../../../hg_mp/fe/gen_sp.v(137)
- u_bus_top/reg5_syn_196.f[0] cell (LUT5) 0.424 r 7.295
- exdev_ctl_a/reg8_syn_103.a[0] (exdev_ctl_a/u_gen_sp/mux31_syn_150) net (fanout = 1) 0.456 r 7.751 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_a/reg8_syn_103.f[0] cell (LUT5) 0.424 r 8.175
- exdev_ctl_a/reg8_syn_109.d[1] (exdev_ctl_a/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.612 r 8.787
- exdev_ctl_a/reg8_syn_109.f[1] cell (LUT5) 0.262 r 9.049
- exdev_ctl_a/u_gen_sp/reg0_syn_81.sr (exdev_ctl_a/u_gen_sp/mux31_syn_19) net (fanout = 8) 0.996 r 10.045 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_a/u_gen_sp/reg0_syn_81 path2reg 0.143 10.188
- Arrival time 10.188 (7 lvl)
-
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- exdev_ctl_a/u_gen_sp/reg0_syn_81.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 20.833 22.878
----------------------------------------------------------------------------------------------------------
- cell setup -0.187 22.691
- clock uncertainty -0.000 22.691
- clock recovergence pessimism 0.095 22.786
- Required time 22.786
----------------------------------------------------------------------------------------------------------
- Slack 12.598ns
+ Slack 12.660ns
---------------------------------------------------------------------------------------------------------
Hold checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1 (10 paths)
+Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1 (10 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.089 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[75]_syn_8.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.addra[8] (rising edge triggered by clock a_pclk)
+ Clock group: a_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.334ns (logic 0.109ns, net 0.225ns, 32% logic)
+ Logic Levels: 1 ( EMB=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[75]_syn_8.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[75]_syn_8.q[0] clk2q 0.109 r 2.047
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.addra[8] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[65]) net (fanout = 2) 0.225 r 2.272 ../../../../hg_mp/fe/prebuffer.v(331)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1 path2reg (EMB) 0.000 2.272
+ Arrival time 2.272 (1 lvl)
+
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.200 2.330
+ clock uncertainty 0.000 2.330
+ clock recovergence pessimism -0.147 2.183
+ Required time 2.183
+---------------------------------------------------------------------------------------------------------
+ Slack 0.089ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check): 0.195 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[95]_syn_22.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.addra[3] (rising edge triggered by clock a_pclk)
+ Clock group: a_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.440ns (logic 0.109ns, net 0.331ns, 24% logic)
+ Logic Levels: 1 ( EMB=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[95]_syn_22.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[95]_syn_22.q[0] clk2q 0.109 r 2.047
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.addra[3] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[60]) net (fanout = 2) 0.331 r 2.378 ../../../../hg_mp/fe/prebuffer.v(331)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1 path2reg (EMB) 0.000 2.378
+ Arrival time 2.378 (1 lvl)
+
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.200 2.330
+ clock uncertainty 0.000 2.330
+ clock recovergence pessimism -0.147 2.183
+ Required time 2.183
+---------------------------------------------------------------------------------------------------------
+ Slack 0.195ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check): 0.196 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_735.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.addra[9] (rising edge triggered by clock a_pclk)
+ Clock group: a_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.441ns (logic 0.109ns, net 0.332ns, 24% logic)
+ Logic Levels: 1 ( EMB=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_735.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_735.q[0] clk2q 0.109 r 2.047
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.addra[9] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[66]) net (fanout = 2) 0.332 r 2.379 ../../../../hg_mp/fe/prebuffer.v(331)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1 path2reg (EMB) 0.000 2.379
+ Arrival time 2.379 (1 lvl)
+
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.200 2.330
+ clock uncertainty 0.000 2.330
+ clock recovergence pessimism -0.147 2.183
+ Required time 2.183
+---------------------------------------------------------------------------------------------------------
+ Slack 0.196ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1 (8 paths)
---------------------------------------------------------------------------------------------------------
Slack (hold check): 0.114 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_741.clk (rising edge triggered by clock a_pclk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.addra[7] (rising edge triggered by clock a_pclk)
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_547.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dia[5] (rising edge triggered by clock a_pclk)
Clock group: a_lvds_clk_p
Process: Fast
Data Path Delay: 0.359ns (logic 0.109ns, net 0.250ns, 30% logic)
@@ -542,19 +614,19 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_s
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_741.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_547.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_741.q[0] clk2q 0.109 r 2.047
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.addra[7] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[34]) net (fanout = 2) 0.250 r 2.297 ../../../../hg_mp/fe/prebuffer.v(327)
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1 path2reg (EMB) 0.000 2.297
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_547.q[0] clk2q 0.109 r 2.047
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dia[5] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[21]) net (fanout = 2) 0.250 r 2.297 ../../../../hg_mp/fe/prebuffer.v(329)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1 path2reg (EMB) 0.000 2.297
Arrival time 2.297 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell hold 0.200 2.330
@@ -566,12 +638,12 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_s
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.234 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_652.clk (rising edge triggered by clock a_pclk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.addra[5] (rising edge triggered by clock a_pclk)
+ Slack (hold check): 0.218 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_549.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dia[3] (rising edge triggered by clock a_pclk)
Clock group: a_lvds_clk_p
Process: Fast
- Data Path Delay: 0.479ns (logic 0.109ns, net 0.370ns, 22% logic)
+ Data Path Delay: 0.463ns (logic 0.109ns, net 0.354ns, 23% logic)
Logic Levels: 1 ( EMB=1 )
Point Type Incr Path Info
@@ -580,19 +652,19 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_s
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_652.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_549.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_652.q[1] clk2q 0.109 r 2.047
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.addra[5] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[32]) net (fanout = 2) 0.370 r 2.417 ../../../../hg_mp/fe/prebuffer.v(327)
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1 path2reg (EMB) 0.000 2.417
- Arrival time 2.417 (1 lvl)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_549.q[0] clk2q 0.109 r 2.047
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dia[3] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[19]) net (fanout = 2) 0.354 r 2.401 ../../../../hg_mp/fe/prebuffer.v(329)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1 path2reg (EMB) 0.000 2.401
+ Arrival time 2.401 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell hold 0.200 2.330
@@ -600,13 +672,13 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_s
clock recovergence pessimism -0.147 2.183
Required time 2.183
---------------------------------------------------------------------------------------------------------
- Slack 0.234ns
+ Slack 0.218ns
---------------------------------------------------------------------------------------------------------
Slack (hold check): 0.311 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_648.clk (rising edge triggered by clock a_pclk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.addra[12] (rising edge triggered by clock a_pclk)
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_512.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dia[6] (rising edge triggered by clock a_pclk)
Clock group: a_lvds_clk_p
Process: Fast
Data Path Delay: 0.556ns (logic 0.109ns, net 0.447ns, 19% logic)
@@ -618,19 +690,19 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_s
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_648.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_512.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_648.q[1] clk2q 0.109 r 2.047
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.addra[12] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[39]) net (fanout = 2) 0.447 r 2.494 ../../../../hg_mp/fe/prebuffer.v(327)
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1 path2reg (EMB) 0.000 2.494
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_512.q[0] clk2q 0.109 r 2.047
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dia[6] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[22]) net (fanout = 2) 0.447 r 2.494 ../../../../hg_mp/fe/prebuffer.v(329)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1 path2reg (EMB) 0.000 2.494
Arrival time 2.494 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell hold 0.200 2.330
@@ -642,79 +714,119 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_s
---------------------------------------------------------------------------------------------------------
-Paths for end point u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_333 (1 paths)
+Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1 (8 paths)
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.183 ns
- Start Point: u_bus_top/u_local_bus_slve_cis/reg29_syn_227.clk (rising edge triggered by clock clk_adc)
- End Point: u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_333.mi[0] (rising edge triggered by clock a_pclk)
+ Slack (hold check): 0.114 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add8_syn_69.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dia[1] (rising edge triggered by clock a_pclk)
Clock group: a_lvds_clk_p
Process: Fast
- Data Path Delay: 0.436ns (logic 0.204ns, net 0.232ns, 46% logic)
- Logic Levels: 0
+ Data Path Delay: 0.359ns (logic 0.109ns, net 0.250ns, 30% logic)
+ Logic Levels: 1 ( EMB=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
- u_pll/pll_inst.clkc[4] 0.000 0.000
- u_bus_top/u_local_bus_slve_cis/reg29_syn_227.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add8_syn_69.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- u_bus_top/u_local_bus_slve_cis/reg29_syn_227.q[0] clk2q 0.109 r 2.047
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_333.mi[0] (u_pixel_cdc/u_clk_cis_frame_num/signal_from[4]) net (fanout = 3) 0.232 r 2.279 ../../../../hg_mp/cdc/cdc_sync.v(9)
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_333 path2reg0 0.095 2.374
- Arrival time 2.374 (0 lvl)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add8_syn_69.q[0] clk2q 0.109 r 2.047
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dia[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[17]) net (fanout = 2) 0.250 r 2.297 ../../../../hg_mp/fe/prebuffer.v(329)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1 path2reg (EMB) 0.000 2.297
+ Arrival time 2.297 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_333.clk (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
- cell hold 0.061 2.191
- clock uncertainty 0.000 2.191
- clock recovergence pessimism 0.000 2.191
- Required time 2.191
+ cell hold 0.200 2.330
+ clock uncertainty 0.000 2.330
+ clock recovergence pessimism -0.147 2.183
+ Required time 2.183
---------------------------------------------------------------------------------------------------------
- Slack 0.183ns
+ Slack 0.114ns
---------------------------------------------------------------------------------------------------------
-Paths for end point exdev_ctl_a/reg6_syn_89 (1 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.183 ns
- Start Point: u_bus_top/u_local_bus_slve_cis/reg40_syn_204.clk (rising edge triggered by clock clk_adc)
- End Point: exdev_ctl_a/reg6_syn_89.mi[0] (rising edge triggered by clock a_pclk)
+ Slack (hold check): 0.196 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_549.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dia[3] (rising edge triggered by clock a_pclk)
Clock group: a_lvds_clk_p
Process: Fast
- Data Path Delay: 0.436ns (logic 0.204ns, net 0.232ns, 46% logic)
- Logic Levels: 0
+ Data Path Delay: 0.441ns (logic 0.109ns, net 0.332ns, 24% logic)
+ Logic Levels: 1 ( EMB=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
- u_pll/pll_inst.clkc[4] 0.000 0.000
- u_bus_top/u_local_bus_slve_cis/reg40_syn_204.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_549.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- u_bus_top/u_local_bus_slve_cis/reg40_syn_204.q[0] clk2q 0.109 r 2.047
- exdev_ctl_a/reg6_syn_89.mi[0] (u_bus_top/u_local_bus_slve_cis/reg1[18]) net (fanout = 3) 0.232 r 2.279 ../../../../hg_mp/local_bus/local_bus_slve_cis.v(55)
- exdev_ctl_a/reg6_syn_89 path2reg0 0.095 2.374
- Arrival time 2.374 (0 lvl)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_549.q[0] clk2q 0.109 r 2.047
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dia[3] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[19]) net (fanout = 2) 0.332 r 2.379 ../../../../hg_mp/fe/prebuffer.v(329)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1 path2reg (EMB) 0.000 2.379
+ Arrival time 2.379 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- exdev_ctl_a/reg6_syn_89.clk (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
- cell hold 0.061 2.191
- clock uncertainty 0.000 2.191
- clock recovergence pessimism 0.000 2.191
- Required time 2.191
+ cell hold 0.200 2.330
+ clock uncertainty 0.000 2.330
+ clock recovergence pessimism -0.147 2.183
+ Required time 2.183
---------------------------------------------------------------------------------------------------------
- Slack 0.183ns
+ Slack 0.196ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check): 0.234 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_548.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dia[0] (rising edge triggered by clock a_pclk)
+ Clock group: a_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.479ns (logic 0.109ns, net 0.370ns, 22% logic)
+ Logic Levels: 1 ( EMB=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_548.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_548.q[0] clk2q 0.109 r 2.047
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dia[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[16]) net (fanout = 2) 0.370 r 2.417 ../../../../hg_mp/fe/prebuffer.v(329)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1 path2reg (EMB) 0.000 2.417
+ Arrival time 2.417 (1 lvl)
+
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.200 2.330
+ clock uncertainty 0.000 2.330
+ clock recovergence pessimism -0.147 2.183
+ Required time 2.183
+---------------------------------------------------------------------------------------------------------
+ Slack 0.234ns
---------------------------------------------------------------------------------------------------------
@@ -723,336 +835,336 @@ Paths for end point exdev_ctl_a/reg6_syn_89 (1 paths)
Timing constraint: clock: a_sclk
Clock = a_sclk, period 5.952ns, rising at 0ns, falling at 2.976ns
-282 endpoints analyzed totally, and 722 paths analyzed
+282 endpoints analyzed totally, and 706 paths analyzed
0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 2.239ns
+Minimum period is 2.172ns
---------------------------------------------------------------------------------------------------------
-Paths for end point ua_lvds_rx/reg14_syn_64 (7 paths)
+Paths for end point ua_lvds_rx/rx_clk_sync_reg_syn_5 (7 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 3.713 ns
- Start Point: ua_lvds_rx/reg7_syn_33.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/reg14_syn_64.d[0] (rising edge triggered by clock a_sclk)
+ Slack (setup check): 3.780 ns
+ Start Point: ua_lvds_rx/reg7_syn_44.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 2.087ns (logic 0.891ns, net 1.196ns, 42% logic)
- Logic Levels: 2 ( LUT3=1 LUT5=1 )
+ Data Path Delay: 2.020ns (logic 0.941ns, net 1.079ns, 46% logic)
+ Logic Levels: 2 ( LUT5=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg7_syn_33.clk (ua_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.276
+ ua_lvds_rx/reg7_syn_44.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg7_syn_33.q[0] clk2q 0.146 r 2.422
- ua_lvds_rx/reg14_syn_62.b[0] (ua_lvds_rx/rx_clk_sft[1]) net (fanout = 2) 0.602 r 3.024 encrypted_text(0)
- ua_lvds_rx/reg14_syn_62.f[0] cell (LUT5) 0.431 r 3.455
- ua_lvds_rx/reg14_syn_64.d[0] (ua_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.594 r 4.049 encrypted_text(0)
- ua_lvds_rx/reg14_syn_64 path2reg0 (LUT3) 0.314 4.363
- Arrival time 4.363 (2 lvl)
+ ua_lvds_rx/reg7_syn_44.q[1] clk2q 0.146 r 2.556
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.a[0] (ua_lvds_rx/rx_clk_sft[0]) net (fanout = 2) 0.623 r 3.179 encrypted_text(0)
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.424 r 3.603
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ua_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.456 r 4.059 encrypted_text(0)
+ ua_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.430
+ Arrival time 4.430 (2 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg14_syn_64.clk (ua_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 7.997
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 8.118
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 7.881
- clock uncertainty -0.000 7.881
- clock recovergence pessimism 0.195 8.076
- Required time 8.076
+ cell setup -0.116 8.002
+ clock uncertainty -0.000 8.002
+ clock recovergence pessimism 0.208 8.210
+ Required time 8.210
---------------------------------------------------------------------------------------------------------
- Slack 3.713ns
+ Slack 3.780ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 3.811 ns
- Start Point: ua_lvds_rx/reg7_syn_28.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/reg14_syn_64.d[0] (rising edge triggered by clock a_sclk)
+ Slack (setup check): 3.815 ns
+ Start Point: ua_lvds_rx/reg7_syn_47.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 2.004ns (logic 0.808ns, net 1.196ns, 40% logic)
- Logic Levels: 2 ( LUT3=1 LUT5=1 )
+ Data Path Delay: 2.000ns (logic 0.779ns, net 1.221ns, 38% logic)
+ Logic Levels: 2 ( LUT5=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg7_syn_28.clk (ua_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.276
+ ua_lvds_rx/reg7_syn_47.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg7_syn_28.q[1] clk2q 0.146 r 2.422
- ua_lvds_rx/reg14_syn_62.c[0] (ua_lvds_rx/rx_clk_sft[2]) net (fanout = 2) 0.602 r 3.024 encrypted_text(0)
- ua_lvds_rx/reg14_syn_62.f[0] cell (LUT5) 0.348 r 3.372
- ua_lvds_rx/reg14_syn_64.d[0] (ua_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.594 r 3.966 encrypted_text(0)
- ua_lvds_rx/reg14_syn_64 path2reg0 (LUT3) 0.314 4.280
- Arrival time 4.280 (2 lvl)
+ ua_lvds_rx/reg7_syn_47.q[0] clk2q 0.146 r 2.556
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.d[0] (ua_lvds_rx/rx_clk_sft[3]) net (fanout = 2) 0.765 r 3.321 encrypted_text(0)
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.262 r 3.583
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ua_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.456 r 4.039 encrypted_text(0)
+ ua_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.410
+ Arrival time 4.410 (2 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg14_syn_64.clk (ua_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 7.997
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 8.118
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 7.881
- clock uncertainty -0.000 7.881
- clock recovergence pessimism 0.210 8.091
- Required time 8.091
+ cell setup -0.116 8.002
+ clock uncertainty -0.000 8.002
+ clock recovergence pessimism 0.223 8.225
+ Required time 8.225
---------------------------------------------------------------------------------------------------------
- Slack 3.811ns
+ Slack 3.815ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 3.988 ns
- Start Point: ua_lvds_rx/reg7_syn_25.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/reg14_syn_64.d[0] (rising edge triggered by clock a_sclk)
+ Slack (setup check): 3.849 ns
+ Start Point: ua_lvds_rx/reg7_syn_38.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 1.812ns (logic 0.742ns, net 1.070ns, 40% logic)
- Logic Levels: 2 ( LUT3=1 LUT5=1 )
+ Data Path Delay: 1.923ns (logic 0.865ns, net 1.058ns, 44% logic)
+ Logic Levels: 2 ( LUT5=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg7_syn_25.clk (ua_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.276
+ ua_lvds_rx/reg7_syn_38.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg7_syn_25.q[0] clk2q 0.146 r 2.422
- ua_lvds_rx/reg14_syn_62.e[0] (ua_lvds_rx/rx_clk_sft[4]) net (fanout = 2) 0.476 r 2.898 encrypted_text(0)
- ua_lvds_rx/reg14_syn_62.f[0] cell (LUT5) 0.282 r 3.180
- ua_lvds_rx/reg14_syn_64.d[0] (ua_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.594 r 3.774 encrypted_text(0)
- ua_lvds_rx/reg14_syn_64 path2reg0 (LUT3) 0.314 4.088
- Arrival time 4.088 (2 lvl)
+ ua_lvds_rx/reg7_syn_38.q[1] clk2q 0.146 r 2.556
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.c[0] (ua_lvds_rx/rx_clk_sft[2]) net (fanout = 2) 0.602 r 3.158 encrypted_text(0)
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.348 r 3.506
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ua_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.456 r 3.962 encrypted_text(0)
+ ua_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.333
+ Arrival time 4.333 (2 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg14_syn_64.clk (ua_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 7.997
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 8.118
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 7.881
- clock uncertainty -0.000 7.881
- clock recovergence pessimism 0.195 8.076
- Required time 8.076
+ cell setup -0.116 8.002
+ clock uncertainty -0.000 8.002
+ clock recovergence pessimism 0.180 8.182
+ Required time 8.182
---------------------------------------------------------------------------------------------------------
- Slack 3.988ns
+ Slack 3.849ns
---------------------------------------------------------------------------------------------------------
-Paths for end point ua_lvds_rx/reg8_syn_155 (9 paths)
+Paths for end point ua_lvds_rx/reg8_syn_145 (9 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.003 ns
- Start Point: ua_lvds_rx/reg8_syn_161.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/reg8_syn_155.c[1] (rising edge triggered by clock a_sclk)
+ Slack (setup check): 4.058 ns
+ Start Point: ua_lvds_rx/sync0_reg_syn_4.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/reg8_syn_145.d[1] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 1.797ns (logic 0.701ns, net 1.096ns, 39% logic)
+ Data Path Delay: 1.714ns (logic 0.655ns, net 1.059ns, 38% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg8_syn_161.clk (ua_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.276
+ ua_lvds_rx/sync0_reg_syn_4.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg8_syn_161.q[0] clk2q 0.146 r 2.422
- ua_lvds_rx/reg8_syn_155.c[1] (ua_lvds_rx/rx_data[37]) net (fanout = 4) 1.096 r 3.518 encrypted_text(0)
- ua_lvds_rx/reg8_syn_155 path2reg0 0.555 4.073
- Arrival time 4.073 (1 lvl)
+ ua_lvds_rx/sync0_reg_syn_4.q[1] clk2q 0.146 r 2.556
+ ua_lvds_rx/reg8_syn_145.d[1] (ua_lvds_rx/sync0) net (fanout = 43) 1.059 r 3.615 encrypted_text(0)
+ ua_lvds_rx/reg8_syn_145 path2reg0 0.509 4.124
+ Arrival time 4.124 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg8_syn_155.clk (ua_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 7.997
+ ua_lvds_rx/reg8_syn_145.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 8.118
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 7.881
- clock uncertainty -0.000 7.881
- clock recovergence pessimism 0.195 8.076
- Required time 8.076
+ cell setup -0.116 8.002
+ clock uncertainty -0.000 8.002
+ clock recovergence pessimism 0.180 8.182
+ Required time 8.182
---------------------------------------------------------------------------------------------------------
- Slack 4.003ns
+ Slack 4.058ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.003 ns
- Start Point: ua_lvds_rx/reg8_syn_161.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/reg8_syn_155.c[0] (rising edge triggered by clock a_sclk)
+ Slack (setup check): 4.058 ns
+ Start Point: ua_lvds_rx/sync0_reg_syn_4.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/reg8_syn_145.d[0] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 1.797ns (logic 0.701ns, net 1.096ns, 39% logic)
+ Data Path Delay: 1.714ns (logic 0.655ns, net 1.059ns, 38% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg8_syn_161.clk (ua_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.276
+ ua_lvds_rx/sync0_reg_syn_4.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg8_syn_161.q[0] clk2q 0.146 r 2.422
- ua_lvds_rx/reg8_syn_155.c[0] (ua_lvds_rx/rx_data[37]) net (fanout = 4) 1.096 r 3.518 encrypted_text(0)
- ua_lvds_rx/reg8_syn_155 path2reg0 0.555 4.073
- Arrival time 4.073 (1 lvl)
+ ua_lvds_rx/sync0_reg_syn_4.q[1] clk2q 0.146 r 2.556
+ ua_lvds_rx/reg8_syn_145.d[0] (ua_lvds_rx/sync0) net (fanout = 43) 1.059 r 3.615 encrypted_text(0)
+ ua_lvds_rx/reg8_syn_145 path2reg0 0.509 4.124
+ Arrival time 4.124 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg8_syn_155.clk (ua_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 7.997
+ ua_lvds_rx/reg8_syn_145.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 8.118
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 7.881
- clock uncertainty -0.000 7.881
- clock recovergence pessimism 0.195 8.076
- Required time 8.076
+ cell setup -0.116 8.002
+ clock uncertainty -0.000 8.002
+ clock recovergence pessimism 0.180 8.182
+ Required time 8.182
---------------------------------------------------------------------------------------------------------
- Slack 4.003ns
+ Slack 4.058ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.125 ns
- Start Point: ua_lvds_rx/reg8_syn_166.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/reg8_syn_155.d[1] (rising edge triggered by clock a_sclk)
+ Slack (setup check): 4.198 ns
+ Start Point: ua_lvds_rx/reg8_syn_145.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/reg8_syn_145.a[1] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 1.647ns (logic 0.655ns, net 0.992ns, 39% logic)
+ Data Path Delay: 1.638ns (logic 0.878ns, net 0.760ns, 53% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg8_syn_166.clk (ua_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.276
+ ua_lvds_rx/reg8_syn_145.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg8_syn_166.q[0] clk2q 0.146 r 2.422
- ua_lvds_rx/reg8_syn_155.d[1] (ua_lvds_rx/sync0) net (fanout = 45) 0.992 r 3.414 encrypted_text(0)
- ua_lvds_rx/reg8_syn_155 path2reg0 0.509 3.923
- Arrival time 3.923 (1 lvl)
+ ua_lvds_rx/reg8_syn_145.q[0] clk2q 0.146 r 2.556
+ ua_lvds_rx/reg8_syn_145.a[1] (ua_lvds_rx/para_data[2]) net (fanout = 3) 0.760 r 3.316 encrypted_text(0)
+ ua_lvds_rx/reg8_syn_145 path2reg0 0.732 4.048
+ Arrival time 4.048 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg8_syn_155.clk (ua_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 7.997
+ ua_lvds_rx/reg8_syn_145.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 8.118
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 7.881
- clock uncertainty -0.000 7.881
- clock recovergence pessimism 0.167 8.048
- Required time 8.048
+ cell setup -0.116 8.002
+ clock uncertainty -0.000 8.002
+ clock recovergence pessimism 0.244 8.246
+ Required time 8.246
---------------------------------------------------------------------------------------------------------
- Slack 4.125ns
+ Slack 4.198ns
---------------------------------------------------------------------------------------------------------
-Paths for end point ua_lvds_rx/reg3_syn_198 (5 paths)
+Paths for end point ua_lvds_rx/reg8_syn_157 (9 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.009 ns
- Start Point: ua_lvds_rx/reg8_syn_161.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/reg3_syn_198.b[0] (rising edge triggered by clock a_sclk)
+ Slack (setup check): 4.092 ns
+ Start Point: ua_lvds_rx/sync0_reg_syn_4.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/reg8_syn_157.d[1] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 1.791ns (logic 0.695ns, net 1.096ns, 38% logic)
- Logic Levels: 1 ( LUT5=1 )
+ Data Path Delay: 1.680ns (logic 0.655ns, net 1.025ns, 38% logic)
+ Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg8_syn_161.clk (ua_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.276
+ ua_lvds_rx/sync0_reg_syn_4.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg8_syn_161.q[0] clk2q 0.146 r 2.422
- ua_lvds_rx/reg3_syn_198.b[0] (ua_lvds_rx/rx_data[37]) net (fanout = 4) 1.096 r 3.518 encrypted_text(0)
- ua_lvds_rx/reg3_syn_198 path2reg0 (LUT5) 0.549 4.067
- Arrival time 4.067 (1 lvl)
+ ua_lvds_rx/sync0_reg_syn_4.q[1] clk2q 0.146 r 2.556
+ ua_lvds_rx/reg8_syn_157.d[1] (ua_lvds_rx/sync0) net (fanout = 43) 1.025 r 3.581 encrypted_text(0)
+ ua_lvds_rx/reg8_syn_157 path2reg0 0.509 4.090
+ Arrival time 4.090 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg3_syn_198.clk (ua_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 7.997
+ ua_lvds_rx/reg8_syn_157.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 8.118
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 7.881
- clock uncertainty -0.000 7.881
- clock recovergence pessimism 0.195 8.076
- Required time 8.076
+ cell setup -0.116 8.002
+ clock uncertainty -0.000 8.002
+ clock recovergence pessimism 0.180 8.182
+ Required time 8.182
---------------------------------------------------------------------------------------------------------
- Slack 4.009ns
+ Slack 4.092ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.454 ns
- Start Point: ua_lvds_rx/reg8_syn_198.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/reg3_syn_198.c[0] (rising edge triggered by clock a_sclk)
+ Slack (setup check): 4.092 ns
+ Start Point: ua_lvds_rx/sync0_reg_syn_4.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/reg8_syn_157.d[0] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 1.361ns (logic 0.612ns, net 0.749ns, 44% logic)
- Logic Levels: 1 ( LUT5=1 )
+ Data Path Delay: 1.680ns (logic 0.655ns, net 1.025ns, 38% logic)
+ Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg8_syn_198.clk (ua_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.276
+ ua_lvds_rx/sync0_reg_syn_4.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg8_syn_198.q[1] clk2q 0.146 r 2.422
- ua_lvds_rx/reg3_syn_198.c[0] (ua_lvds_rx/rx_data[38]) net (fanout = 2) 0.749 r 3.171 encrypted_text(0)
- ua_lvds_rx/reg3_syn_198 path2reg0 (LUT5) 0.466 3.637
- Arrival time 3.637 (1 lvl)
+ ua_lvds_rx/sync0_reg_syn_4.q[1] clk2q 0.146 r 2.556
+ ua_lvds_rx/reg8_syn_157.d[0] (ua_lvds_rx/sync0) net (fanout = 43) 1.025 r 3.581 encrypted_text(0)
+ ua_lvds_rx/reg8_syn_157 path2reg0 0.509 4.090
+ Arrival time 4.090 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg3_syn_198.clk (ua_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 7.997
+ ua_lvds_rx/reg8_syn_157.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 8.118
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 7.881
- clock uncertainty -0.000 7.881
- clock recovergence pessimism 0.210 8.091
- Required time 8.091
+ cell setup -0.116 8.002
+ clock uncertainty -0.000 8.002
+ clock recovergence pessimism 0.180 8.182
+ Required time 8.182
---------------------------------------------------------------------------------------------------------
- Slack 4.454ns
+ Slack 4.092ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.486 ns
- Start Point: ua_lvds_rx/reg14_syn_62.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/reg3_syn_198.e[0] (rising edge triggered by clock a_sclk)
+ Slack (setup check): 4.387 ns
+ Start Point: ua_lvds_rx/sync0_reg_syn_4.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/reg8_syn_157.mi[0] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 1.286ns (logic 0.546ns, net 0.740ns, 42% logic)
- Logic Levels: 1 ( LUT5=1 )
+ Data Path Delay: 1.385ns (logic 0.553ns, net 0.832ns, 39% logic)
+ Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg14_syn_62.clk (ua_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.276
+ ua_lvds_rx/sync0_reg_syn_4.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg14_syn_62.q[0] clk2q 0.146 r 2.422
- ua_lvds_rx/reg3_syn_198.e[0] (ua_lvds_rx/sync1) net (fanout = 32) 0.740 r 3.162 encrypted_text(0)
- ua_lvds_rx/reg3_syn_198 path2reg0 (LUT5) 0.400 3.562
- Arrival time 3.562 (1 lvl)
+ ua_lvds_rx/sync0_reg_syn_4.q[0] clk2q 0.146 r 2.556
+ ua_lvds_rx/reg8_syn_157.mi[0] (ua_lvds_rx/sync1) net (fanout = 32) 0.832 r 3.388 encrypted_text(0)
+ ua_lvds_rx/reg8_syn_157 path2reg0 0.407 3.795
+ Arrival time 3.795 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg3_syn_198.clk (ua_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 7.997
+ ua_lvds_rx/reg8_syn_157.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 8.118
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 7.881
- clock uncertainty -0.000 7.881
- clock recovergence pessimism 0.167 8.048
- Required time 8.048
+ cell setup -0.116 8.002
+ clock uncertainty -0.000 8.002
+ clock recovergence pessimism 0.180 8.182
+ Required time 8.182
---------------------------------------------------------------------------------------------------------
- Slack 4.486ns
+ Slack 4.387ns
---------------------------------------------------------------------------------------------------------
Hold checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point ua_lvds_rx/ramread0_syn_32 (2 paths)
+Paths for end point ua_lvds_rx/ramread0_syn_102 (2 paths)
---------------------------------------------------------------------------------------------------------
Slack (hold check): 0.092 ns
- Start Point: ua_lvds_rx/reg3_syn_190.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/ramread0_syn_32.c[1] (rising edge triggered by clock a_sclk)
+ Start Point: ua_lvds_rx/reg3_syn_184.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/ramread0_syn_102.b[1] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Fast
Data Path Delay: 0.220ns (logic 0.109ns, net 0.111ns, 49% logic)
@@ -1062,136 +1174,66 @@ Paths for end point ua_lvds_rx/ramread0_syn_32 (2 paths)
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg3_syn_190.clk (ua_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 1.938
+ ua_lvds_rx/reg3_syn_184.clk (ua_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg3_syn_190.q[1] clk2q 0.109 r 2.047
- ua_lvds_rx/ramread0_syn_32.c[1] (ua_lvds_rx/para_data[6]) net (fanout = 2) 0.111 r 2.158 encrypted_text(0)
- ua_lvds_rx/ramread0_syn_32 path2reg 0.000 2.158
- Arrival time 2.158 (1 lvl)
+ ua_lvds_rx/reg3_syn_184.q[0] clk2q 0.109 r 2.138
+ ua_lvds_rx/ramread0_syn_102.b[1] (ua_lvds_rx/para_data[25]) net (fanout = 2) 0.111 r 2.249 encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_102 path2reg 0.000 2.249
+ Arrival time 2.249 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/ramread0_syn_32.clk (ua_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.130
+ ua_lvds_rx/ramread0_syn_102.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.243
- clock uncertainty 0.000 2.243
- clock recovergence pessimism -0.177 2.066
- Required time 2.066
+ cell hold 0.113 2.343
+ clock uncertainty 0.000 2.343
+ clock recovergence pessimism -0.186 2.157
+ Required time 2.157
---------------------------------------------------------------------------------------------------------
Slack 0.092ns
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.369 ns
+ Slack (hold check): 0.409 ns
Start Point: ua_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/ramread0_syn_32.c[0] (rising edge triggered by clock a_sclk)
- Clock group: a_lvds_clk_p
- Process: Fast
- Data Path Delay: 0.527ns (logic 0.109ns, net 0.418ns, 20% logic)
- Logic Levels: 1
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg16_syn_31.clk (ua_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 1.938
----------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg16_syn_31.q[0] clk2q 0.109 r 2.047
- ua_lvds_rx/ramread0_syn_32.c[0] (ua_lvds_rx/wcnt[2]) net (fanout = 9) 0.418 r 2.465 encrypted_text(0)
- ua_lvds_rx/ramread0_syn_32 path2reg 0.000 2.465
- Arrival time 2.465 (1 lvl)
-
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/ramread0_syn_32.clk (ua_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.130
----------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.243
- clock uncertainty 0.000 2.243
- clock recovergence pessimism -0.147 2.096
- Required time 2.096
----------------------------------------------------------------------------------------------------------
- Slack 0.369ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point ua_lvds_rx/ramread0_syn_102 (2 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.114 ns
- Start Point: ua_lvds_rx/reg16_syn_33.clk (rising edge triggered by clock a_sclk)
End Point: ua_lvds_rx/ramread0_syn_102.b[0] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Fast
- Data Path Delay: 0.242ns (logic 0.109ns, net 0.133ns, 45% logic)
+ Data Path Delay: 0.551ns (logic 0.109ns, net 0.442ns, 19% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg16_syn_33.clk (ua_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 1.938
+ ua_lvds_rx/reg16_syn_31.clk (ua_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg16_syn_33.q[0] clk2q 0.109 r 2.047
- ua_lvds_rx/ramread0_syn_102.b[0] (ua_lvds_rx/wcnt[1]) net (fanout = 10) 0.133 r 2.180 encrypted_text(0)
- ua_lvds_rx/ramread0_syn_102 path2reg 0.000 2.180
- Arrival time 2.180 (1 lvl)
+ ua_lvds_rx/reg16_syn_31.q[1] clk2q 0.109 r 2.138
+ ua_lvds_rx/ramread0_syn_102.b[0] (ua_lvds_rx/wcnt[1]) net (fanout = 10) 0.442 r 2.580 encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_102 path2reg 0.000 2.580
+ Arrival time 2.580 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/ramread0_syn_102.clk (ua_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.130
+ ua_lvds_rx/ramread0_syn_102.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.243
- clock uncertainty 0.000 2.243
- clock recovergence pessimism -0.177 2.066
- Required time 2.066
+ cell hold 0.113 2.343
+ clock uncertainty 0.000 2.343
+ clock recovergence pessimism -0.172 2.171
+ Required time 2.171
---------------------------------------------------------------------------------------------------------
- Slack 0.114ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check): 0.289 ns
- Start Point: ua_lvds_rx/reg8_syn_147.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/ramread0_syn_102.b[1] (rising edge triggered by clock a_sclk)
- Clock group: a_lvds_clk_p
- Process: Fast
- Data Path Delay: 0.431ns (logic 0.109ns, net 0.322ns, 25% logic)
- Logic Levels: 1
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg8_syn_147.clk (ua_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 1.938
----------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg8_syn_147.q[0] clk2q 0.109 r 2.047
- ua_lvds_rx/ramread0_syn_102.b[1] (ua_lvds_rx/para_data[25]) net (fanout = 3) 0.322 r 2.369 encrypted_text(0)
- ua_lvds_rx/ramread0_syn_102 path2reg 0.000 2.369
- Arrival time 2.369 (1 lvl)
-
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/ramread0_syn_102.clk (ua_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.130
----------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.243
- clock uncertainty 0.000 2.243
- clock recovergence pessimism -0.163 2.080
- Required time 2.080
----------------------------------------------------------------------------------------------------------
- Slack 0.289ns
+ Slack 0.409ns
---------------------------------------------------------------------------------------------------------
Paths for end point ua_lvds_rx/ramread0_syn_116 (2 paths)
---------------------------------------------------------------------------------------------------------
Slack (hold check): 0.167 ns
- Start Point: ua_lvds_rx/reg3_syn_198.clk (rising edge triggered by clock a_sclk)
+ Start Point: ua_lvds_rx/reg14_syn_62.clk (rising edge triggered by clock a_sclk)
End Point: ua_lvds_rx/ramread0_syn_116.c[1] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Fast
@@ -1202,59 +1244,129 @@ Paths for end point ua_lvds_rx/ramread0_syn_116 (2 paths)
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg3_syn_198.clk (ua_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 1.938
+ ua_lvds_rx/reg14_syn_62.clk (ua_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg3_syn_198.q[1] clk2q 0.109 r 2.047
- ua_lvds_rx/ramread0_syn_116.c[1] (ua_lvds_rx/para_data[34]) net (fanout = 2) 0.216 r 2.263 encrypted_text(0)
- ua_lvds_rx/ramread0_syn_116 path2reg 0.000 2.263
- Arrival time 2.263 (1 lvl)
+ ua_lvds_rx/reg14_syn_62.q[0] clk2q 0.109 r 2.138
+ ua_lvds_rx/ramread0_syn_116.c[1] (ua_lvds_rx/para_data[34]) net (fanout = 2) 0.216 r 2.354 encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_116 path2reg 0.000 2.354
+ Arrival time 2.354 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/ramread0_syn_116.clk (ua_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.130
+ ua_lvds_rx/ramread0_syn_116.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.243
- clock uncertainty 0.000 2.243
- clock recovergence pessimism -0.147 2.096
- Required time 2.096
+ cell hold 0.113 2.343
+ clock uncertainty 0.000 2.343
+ clock recovergence pessimism -0.156 2.187
+ Required time 2.187
---------------------------------------------------------------------------------------------------------
Slack 0.167ns
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.415 ns
+ Slack (hold check): 0.345 ns
Start Point: ua_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock a_sclk)
End Point: ua_lvds_rx/ramread0_syn_116.c[0] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Fast
- Data Path Delay: 0.573ns (logic 0.109ns, net 0.464ns, 19% logic)
+ Data Path Delay: 0.503ns (logic 0.109ns, net 0.394ns, 21% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg16_syn_31.clk (ua_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 1.938
+ ua_lvds_rx/reg16_syn_31.clk (ua_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg16_syn_31.q[0] clk2q 0.109 r 2.047
- ua_lvds_rx/ramread0_syn_116.c[0] (ua_lvds_rx/wcnt[2]) net (fanout = 9) 0.464 r 2.511 encrypted_text(0)
- ua_lvds_rx/ramread0_syn_116 path2reg 0.000 2.511
- Arrival time 2.511 (1 lvl)
+ ua_lvds_rx/reg16_syn_31.q[0] clk2q 0.109 r 2.138
+ ua_lvds_rx/ramread0_syn_116.c[0] (ua_lvds_rx/wcnt[2]) net (fanout = 9) 0.394 r 2.532 encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_116 path2reg 0.000 2.532
+ Arrival time 2.532 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/ramread0_syn_116.clk (ua_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.130
+ ua_lvds_rx/ramread0_syn_116.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.243
- clock uncertainty 0.000 2.243
- clock recovergence pessimism -0.147 2.096
- Required time 2.096
+ cell hold 0.113 2.343
+ clock uncertainty 0.000 2.343
+ clock recovergence pessimism -0.156 2.187
+ Required time 2.187
---------------------------------------------------------------------------------------------------------
- Slack 0.415ns
+ Slack 0.345ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point ua_lvds_rx/ramread0_syn_116 (2 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.167 ns
+ Start Point: ua_lvds_rx/reg3_syn_195.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/ramread0_syn_116.a[1] (rising edge triggered by clock a_sclk)
+ Clock group: a_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.325ns (logic 0.109ns, net 0.216ns, 33% logic)
+ Logic Levels: 1
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
+ ua_lvds_rx/reg3_syn_195.clk (ua_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.029
+---------------------------------------------------------------------------------------------------------
+ ua_lvds_rx/reg3_syn_195.q[1] clk2q 0.109 r 2.138
+ ua_lvds_rx/ramread0_syn_116.a[1] (ua_lvds_rx/para_data[32]) net (fanout = 2) 0.216 r 2.354 encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_116 path2reg 0.000 2.354
+ Arrival time 2.354 (1 lvl)
+
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
+ ua_lvds_rx/ramread0_syn_116.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.230
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.113 2.343
+ clock uncertainty 0.000 2.343
+ clock recovergence pessimism -0.156 2.187
+ Required time 2.187
+---------------------------------------------------------------------------------------------------------
+ Slack 0.167ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check): 0.586 ns
+ Start Point: ua_lvds_rx/reg16_syn_33.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/ramread0_syn_116.a[0] (rising edge triggered by clock a_sclk)
+ Clock group: a_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.744ns (logic 0.109ns, net 0.635ns, 14% logic)
+ Logic Levels: 1
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
+ ua_lvds_rx/reg16_syn_33.clk (ua_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.029
+---------------------------------------------------------------------------------------------------------
+ ua_lvds_rx/reg16_syn_33.q[0] clk2q 0.109 r 2.138
+ ua_lvds_rx/ramread0_syn_116.a[0] (ua_lvds_rx/wcnt[0]) net (fanout = 11) 0.635 r 2.773 encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_116 path2reg 0.000 2.773
+ Arrival time 2.773 (1 lvl)
+
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
+ ua_lvds_rx/ramread0_syn_116.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.230
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.113 2.343
+ clock uncertainty 0.000 2.343
+ clock recovergence pessimism -0.156 2.187
+ Required time 2.187
+---------------------------------------------------------------------------------------------------------
+ Slack 0.586ns
---------------------------------------------------------------------------------------------------------
@@ -1273,115 +1385,19 @@ Minimum period is 0ns
Timing constraint: clock: b_pclk
Clock = b_pclk, period 20.833ns, rising at 0ns, falling at 10.417ns
-5876 endpoints analyzed totally, and 105758 paths analyzed
+5874 endpoints analyzed totally, and 101266 paths analyzed
0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 10.242ns
+Minimum period is 10.093ns
---------------------------------------------------------------------------------------------------------
-Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23 (171 paths)
+Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 (70 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 10.591 ns
+ Slack (setup check): 10.740 ns
Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.a[1] (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0] (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 10.271ns (logic 6.287ns, net 3.984ns, 61% logic)
- Logic Levels: 6 ( LUT5=4 ADDER=2 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 2.067
----------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[1] clk2q 3.433 r 5.500
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 0.882 r 6.382
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 7.088
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.088
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.f[0] cell (ADDER) 0.144 r 7.232
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7]) net (fanout = 1) 1.048 r 8.280
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[1] cell (LUT5) 0.424 r 8.704
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234) net (fanout = 1) 0.738 r 9.442 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[0] cell (LUT5) 0.424 r 9.866
- sampling_fe_a/reg1_syn_61.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238) net (fanout = 1) 0.755 r 10.621 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/reg1_syn_61.f[0] cell (LUT5) 0.424 r 11.045
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.561 r 11.606 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23 path2reg0 (LUT5) 0.732 12.338
- Arrival time 12.338 (6 lvl)
-
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 20.833 22.878
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 22.762
- clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.167 22.929
- Required time 22.929
----------------------------------------------------------------------------------------------------------
- Slack 10.591ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check): 10.591 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.a[0] (rising edge triggered by clock b_pclk)
- Clock group: b_lvds_clk_p
- Process: Slow
- Data Path Delay: 10.271ns (logic 6.287ns, net 3.984ns, 61% logic)
- Logic Levels: 6 ( LUT5=4 ADDER=2 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 2.067
----------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[1] clk2q 3.433 r 5.500
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 0.882 r 6.382
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 7.088
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.088
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.f[0] cell (ADDER) 0.144 r 7.232
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7]) net (fanout = 1) 1.048 r 8.280
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[1] cell (LUT5) 0.424 r 8.704
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234) net (fanout = 1) 0.738 r 9.442 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[0] cell (LUT5) 0.424 r 9.866
- sampling_fe_a/reg1_syn_61.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238) net (fanout = 1) 0.755 r 10.621 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/reg1_syn_61.f[0] cell (LUT5) 0.424 r 11.045
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.561 r 11.606 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23 path2reg0 (LUT5) 0.732 12.338
- Arrival time 12.338 (6 lvl)
-
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 20.833 22.878
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 22.762
- clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.167 22.929
- Required time 22.929
----------------------------------------------------------------------------------------------------------
- Slack 10.591ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check): 10.598 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.a[1] (rising edge triggered by clock b_pclk)
- Clock group: b_lvds_clk_p
- Process: Slow
- Data Path Delay: 10.264ns (logic 6.281ns, net 3.983ns, 61% logic)
+ Data Path Delay: 10.050ns (logic 6.455ns, net 3.595ns, 64% logic)
Logic Levels: 6 ( LUT5=4 ADDER=2 )
Point Type Incr Path Info
@@ -1394,47 +1410,49 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_
launch clock edge 0.000 2.067
---------------------------------------------------------------------------------------------------------
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[0] clk2q 3.433 r 5.500
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 0.881 r 6.381
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 7.008
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 7.008
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 7.081
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.081
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.f[0] cell (ADDER) 0.144 r 7.225
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7]) net (fanout = 1) 1.048 r 8.273
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[1] cell (LUT5) 0.424 r 8.697
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234) net (fanout = 1) 0.738 r 9.435 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[0] cell (LUT5) 0.424 r 9.859
- sampling_fe_a/reg1_syn_61.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238) net (fanout = 1) 0.755 r 10.614 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/reg1_syn_61.f[0] cell (LUT5) 0.424 r 11.038
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.561 r 11.599 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23 path2reg0 (LUT5) 0.732 12.331
- Arrival time 12.331 (6 lvl)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 0.886 r 6.386
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 7.013
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 7.013
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 7.086
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.086
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 7.159
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 7.159
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 7.232
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 7.232
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.587
+ u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.827 r 8.414
+ u_bus_top/u_local_bus_slve_cis/reg50_syn_201.f[0] cell (LUT5) 0.424 r 8.838
+ u_bus_top/reg3_syn_167.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.615 r 9.453 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_bus_top/reg3_syn_167.f[0] cell (LUT5) 0.424 r 9.877
+ u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net (fanout = 1) 0.603 r 10.480 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.f[0] cell (LUT5) 0.431 r 10.911
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.664 r 11.575 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.542 12.117
+ Arrival time 12.117 (6 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 20.833 22.878
---------------------------------------------------------------------------------------------------------
cell setup -0.116 22.762
clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.167 22.929
- Required time 22.929
+ clock recovergence pessimism 0.095 22.857
+ Required time 22.857
---------------------------------------------------------------------------------------------------------
- Slack 10.598ns
+ Slack 10.740ns
---------------------------------------------------------------------------------------------------------
-Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514 (70 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check): 10.711 ns
+ Slack (setup check): 10.763 ns
Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.a[0] (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0] (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 10.151ns (logic 6.097ns, net 4.054ns, 60% logic)
- Logic Levels: 6 ( LUT5=3 ADDER=2 )
+ Data Path Delay: 10.027ns (logic 6.388ns, net 3.639ns, 63% logic)
+ Logic Levels: 6 ( LUT5=4 ADDER=2 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -1445,44 +1463,96 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 2.067
---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[1] clk2q 3.433 r 5.500
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 0.882 r 6.382
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 7.088
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.088
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.f[0] cell (ADDER) 0.144 r 7.232
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7]) net (fanout = 1) 1.048 r 8.280
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[1] cell (LUT5) 0.424 r 8.704
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234) net (fanout = 1) 0.738 r 9.442 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[0] cell (LUT5) 0.424 r 9.866
- sampling_fe_a/reg1_syn_61.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238) net (fanout = 1) 0.755 r 10.621 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/reg1_syn_61.f[0] cell (LUT5) 0.424 r 11.045
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.631 r 11.676 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514 path2reg0 0.542 12.218
- Arrival time 12.218 (6 lvl)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[3] clk2q 3.433 r 5.500
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[7]) net (fanout = 1) 0.930 r 6.430
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.706 r 7.136
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 7.136
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 7.209
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 7.209
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.564
+ u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.827 r 8.391
+ u_bus_top/u_local_bus_slve_cis/reg50_syn_201.f[0] cell (LUT5) 0.424 r 8.815
+ u_bus_top/reg3_syn_167.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.615 r 9.430 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_bus_top/reg3_syn_167.f[0] cell (LUT5) 0.424 r 9.854
+ u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net (fanout = 1) 0.603 r 10.457 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.f[0] cell (LUT5) 0.431 r 10.888
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.664 r 11.552 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.542 12.094
+ Arrival time 12.094 (6 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 20.833 22.878
---------------------------------------------------------------------------------------------------------
cell setup -0.116 22.762
clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.167 22.929
- Required time 22.929
+ clock recovergence pessimism 0.095 22.857
+ Required time 22.857
---------------------------------------------------------------------------------------------------------
- Slack 10.711ns
+ Slack 10.763ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 10.718 ns
+ Slack (setup check): 10.810 ns
Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.a[0] (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0] (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 10.144ns (logic 6.091ns, net 4.053ns, 60% logic)
- Logic Levels: 6 ( LUT5=3 ADDER=2 )
+ Data Path Delay: 9.980ns (logic 6.236ns, net 3.744ns, 62% logic)
+ Logic Levels: 6 ( LUT5=4 ADDER=2 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 2.067
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[6] clk2q 3.433 r 5.500
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[10]) net (fanout = 1) 1.035 r 6.535
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.627 r 7.162
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 7.162
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.517
+ u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.827 r 8.344
+ u_bus_top/u_local_bus_slve_cis/reg50_syn_201.f[0] cell (LUT5) 0.424 r 8.768
+ u_bus_top/reg3_syn_167.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.615 r 9.383 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_bus_top/reg3_syn_167.f[0] cell (LUT5) 0.424 r 9.807
+ u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net (fanout = 1) 0.603 r 10.410 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.f[0] cell (LUT5) 0.431 r 10.841
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.664 r 11.505 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.542 12.047
+ Arrival time 12.047 (6 lvl)
+
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 20.833 22.878
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.116 22.762
+ clock uncertainty -0.000 22.762
+ clock recovergence pessimism 0.095 22.857
+ Required time 22.857
+---------------------------------------------------------------------------------------------------------
+ Slack 10.810ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 (171 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check): 10.755 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (rising edge triggered by clock b_pclk)
+ Clock group: b_lvds_clk_p
+ Process: Slow
+ Data Path Delay: 10.035ns (logic 6.645ns, net 3.390ns, 66% logic)
+ Logic Levels: 6 ( LUT5=4 ADDER=2 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -1494,45 +1564,49 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/
launch clock edge 0.000 2.067
---------------------------------------------------------------------------------------------------------
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[0] clk2q 3.433 r 5.500
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 0.881 r 6.381
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 7.008
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 7.008
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 7.081
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.081
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.f[0] cell (ADDER) 0.144 r 7.225
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7]) net (fanout = 1) 1.048 r 8.273
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[1] cell (LUT5) 0.424 r 8.697
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234) net (fanout = 1) 0.738 r 9.435 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[0] cell (LUT5) 0.424 r 9.859
- sampling_fe_a/reg1_syn_61.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238) net (fanout = 1) 0.755 r 10.614 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/reg1_syn_61.f[0] cell (LUT5) 0.424 r 11.038
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.631 r 11.669 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514 path2reg0 0.542 12.211
- Arrival time 12.211 (6 lvl)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 0.886 r 6.386
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 7.013
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 7.013
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 7.086
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.086
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 7.159
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 7.159
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 7.232
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 7.232
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.587
+ u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.827 r 8.414
+ u_bus_top/u_local_bus_slve_cis/reg50_syn_201.f[0] cell (LUT5) 0.424 r 8.838
+ u_bus_top/reg3_syn_167.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.615 r 9.453 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_bus_top/reg3_syn_167.f[0] cell (LUT5) 0.424 r 9.877
+ u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net (fanout = 1) 0.603 r 10.480 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.f[0] cell (LUT5) 0.431 r 10.911
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.459 r 11.370 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 12.102
+ Arrival time 12.102 (6 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 20.833 22.878
---------------------------------------------------------------------------------------------------------
cell setup -0.116 22.762
clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.167 22.929
- Required time 22.929
+ clock recovergence pessimism 0.095 22.857
+ Required time 22.857
---------------------------------------------------------------------------------------------------------
- Slack 10.718ns
+ Slack 10.755ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 10.783 ns
+ Slack (setup check): 10.755 ns
Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.a[0] (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[0] (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 10.079ns (logic 6.018ns, net 4.061ns, 59% logic)
- Logic Levels: 6 ( LUT5=3 ADDER=2 )
+ Data Path Delay: 10.035ns (logic 6.645ns, net 3.390ns, 66% logic)
+ Logic Levels: 6 ( LUT5=4 ADDER=2 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -1543,46 +1617,50 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 2.067
---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[2] clk2q 3.433 r 5.500
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[6]) net (fanout = 1) 0.889 r 6.389
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.627 r 7.016
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.016
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.f[0] cell (ADDER) 0.144 r 7.160
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7]) net (fanout = 1) 1.048 r 8.208
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[1] cell (LUT5) 0.424 r 8.632
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234) net (fanout = 1) 0.738 r 9.370 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[0] cell (LUT5) 0.424 r 9.794
- sampling_fe_a/reg1_syn_61.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238) net (fanout = 1) 0.755 r 10.549 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/reg1_syn_61.f[0] cell (LUT5) 0.424 r 10.973
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.631 r 11.604 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514 path2reg0 0.542 12.146
- Arrival time 12.146 (6 lvl)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[0] clk2q 3.433 r 5.500
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 0.886 r 6.386
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 7.013
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 7.013
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 7.086
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.086
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 7.159
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 7.159
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 7.232
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 7.232
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.587
+ u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.827 r 8.414
+ u_bus_top/u_local_bus_slve_cis/reg50_syn_201.f[0] cell (LUT5) 0.424 r 8.838
+ u_bus_top/reg3_syn_167.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.615 r 9.453 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_bus_top/reg3_syn_167.f[0] cell (LUT5) 0.424 r 9.877
+ u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net (fanout = 1) 0.603 r 10.480 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.f[0] cell (LUT5) 0.431 r 10.911
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.459 r 11.370 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 12.102
+ Arrival time 12.102 (6 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 20.833 22.878
---------------------------------------------------------------------------------------------------------
cell setup -0.116 22.762
clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.167 22.929
- Required time 22.929
+ clock recovergence pessimism 0.095 22.857
+ Required time 22.857
---------------------------------------------------------------------------------------------------------
- Slack 10.783ns
+ Slack 10.755ns
---------------------------------------------------------------------------------------------------------
-Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_74 (214 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check): 11.561 ns
- Start Point: exdev_ctl_b/u_gen_sp/reg9_syn_89.clk (rising edge triggered by clock b_pclk)
- End Point: exdev_ctl_b/u_gen_sp/reg0_syn_74.sr (rising edge triggered by clock b_pclk)
+ Slack (setup check): 10.778 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 9.021ns (logic 4.365ns, net 4.656ns, 48% logic)
- Logic Levels: 8 ( LUT5=5 ADDER=2 LUT4=1 )
+ Data Path Delay: 10.012ns (logic 6.578ns, net 3.434ns, 65% logic)
+ Logic Levels: 6 ( LUT5=4 ADDER=2 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -1590,57 +1668,51 @@ Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_74 (214 paths)
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- exdev_ctl_b/u_gen_sp/reg9_syn_89.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 2.276
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 2.067
---------------------------------------------------------------------------------------------------------
- exdev_ctl_b/u_gen_sp/reg9_syn_89.q[1] clk2q 0.146 r 2.422
- exdev_ctl_b/u_gen_sp/sub1_syn_102.a[1] (exdev_ctl_b/u_gen_sp/sp_t_d1[1]) net (fanout = 1) 0.602 r 3.024 ../../../../hg_mp/fe/gen_sp.v(87)
- exdev_ctl_b/u_gen_sp/sub1_syn_102.fco cell (ADDER) 0.881 r 3.905
- exdev_ctl_b/u_gen_sp/sub1_syn_103.fci (exdev_ctl_b/u_gen_sp/sub1_syn_87) net (fanout = 1) 0.000 f 3.905 ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_b/u_gen_sp/sub1_syn_103.fco cell (ADDER) 0.132 r 4.037
- exdev_ctl_b/u_gen_sp/sub1_syn_104.fci (exdev_ctl_b/u_gen_sp/sub1_syn_91) net (fanout = 1) 0.000 f 4.037 ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_b/u_gen_sp/sub1_syn_104.fco cell (ADDER) 0.132 r 4.169
- exdev_ctl_b/u_gen_sp/sub1_syn_105.fci (exdev_ctl_b/u_gen_sp/sub1_syn_95) net (fanout = 1) 0.000 f 4.169 ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_b/u_gen_sp/sub1_syn_105.fx[0] cell (ADDER) 0.387 r 4.556
- u_a_sp_sampling/reg0_syn_27.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12]) net (fanout = 1) 0.591 r 5.147
- u_a_sp_sampling/reg0_syn_27.f[0] cell (LUT4) 0.424 r 5.571
- exdev_ctl_b/u_gen_sp/reg9_syn_103.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_139) net (fanout = 1) 0.594 r 6.165 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_gen_sp/reg9_syn_103.f[0] cell (LUT5) 0.424 r 6.589
- sampling_fe_a/u_ad_sampling/sp_1d_reg_syn_8.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_141) net (fanout = 1) 0.456 r 7.045 ../../../../hg_mp/fe/gen_sp.v(137)
- sampling_fe_a/u_ad_sampling/sp_1d_reg_syn_8.f[0] cell (LUT5) 0.424 r 7.469
- u_bus_top/u_local_bus_slve_cis/reg53_syn_51.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_149) net (fanout = 1) 0.594 r 8.063 ../../../../hg_mp/fe/gen_sp.v(137)
- u_bus_top/u_local_bus_slve_cis/reg53_syn_51.f[0] cell (LUT5) 0.424 r 8.487
- u_bus_top/u_local_bus_slve_cis/reg54_syn_47.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.456 r 8.943
- u_bus_top/u_local_bus_slve_cis/reg54_syn_47.f[0] cell (LUT5) 0.424 r 9.367
- u_bus_top/u_local_bus_slve_cis/reg55_syn_42.a[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2) net (fanout = 1) 0.738 r 10.105
- u_bus_top/u_local_bus_slve_cis/reg55_syn_42.f[1] cell (LUT5) 0.424 r 10.529
- exdev_ctl_b/u_gen_sp/reg0_syn_74.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net (fanout = 8) 0.625 r 11.154 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_gen_sp/reg0_syn_74 path2reg 0.143 11.297
- Arrival time 11.297 (8 lvl)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[3] clk2q 3.433 r 5.500
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[7]) net (fanout = 1) 0.930 r 6.430
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.706 r 7.136
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 7.136
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 7.209
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 7.209
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.564
+ u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.827 r 8.391
+ u_bus_top/u_local_bus_slve_cis/reg50_syn_201.f[0] cell (LUT5) 0.424 r 8.815
+ u_bus_top/reg3_syn_167.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.615 r 9.430 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_bus_top/reg3_syn_167.f[0] cell (LUT5) 0.424 r 9.854
+ u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net (fanout = 1) 0.603 r 10.457 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.f[0] cell (LUT5) 0.431 r 10.888
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.459 r 11.347 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 12.079
+ Arrival time 12.079 (6 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- exdev_ctl_b/u_gen_sp/reg0_syn_74.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 20.833 22.878
---------------------------------------------------------------------------------------------------------
- cell setup -0.187 22.691
- clock uncertainty -0.000 22.691
- clock recovergence pessimism 0.167 22.858
- Required time 22.858
+ cell setup -0.116 22.762
+ clock uncertainty -0.000 22.762
+ clock recovergence pessimism 0.095 22.857
+ Required time 22.857
---------------------------------------------------------------------------------------------------------
- Slack 11.561ns
+ Slack 10.778ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 11.662 ns
- Start Point: exdev_ctl_b/u_gen_sp/reg8_syn_107.clk (rising edge triggered by clock b_pclk)
- End Point: exdev_ctl_b/u_gen_sp/reg0_syn_74.sr (rising edge triggered by clock b_pclk)
+Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_77 (214 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check): 12.253 ns
+ Start Point: exdev_ctl_b/u_gen_sp/reg9_syn_78.clk (rising edge triggered by clock b_pclk)
+ End Point: exdev_ctl_b/u_gen_sp/reg0_syn_77.sr (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 8.920ns (logic 4.101ns, net 4.819ns, 45% logic)
- Logic Levels: 8 ( LUT5=5 ADDER=2 LUT4=1 )
+ Data Path Delay: 8.329ns (logic 3.667ns, net 4.662ns, 44% logic)
+ Logic Levels: 7 ( LUT5=4 ADDER=2 LUT2=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -1648,35 +1720,33 @@ Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_74 (214 paths)
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- exdev_ctl_b/u_gen_sp/reg8_syn_107.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ exdev_ctl_b/u_gen_sp/reg9_syn_78.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- exdev_ctl_b/u_gen_sp/reg8_syn_107.q[0] clk2q 0.146 r 2.422
- exdev_ctl_b/u_gen_sp/sub1_syn_104.a[1] (exdev_ctl_b/u_gen_sp/sp_t_d1[9]) net (fanout = 1) 0.765 r 3.187 ../../../../hg_mp/fe/gen_sp.v(87)
- exdev_ctl_b/u_gen_sp/sub1_syn_104.fco cell (ADDER) 0.881 r 4.068
- exdev_ctl_b/u_gen_sp/sub1_syn_105.fci (exdev_ctl_b/u_gen_sp/sub1_syn_95) net (fanout = 1) 0.000 f 4.068 ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_b/u_gen_sp/sub1_syn_105.fx[0] cell (ADDER) 0.387 r 4.455
- u_a_sp_sampling/reg0_syn_27.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12]) net (fanout = 1) 0.591 r 5.046
- u_a_sp_sampling/reg0_syn_27.f[0] cell (LUT4) 0.424 r 5.470
- exdev_ctl_b/u_gen_sp/reg9_syn_103.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_139) net (fanout = 1) 0.594 r 6.064 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_gen_sp/reg9_syn_103.f[0] cell (LUT5) 0.424 r 6.488
- sampling_fe_a/u_ad_sampling/sp_1d_reg_syn_8.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_141) net (fanout = 1) 0.456 r 6.944 ../../../../hg_mp/fe/gen_sp.v(137)
- sampling_fe_a/u_ad_sampling/sp_1d_reg_syn_8.f[0] cell (LUT5) 0.424 r 7.368
- u_bus_top/u_local_bus_slve_cis/reg53_syn_51.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_149) net (fanout = 1) 0.594 r 7.962 ../../../../hg_mp/fe/gen_sp.v(137)
- u_bus_top/u_local_bus_slve_cis/reg53_syn_51.f[0] cell (LUT5) 0.424 r 8.386
- u_bus_top/u_local_bus_slve_cis/reg54_syn_47.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.456 r 8.842
- u_bus_top/u_local_bus_slve_cis/reg54_syn_47.f[0] cell (LUT5) 0.424 r 9.266
- u_bus_top/u_local_bus_slve_cis/reg55_syn_42.a[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2) net (fanout = 1) 0.738 r 10.004
- u_bus_top/u_local_bus_slve_cis/reg55_syn_42.f[1] cell (LUT5) 0.424 r 10.428
- exdev_ctl_b/u_gen_sp/reg0_syn_74.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net (fanout = 8) 0.625 r 11.053 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_gen_sp/reg0_syn_74 path2reg 0.143 11.196
- Arrival time 11.196 (8 lvl)
+ exdev_ctl_b/u_gen_sp/reg9_syn_78.q[1] clk2q 0.146 r 2.422
+ exdev_ctl_b/u_gen_sp/sub1_syn_104.a[0] (exdev_ctl_b/u_gen_sp/sp_t_d1[7]) net (fanout = 1) 0.803 r 3.225 ../../../../hg_mp/fe/gen_sp.v(87)
+ exdev_ctl_b/u_gen_sp/sub1_syn_104.fco cell (ADDER) 0.947 r 4.172
+ exdev_ctl_b/u_gen_sp/sub1_syn_105.fci (exdev_ctl_b/u_gen_sp/sub1_syn_95) net (fanout = 1) 0.000 f 4.172 ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_105.fx[0] cell (ADDER) 0.387 r 4.559
+ u_pixel_cdc/u_clkb_mipi_total_num/reg1_syn_415.a[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12]) net (fanout = 1) 0.648 r 5.207
+ u_pixel_cdc/u_clkb_mipi_total_num/reg1_syn_415.f[1] cell (LUT5) 0.424 r 5.631
+ exdev_ctl_b/u_gen_sp/reg9_syn_69.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_138) net (fanout = 1) 0.738 r 6.369 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_b/u_gen_sp/reg9_syn_69.f[0] cell (LUT5) 0.424 r 6.793
+ u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_464.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_140) net (fanout = 1) 0.456 r 7.249 ../../../../hg_mp/fe/gen_sp.v(137)
+ u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_464.f[1] cell (LUT5) 0.424 r 7.673
+ u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_456.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_148) net (fanout = 1) 0.468 r 8.141 ../../../../hg_mp/fe/gen_sp.v(137)
+ u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_456.f[1] cell (LUT5) 0.424 r 8.565
+ u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_517.c[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.676 r 9.241
+ u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_517.f[0] cell (LUT2) 0.348 r 9.589
+ exdev_ctl_b/u_gen_sp/reg0_syn_77.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net (fanout = 8) 0.873 r 10.462 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_b/u_gen_sp/reg0_syn_77 path2reg 0.143 10.605
+ Arrival time 10.605 (7 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- exdev_ctl_b/u_gen_sp/reg0_syn_74.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ exdev_ctl_b/u_gen_sp/reg0_syn_77.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 20.833 22.878
---------------------------------------------------------------------------------------------------------
cell setup -0.187 22.691
@@ -1684,17 +1754,17 @@ Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_74 (214 paths)
clock recovergence pessimism 0.167 22.858
Required time 22.858
---------------------------------------------------------------------------------------------------------
- Slack 11.662ns
+ Slack 12.253ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 11.726 ns
- Start Point: exdev_ctl_b/u_gen_sp/reg9_syn_106.clk (rising edge triggered by clock b_pclk)
- End Point: exdev_ctl_b/u_gen_sp/reg0_syn_74.sr (rising edge triggered by clock b_pclk)
+ Slack (setup check): 12.379 ns
+ Start Point: exdev_ctl_b/u_gen_sp/reg9_syn_92.clk (rising edge triggered by clock b_pclk)
+ End Point: exdev_ctl_b/u_gen_sp/reg0_syn_77.sr (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 8.856ns (logic 4.320ns, net 4.536ns, 48% logic)
- Logic Levels: 8 ( LUT5=5 ADDER=2 LUT4=1 )
+ Data Path Delay: 8.203ns (logic 3.865ns, net 4.338ns, 47% logic)
+ Logic Levels: 7 ( LUT5=4 ADDER=2 LUT2=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -1702,39 +1772,37 @@ Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_74 (214 paths)
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- exdev_ctl_b/u_gen_sp/reg9_syn_106.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ exdev_ctl_b/u_gen_sp/reg9_syn_92.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- exdev_ctl_b/u_gen_sp/reg9_syn_106.q[0] clk2q 0.146 r 2.422
- exdev_ctl_b/u_gen_sp/sub1_syn_102.b[0] (exdev_ctl_b/u_gen_sp/sp_t_d1[0]) net (fanout = 1) 0.482 r 2.904 ../../../../hg_mp/fe/gen_sp.v(87)
- exdev_ctl_b/u_gen_sp/sub1_syn_102.fco cell (ADDER) 0.836 r 3.740
- exdev_ctl_b/u_gen_sp/sub1_syn_103.fci (exdev_ctl_b/u_gen_sp/sub1_syn_87) net (fanout = 1) 0.000 f 3.740 ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_b/u_gen_sp/sub1_syn_103.fco cell (ADDER) 0.132 r 3.872
- exdev_ctl_b/u_gen_sp/sub1_syn_104.fci (exdev_ctl_b/u_gen_sp/sub1_syn_91) net (fanout = 1) 0.000 f 3.872 ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_b/u_gen_sp/sub1_syn_104.fco cell (ADDER) 0.132 r 4.004
- exdev_ctl_b/u_gen_sp/sub1_syn_105.fci (exdev_ctl_b/u_gen_sp/sub1_syn_95) net (fanout = 1) 0.000 f 4.004 ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_b/u_gen_sp/sub1_syn_105.fx[0] cell (ADDER) 0.387 r 4.391
- u_a_sp_sampling/reg0_syn_27.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12]) net (fanout = 1) 0.591 r 4.982
- u_a_sp_sampling/reg0_syn_27.f[0] cell (LUT4) 0.424 r 5.406
- exdev_ctl_b/u_gen_sp/reg9_syn_103.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_139) net (fanout = 1) 0.594 r 6.000 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_gen_sp/reg9_syn_103.f[0] cell (LUT5) 0.424 r 6.424
- sampling_fe_a/u_ad_sampling/sp_1d_reg_syn_8.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_141) net (fanout = 1) 0.456 r 6.880 ../../../../hg_mp/fe/gen_sp.v(137)
- sampling_fe_a/u_ad_sampling/sp_1d_reg_syn_8.f[0] cell (LUT5) 0.424 r 7.304
- u_bus_top/u_local_bus_slve_cis/reg53_syn_51.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_149) net (fanout = 1) 0.594 r 7.898 ../../../../hg_mp/fe/gen_sp.v(137)
- u_bus_top/u_local_bus_slve_cis/reg53_syn_51.f[0] cell (LUT5) 0.424 r 8.322
- u_bus_top/u_local_bus_slve_cis/reg54_syn_47.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.456 r 8.778
- u_bus_top/u_local_bus_slve_cis/reg54_syn_47.f[0] cell (LUT5) 0.424 r 9.202
- u_bus_top/u_local_bus_slve_cis/reg55_syn_42.a[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2) net (fanout = 1) 0.738 r 9.940
- u_bus_top/u_local_bus_slve_cis/reg55_syn_42.f[1] cell (LUT5) 0.424 r 10.364
- exdev_ctl_b/u_gen_sp/reg0_syn_74.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net (fanout = 8) 0.625 r 10.989 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_gen_sp/reg0_syn_74 path2reg 0.143 11.132
- Arrival time 11.132 (8 lvl)
+ exdev_ctl_b/u_gen_sp/reg9_syn_92.q[0] clk2q 0.146 r 2.422
+ exdev_ctl_b/u_gen_sp/sub1_syn_102.a[1] (exdev_ctl_b/u_gen_sp/sp_t_d1[1]) net (fanout = 1) 0.479 r 2.901 ../../../../hg_mp/fe/gen_sp.v(87)
+ exdev_ctl_b/u_gen_sp/sub1_syn_102.fco cell (ADDER) 0.881 r 3.782
+ exdev_ctl_b/u_gen_sp/sub1_syn_103.fci (exdev_ctl_b/u_gen_sp/sub1_syn_87) net (fanout = 1) 0.000 f 3.782 ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_103.fco cell (ADDER) 0.132 r 3.914
+ exdev_ctl_b/u_gen_sp/sub1_syn_104.fci (exdev_ctl_b/u_gen_sp/sub1_syn_91) net (fanout = 1) 0.000 f 3.914 ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_104.fco cell (ADDER) 0.132 r 4.046
+ exdev_ctl_b/u_gen_sp/sub1_syn_105.fci (exdev_ctl_b/u_gen_sp/sub1_syn_95) net (fanout = 1) 0.000 f 4.046 ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_105.fx[0] cell (ADDER) 0.387 r 4.433
+ u_pixel_cdc/u_clkb_mipi_total_num/reg1_syn_415.a[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12]) net (fanout = 1) 0.648 r 5.081
+ u_pixel_cdc/u_clkb_mipi_total_num/reg1_syn_415.f[1] cell (LUT5) 0.424 r 5.505
+ exdev_ctl_b/u_gen_sp/reg9_syn_69.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_138) net (fanout = 1) 0.738 r 6.243 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_b/u_gen_sp/reg9_syn_69.f[0] cell (LUT5) 0.424 r 6.667
+ u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_464.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_140) net (fanout = 1) 0.456 r 7.123 ../../../../hg_mp/fe/gen_sp.v(137)
+ u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_464.f[1] cell (LUT5) 0.424 r 7.547
+ u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_456.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_148) net (fanout = 1) 0.468 r 8.015 ../../../../hg_mp/fe/gen_sp.v(137)
+ u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_456.f[1] cell (LUT5) 0.424 r 8.439
+ u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_517.c[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.676 r 9.115
+ u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_517.f[0] cell (LUT2) 0.348 r 9.463
+ exdev_ctl_b/u_gen_sp/reg0_syn_77.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net (fanout = 8) 0.873 r 10.336 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_b/u_gen_sp/reg0_syn_77 path2reg 0.143 10.479
+ Arrival time 10.479 (7 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- exdev_ctl_b/u_gen_sp/reg0_syn_74.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ exdev_ctl_b/u_gen_sp/reg0_syn_77.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 20.833 22.878
---------------------------------------------------------------------------------------------------------
cell setup -0.187 22.691
@@ -1742,249 +1810,73 @@ Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_74 (214 paths)
clock recovergence pessimism 0.167 22.858
Required time 22.858
---------------------------------------------------------------------------------------------------------
- Slack 11.726ns
+ Slack 12.379ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check): 12.427 ns
+ Start Point: exdev_ctl_b/u_gen_sp/reg9_syn_90.clk (rising edge triggered by clock b_pclk)
+ End Point: exdev_ctl_b/u_gen_sp/reg0_syn_77.sr (rising edge triggered by clock b_pclk)
+ Clock group: b_lvds_clk_p
+ Process: Slow
+ Data Path Delay: 8.155ns (logic 3.820ns, net 4.335ns, 46% logic)
+ Logic Levels: 7 ( LUT5=4 ADDER=2 LUT2=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ exdev_ctl_b/u_gen_sp/reg9_syn_90.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 2.276
+---------------------------------------------------------------------------------------------------------
+ exdev_ctl_b/u_gen_sp/reg9_syn_90.q[1] clk2q 0.146 r 2.422
+ exdev_ctl_b/u_gen_sp/sub1_syn_102.b[0] (exdev_ctl_b/u_gen_sp/sp_t_d1[0]) net (fanout = 1) 0.476 r 2.898 ../../../../hg_mp/fe/gen_sp.v(87)
+ exdev_ctl_b/u_gen_sp/sub1_syn_102.fco cell (ADDER) 0.836 r 3.734
+ exdev_ctl_b/u_gen_sp/sub1_syn_103.fci (exdev_ctl_b/u_gen_sp/sub1_syn_87) net (fanout = 1) 0.000 f 3.734 ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_103.fco cell (ADDER) 0.132 r 3.866
+ exdev_ctl_b/u_gen_sp/sub1_syn_104.fci (exdev_ctl_b/u_gen_sp/sub1_syn_91) net (fanout = 1) 0.000 f 3.866 ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_104.fco cell (ADDER) 0.132 r 3.998
+ exdev_ctl_b/u_gen_sp/sub1_syn_105.fci (exdev_ctl_b/u_gen_sp/sub1_syn_95) net (fanout = 1) 0.000 f 3.998 ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_105.fx[0] cell (ADDER) 0.387 r 4.385
+ u_pixel_cdc/u_clkb_mipi_total_num/reg1_syn_415.a[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12]) net (fanout = 1) 0.648 r 5.033
+ u_pixel_cdc/u_clkb_mipi_total_num/reg1_syn_415.f[1] cell (LUT5) 0.424 r 5.457
+ exdev_ctl_b/u_gen_sp/reg9_syn_69.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_138) net (fanout = 1) 0.738 r 6.195 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_b/u_gen_sp/reg9_syn_69.f[0] cell (LUT5) 0.424 r 6.619
+ u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_464.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_140) net (fanout = 1) 0.456 r 7.075 ../../../../hg_mp/fe/gen_sp.v(137)
+ u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_464.f[1] cell (LUT5) 0.424 r 7.499
+ u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_456.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_148) net (fanout = 1) 0.468 r 7.967 ../../../../hg_mp/fe/gen_sp.v(137)
+ u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_456.f[1] cell (LUT5) 0.424 r 8.391
+ u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_517.c[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.676 r 9.067
+ u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_517.f[0] cell (LUT2) 0.348 r 9.415
+ exdev_ctl_b/u_gen_sp/reg0_syn_77.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net (fanout = 8) 0.873 r 10.288 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_b/u_gen_sp/reg0_syn_77 path2reg 0.143 10.431
+ Arrival time 10.431 (7 lvl)
+
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ exdev_ctl_b/u_gen_sp/reg0_syn_77.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 20.833 22.878
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.187 22.691
+ clock uncertainty -0.000 22.691
+ clock recovergence pessimism 0.167 22.858
+ Required time 22.858
+---------------------------------------------------------------------------------------------------------
+ Slack 12.427ns
---------------------------------------------------------------------------------------------------------
Hold checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1 (10 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.080 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_663.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.addra[3] (rising edge triggered by clock b_pclk)
- Clock group: b_lvds_clk_p
- Process: Fast
- Data Path Delay: 0.325ns (logic 0.109ns, net 0.216ns, 33% logic)
- Logic Levels: 1 ( EMB=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_663.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 1.938
----------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_663.q[0] clk2q 0.109 r 2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.addra[3] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[100]) net (fanout = 2) 0.216 r 2.263 ../../../../hg_mp/fe/prebuffer_rev.v(329)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1 path2reg (EMB) 0.000 2.263
- Arrival time 2.263 (1 lvl)
-
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 0.000 2.130
----------------------------------------------------------------------------------------------------------
- cell hold 0.200 2.330
- clock uncertainty 0.000 2.330
- clock recovergence pessimism -0.147 2.183
- Required time 2.183
----------------------------------------------------------------------------------------------------------
- Slack 0.080ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check): 0.089 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_625.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.addra[6] (rising edge triggered by clock b_pclk)
- Clock group: b_lvds_clk_p
- Process: Fast
- Data Path Delay: 0.334ns (logic 0.109ns, net 0.225ns, 32% logic)
- Logic Levels: 1 ( EMB=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_625.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 1.938
----------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_625.q[0] clk2q 0.109 r 2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.addra[6] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[103]) net (fanout = 2) 0.225 r 2.272 ../../../../hg_mp/fe/prebuffer_rev.v(329)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1 path2reg (EMB) 0.000 2.272
- Arrival time 2.272 (1 lvl)
-
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 0.000 2.130
----------------------------------------------------------------------------------------------------------
- cell hold 0.200 2.330
- clock uncertainty 0.000 2.330
- clock recovergence pessimism -0.147 2.183
- Required time 2.183
----------------------------------------------------------------------------------------------------------
- Slack 0.089ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check): 0.234 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_665.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.addra[4] (rising edge triggered by clock b_pclk)
- Clock group: b_lvds_clk_p
- Process: Fast
- Data Path Delay: 0.479ns (logic 0.109ns, net 0.370ns, 22% logic)
- Logic Levels: 1 ( EMB=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_665.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 1.938
----------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_665.q[0] clk2q 0.109 r 2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.addra[4] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[101]) net (fanout = 2) 0.370 r 2.417 ../../../../hg_mp/fe/prebuffer_rev.v(329)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1 path2reg (EMB) 0.000 2.417
- Arrival time 2.417 (1 lvl)
-
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 0.000 2.130
----------------------------------------------------------------------------------------------------------
- cell hold 0.200 2.330
- clock uncertainty 0.000 2.330
- clock recovergence pessimism -0.147 2.183
- Required time 2.183
----------------------------------------------------------------------------------------------------------
- Slack 0.234ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1 (8 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.080 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_27.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.dia[0] (rising edge triggered by clock b_pclk)
- Clock group: b_lvds_clk_p
- Process: Fast
- Data Path Delay: 0.325ns (logic 0.109ns, net 0.216ns, 33% logic)
- Logic Levels: 1 ( EMB=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_27.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 1.938
----------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_27.q[0] clk2q 0.109 r 2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.dia[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[80]) net (fanout = 2) 0.216 r 2.263 ../../../../hg_mp/fe/prebuffer_rev.v(327)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1 path2reg (EMB) 0.000 2.263
- Arrival time 2.263 (1 lvl)
-
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 0.000 2.130
----------------------------------------------------------------------------------------------------------
- cell hold 0.200 2.330
- clock uncertainty 0.000 2.330
- clock recovergence pessimism -0.147 2.183
- Required time 2.183
----------------------------------------------------------------------------------------------------------
- Slack 0.080ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check): 0.130 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_666.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.dia[2] (rising edge triggered by clock b_pclk)
- Clock group: b_lvds_clk_p
- Process: Fast
- Data Path Delay: 0.375ns (logic 0.109ns, net 0.266ns, 29% logic)
- Logic Levels: 1 ( EMB=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_666.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 1.938
----------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_666.q[0] clk2q 0.109 r 2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.dia[2] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[82]) net (fanout = 2) 0.266 r 2.313 ../../../../hg_mp/fe/prebuffer_rev.v(327)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1 path2reg (EMB) 0.000 2.313
- Arrival time 2.313 (1 lvl)
-
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 0.000 2.130
----------------------------------------------------------------------------------------------------------
- cell hold 0.200 2.330
- clock uncertainty 0.000 2.330
- clock recovergence pessimism -0.147 2.183
- Required time 2.183
----------------------------------------------------------------------------------------------------------
- Slack 0.130ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check): 0.186 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_543.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.dia[7] (rising edge triggered by clock b_pclk)
- Clock group: b_lvds_clk_p
- Process: Fast
- Data Path Delay: 0.431ns (logic 0.109ns, net 0.322ns, 25% logic)
- Logic Levels: 1 ( EMB=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_543.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 1.938
----------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_543.q[0] clk2q 0.109 r 2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.dia[7] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[87]) net (fanout = 2) 0.322 r 2.369 ../../../../hg_mp/fe/prebuffer_rev.v(327)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1 path2reg (EMB) 0.000 2.369
- Arrival time 2.369 (1 lvl)
-
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 0.000 2.130
----------------------------------------------------------------------------------------------------------
- cell hold 0.200 2.330
- clock uncertainty 0.000 2.330
- clock recovergence pessimism -0.147 2.183
- Required time 2.183
----------------------------------------------------------------------------------------------------------
- Slack 0.186ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1 (10 paths)
+Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1 (10 paths)
---------------------------------------------------------------------------------------------------------
Slack (hold check): 0.114 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_712.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.addra[11] (rising edge triggered by clock b_pclk)
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_719.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[12] (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Fast
Data Path Delay: 0.359ns (logic 0.109ns, net 0.250ns, 30% logic)
@@ -1996,19 +1888,19 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/in
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_712.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_719.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_712.q[0] clk2q 0.109 r 2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.addra[11] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[68]) net (fanout = 2) 0.250 r 2.297 ../../../../hg_mp/fe/prebuffer_rev.v(329)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1 path2reg (EMB) 0.000 2.297
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_719.q[0] clk2q 0.109 r 2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[12] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[39]) net (fanout = 2) 0.250 r 2.297 ../../../../hg_mp/fe/prebuffer_rev.v(331)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1 path2reg (EMB) 0.000 2.297
Arrival time 2.297 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell hold 0.200 2.330
@@ -2020,12 +1912,12 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/in
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.205 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_712.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.addra[10] (rising edge triggered by clock b_pclk)
+ Slack (hold check): 0.114 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_721.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[11] (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Fast
- Data Path Delay: 0.450ns (logic 0.109ns, net 0.341ns, 24% logic)
+ Data Path Delay: 0.359ns (logic 0.109ns, net 0.250ns, 30% logic)
Logic Levels: 1 ( EMB=1 )
Point Type Incr Path Info
@@ -2034,19 +1926,19 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/in
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_712.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_721.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_712.q[1] clk2q 0.109 r 2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.addra[10] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[67]) net (fanout = 2) 0.341 r 2.388 ../../../../hg_mp/fe/prebuffer_rev.v(329)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1 path2reg (EMB) 0.000 2.388
- Arrival time 2.388 (1 lvl)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_721.q[0] clk2q 0.109 r 2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[11] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[38]) net (fanout = 2) 0.250 r 2.297 ../../../../hg_mp/fe/prebuffer_rev.v(331)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1 path2reg (EMB) 0.000 2.297
+ Arrival time 2.297 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell hold 0.200 2.330
@@ -2054,16 +1946,16 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/in
clock recovergence pessimism -0.147 2.183
Required time 2.183
---------------------------------------------------------------------------------------------------------
- Slack 0.205ns
+ Slack 0.114ns
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.302 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_703.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.addra[9] (rising edge triggered by clock b_pclk)
+ Slack (hold check): 0.195 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_719.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[3] (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Fast
- Data Path Delay: 0.547ns (logic 0.109ns, net 0.438ns, 19% logic)
+ Data Path Delay: 0.440ns (logic 0.109ns, net 0.331ns, 24% logic)
Logic Levels: 1 ( EMB=1 )
Point Type Incr Path Info
@@ -2072,19 +1964,19 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/in
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_703.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_719.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_703.q[1] clk2q 0.109 r 2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.addra[9] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[66]) net (fanout = 2) 0.438 r 2.485 ../../../../hg_mp/fe/prebuffer_rev.v(329)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1 path2reg (EMB) 0.000 2.485
- Arrival time 2.485 (1 lvl)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_719.q[1] clk2q 0.109 r 2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[3] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[30]) net (fanout = 2) 0.331 r 2.378 ../../../../hg_mp/fe/prebuffer_rev.v(331)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1 path2reg (EMB) 0.000 2.378
+ Arrival time 2.378 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell hold 0.200 2.330
@@ -2092,7 +1984,239 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/in
clock recovergence pessimism -0.147 2.183
Required time 2.183
---------------------------------------------------------------------------------------------------------
- Slack 0.302ns
+ Slack 0.195ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1 (8 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.147 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_624.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.dia[4] (rising edge triggered by clock b_pclk)
+ Clock group: b_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.392ns (logic 0.109ns, net 0.283ns, 27% logic)
+ Logic Levels: 1 ( EMB=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_624.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_624.q[0] clk2q 0.109 r 2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.dia[4] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[12]) net (fanout = 2) 0.283 r 2.330 ../../../../hg_mp/fe/prebuffer_rev.v(329)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1 path2reg (EMB) 0.000 2.330
+ Arrival time 2.330 (1 lvl)
+
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.200 2.330
+ clock uncertainty 0.000 2.330
+ clock recovergence pessimism -0.147 2.183
+ Required time 2.183
+---------------------------------------------------------------------------------------------------------
+ Slack 0.147ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check): 0.186 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_606.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.dia[7] (rising edge triggered by clock b_pclk)
+ Clock group: b_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.431ns (logic 0.109ns, net 0.322ns, 25% logic)
+ Logic Levels: 1 ( EMB=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_606.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_606.q[0] clk2q 0.109 r 2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.dia[7] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[15]) net (fanout = 2) 0.322 r 2.369 ../../../../hg_mp/fe/prebuffer_rev.v(329)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1 path2reg (EMB) 0.000 2.369
+ Arrival time 2.369 (1 lvl)
+
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.200 2.330
+ clock uncertainty 0.000 2.330
+ clock recovergence pessimism -0.147 2.183
+ Required time 2.183
+---------------------------------------------------------------------------------------------------------
+ Slack 0.186ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check): 0.186 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_606.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.dia[5] (rising edge triggered by clock b_pclk)
+ Clock group: b_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.431ns (logic 0.109ns, net 0.322ns, 25% logic)
+ Logic Levels: 1 ( EMB=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_606.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_606.q[1] clk2q 0.109 r 2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.dia[5] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[13]) net (fanout = 2) 0.322 r 2.369 ../../../../hg_mp/fe/prebuffer_rev.v(329)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1 path2reg (EMB) 0.000 2.369
+ Arrival time 2.369 (1 lvl)
+
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.200 2.330
+ clock uncertainty 0.000 2.330
+ clock recovergence pessimism -0.147 2.183
+ Required time 2.183
+---------------------------------------------------------------------------------------------------------
+ Slack 0.186ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1 (8 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.186 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_582.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[7] (rising edge triggered by clock b_pclk)
+ Clock group: b_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.431ns (logic 0.109ns, net 0.322ns, 25% logic)
+ Logic Levels: 1 ( EMB=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_582.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_582.q[0] clk2q 0.109 r 2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[7] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[47]) net (fanout = 2) 0.322 r 2.369 ../../../../hg_mp/fe/prebuffer_rev.v(329)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1 path2reg (EMB) 0.000 2.369
+ Arrival time 2.369 (1 lvl)
+
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.200 2.330
+ clock uncertainty 0.000 2.330
+ clock recovergence pessimism -0.147 2.183
+ Required time 2.183
+---------------------------------------------------------------------------------------------------------
+ Slack 0.186ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check): 0.311 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_574.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[1] (rising edge triggered by clock b_pclk)
+ Clock group: b_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.556ns (logic 0.109ns, net 0.447ns, 19% logic)
+ Logic Levels: 1 ( EMB=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_574.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_574.q[0] clk2q 0.109 r 2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[41]) net (fanout = 2) 0.447 r 2.494 ../../../../hg_mp/fe/prebuffer_rev.v(329)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1 path2reg (EMB) 0.000 2.494
+ Arrival time 2.494 (1 lvl)
+
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.200 2.330
+ clock uncertainty 0.000 2.330
+ clock recovergence pessimism -0.147 2.183
+ Required time 2.183
+---------------------------------------------------------------------------------------------------------
+ Slack 0.311ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check): 0.411 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_525.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[5] (rising edge triggered by clock b_pclk)
+ Clock group: b_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.656ns (logic 0.109ns, net 0.547ns, 16% logic)
+ Logic Levels: 1 ( EMB=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_525.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_525.q[1] clk2q 0.109 r 2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[5] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[45]) net (fanout = 2) 0.547 r 2.594 ../../../../hg_mp/fe/prebuffer_rev.v(329)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1 path2reg (EMB) 0.000 2.594
+ Arrival time 2.594 (1 lvl)
+
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.200 2.330
+ clock uncertainty 0.000 2.330
+ clock recovergence pessimism -0.147 2.183
+ Required time 2.183
+---------------------------------------------------------------------------------------------------------
+ Slack 0.411ns
---------------------------------------------------------------------------------------------------------
@@ -2101,126 +2225,230 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/in
Timing constraint: clock: b_sclk
Clock = b_sclk, period 5.952ns, rising at 0ns, falling at 2.976ns
-282 endpoints analyzed totally, and 690 paths analyzed
+282 endpoints analyzed totally, and 706 paths analyzed
0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 1.853ns
+Minimum period is 2.158ns
---------------------------------------------------------------------------------------------------------
Paths for end point ub_lvds_rx/rx_clk_sync_reg_syn_5 (7 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.099 ns
- Start Point: ub_lvds_rx/reg7_syn_32.clk (rising edge triggered by clock b_sclk)
+ Slack (setup check): 3.794 ns
+ Start Point: ub_lvds_rx/reg7_syn_33.clk (rising edge triggered by clock b_sclk)
End Point: ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 1.701ns (logic 0.941ns, net 0.760ns, 55% logic)
+ Data Path Delay: 2.006ns (logic 0.948ns, net 1.058ns, 47% logic)
Logic Levels: 2 ( LUT5=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg7_syn_32.clk (ub_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.410
+ ub_lvds_rx/reg7_syn_33.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg7_syn_32.q[1] clk2q 0.146 r 2.556
- ub_lvds_rx/rx_clk_sync_reg_syn_5.a[0] (ub_lvds_rx/rx_clk_sft[0]) net (fanout = 2) 0.602 r 3.158 encrypted_text(0)
- ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.424 r 3.582
- ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.158 r 3.740 encrypted_text(0)
- ub_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.111
- Arrival time 4.111 (2 lvl)
+ ub_lvds_rx/reg7_syn_33.q[0] clk2q 0.146 r 2.422
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.b[0] (ub_lvds_rx/rx_clk_sft[1]) net (fanout = 2) 0.602 r 3.024 encrypted_text(0)
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.431 r 3.455
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.456 r 3.911 encrypted_text(0)
+ ub_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.282
+ Arrival time 4.282 (2 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/rx_clk_sync_reg_syn_5.clk (ub_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 8.118
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 7.997
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 8.002
- clock uncertainty -0.000 8.002
- clock recovergence pessimism 0.208 8.210
- Required time 8.210
+ cell setup -0.116 7.881
+ clock uncertainty -0.000 7.881
+ clock recovergence pessimism 0.195 8.076
+ Required time 8.076
---------------------------------------------------------------------------------------------------------
- Slack 4.099ns
+ Slack 3.794ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.175 ns
+ Slack (setup check): 4.018 ns
Start Point: ub_lvds_rx/reg7_syn_25.clk (rising edge triggered by clock b_sclk)
End Point: ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 1.625ns (logic 0.865ns, net 0.760ns, 53% logic)
+ Data Path Delay: 1.797ns (logic 0.865ns, net 0.932ns, 48% logic)
Logic Levels: 2 ( LUT5=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg7_syn_25.clk (ub_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.410
+ ub_lvds_rx/reg7_syn_25.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg7_syn_25.q[1] clk2q 0.146 r 2.556
- ub_lvds_rx/rx_clk_sync_reg_syn_5.c[0] (ub_lvds_rx/rx_clk_sft[2]) net (fanout = 2) 0.602 r 3.158 encrypted_text(0)
- ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.348 r 3.506
- ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.158 r 3.664 encrypted_text(0)
- ub_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.035
- Arrival time 4.035 (2 lvl)
+ ub_lvds_rx/reg7_syn_25.q[1] clk2q 0.146 r 2.422
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.c[0] (ub_lvds_rx/rx_clk_sft[2]) net (fanout = 2) 0.476 r 2.898 encrypted_text(0)
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.348 r 3.246
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.456 r 3.702 encrypted_text(0)
+ ub_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.073
+ Arrival time 4.073 (2 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/rx_clk_sync_reg_syn_5.clk (ub_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 8.118
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 7.997
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 8.002
- clock uncertainty -0.000 8.002
- clock recovergence pessimism 0.208 8.210
- Required time 8.210
+ cell setup -0.116 7.881
+ clock uncertainty -0.000 7.881
+ clock recovergence pessimism 0.210 8.091
+ Required time 8.091
---------------------------------------------------------------------------------------------------------
- Slack 4.175ns
+ Slack 4.018ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.364 ns
- Start Point: ub_lvds_rx/reg7_syn_32.clk (rising edge triggered by clock b_sclk)
+ Slack (setup check): 4.087 ns
+ Start Point: ub_lvds_rx/reg7_syn_25.clk (rising edge triggered by clock b_sclk)
End Point: ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 1.436ns (logic 0.948ns, net 0.488ns, 66% logic)
+ Data Path Delay: 1.728ns (logic 0.799ns, net 0.929ns, 46% logic)
Logic Levels: 2 ( LUT5=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg7_syn_32.clk (ub_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.410
+ ub_lvds_rx/reg7_syn_25.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg7_syn_32.q[0] clk2q 0.146 r 2.556
- ub_lvds_rx/rx_clk_sync_reg_syn_5.b[0] (ub_lvds_rx/rx_clk_sft[1]) net (fanout = 2) 0.330 r 2.886 encrypted_text(0)
- ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.431 r 3.317
- ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.158 r 3.475 encrypted_text(0)
- ub_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 3.846
- Arrival time 3.846 (2 lvl)
+ ub_lvds_rx/reg7_syn_25.q[0] clk2q 0.146 r 2.422
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.e[0] (ub_lvds_rx/rx_clk_sft[4]) net (fanout = 2) 0.473 r 2.895 encrypted_text(0)
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.282 r 3.177
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.456 r 3.633 encrypted_text(0)
+ ub_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.004
+ Arrival time 4.004 (2 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/rx_clk_sync_reg_syn_5.clk (ub_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 8.118
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 7.997
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 8.002
- clock uncertainty -0.000 8.002
- clock recovergence pessimism 0.208 8.210
- Required time 8.210
+ cell setup -0.116 7.881
+ clock uncertainty -0.000 7.881
+ clock recovergence pessimism 0.210 8.091
+ Required time 8.091
---------------------------------------------------------------------------------------------------------
- Slack 4.364ns
+ Slack 4.087ns
---------------------------------------------------------------------------------------------------------
-Paths for end point ub_lvds_rx/reg8_syn_145 (9 paths)
+Paths for end point ub_lvds_rx/reg16_syn_31 (4 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check): 4.143 ns
+ Start Point: ub_lvds_rx/para_en_reg_syn_5.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/reg16_syn_31.a[0] (rising edge triggered by clock b_sclk)
+ Clock group: b_lvds_clk_p
+ Process: Slow
+ Data Path Delay: 1.672ns (logic 0.688ns, net 0.984ns, 41% logic)
+ Logic Levels: 1 ( LUT4=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
+ ub_lvds_rx/para_en_reg_syn_5.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.276
+---------------------------------------------------------------------------------------------------------
+ ub_lvds_rx/para_en_reg_syn_5.q[1] clk2q 0.146 r 2.422
+ ub_lvds_rx/reg16_syn_31.a[0] (ub_lvds_rx/para_en) net (fanout = 11) 0.984 r 3.406 encrypted_text(0)
+ ub_lvds_rx/reg16_syn_31 path2reg0 (LUT4) 0.542 3.948
+ Arrival time 3.948 (1 lvl)
+
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
+ ub_lvds_rx/reg16_syn_31.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 7.997
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.116 7.881
+ clock uncertainty -0.000 7.881
+ clock recovergence pessimism 0.210 8.091
+ Required time 8.091
+---------------------------------------------------------------------------------------------------------
+ Slack 4.143ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check): 4.403 ns
+ Start Point: ub_lvds_rx/reg16_syn_33.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/reg16_syn_31.b[0] (rising edge triggered by clock b_sclk)
+ Clock group: b_lvds_clk_p
+ Process: Slow
+ Data Path Delay: 1.369ns (logic 0.695ns, net 0.674ns, 50% logic)
+ Logic Levels: 1 ( LUT4=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
+ ub_lvds_rx/reg16_syn_33.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.276
+---------------------------------------------------------------------------------------------------------
+ ub_lvds_rx/reg16_syn_33.q[0] clk2q 0.146 r 2.422
+ ub_lvds_rx/reg16_syn_31.b[0] (ub_lvds_rx/wcnt[0]) net (fanout = 11) 0.674 r 3.096 encrypted_text(0)
+ ub_lvds_rx/reg16_syn_31 path2reg0 (LUT4) 0.549 3.645
+ Arrival time 3.645 (1 lvl)
+
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
+ ub_lvds_rx/reg16_syn_31.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 7.997
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.116 7.881
+ clock uncertainty -0.000 7.881
+ clock recovergence pessimism 0.167 8.048
+ Required time 8.048
+---------------------------------------------------------------------------------------------------------
+ Slack 4.403ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check): 4.442 ns
+ Start Point: ub_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/reg16_syn_31.c[0] (rising edge triggered by clock b_sclk)
+ Clock group: b_lvds_clk_p
+ Process: Slow
+ Data Path Delay: 1.394ns (logic 0.612ns, net 0.782ns, 43% logic)
+ Logic Levels: 1 ( LUT4=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
+ ub_lvds_rx/reg16_syn_31.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.276
+---------------------------------------------------------------------------------------------------------
+ ub_lvds_rx/reg16_syn_31.q[1] clk2q 0.146 r 2.422
+ ub_lvds_rx/reg16_syn_31.c[0] (ub_lvds_rx/wcnt[1]) net (fanout = 10) 0.782 r 3.204 encrypted_text(0)
+ ub_lvds_rx/reg16_syn_31 path2reg0 (LUT4) 0.466 3.670
+ Arrival time 3.670 (1 lvl)
+
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
+ ub_lvds_rx/reg16_syn_31.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 7.997
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.116 7.881
+ clock uncertainty -0.000 7.881
+ clock recovergence pessimism 0.231 8.112
+ Required time 8.112
+---------------------------------------------------------------------------------------------------------
+ Slack 4.442ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point ub_lvds_rx/reg8_syn_147 (9 paths)
---------------------------------------------------------------------------------------------------------
Slack (setup check): 4.145 ns
- Start Point: ub_lvds_rx/reg8_syn_145.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/reg8_syn_145.a[1] (rising edge triggered by clock b_sclk)
+ Start Point: ub_lvds_rx/reg8_syn_147.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/reg8_syn_147.a[1] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Slow
Data Path Delay: 1.691ns (logic 0.878ns, net 0.813ns, 51% logic)
@@ -2230,207 +2458,103 @@ Paths for end point ub_lvds_rx/reg8_syn_145 (9 paths)
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_145.clk (ub_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.410
+ ub_lvds_rx/reg8_syn_147.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg8_syn_145.q[0] clk2q 0.146 r 2.556
- ub_lvds_rx/reg8_syn_145.a[1] (ub_lvds_rx/para_data[25]) net (fanout = 3) 0.813 r 3.369 encrypted_text(0)
- ub_lvds_rx/reg8_syn_145 path2reg0 0.732 4.101
- Arrival time 4.101 (1 lvl)
+ ub_lvds_rx/reg8_syn_147.q[0] clk2q 0.146 r 2.422
+ ub_lvds_rx/reg8_syn_147.a[1] (ub_lvds_rx/para_data[11]) net (fanout = 3) 0.813 r 3.235 encrypted_text(0)
+ ub_lvds_rx/reg8_syn_147 path2reg0 0.732 3.967
+ Arrival time 3.967 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_145.clk (ub_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 8.118
+ ub_lvds_rx/reg8_syn_147.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 7.997
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 8.002
- clock uncertainty -0.000 8.002
- clock recovergence pessimism 0.244 8.246
- Required time 8.246
+ cell setup -0.116 7.881
+ clock uncertainty -0.000 7.881
+ clock recovergence pessimism 0.231 8.112
+ Required time 8.112
---------------------------------------------------------------------------------------------------------
Slack 4.145ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.156 ns
- Start Point: ub_lvds_rx/reg8_syn_143.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/reg8_syn_145.b[1] (rising edge triggered by clock b_sclk)
+ Slack (setup check): 4.294 ns
+ Start Point: ub_lvds_rx/reg12_syn_17.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/reg8_syn_147.d[1] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 1.616ns (logic 0.803ns, net 0.813ns, 49% logic)
+ Data Path Delay: 1.478ns (logic 0.655ns, net 0.823ns, 44% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_143.clk (ub_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.410
+ ub_lvds_rx/reg12_syn_17.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg8_syn_143.q[1] clk2q 0.146 r 2.556
- ub_lvds_rx/reg8_syn_145.b[1] (ub_lvds_rx/rx_data[28]) net (fanout = 4) 0.813 r 3.369 encrypted_text(0)
- ub_lvds_rx/reg8_syn_145 path2reg0 0.657 4.026
- Arrival time 4.026 (1 lvl)
+ ub_lvds_rx/reg12_syn_17.q[0] clk2q 0.146 r 2.422
+ ub_lvds_rx/reg8_syn_147.d[1] (ub_lvds_rx/sync0) net (fanout = 43) 0.823 r 3.245 encrypted_text(0)
+ ub_lvds_rx/reg8_syn_147 path2reg0 0.509 3.754
+ Arrival time 3.754 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_145.clk (ub_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 8.118
+ ub_lvds_rx/reg8_syn_147.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 7.997
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 8.002
- clock uncertainty -0.000 8.002
- clock recovergence pessimism 0.180 8.182
- Required time 8.182
+ cell setup -0.116 7.881
+ clock uncertainty -0.000 7.881
+ clock recovergence pessimism 0.167 8.048
+ Required time 8.048
---------------------------------------------------------------------------------------------------------
- Slack 4.156ns
+ Slack 4.294ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.156 ns
- Start Point: ub_lvds_rx/reg8_syn_143.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/reg8_syn_145.b[0] (rising edge triggered by clock b_sclk)
+ Slack (setup check): 4.294 ns
+ Start Point: ub_lvds_rx/reg12_syn_17.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/reg8_syn_147.d[0] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 1.616ns (logic 0.803ns, net 0.813ns, 49% logic)
+ Data Path Delay: 1.478ns (logic 0.655ns, net 0.823ns, 44% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_143.clk (ub_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.410
+ ub_lvds_rx/reg12_syn_17.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg8_syn_143.q[1] clk2q 0.146 r 2.556
- ub_lvds_rx/reg8_syn_145.b[0] (ub_lvds_rx/rx_data[28]) net (fanout = 4) 0.813 r 3.369 encrypted_text(0)
- ub_lvds_rx/reg8_syn_145 path2reg0 0.657 4.026
- Arrival time 4.026 (1 lvl)
+ ub_lvds_rx/reg12_syn_17.q[0] clk2q 0.146 r 2.422
+ ub_lvds_rx/reg8_syn_147.d[0] (ub_lvds_rx/sync0) net (fanout = 43) 0.823 r 3.245 encrypted_text(0)
+ ub_lvds_rx/reg8_syn_147 path2reg0 0.509 3.754
+ Arrival time 3.754 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_145.clk (ub_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 8.118
+ ub_lvds_rx/reg8_syn_147.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 7.997
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 8.002
- clock uncertainty -0.000 8.002
- clock recovergence pessimism 0.180 8.182
- Required time 8.182
+ cell setup -0.116 7.881
+ clock uncertainty -0.000 7.881
+ clock recovergence pessimism 0.167 8.048
+ Required time 8.048
---------------------------------------------------------------------------------------------------------
- Slack 4.156ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point ub_lvds_rx/reg8_syn_149 (9 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.166 ns
- Start Point: ub_lvds_rx/reg8_syn_131.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/reg8_syn_149.b[1] (rising edge triggered by clock b_sclk)
- Clock group: b_lvds_clk_p
- Process: Slow
- Data Path Delay: 1.606ns (logic 0.803ns, net 0.803ns, 49% logic)
- Logic Levels: 1
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_131.clk (ub_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.410
----------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg8_syn_131.q[0] clk2q 0.146 r 2.556
- ub_lvds_rx/reg8_syn_149.b[1] (ub_lvds_rx/rx_data[24]) net (fanout = 3) 0.803 r 3.359 encrypted_text(0)
- ub_lvds_rx/reg8_syn_149 path2reg0 0.657 4.016
- Arrival time 4.016 (1 lvl)
-
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_149.clk (ub_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 8.118
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 8.002
- clock uncertainty -0.000 8.002
- clock recovergence pessimism 0.180 8.182
- Required time 8.182
----------------------------------------------------------------------------------------------------------
- Slack 4.166ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check): 4.166 ns
- Start Point: ub_lvds_rx/reg8_syn_131.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/reg8_syn_149.b[0] (rising edge triggered by clock b_sclk)
- Clock group: b_lvds_clk_p
- Process: Slow
- Data Path Delay: 1.606ns (logic 0.803ns, net 0.803ns, 49% logic)
- Logic Levels: 1
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_131.clk (ub_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.410
----------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg8_syn_131.q[0] clk2q 0.146 r 2.556
- ub_lvds_rx/reg8_syn_149.b[0] (ub_lvds_rx/rx_data[24]) net (fanout = 3) 0.803 r 3.359 encrypted_text(0)
- ub_lvds_rx/reg8_syn_149 path2reg0 0.657 4.016
- Arrival time 4.016 (1 lvl)
-
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_149.clk (ub_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 8.118
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 8.002
- clock uncertainty -0.000 8.002
- clock recovergence pessimism 0.180 8.182
- Required time 8.182
----------------------------------------------------------------------------------------------------------
- Slack 4.166ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check): 4.324 ns
- Start Point: ub_lvds_rx/sync0_reg_syn_4.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/reg8_syn_149.d[1] (rising edge triggered by clock b_sclk)
- Clock group: b_lvds_clk_p
- Process: Slow
- Data Path Delay: 1.491ns (logic 0.655ns, net 0.836ns, 43% logic)
- Logic Levels: 1
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/sync0_reg_syn_4.clk (ub_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.410
----------------------------------------------------------------------------------------------------------
- ub_lvds_rx/sync0_reg_syn_4.q[1] clk2q 0.146 r 2.556
- ub_lvds_rx/reg8_syn_149.d[1] (ub_lvds_rx/sync0) net (fanout = 41) 0.836 r 3.392 encrypted_text(0)
- ub_lvds_rx/reg8_syn_149 path2reg0 0.509 3.901
- Arrival time 3.901 (1 lvl)
-
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_149.clk (ub_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 8.118
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 8.002
- clock uncertainty -0.000 8.002
- clock recovergence pessimism 0.223 8.225
- Required time 8.225
----------------------------------------------------------------------------------------------------------
- Slack 4.324ns
+ Slack 4.294ns
---------------------------------------------------------------------------------------------------------
Hold checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point ub_lvds_rx/ramread0_syn_74 (2 paths)
+Paths for end point ub_lvds_rx/ramread0_syn_102 (2 paths)
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.104 ns
- Start Point: ub_lvds_rx/reg3_syn_180.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/ramread0_syn_74.c[1] (rising edge triggered by clock b_sclk)
+ Slack (hold check): 0.167 ns
+ Start Point: ub_lvds_rx/reg8_syn_161.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/ramread0_syn_102.c[1] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Fast
Data Path Delay: 0.325ns (logic 0.109ns, net 0.216ns, 33% logic)
@@ -2440,101 +2564,31 @@ Paths for end point ub_lvds_rx/ramread0_syn_74 (2 paths)
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg3_syn_180.clk (ub_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.029
+ ub_lvds_rx/reg8_syn_161.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg3_syn_180.q[0] clk2q 0.109 r 2.138
- ub_lvds_rx/ramread0_syn_74.c[1] (ub_lvds_rx/para_data[18]) net (fanout = 2) 0.216 r 2.354 encrypted_text(0)
- ub_lvds_rx/ramread0_syn_74 path2reg 0.000 2.354
- Arrival time 2.354 (1 lvl)
+ ub_lvds_rx/reg8_syn_161.q[0] clk2q 0.109 r 2.047
+ ub_lvds_rx/ramread0_syn_102.c[1] (ub_lvds_rx/para_data[26]) net (fanout = 2) 0.216 r 2.263 encrypted_text(0)
+ ub_lvds_rx/ramread0_syn_102 path2reg 0.000 2.263
+ Arrival time 2.263 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/ramread0_syn_74.clk (ub_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.230
+ ub_lvds_rx/ramread0_syn_102.clk (ub_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.343
- clock uncertainty 0.000 2.343
- clock recovergence pessimism -0.093 2.250
- Required time 2.250
+ cell hold 0.113 2.243
+ clock uncertainty 0.000 2.243
+ clock recovergence pessimism -0.147 2.096
+ Required time 2.096
---------------------------------------------------------------------------------------------------------
- Slack 0.104ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check): 0.199 ns
- Start Point: ub_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/ramread0_syn_74.c[0] (rising edge triggered by clock b_sclk)
- Clock group: b_lvds_clk_p
- Process: Fast
- Data Path Delay: 0.357ns (logic 0.109ns, net 0.248ns, 30% logic)
- Logic Levels: 1
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg16_syn_31.clk (ub_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.029
----------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg16_syn_31.q[0] clk2q 0.109 r 2.138
- ub_lvds_rx/ramread0_syn_74.c[0] (ub_lvds_rx/wcnt[2]) net (fanout = 9) 0.248 r 2.386 encrypted_text(0)
- ub_lvds_rx/ramread0_syn_74 path2reg 0.000 2.386
- Arrival time 2.386 (1 lvl)
-
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/ramread0_syn_74.clk (ub_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.230
----------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.343
- clock uncertainty 0.000 2.343
- clock recovergence pessimism -0.156 2.187
- Required time 2.187
----------------------------------------------------------------------------------------------------------
- Slack 0.199ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point ub_lvds_rx/ramread0_syn_102 (2 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.113 ns
- Start Point: ub_lvds_rx/reg3_syn_175.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/ramread0_syn_102.a[1] (rising edge triggered by clock b_sclk)
- Clock group: b_lvds_clk_p
- Process: Fast
- Data Path Delay: 0.334ns (logic 0.109ns, net 0.225ns, 32% logic)
- Logic Levels: 1
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg3_syn_175.clk (ub_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.029
----------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg3_syn_175.q[1] clk2q 0.109 r 2.138
- ub_lvds_rx/ramread0_syn_102.a[1] (ub_lvds_rx/para_data[24]) net (fanout = 2) 0.225 r 2.363 encrypted_text(0)
- ub_lvds_rx/ramread0_syn_102 path2reg 0.000 2.363
- Arrival time 2.363 (1 lvl)
-
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/ramread0_syn_102.clk (ub_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.230
----------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.343
- clock uncertainty 0.000 2.343
- clock recovergence pessimism -0.093 2.250
- Required time 2.250
----------------------------------------------------------------------------------------------------------
- Slack 0.113ns
+ Slack 0.167ns
---------------------------------------------------------------------------------------------------------
Slack (hold check): 0.345 ns
- Start Point: ub_lvds_rx/reg16_syn_33.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/ramread0_syn_102.a[0] (rising edge triggered by clock b_sclk)
+ Start Point: ub_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/ramread0_syn_102.c[0] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Fast
Data Path Delay: 0.503ns (logic 0.109ns, net 0.394ns, 21% logic)
@@ -2544,33 +2598,103 @@ Paths for end point ub_lvds_rx/ramread0_syn_102 (2 paths)
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg16_syn_33.clk (ub_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.029
+ ub_lvds_rx/reg16_syn_31.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg16_syn_33.q[0] clk2q 0.109 r 2.138
- ub_lvds_rx/ramread0_syn_102.a[0] (ub_lvds_rx/wcnt[0]) net (fanout = 11) 0.394 r 2.532 encrypted_text(0)
- ub_lvds_rx/ramread0_syn_102 path2reg 0.000 2.532
- Arrival time 2.532 (1 lvl)
+ ub_lvds_rx/reg16_syn_31.q[0] clk2q 0.109 r 2.047
+ ub_lvds_rx/ramread0_syn_102.c[0] (ub_lvds_rx/wcnt[2]) net (fanout = 9) 0.394 r 2.441 encrypted_text(0)
+ ub_lvds_rx/ramread0_syn_102 path2reg 0.000 2.441
+ Arrival time 2.441 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/ramread0_syn_102.clk (ub_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.230
+ ub_lvds_rx/ramread0_syn_102.clk (ub_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.343
- clock uncertainty 0.000 2.343
- clock recovergence pessimism -0.156 2.187
- Required time 2.187
+ cell hold 0.113 2.243
+ clock uncertainty 0.000 2.243
+ clock recovergence pessimism -0.147 2.096
+ Required time 2.096
---------------------------------------------------------------------------------------------------------
Slack 0.345ns
---------------------------------------------------------------------------------------------------------
-Paths for end point ub_lvds_rx/ramread0_syn_74 (1 paths)
+Paths for end point ub_lvds_rx/ramread0_syn_18 (2 paths)
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.113 ns
- Start Point: ub_lvds_rx/reg3_syn_180.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/ramread0_syn_74.d[1] (rising edge triggered by clock b_sclk)
+ Slack (hold check): 0.167 ns
+ Start Point: ub_lvds_rx/reg3_syn_163.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/ramread0_syn_18.c[1] (rising edge triggered by clock b_sclk)
+ Clock group: b_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.325ns (logic 0.109ns, net 0.216ns, 33% logic)
+ Logic Levels: 1
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
+ ub_lvds_rx/reg3_syn_163.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ ub_lvds_rx/reg3_syn_163.q[1] clk2q 0.109 r 2.047
+ ub_lvds_rx/ramread0_syn_18.c[1] (ub_lvds_rx/para_data[2]) net (fanout = 2) 0.216 r 2.263 encrypted_text(0)
+ ub_lvds_rx/ramread0_syn_18 path2reg 0.000 2.263
+ Arrival time 2.263 (1 lvl)
+
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
+ ub_lvds_rx/ramread0_syn_18.clk (ub_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.113 2.243
+ clock uncertainty 0.000 2.243
+ clock recovergence pessimism -0.147 2.096
+ Required time 2.096
+---------------------------------------------------------------------------------------------------------
+ Slack 0.167ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check): 0.199 ns
+ Start Point: ub_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/ramread0_syn_18.c[0] (rising edge triggered by clock b_sclk)
+ Clock group: b_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.357ns (logic 0.109ns, net 0.248ns, 30% logic)
+ Logic Levels: 1
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
+ ub_lvds_rx/reg16_syn_31.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ ub_lvds_rx/reg16_syn_31.q[0] clk2q 0.109 r 2.047
+ ub_lvds_rx/ramread0_syn_18.c[0] (ub_lvds_rx/wcnt[2]) net (fanout = 9) 0.248 r 2.295 encrypted_text(0)
+ ub_lvds_rx/ramread0_syn_18 path2reg 0.000 2.295
+ Arrival time 2.295 (1 lvl)
+
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
+ ub_lvds_rx/ramread0_syn_18.clk (ub_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.113 2.243
+ clock uncertainty 0.000 2.243
+ clock recovergence pessimism -0.147 2.096
+ Required time 2.096
+---------------------------------------------------------------------------------------------------------
+ Slack 0.199ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point ub_lvds_rx/ramread0_syn_102 (1 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.176 ns
+ Start Point: ub_lvds_rx/reg3_syn_185.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/ramread0_syn_102.d[1] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Fast
Data Path Delay: 0.334ns (logic 0.109ns, net 0.225ns, 32% logic)
@@ -2580,25 +2704,25 @@ Paths for end point ub_lvds_rx/ramread0_syn_74 (1 paths)
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg3_syn_180.clk (ub_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.029
+ ub_lvds_rx/reg3_syn_185.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg3_syn_180.q[1] clk2q 0.109 r 2.138
- ub_lvds_rx/ramread0_syn_74.d[1] (ub_lvds_rx/para_data[19]) net (fanout = 2) 0.225 r 2.363 encrypted_text(0)
- ub_lvds_rx/ramread0_syn_74 path2reg 0.000 2.363
- Arrival time 2.363 (1 lvl)
+ ub_lvds_rx/reg3_syn_185.q[1] clk2q 0.109 r 2.047
+ ub_lvds_rx/ramread0_syn_102.d[1] (ub_lvds_rx/para_data[27]) net (fanout = 2) 0.225 r 2.272 encrypted_text(0)
+ ub_lvds_rx/ramread0_syn_102 path2reg 0.000 2.272
+ Arrival time 2.272 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/ramread0_syn_74.clk (ub_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.230
+ ub_lvds_rx/ramread0_syn_102.clk (ub_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.343
- clock uncertainty 0.000 2.343
- clock recovergence pessimism -0.093 2.250
- Required time 2.250
+ cell hold 0.113 2.243
+ clock uncertainty 0.000 2.243
+ clock recovergence pessimism -0.147 2.096
+ Required time 2.096
---------------------------------------------------------------------------------------------------------
- Slack 0.113ns
+ Slack 0.176ns
---------------------------------------------------------------------------------------------------------
@@ -2617,323 +2741,61 @@ Minimum period is 0ns
Timing constraint: clock: S_clk
Clock = S_clk, period 9.258ns, rising at 0ns, falling at 4.63ns
-8572 endpoints analyzed totally, and 111938 paths analyzed
+8640 endpoints analyzed totally, and 107786 paths analyzed
0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 9.15ns
+Minimum period is 9.05ns
---------------------------------------------------------------------------------------------------------
-Paths for end point reg7_syn_149 (188 paths)
+Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/add9_syn_86 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 0.108 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb (rising edge triggered by clock S_clk)
- End Point: reg7_syn_149.a[0] (rising edge triggered by clock S_clk)
+ Slack (setup check): 0.208 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/add9_syn_86.mi[0] (rising edge triggered by clock S_clk)
Clock group: clock_source
Process: Slow
- Data Path Delay: 8.970ns (logic 4.127ns, net 4.843ns, 46% logic)
- Logic Levels: 7 ( LUT5=5 LUT3=2 )
+ Data Path Delay: 1.833ns (logic 0.720ns, net 1.113ns, 39% logic)
+ Logic Levels: 1 ( LUT5=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge 0.000 2.410
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dob[2] clk2q 0.833 r 3.243
- adj_datao_b1[2]_syn_73.b[1] (sampling_fe_a/u_sort/u_data_prebuffer/dou_i[1][18]) net (fanout = 2) 1.170 r 4.413 ../../../../hg_mp/fe/prebuffer.v(279)
- adj_datao_b1[2]_syn_73.f[1] cell (LUT5) 0.431 r 4.844
- adj_datao_b1[2]_syn_79.a[1] (adj_datao_b1[2]_syn_16) net (fanout = 1) 0.689 r 5.533
- adj_datao_b1[2]_syn_79.f[1] cell (LUT3) 0.424 r 5.957
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_79.a[1] (adj_datao_b1[2]_syn_18) net (fanout = 1) 0.456 r 6.413
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_79.f[1] cell (LUT3) 0.424 r 6.837
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_488.a[1] (adj_datao_b1[2]_syn_32) net (fanout = 2) 0.608 r 7.445
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_488.fx[0] cell (LUT5) 0.618 r 8.063
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg10_syn_128.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[2]) net (fanout = 1) 0.567 r 8.630 ../../../../hg_mp/fe/read_ram_data.v(47)
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg10_syn_128.f[0] cell (LUT5) 0.431 r 9.061
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_59.a[0] (adj_datao_b1[2]_syn_39) net (fanout = 1) 0.615 r 9.676
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_59.f[0] cell (LUT5) 0.424 r 10.100
- reg7_syn_149.a[0] (adj_datao_b1[2]_syn_43) net (fanout = 1) 0.738 r 10.838 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1044)
- reg7_syn_149 path2reg0 (LUT5) 0.542 11.380
- Arrival time 11.380 (7 lvl)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.q[1] clk2q 0.146 r 2.422
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_49.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/raw_switch[0]) net (fanout = 14) 0.418 r 2.840 ../../../../hg_mp/fe/prebuffer_rev.v(272)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_49.f[0] cell (LUT5) 0.431 r 3.271
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/add9_syn_86.mi[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_13) net (fanout = 4) 0.695 r 3.966 ../../../../hg_mp/fe/prebuffer_rev.v(301)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/add9_syn_86 path2reg0 0.143 4.109
+ Arrival time 4.109 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- reg7_syn_149.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- capture clock edge 9.258 11.424
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/add9_syn_86.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ capture clock edge 2.267 4.433
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 11.308
- clock uncertainty -0.000 11.308
- clock recovergence pessimism 0.180 11.488
- Required time 11.488
+ cell setup -0.116 4.317
+ clock uncertainty -0.000 4.317
+ clock recovergence pessimism 0.000 4.317
+ Required time 4.317
---------------------------------------------------------------------------------------------------------
- Slack 0.108ns
+ Slack 0.208ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 0.108 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb (rising edge triggered by clock S_clk)
- End Point: reg7_syn_149.a[0] (rising edge triggered by clock S_clk)
- Clock group: clock_source
- Process: Slow
- Data Path Delay: 8.970ns (logic 4.127ns, net 4.843ns, 46% logic)
- Logic Levels: 7 ( LUT5=5 LUT3=2 )
-
- Point Type Incr Path Info
+Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2 (1 paths)
---------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge 0.000 2.410
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dob[2] clk2q 0.833 r 3.243
- adj_datao_b1[2]_syn_73.b[1] (sampling_fe_a/u_sort/u_data_prebuffer/dou_i[1][18]) net (fanout = 2) 1.170 r 4.413 ../../../../hg_mp/fe/prebuffer.v(279)
- adj_datao_b1[2]_syn_73.f[1] cell (LUT5) 0.431 r 4.844
- adj_datao_b1[2]_syn_79.a[1] (adj_datao_b1[2]_syn_16) net (fanout = 1) 0.689 r 5.533
- adj_datao_b1[2]_syn_79.f[1] cell (LUT3) 0.424 r 5.957
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_79.a[1] (adj_datao_b1[2]_syn_18) net (fanout = 1) 0.456 r 6.413
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_79.f[1] cell (LUT3) 0.424 r 6.837
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_488.a[0] (adj_datao_b1[2]_syn_32) net (fanout = 2) 0.608 r 7.445
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_488.fx[0] cell (LUT5) 0.618 r 8.063
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg10_syn_128.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[2]) net (fanout = 1) 0.567 r 8.630 ../../../../hg_mp/fe/read_ram_data.v(47)
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg10_syn_128.f[0] cell (LUT5) 0.431 r 9.061
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_59.a[0] (adj_datao_b1[2]_syn_39) net (fanout = 1) 0.615 r 9.676
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_59.f[0] cell (LUT5) 0.424 r 10.100
- reg7_syn_149.a[0] (adj_datao_b1[2]_syn_43) net (fanout = 1) 0.738 r 10.838 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1044)
- reg7_syn_149 path2reg0 (LUT5) 0.542 11.380
- Arrival time 11.380 (7 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- reg7_syn_149.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- capture clock edge 9.258 11.424
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 11.308
- clock uncertainty -0.000 11.308
- clock recovergence pessimism 0.180 11.488
- Required time 11.488
----------------------------------------------------------------------------------------------------------
- Slack 0.108ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check): 0.415 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb (rising edge triggered by clock S_clk)
- End Point: reg7_syn_149.a[0] (rising edge triggered by clock S_clk)
- Clock group: clock_source
- Process: Slow
- Data Path Delay: 8.663ns (logic 4.120ns, net 4.543ns, 47% logic)
- Logic Levels: 7 ( LUT5=5 LUT3=2 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge 0.000 2.410
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dob[2] clk2q 0.833 r 3.243
- adj_datao_b1[2]_syn_73.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/dou_i[0][18]) net (fanout = 2) 0.870 r 4.113 ../../../../hg_mp/fe/prebuffer.v(279)
- adj_datao_b1[2]_syn_73.f[1] cell (LUT5) 0.424 r 4.537
- adj_datao_b1[2]_syn_79.a[1] (adj_datao_b1[2]_syn_16) net (fanout = 1) 0.689 r 5.226
- adj_datao_b1[2]_syn_79.f[1] cell (LUT3) 0.424 r 5.650
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_79.a[1] (adj_datao_b1[2]_syn_18) net (fanout = 1) 0.456 r 6.106
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_79.f[1] cell (LUT3) 0.424 r 6.530
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_488.a[1] (adj_datao_b1[2]_syn_32) net (fanout = 2) 0.608 r 7.138
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_488.fx[0] cell (LUT5) 0.618 r 7.756
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg10_syn_128.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[2]) net (fanout = 1) 0.567 r 8.323 ../../../../hg_mp/fe/read_ram_data.v(47)
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg10_syn_128.f[0] cell (LUT5) 0.431 r 8.754
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_59.a[0] (adj_datao_b1[2]_syn_39) net (fanout = 1) 0.615 r 9.369
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_59.f[0] cell (LUT5) 0.424 r 9.793
- reg7_syn_149.a[0] (adj_datao_b1[2]_syn_43) net (fanout = 1) 0.738 r 10.531 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1044)
- reg7_syn_149 path2reg0 (LUT5) 0.542 11.073
- Arrival time 11.073 (7 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- reg7_syn_149.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- capture clock edge 9.258 11.424
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 11.308
- clock uncertainty -0.000 11.308
- clock recovergence pessimism 0.180 11.488
- Required time 11.488
----------------------------------------------------------------------------------------------------------
- Slack 0.415ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point reg7_syn_152 (114 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check): 0.309 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clkb (rising edge triggered by clock S_clk)
- End Point: reg7_syn_152.a[0] (rising edge triggered by clock S_clk)
- Clock group: clock_source
- Process: Slow
- Data Path Delay: 8.769ns (logic 3.926ns, net 4.843ns, 44% logic)
- Logic Levels: 7 ( LUT5=4 LUT4=3 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clkb (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge 0.000 2.410
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.dob[5] clk2q 0.833 r 3.243
- reg6_syn_164.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/dou_i[1][45]) net (fanout = 1) 0.852 r 4.095 ../../../../hg_mp/fe/prebuffer.v(279)
- reg6_syn_164.f[0] cell (LUT4) 0.431 r 4.526
- adj_datao_b1[21]_syn_70.a[1] (adj_datao_b1[21]_syn_22) net (fanout = 1) 0.918 r 5.444
- adj_datao_b1[21]_syn_70.f[1] cell (LUT4) 0.424 r 5.868
- u_bus_top/u_local_bus_slve_cis/sel23_syn_6787.a[0] (adj_datao_b1[21]_syn_26) net (fanout = 2) 0.794 r 6.662
- u_bus_top/u_local_bus_slve_cis/sel23_syn_6787.f[0] cell (LUT4) 0.424 r 7.086
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_491.a[0] (adj_datao_b1[5]_syn_20) net (fanout = 1) 0.468 r 7.554
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_491.f[0] cell (LUT5) 0.424 r 7.978
- u_bus_top/reg15_syn_186.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[5]) net (fanout = 1) 0.672 r 8.650 ../../../../hg_mp/fe/read_ram_data.v(47)
- u_bus_top/reg15_syn_186.f[1] cell (LUT5) 0.424 r 9.074
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_56.a[1] (adj_datao_b1[5]_syn_27) net (fanout = 1) 0.468 r 9.542
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_56.f[1] cell (LUT5) 0.424 r 9.966
- reg7_syn_152.a[0] (adj_datao_b1[5]_syn_31) net (fanout = 1) 0.671 r 10.637 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1044)
- reg7_syn_152 path2reg0 (LUT5) 0.542 11.179
- Arrival time 11.179 (7 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- reg7_syn_152.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- capture clock edge 9.258 11.424
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 11.308
- clock uncertainty -0.000 11.308
- clock recovergence pessimism 0.180 11.488
- Required time 11.488
----------------------------------------------------------------------------------------------------------
- Slack 0.309ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check): 0.591 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb (rising edge triggered by clock S_clk)
- End Point: reg7_syn_152.a[0] (rising edge triggered by clock S_clk)
- Clock group: clock_source
- Process: Slow
- Data Path Delay: 8.487ns (logic 3.764ns, net 4.723ns, 44% logic)
- Logic Levels: 7 ( LUT5=4 LUT4=2 LUT3=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge 0.000 2.410
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dob[5] clk2q 0.833 r 3.243
- clkmipi_rstn_reg_syn_13.d[0] (sampling_fe_a/u_sort/u_data_prebuffer/dou_i[0][21]) net (fanout = 1) 0.673 r 3.916 ../../../../hg_mp/fe/prebuffer.v(279)
- clkmipi_rstn_reg_syn_13.f[0] cell (LUT3) 0.262 r 4.178
- adj_datao_b1[21]_syn_70.b[1] (adj_datao_b1[21]_syn_24) net (fanout = 1) 0.977 r 5.155
- adj_datao_b1[21]_syn_70.f[1] cell (LUT4) 0.431 r 5.586
- u_bus_top/u_local_bus_slve_cis/sel23_syn_6787.a[0] (adj_datao_b1[21]_syn_26) net (fanout = 2) 0.794 r 6.380
- u_bus_top/u_local_bus_slve_cis/sel23_syn_6787.f[0] cell (LUT4) 0.424 r 6.804
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_491.a[0] (adj_datao_b1[5]_syn_20) net (fanout = 1) 0.468 r 7.272
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_491.f[0] cell (LUT5) 0.424 r 7.696
- u_bus_top/reg15_syn_186.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[5]) net (fanout = 1) 0.672 r 8.368 ../../../../hg_mp/fe/read_ram_data.v(47)
- u_bus_top/reg15_syn_186.f[1] cell (LUT5) 0.424 r 8.792
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_56.a[1] (adj_datao_b1[5]_syn_27) net (fanout = 1) 0.468 r 9.260
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_56.f[1] cell (LUT5) 0.424 r 9.684
- reg7_syn_152.a[0] (adj_datao_b1[5]_syn_31) net (fanout = 1) 0.671 r 10.355 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1044)
- reg7_syn_152 path2reg0 (LUT5) 0.542 10.897
- Arrival time 10.897 (7 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- reg7_syn_152.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- capture clock edge 9.258 11.424
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 11.308
- clock uncertainty -0.000 11.308
- clock recovergence pessimism 0.180 11.488
- Required time 11.488
----------------------------------------------------------------------------------------------------------
- Slack 0.591ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check): 0.607 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst_syn_1.clkb (rising edge triggered by clock S_clk)
- End Point: reg7_syn_152.a[0] (rising edge triggered by clock S_clk)
- Clock group: clock_source
- Process: Slow
- Data Path Delay: 8.471ns (logic 3.919ns, net 4.552ns, 46% logic)
- Logic Levels: 7 ( LUT5=4 LUT4=3 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst_syn_1.clkb (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge 0.000 2.410
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst_syn_1.dob[5] clk2q 0.833 r 3.243
- reg6_syn_164.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/dou_i[0][45]) net (fanout = 1) 0.561 r 3.804 ../../../../hg_mp/fe/prebuffer.v(279)
- reg6_syn_164.f[0] cell (LUT4) 0.424 r 4.228
- adj_datao_b1[21]_syn_70.a[1] (adj_datao_b1[21]_syn_22) net (fanout = 1) 0.918 r 5.146
- adj_datao_b1[21]_syn_70.f[1] cell (LUT4) 0.424 r 5.570
- u_bus_top/u_local_bus_slve_cis/sel23_syn_6787.a[0] (adj_datao_b1[21]_syn_26) net (fanout = 2) 0.794 r 6.364
- u_bus_top/u_local_bus_slve_cis/sel23_syn_6787.f[0] cell (LUT4) 0.424 r 6.788
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_491.a[0] (adj_datao_b1[5]_syn_20) net (fanout = 1) 0.468 r 7.256
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_491.f[0] cell (LUT5) 0.424 r 7.680
- u_bus_top/reg15_syn_186.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[5]) net (fanout = 1) 0.672 r 8.352 ../../../../hg_mp/fe/read_ram_data.v(47)
- u_bus_top/reg15_syn_186.f[1] cell (LUT5) 0.424 r 8.776
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_56.a[1] (adj_datao_b1[5]_syn_27) net (fanout = 1) 0.468 r 9.244
- sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_56.f[1] cell (LUT5) 0.424 r 9.668
- reg7_syn_152.a[0] (adj_datao_b1[5]_syn_31) net (fanout = 1) 0.671 r 10.339 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1044)
- reg7_syn_152 path2reg0 (LUT5) 0.542 10.881
- Arrival time 10.881 (7 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- reg7_syn_152.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- capture clock edge 9.258 11.424
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 11.308
- clock uncertainty -0.000 11.308
- clock recovergence pessimism 0.180 11.488
- Required time 11.488
----------------------------------------------------------------------------------------------------------
- Slack 0.607ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_97 (1 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check): 0.353 ns
+ Slack (setup check): 0.279 ns
Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk (rising edge triggered by clock a_pclk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_97.mi[0] (rising edge triggered by clock S_clk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2.mi[0] (rising edge triggered by clock S_clk)
Clock group: clock_source
Process: Slow
- Data Path Delay: 1.688ns (logic 0.720ns, net 0.968ns, 42% logic)
+ Data Path Delay: 1.762ns (logic 0.720ns, net 1.042ns, 40% logic)
Logic Levels: 1 ( LUT5=1 )
Point Type Incr Path Info
@@ -2946,17 +2808,17 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_97 (1 paths)
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.q[1] clk2q 0.146 r 2.422
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_75.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0]) net (fanout = 14) 0.257 r 2.679 ../../../../hg_mp/fe/prebuffer.v(268)
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_75.f[0] cell (LUT5) 0.431 r 3.110
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_97.mi[0] (sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13) net (fanout = 7) 0.711 r 3.821 ../../../../hg_mp/fe/prebuffer.v(297)
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_97 path2reg0 0.143 3.964
- Arrival time 3.964 (1 lvl)
+ sampling_fe_a/u_sort/u_transfer_300_to_200/data_f_b4_n87_syn_28.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0]) net (fanout = 14) 0.528 r 2.950 ../../../../hg_mp/fe/prebuffer.v(272)
+ sampling_fe_a/u_sort/u_transfer_300_to_200/data_f_b4_n87_syn_28.f[0] cell (LUT5) 0.431 r 3.381
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2.mi[0] (sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13) net (fanout = 12) 0.514 r 3.895 ../../../../hg_mp/fe/prebuffer.v(301)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2 path2reg0 0.143 4.038
+ Arrival time 4.038 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_97.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
capture clock edge 2.267 4.433
---------------------------------------------------------------------------------------------------------
cell setup -0.116 4.317
@@ -2964,97 +2826,19 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_97 (1 paths)
clock recovergence pessimism 0.000 4.317
Required time 4.317
---------------------------------------------------------------------------------------------------------
- Slack 0.353ns
+ Slack 0.279ns
---------------------------------------------------------------------------------------------------------
-Hold checks:
+Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2 (1 paths)
---------------------------------------------------------------------------------------------------------
-Paths for end point u_mipi_sot_min/reg1_syn_265 (1 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.067 ns
- Start Point: u_bus_top/reg19_syn_84.clk (rising edge triggered by clock clk_adc)
- End Point: u_mipi_sot_min/reg1_syn_265.mi[1] (rising edge triggered by clock S_clk)
+ Slack (setup check): 0.279 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2.mi[1] (rising edge triggered by clock S_clk)
Clock group: clock_source
- Process: Fast
- Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[4] 0.000 0.000
- u_bus_top/reg19_syn_84.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4)
- launch clock edge 0.000 1.938
----------------------------------------------------------------------------------------------------------
- u_bus_top/reg19_syn_84.q[1] clk2q 0.109 r 2.047
- u_mipi_sot_min/reg1_syn_265.mi[1] (u_mipi_sot_min/signal_from[3]) net (fanout = 1) 0.216 r 2.263 ../../../../hg_mp/cdc/cdc_sync.v(9)
- u_mipi_sot_min/reg1_syn_265 path2reg1 0.095 2.358
- Arrival time 2.358 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- u_mipi_sot_min/reg1_syn_265.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- capture clock edge 0.000 2.230
----------------------------------------------------------------------------------------------------------
- cell hold 0.061 2.291
- clock uncertainty 0.000 2.291
- clock recovergence pessimism 0.000 2.291
- Required time 2.291
----------------------------------------------------------------------------------------------------------
- Slack 0.067ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point u_mipi_sot_min/reg1_syn_283 (1 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.067 ns
- Start Point: u_bus_top/reg18_syn_72.clk (rising edge triggered by clock clk_adc)
- End Point: u_mipi_sot_min/reg1_syn_283.mi[1] (rising edge triggered by clock S_clk)
- Clock group: clock_source
- Process: Fast
- Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[4] 0.000 0.000
- u_bus_top/reg18_syn_72.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4)
- launch clock edge 0.000 1.938
----------------------------------------------------------------------------------------------------------
- u_bus_top/reg18_syn_72.q[0] clk2q 0.109 r 2.047
- u_mipi_sot_min/reg1_syn_283.mi[1] (u_mipi_sot_min/signal_from[2]) net (fanout = 1) 0.216 r 2.263 ../../../../hg_mp/cdc/cdc_sync.v(9)
- u_mipi_sot_min/reg1_syn_283 path2reg1 0.095 2.358
- Arrival time 2.358 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- u_mipi_sot_min/reg1_syn_283.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- capture clock edge 0.000 2.230
----------------------------------------------------------------------------------------------------------
- cell hold 0.061 2.291
- clock uncertainty 0.000 2.291
- clock recovergence pessimism 0.000 2.291
- Required time 2.291
----------------------------------------------------------------------------------------------------------
- Slack 0.067ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point reg13_syn_43 (1 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.075 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/channelPart/wr_end_reg_syn_8.clk (rising edge triggered by clock a_pclk)
- End Point: reg13_syn_43.mi[0] (rising edge triggered by clock S_clk)
- Clock group: clock_source
- Process: Fast
- Data Path Delay: 0.428ns (logic 0.204ns, net 0.224ns, 47% logic)
- Logic Levels: 0
+ Process: Slow
+ Data Path Delay: 1.762ns (logic 0.720ns, net 1.042ns, 40% logic)
+ Logic Levels: 1 ( LUT5=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -3062,19 +2846,61 @@ Paths for end point reg13_syn_43 (1 paths)
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/channelPart/wr_end_reg_syn_8.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 1.938
+ sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/channelPart/wr_end_reg_syn_8.q[0] clk2q 0.109 r 2.047
- reg13_syn_43.mi[0] (sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/u0_rdsoft_n/signal_from[0]) net (fanout = 7) 0.224 r 2.271 ../../../../hg_mp/cdc/cdc_sync.v(9)
- reg13_syn_43 path2reg0 0.095 2.366
- Arrival time 2.366 (0 lvl)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.q[1] clk2q 0.146 r 2.422
+ sampling_fe_a/u_sort/u_transfer_300_to_200/data_f_b4_n87_syn_28.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0]) net (fanout = 14) 0.528 r 2.950 ../../../../hg_mp/fe/prebuffer.v(272)
+ sampling_fe_a/u_sort/u_transfer_300_to_200/data_f_b4_n87_syn_28.f[0] cell (LUT5) 0.431 r 3.381
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2.mi[1] (sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13) net (fanout = 12) 0.514 r 3.895 ../../../../hg_mp/fe/prebuffer.v(301)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2 path2reg1 0.143 4.038
+ Arrival time 4.038 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- reg13_syn_43.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ capture clock edge 2.267 4.433
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.116 4.317
+ clock uncertainty -0.000 4.317
+ clock recovergence pessimism 0.000 4.317
+ Required time 4.317
+---------------------------------------------------------------------------------------------------------
+ Slack 0.279ns
+
+---------------------------------------------------------------------------------------------------------
+
+Hold checks:
+---------------------------------------------------------------------------------------------------------
+Paths for end point u_mipi_eot_min/reg1_syn_275 (1 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.067 ns
+ Start Point: u_bus_top/reg18_syn_74.clk (rising edge triggered by clock clk_adc)
+ End Point: u_mipi_eot_min/reg1_syn_275.mi[1] (rising edge triggered by clock S_clk)
+ Clock group: clock_source
+ Process: Fast
+ Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[4] 0.000 0.000
+ u_bus_top/reg18_syn_74.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ u_bus_top/reg18_syn_74.q[1] clk2q 0.109 r 2.047
+ u_mipi_eot_min/reg1_syn_275.mi[1] (u_mipi_eot_min/signal_from[1]) net (fanout = 1) 0.216 r 2.263 ../../../../hg_mp/cdc/cdc_sync.v(9)
+ u_mipi_eot_min/reg1_syn_275 path2reg1 0.095 2.358
+ Arrival time 2.358 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ u_mipi_eot_min/reg1_syn_275.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
cell hold 0.061 2.291
@@ -3082,20 +2908,138 @@ Paths for end point reg13_syn_43 (1 paths)
clock recovergence pessimism 0.000 2.291
Required time 2.291
---------------------------------------------------------------------------------------------------------
- Slack 0.075ns
+ Slack 0.067ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point add0_syn_146 (1 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.067 ns
+ Start Point: reg36_syn_118.clk (rising edge triggered by clock clk_adc)
+ End Point: add0_syn_146.mi[0] (rising edge triggered by clock S_clk)
+ Clock group: clock_source
+ Process: Fast
+ Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[4] 0.000 0.000
+ reg36_syn_118.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ reg36_syn_118.q[1] clk2q 0.109 r 2.047
+ add0_syn_146.mi[0] (u_pic_cnt/signal_from[9]) net (fanout = 2) 0.216 r 2.263 ../../../../hg_mp/cdc/cdc_sync.v(9)
+ add0_syn_146 path2reg0 0.095 2.358
+ Arrival time 2.358 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ add0_syn_146.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ capture clock edge 0.000 2.230
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.061 2.291
+ clock uncertainty 0.000 2.291
+ clock recovergence pessimism 0.000 2.291
+ Required time 2.291
+---------------------------------------------------------------------------------------------------------
+ Slack 0.067ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point u_pic_cnt/reg1_syn_465 (1 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.067 ns
+ Start Point: reg36_syn_130.clk (rising edge triggered by clock clk_adc)
+ End Point: u_pic_cnt/reg1_syn_465.mi[0] (rising edge triggered by clock S_clk)
+ Clock group: clock_source
+ Process: Fast
+ Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[4] 0.000 0.000
+ reg36_syn_130.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ reg36_syn_130.q[0] clk2q 0.109 r 2.047
+ u_pic_cnt/reg1_syn_465.mi[0] (u_pic_cnt/signal_from[4]) net (fanout = 2) 0.216 r 2.263 ../../../../hg_mp/cdc/cdc_sync.v(9)
+ u_pic_cnt/reg1_syn_465 path2reg0 0.095 2.358
+ Arrival time 2.358 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ u_pic_cnt/reg1_syn_465.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ capture clock edge 0.000 2.230
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.061 2.291
+ clock uncertainty 0.000 2.291
+ clock recovergence pessimism 0.000 2.291
+ Required time 2.291
+---------------------------------------------------------------------------------------------------------
+ Slack 0.067ns
---------------------------------------------------------------------------------------------------------
Recovery checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070 (2 paths)
+Paths for end point U_rgb_to_csi_pakage/reg10_syn_53_syn_2 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (recovery check): 5.584 ns
+ Slack (recovery check): 5.512 ns
Start Point: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
- End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070.sr (rising edge triggered by clock S_clk)
+ End Point: U_rgb_to_csi_pakage/reg10_syn_53_syn_2.sr (rising edge triggered by clock S_clk)
Clock group: clock_source
Process: Slow
- Data Path Delay: 3.310ns (logic 0.699ns, net 2.611ns, 21% logic)
+ Data Path Delay: 3.382ns (logic 0.494ns, net 2.888ns, 14% logic)
+ Logic Levels: 1 ( LUT2=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge 0.000 2.410
+---------------------------------------------------------------------------------------------------------
+ U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0] clk2q 0.146 r 2.556
+ U_rgb_to_csi_pakage/S_frame_start_delay_n_edge_1d_reg_syn_6_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.892 r 3.448 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
+ U_rgb_to_csi_pakage/S_frame_start_delay_n_edge_1d_reg_syn_6_syn_2.f[0] cell (LUT2) 0.205 r 3.653
+ U_rgb_to_csi_pakage/reg10_syn_53_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n_dup_1) net (fanout = 10) 1.996 r 5.649 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
+ U_rgb_to_csi_pakage/reg10_syn_53_syn_2 path2reg 0.143 5.792
+ Arrival time 5.792 (1 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ U_rgb_to_csi_pakage/reg10_syn_53_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ capture clock edge 9.258 11.424
+---------------------------------------------------------------------------------------------------------
+ cell recovery -0.300 11.124
+ clock uncertainty -0.000 11.124
+ clock recovergence pessimism 0.180 11.304
+ Required time 11.304
+---------------------------------------------------------------------------------------------------------
+ Slack 5.512ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2 (2 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (recovery check): 5.735 ns
+ Start Point: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
+ End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2.sr (rising edge triggered by clock S_clk)
+ Clock group: clock_source
+ Process: Slow
+ Data Path Delay: 3.159ns (logic 0.756ns, net 2.403ns, 23% logic)
Logic Levels: 2 ( LUT2=2 )
Point Type Incr Path Info
@@ -3108,19 +3052,19 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0] clk2q 0.146 r 2.556
- reg21_syn_52_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.378 r 2.934 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
- reg21_syn_52_syn_2.f[0] cell (LUT2) 0.262 r 3.196
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.d[0] (U_rgb_to_csi_pakage/S_rst_n) net (fanout = 29) 0.751 r 3.947 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.f[0] cell (LUT2) 0.205 r 4.152
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net (fanout = 18) 1.482 r 5.634 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070 path2reg 0.086 5.720
- Arrival time 5.720 (2 lvl)
+ reg20_syn_64_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.530 r 3.086 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
+ reg20_syn_64_syn_2.f[0] cell (LUT2) 0.262 r 3.348
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_620.d[0] (U_rgb_to_csi_pakage/S_rst_n_dup_5) net (fanout = 26) 0.727 r 4.075 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_620.f[0] cell (LUT2) 0.262 r 4.337
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst) net (fanout = 16) 1.146 r 5.483 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2 path2reg 0.086 5.569
+ Arrival time 5.569 (2 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
capture clock edge 9.258 11.424
---------------------------------------------------------------------------------------------------------
cell recovery -0.300 11.124
@@ -3128,16 +3072,16 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070
clock recovergence pessimism 0.180 11.304
Required time 11.304
---------------------------------------------------------------------------------------------------------
- Slack 5.584ns
+ Slack 5.735ns
---------------------------------------------------------------------------------------------------------
- Slack (recovery check): 5.858 ns
+ Slack (recovery check): 6.339 ns
Start Point: adj_vsynco_reg_syn_5.clk (rising edge triggered by clock S_clk)
- End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070.sr (rising edge triggered by clock S_clk)
+ End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2.sr (rising edge triggered by clock S_clk)
Clock group: clock_source
Process: Slow
- Data Path Delay: 3.036ns (logic 0.483ns, net 2.553ns, 15% logic)
+ Data Path Delay: 2.555ns (logic 0.580ns, net 1.975ns, 22% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
@@ -3149,18 +3093,18 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070
adj_vsynco_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- adj_vsynco_reg_syn_5.q[1] clk2q 0.146 r 2.556
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.c[0] (U_rgb_to_csi_pakage/I_rgb_vsync) net (fanout = 10) 1.071 r 3.627 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.f[0] cell (LUT2) 0.251 r 3.878
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net (fanout = 18) 1.482 r 5.360 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070 path2reg 0.086 5.446
- Arrival time 5.446 (1 lvl)
+ adj_vsynco_reg_syn_5.q[0] clk2q 0.146 r 2.556
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_620.c[0] (U_rgb_to_csi_pakage/I_rgb_vsync) net (fanout = 7) 0.829 r 3.385 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_620.f[0] cell (LUT2) 0.348 r 3.733
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst) net (fanout = 16) 1.146 r 4.879 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2 path2reg 0.086 4.965
+ Arrival time 4.965 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
capture clock edge 9.258 11.424
---------------------------------------------------------------------------------------------------------
cell recovery -0.300 11.124
@@ -3168,19 +3112,19 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070
clock recovergence pessimism 0.180 11.304
Required time 11.304
---------------------------------------------------------------------------------------------------------
- Slack 5.858ns
+ Slack 6.339ns
---------------------------------------------------------------------------------------------------------
-Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2 (2 paths)
+Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284 (2 paths)
---------------------------------------------------------------------------------------------------------
- Slack (recovery check): 6.014 ns
+ Slack (recovery check): 5.754 ns
Start Point: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
- End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2.sr (rising edge triggered by clock S_clk)
+ End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.sr (rising edge triggered by clock S_clk)
Clock group: clock_source
Process: Slow
- Data Path Delay: 2.880ns (logic 0.699ns, net 2.181ns, 24% logic)
- Logic Levels: 2 ( LUT2=2 )
+ Data Path Delay: 3.140ns (logic 0.699ns, net 2.441ns, 22% logic)
+ Logic Levels: 2 ( LUT4=1 LUT2=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -3192,19 +3136,19 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0] clk2q 0.146 r 2.556
- reg21_syn_52_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.378 r 2.934 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
- reg21_syn_52_syn_2.f[0] cell (LUT2) 0.262 r 3.196
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.d[0] (U_rgb_to_csi_pakage/S_rst_n) net (fanout = 29) 0.751 r 3.947 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.f[0] cell (LUT2) 0.205 r 4.152
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net (fanout = 18) 1.052 r 5.204 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2 path2reg 0.086 5.290
- Arrival time 5.290 (2 lvl)
+ reg20_syn_64_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.530 r 3.086 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
+ reg20_syn_64_syn_2.f[0] cell (LUT2) 0.262 r 3.348
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_34_syn_2.d[1] (U_rgb_to_csi_pakage/S_rst_n_dup_5) net (fanout = 26) 0.874 r 4.222 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_34_syn_2.f[1] cell (LUT4) 0.205 r 4.427
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net (fanout = 17) 1.037 r 5.464 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284 path2reg 0.086 5.550
+ Arrival time 5.550 (2 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
capture clock edge 9.258 11.424
---------------------------------------------------------------------------------------------------------
cell recovery -0.300 11.124
@@ -3212,17 +3156,17 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_
clock recovergence pessimism 0.180 11.304
Required time 11.304
---------------------------------------------------------------------------------------------------------
- Slack 6.014ns
+ Slack 5.754ns
---------------------------------------------------------------------------------------------------------
- Slack (recovery check): 6.288 ns
+ Slack (recovery check): 6.319 ns
Start Point: adj_vsynco_reg_syn_5.clk (rising edge triggered by clock S_clk)
- End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2.sr (rising edge triggered by clock S_clk)
+ End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.sr (rising edge triggered by clock S_clk)
Clock group: clock_source
Process: Slow
- Data Path Delay: 2.606ns (logic 0.483ns, net 2.123ns, 18% logic)
- Logic Levels: 1 ( LUT2=1 )
+ Data Path Delay: 2.575ns (logic 0.483ns, net 2.092ns, 18% logic)
+ Logic Levels: 1 ( LUT4=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -3233,18 +3177,18 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_
adj_vsynco_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- adj_vsynco_reg_syn_5.q[1] clk2q 0.146 r 2.556
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.c[0] (U_rgb_to_csi_pakage/I_rgb_vsync) net (fanout = 10) 1.071 r 3.627 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.f[0] cell (LUT2) 0.251 r 3.878
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net (fanout = 18) 1.052 r 4.930 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2 path2reg 0.086 5.016
- Arrival time 5.016 (1 lvl)
+ adj_vsynco_reg_syn_5.q[0] clk2q 0.146 r 2.556
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_34_syn_2.c[1] (U_rgb_to_csi_pakage/I_rgb_vsync) net (fanout = 7) 1.055 r 3.611 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_34_syn_2.f[1] cell (LUT4) 0.251 r 3.862
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net (fanout = 17) 1.037 r 4.899 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284 path2reg 0.086 4.985
+ Arrival time 4.985 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
capture clock edge 9.258 11.424
---------------------------------------------------------------------------------------------------------
cell recovery -0.300 11.124
@@ -3252,104 +3196,20 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_
clock recovergence pessimism 0.180 11.304
Required time 11.304
---------------------------------------------------------------------------------------------------------
- Slack 6.288ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2 (2 paths)
----------------------------------------------------------------------------------------------------------
- Slack (recovery check): 6.026 ns
- Start Point: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
- End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2.sr (rising edge triggered by clock S_clk)
- Clock group: clock_source
- Process: Slow
- Data Path Delay: 2.868ns (logic 0.699ns, net 2.169ns, 24% logic)
- Logic Levels: 2 ( LUT2=2 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge 0.000 2.410
----------------------------------------------------------------------------------------------------------
- U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0] clk2q 0.146 r 2.556
- reg21_syn_52_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.378 r 2.934 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
- reg21_syn_52_syn_2.f[0] cell (LUT2) 0.262 r 3.196
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.d[0] (U_rgb_to_csi_pakage/S_rst_n) net (fanout = 29) 0.751 r 3.947 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.f[0] cell (LUT2) 0.205 r 4.152
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net (fanout = 18) 1.040 r 5.192 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2 path2reg 0.086 5.278
- Arrival time 5.278 (2 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- capture clock edge 9.258 11.424
----------------------------------------------------------------------------------------------------------
- cell recovery -0.300 11.124
- clock uncertainty -0.000 11.124
- clock recovergence pessimism 0.180 11.304
- Required time 11.304
----------------------------------------------------------------------------------------------------------
- Slack 6.026ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (recovery check): 6.300 ns
- Start Point: adj_vsynco_reg_syn_5.clk (rising edge triggered by clock S_clk)
- End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2.sr (rising edge triggered by clock S_clk)
- Clock group: clock_source
- Process: Slow
- Data Path Delay: 2.594ns (logic 0.483ns, net 2.111ns, 18% logic)
- Logic Levels: 1 ( LUT2=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- adj_vsynco_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge 0.000 2.410
----------------------------------------------------------------------------------------------------------
- adj_vsynco_reg_syn_5.q[1] clk2q 0.146 r 2.556
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.c[0] (U_rgb_to_csi_pakage/I_rgb_vsync) net (fanout = 10) 1.071 r 3.627 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.f[0] cell (LUT2) 0.251 r 3.878
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net (fanout = 18) 1.040 r 4.918 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2 path2reg 0.086 5.004
- Arrival time 5.004 (1 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- capture clock edge 9.258 11.424
----------------------------------------------------------------------------------------------------------
- cell recovery -0.300 11.124
- clock uncertainty -0.000 11.124
- clock recovergence pessimism 0.180 11.304
- Required time 11.304
----------------------------------------------------------------------------------------------------------
- Slack 6.300ns
+ Slack 6.319ns
---------------------------------------------------------------------------------------------------------
Removal checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point U_rgb_to_csi_pakage/reg7_syn_145_syn_2 (1 paths)
+Paths for end point U_rgb_to_csi_pakage/reg12_syn_73_syn_2 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (removal check): 0.773 ns
+ Slack (removal check): 0.685 ns
Start Point: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
- End Point: U_rgb_to_csi_pakage/reg7_syn_145_syn_2.sr (rising edge triggered by clock S_clk)
+ End Point: U_rgb_to_csi_pakage/reg12_syn_73_syn_2.sr (rising edge triggered by clock S_clk)
Clock group: clock_source
Process: Fast
- Data Path Delay: 1.071ns (logic 0.375ns, net 0.696ns, 35% logic)
+ Data Path Delay: 0.967ns (logic 0.375ns, net 0.592ns, 38% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
@@ -3362,36 +3222,36 @@ Paths for end point U_rgb_to_csi_pakage/reg7_syn_145_syn_2 (1 paths)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0] clk2q 0.109 r 2.138
- reg21_syn_54_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.355 r 2.493 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
- reg21_syn_54_syn_2.f[0] cell (LUT2) 0.179 r 2.672
- U_rgb_to_csi_pakage/reg7_syn_145_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n_dup_4) net (fanout = 36) 0.341 r 3.013 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
- U_rgb_to_csi_pakage/reg7_syn_145_syn_2 path2reg 0.087 3.100
- Arrival time 3.100 (1 lvl)
+ reg20_syn_54_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.240 r 2.378 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
+ reg20_syn_54_syn_2.f[0] cell (LUT2) 0.179 r 2.557
+ U_rgb_to_csi_pakage/reg12_syn_73_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n_dup_2) net (fanout = 20) 0.352 r 2.909 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
+ U_rgb_to_csi_pakage/reg12_syn_73_syn_2 path2reg 0.087 2.996
+ Arrival time 2.996 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- U_rgb_to_csi_pakage/reg7_syn_145_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ U_rgb_to_csi_pakage/reg12_syn_73_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
cell removal 0.253 2.483
clock uncertainty 0.000 2.483
- clock recovergence pessimism -0.156 2.327
- Required time 2.327
+ clock recovergence pessimism -0.172 2.311
+ Required time 2.311
---------------------------------------------------------------------------------------------------------
- Slack 0.773ns
+ Slack 0.685ns
---------------------------------------------------------------------------------------------------------
-Paths for end point U_rgb_to_csi_pakage/reg13_syn_67_syn_2 (1 paths)
+Paths for end point U_rgb_to_csi_pakage/reg12_syn_69_syn_2 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (removal check): 0.775 ns
+ Slack (removal check): 0.685 ns
Start Point: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
- End Point: U_rgb_to_csi_pakage/reg13_syn_67_syn_2.sr (rising edge triggered by clock S_clk)
+ End Point: U_rgb_to_csi_pakage/reg12_syn_69_syn_2.sr (rising edge triggered by clock S_clk)
Clock group: clock_source
Process: Fast
- Data Path Delay: 1.073ns (logic 0.375ns, net 0.698ns, 34% logic)
+ Data Path Delay: 0.967ns (logic 0.375ns, net 0.592ns, 38% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
@@ -3404,36 +3264,36 @@ Paths for end point U_rgb_to_csi_pakage/reg13_syn_67_syn_2 (1 paths)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0] clk2q 0.109 r 2.138
- reg21_syn_52_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.240 r 2.378 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
- reg21_syn_52_syn_2.f[0] cell (LUT2) 0.179 r 2.557
- U_rgb_to_csi_pakage/reg13_syn_67_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n) net (fanout = 29) 0.458 r 3.015 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
- U_rgb_to_csi_pakage/reg13_syn_67_syn_2 path2reg 0.087 3.102
- Arrival time 3.102 (1 lvl)
+ reg20_syn_54_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.240 r 2.378 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
+ reg20_syn_54_syn_2.f[0] cell (LUT2) 0.179 r 2.557
+ U_rgb_to_csi_pakage/reg12_syn_69_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n_dup_2) net (fanout = 20) 0.352 r 2.909 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
+ U_rgb_to_csi_pakage/reg12_syn_69_syn_2 path2reg 0.087 2.996
+ Arrival time 2.996 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- U_rgb_to_csi_pakage/reg13_syn_67_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ U_rgb_to_csi_pakage/reg12_syn_69_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
cell removal 0.253 2.483
clock uncertainty 0.000 2.483
- clock recovergence pessimism -0.156 2.327
- Required time 2.327
+ clock recovergence pessimism -0.172 2.311
+ Required time 2.311
---------------------------------------------------------------------------------------------------------
- Slack 0.775ns
+ Slack 0.685ns
---------------------------------------------------------------------------------------------------------
-Paths for end point U_rgb_to_csi_pakage/reg13_syn_79_syn_2 (1 paths)
+Paths for end point U_rgb_to_csi_pakage/reg7_syn_151_syn_2 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (removal check): 0.805 ns
+ Slack (removal check): 0.781 ns
Start Point: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
- End Point: U_rgb_to_csi_pakage/reg13_syn_79_syn_2.sr (rising edge triggered by clock S_clk)
+ End Point: U_rgb_to_csi_pakage/reg7_syn_151_syn_2.sr (rising edge triggered by clock S_clk)
Clock group: clock_source
Process: Fast
- Data Path Delay: 1.103ns (logic 0.375ns, net 0.728ns, 33% logic)
+ Data Path Delay: 1.079ns (logic 0.375ns, net 0.704ns, 34% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
@@ -3446,17 +3306,17 @@ Paths for end point U_rgb_to_csi_pakage/reg13_syn_79_syn_2 (1 paths)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0] clk2q 0.109 r 2.138
- reg21_syn_52_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.240 r 2.378 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
- reg21_syn_52_syn_2.f[0] cell (LUT2) 0.179 r 2.557
- U_rgb_to_csi_pakage/reg13_syn_79_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n) net (fanout = 29) 0.488 r 3.045 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
- U_rgb_to_csi_pakage/reg13_syn_79_syn_2 path2reg 0.087 3.132
- Arrival time 3.132 (1 lvl)
+ reg20_syn_54_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.240 r 2.378 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
+ reg20_syn_54_syn_2.f[0] cell (LUT2) 0.179 r 2.557
+ U_rgb_to_csi_pakage/reg7_syn_151_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n_dup_2) net (fanout = 20) 0.464 r 3.021 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
+ U_rgb_to_csi_pakage/reg7_syn_151_syn_2 path2reg 0.087 3.108
+ Arrival time 3.108 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- U_rgb_to_csi_pakage/reg13_syn_79_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ U_rgb_to_csi_pakage/reg7_syn_151_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
cell removal 0.253 2.483
@@ -3464,7 +3324,7 @@ Paths for end point U_rgb_to_csi_pakage/reg13_syn_79_syn_2 (1 paths)
clock recovergence pessimism -0.156 2.327
Required time 2.327
---------------------------------------------------------------------------------------------------------
- Slack 0.805ns
+ Slack 0.781ns
---------------------------------------------------------------------------------------------------------
@@ -3472,91 +3332,91 @@ Period checks:
---------------------------------------------------------------------------------------------------------
Point Type Setting(ns) Requied(ns) Slack(ns)
---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.clkb min period 9.258 3.400 5.858
sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst_syn_1.clkb min period 9.258 3.400 5.858
sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst_syn_1.clkb min period 9.258 3.400 5.858
sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst_syn_1.clkb min period 9.258 3.400 5.858
sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.clkb min period 9.258 3.400 5.858
sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst_syn_1.clkb min period 9.258 3.400 5.858
sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst_syn_1.clkb min period 9.258 3.400 5.858
sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst_syn_1.clkb min period 9.258 3.400 5.858
sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.clkb min period 9.258 3.400 5.858
sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst_syn_1.clkb min period 9.258 3.400 5.858
sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst_syn_1.clkb min period 9.258 3.400 5.858
sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst_syn_1.clkb min period 9.258 3.400 5.858
sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst_syn_1.clkb min period 9.258 3.400 5.858
sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1.clkb min period 9.258 3.400 5.858
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1.clkb min period 9.258 3.400 5.858
sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb min period 9.258 3.400 5.858
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst_syn_1.clkb min period 9.258 3.400 5.858
sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst_syn_1.clkb min period 9.258 3.400 5.858
sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.clkb min period 9.258 3.400 5.858
sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1.clkb min period 9.258 3.400 5.858
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw min period 9.258 3.300 5.958
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw min period 9.258 3.300 5.958
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw min period 9.258 3.300 5.958
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw min period 9.258 3.300 5.958
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw min period 9.258 3.300 5.958
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw min period 9.258 3.300 5.958
=========================================================================================================
Timing constraint: clock: clk_adc
Clock = clk_adc, period 166.664ns, rising at 0ns, falling at 83.332ns
-4282 endpoints analyzed totally, and 45638 paths analyzed
-3 errors detected : 3 setup errors (TNS = -3.307), 0 hold errors (TNS = 0.000)
-Minimum period is 168.461ns
+4240 endpoints analyzed totally, and 43224 paths analyzed
+3 errors detected : 3 setup errors (TNS = -3.279), 0 hold errors (TNS = 0.000)
+Minimum period is 168.609ns
---------------------------------------------------------------------------------------------------------
-Paths for end point reg40_syn_14 (2 paths)
+Paths for end point reg40_syn_12 (2 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): -1.797 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk (rising edge triggered by clock S_clk_x2)
- End Point: reg40_syn_14.mi[0] (rising edge triggered by clock clk_adc)
+ Slack (setup check): -1.945 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add18_syn_70.clk (rising edge triggered by clock S_clk_x2)
+ End Point: reg40_syn_12.mi[1] (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Slow
- Data Path Delay: 1.336ns (logic 0.540ns, net 0.796ns, 40% logic)
+ Data Path Delay: 1.484ns (logic 0.494ns, net 0.990ns, 33% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add18_syn_70.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.q[0] clk2q 0.146 r 2.556
- reg29_syn_16.c[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d) net (fanout = 3) 0.489 r 3.045 encrypted_text(0)
- reg29_syn_16.f[0] cell (LUT2) 0.251 r 3.296
- reg40_syn_14.mi[0] (O_clk_lp_n_dup_1) net (fanout = 2) 0.307 r 3.603 ../../../../hg_mp/drx_top/huagao_mipi_top.v(42)
- reg40_syn_14 path2reg0 0.143 3.746
- Arrival time 3.746 (1 lvl)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add18_syn_70.q[0] clk2q 0.146 r 2.556
+ reg29_syn_13.d[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d) net (fanout = 1) 0.683 r 3.239 encrypted_text(0)
+ reg29_syn_13.f[0] cell (LUT2) 0.205 r 3.444
+ reg40_syn_12.mi[1] (O_clk_lp_n_dup_1) net (fanout = 2) 0.307 r 3.751 ../../../../hg_mp/drx_top/huagao_mipi_top.v(42)
+ reg40_syn_12 path2reg1 0.143 3.894
+ Arrival time 3.894 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
- reg40_syn_14.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ reg40_syn_12.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4)
capture clock edge 0.020 2.065
---------------------------------------------------------------------------------------------------------
cell setup -0.116 1.949
@@ -3564,35 +3424,35 @@ Paths for end point reg40_syn_14 (2 paths)
clock recovergence pessimism 0.000 1.949
Required time 1.949
---------------------------------------------------------------------------------------------------------
- Slack -1.797ns
+ Slack -1.945ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): -1.738 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk (rising edge triggered by clock S_clk_x2)
- End Point: reg40_syn_14.mi[0] (rising edge triggered by clock clk_adc)
+ Slack (setup check): -1.844 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1_syn_69.clk (rising edge triggered by clock S_clk_x2)
+ End Point: reg40_syn_12.mi[1] (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Slow
- Data Path Delay: 1.277ns (logic 0.494ns, net 0.783ns, 38% logic)
+ Data Path Delay: 1.383ns (logic 0.540ns, net 0.843ns, 39% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1_syn_69.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.q[1] clk2q 0.146 r 2.556
- reg29_syn_16.d[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d) net (fanout = 1) 0.476 r 3.032 encrypted_text(0)
- reg29_syn_16.f[0] cell (LUT2) 0.205 r 3.237
- reg40_syn_14.mi[0] (O_clk_lp_n_dup_1) net (fanout = 2) 0.307 r 3.544 ../../../../hg_mp/drx_top/huagao_mipi_top.v(42)
- reg40_syn_14 path2reg0 0.143 3.687
- Arrival time 3.687 (1 lvl)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1_syn_69.q[0] clk2q 0.146 r 2.556
+ reg29_syn_13.c[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d) net (fanout = 3) 0.536 r 3.092 encrypted_text(0)
+ reg29_syn_13.f[0] cell (LUT2) 0.251 r 3.343
+ reg40_syn_12.mi[1] (O_clk_lp_n_dup_1) net (fanout = 2) 0.307 r 3.650 ../../../../hg_mp/drx_top/huagao_mipi_top.v(42)
+ reg40_syn_12 path2reg1 0.143 3.793
+ Arrival time 3.793 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
- reg40_syn_14.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ reg40_syn_12.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4)
capture clock edge 0.020 2.065
---------------------------------------------------------------------------------------------------------
cell setup -0.116 1.949
@@ -3600,35 +3460,35 @@ Paths for end point reg40_syn_14 (2 paths)
clock recovergence pessimism 0.000 1.949
Required time 1.949
---------------------------------------------------------------------------------------------------------
- Slack -1.738ns
+ Slack -1.844ns
---------------------------------------------------------------------------------------------------------
-Paths for end point reg41_syn_15 (1 paths)
+Paths for end point reg40_syn_12 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): -1.510 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk (rising edge triggered by clock S_clk_x2)
- End Point: reg41_syn_15.mi[0] (rising edge triggered by clock clk_adc)
+ Slack (setup check): -1.334 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1_syn_69.clk (rising edge triggered by clock S_clk_x2)
+ End Point: reg40_syn_12.mi[0] (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Slow
- Data Path Delay: 1.049ns (logic 0.289ns, net 0.760ns, 27% logic)
+ Data Path Delay: 0.873ns (logic 0.289ns, net 0.584ns, 33% logic)
Logic Levels: 0
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1_syn_69.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.q[0] clk2q 0.146 r 2.556
- reg41_syn_15.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d) net (fanout = 3) 0.760 r 3.316 encrypted_text(0)
- reg41_syn_15 path2reg0 0.143 3.459
- Arrival time 3.459 (0 lvl)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1_syn_69.q[0] clk2q 0.146 r 2.556
+ reg40_syn_12.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d) net (fanout = 3) 0.584 r 3.140 encrypted_text(0)
+ reg40_syn_12 path2reg0 0.143 3.283
+ Arrival time 3.283 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
- reg41_syn_15.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ reg40_syn_12.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4)
capture clock edge 0.020 2.065
---------------------------------------------------------------------------------------------------------
cell setup -0.116 1.949
@@ -3636,18 +3496,18 @@ Paths for end point reg41_syn_15 (1 paths)
clock recovergence pessimism 0.000 1.949
Required time 1.949
---------------------------------------------------------------------------------------------------------
- Slack -1.510ns
+ Slack -1.334ns
---------------------------------------------------------------------------------------------------------
-Paths for end point u_bus_top/reg13_syn_216 (1 paths)
+Paths for end point u_bus_top/reg15_syn_166 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 6.926 ns
- Start Point: reg26_syn_241.clk (rising edge triggered by clock S_clk)
- End Point: u_bus_top/reg13_syn_216.mi[0] (rising edge triggered by clock clk_adc)
+ Slack (setup check): 7.526 ns
+ Start Point: reg27_syn_214.clk (rising edge triggered by clock S_clk)
+ End Point: u_bus_top/reg15_syn_166.mi[1] (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Slow
- Data Path Delay: 1.851ns (logic 0.289ns, net 1.562ns, 15% logic)
+ Data Path Delay: 1.251ns (logic 0.289ns, net 0.962ns, 23% logic)
Logic Levels: 0
Point Type Incr Path Info
@@ -3656,17 +3516,17 @@ Paths for end point u_bus_top/reg13_syn_216 (1 paths)
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- reg26_syn_241.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ reg27_syn_214.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- reg26_syn_241.q[1] clk2q 0.146 r 2.556
- u_bus_top/reg13_syn_216.mi[0] (lv_cnt_a[31]) net (fanout = 3) 1.562 r 4.118 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1071)
- u_bus_top/reg13_syn_216 path2reg0 0.143 4.261
- Arrival time 4.261 (0 lvl)
+ reg27_syn_214.q[1] clk2q 0.146 r 2.556
+ u_bus_top/reg15_syn_166.mi[1] (lv_cnt_b[12]) net (fanout = 4) 0.962 r 3.518 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1072)
+ u_bus_top/reg15_syn_166 path2reg1 0.143 3.661
+ Arrival time 3.661 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
- u_bus_top/reg13_syn_216.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ u_bus_top/reg15_syn_166.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4)
capture clock edge 9.258 11.303
---------------------------------------------------------------------------------------------------------
cell setup -0.116 11.187
@@ -3674,53 +3534,17 @@ Paths for end point u_bus_top/reg13_syn_216 (1 paths)
clock recovergence pessimism 0.000 11.187
Required time 11.187
---------------------------------------------------------------------------------------------------------
- Slack 6.926ns
+ Slack 7.526ns
---------------------------------------------------------------------------------------------------------
Hold checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point u_bus_top/reg5_syn_190 (1 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.251 ns
- Start Point: u_bus_top/reg4_syn_178.clk (rising edge triggered by clock clk_adc)
- End Point: u_bus_top/reg5_syn_190.mi[0] (rising edge triggered by clock clk_adc)
- Clock group: clock_source
- Process: Fast
- Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[4] 0.000 0.000
- u_bus_top/reg4_syn_178.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4)
- launch clock edge 0.000 1.938
----------------------------------------------------------------------------------------------------------
- u_bus_top/reg4_syn_178.q[1] clk2q 0.109 r 2.047
- u_bus_top/reg5_syn_190.mi[0] (u_bus_top/adc_cfg_data_o_sync2d_8m[2]) net (fanout = 2) 0.216 r 2.263 ../../../../hg_mp/local_bus/ubus_top.v(94)
- u_bus_top/reg5_syn_190 path2reg0 0.095 2.358
- Arrival time 2.358 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[4] 0.000 0.000
- u_bus_top/reg5_syn_190.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
- capture clock edge 0.000 2.130
----------------------------------------------------------------------------------------------------------
- cell hold 0.061 2.191
- clock uncertainty 0.000 2.191
- clock recovergence pessimism -0.084 2.107
- Required time 2.107
----------------------------------------------------------------------------------------------------------
- Slack 0.251ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point u_bus_top/reg0_syn_220 (1 paths)
+Paths for end point u_bus_top/reg9_syn_165 (1 paths)
---------------------------------------------------------------------------------------------------------
Slack (hold check): 0.258 ns
- Start Point: reg1_syn_184.clk (rising edge triggered by clock S_clk)
- End Point: u_bus_top/reg0_syn_220.mi[1] (rising edge triggered by clock clk_adc)
+ Start Point: reg25_syn_115.clk (rising edge triggered by clock S_clk)
+ End Point: u_bus_top/reg9_syn_165.mi[1] (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Fast
Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic)
@@ -3732,17 +3556,17 @@ Paths for end point u_bus_top/reg0_syn_220 (1 paths)
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- reg1_syn_184.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ reg25_syn_115.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- reg1_syn_184.q[1] clk2q 0.109 r 2.138
- u_bus_top/reg0_syn_220.mi[1] (S_hs_data_reg[19]) net (fanout = 1) 0.216 r 2.354 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1274)
- u_bus_top/reg0_syn_220 path2reg1 0.095 2.449
+ reg25_syn_115.q[1] clk2q 0.109 r 2.138
+ u_bus_top/reg9_syn_165.mi[1] (lv_cnt2bus[6]) net (fanout = 1) 0.216 r 2.354 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1273)
+ u_bus_top/reg9_syn_165 path2reg1 0.095 2.449
Arrival time 2.449 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
- u_bus_top/reg0_syn_220.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ u_bus_top/reg9_syn_165.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell hold 0.061 2.191
@@ -3754,11 +3578,11 @@ Paths for end point u_bus_top/reg0_syn_220 (1 paths)
---------------------------------------------------------------------------------------------------------
-Paths for end point u_bus_top/reg0_syn_217 (1 paths)
+Paths for end point u_bus_top/reg9_syn_165 (1 paths)
---------------------------------------------------------------------------------------------------------
Slack (hold check): 0.258 ns
- Start Point: reg1_syn_181.clk (rising edge triggered by clock S_clk)
- End Point: u_bus_top/reg0_syn_217.mi[0] (rising edge triggered by clock clk_adc)
+ Start Point: reg25_syn_127.clk (rising edge triggered by clock S_clk)
+ End Point: u_bus_top/reg9_syn_165.mi[0] (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Fast
Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic)
@@ -3770,17 +3594,55 @@ Paths for end point u_bus_top/reg0_syn_217 (1 paths)
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- reg1_syn_181.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ reg25_syn_127.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- reg1_syn_181.q[0] clk2q 0.109 r 2.138
- u_bus_top/reg0_syn_217.mi[0] (S_hs_data_reg[25]) net (fanout = 1) 0.216 r 2.354 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1274)
- u_bus_top/reg0_syn_217 path2reg0 0.095 2.449
+ reg25_syn_127.q[1] clk2q 0.109 r 2.138
+ u_bus_top/reg9_syn_165.mi[0] (lv_cnt2bus[8]) net (fanout = 1) 0.216 r 2.354 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1273)
+ u_bus_top/reg9_syn_165 path2reg0 0.095 2.449
Arrival time 2.449 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
- u_bus_top/reg0_syn_217.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ u_bus_top/reg9_syn_165.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.061 2.191
+ clock uncertainty 0.000 2.191
+ clock recovergence pessimism 0.000 2.191
+ Required time 2.191
+---------------------------------------------------------------------------------------------------------
+ Slack 0.258ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point u_bus_top/reg9_syn_152 (1 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.258 ns
+ Start Point: reg25_syn_133.clk (rising edge triggered by clock S_clk)
+ End Point: u_bus_top/reg9_syn_152.mi[1] (rising edge triggered by clock clk_adc)
+ Clock group: clock_source
+ Process: Fast
+ Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ reg25_syn_133.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge 0.000 2.029
+---------------------------------------------------------------------------------------------------------
+ reg25_syn_133.q[0] clk2q 0.109 r 2.138
+ u_bus_top/reg9_syn_152.mi[1] (lv_cnt2bus[3]) net (fanout = 1) 0.216 r 2.354 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1273)
+ u_bus_top/reg9_syn_152 path2reg1 0.095 2.449
+ Arrival time 2.449 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[4] 0.000 0.000
+ u_bus_top/reg9_syn_152.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell hold 0.061 2.191
@@ -3794,14 +3656,14 @@ Paths for end point u_bus_top/reg0_syn_217 (1 paths)
Recovery checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point scan_start_diff/a_ex_frame_en_reg_syn_5 (1 paths)
+Paths for end point scan_start_diff/reg2_syn_21 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (recovery check): 163.286 ns
+ Slack (recovery check): 161.807 ns
Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc)
- End Point: scan_start_diff/a_ex_frame_en_reg_syn_5.sr (rising edge triggered by clock clk_adc)
+ End Point: scan_start_diff/reg2_syn_21.sr (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Slow
- Data Path Delay: 3.014ns (logic 0.551ns, net 2.463ns, 18% logic)
+ Data Path Delay: 4.421ns (logic 0.551ns, net 3.870ns, 12% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
@@ -3812,34 +3674,72 @@ Paths for end point scan_start_diff/a_ex_frame_en_reg_syn_5 (1 paths)
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
clkubus_rstn_reg_syn_8.q[0] clk2q 0.146 r 2.422
- u_bus_top/u_local_bus_slve_cis/reg59_syn_113.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 15) 1.734 r 4.156 ../../../../hg_mp/cdc/cdc_sync.v(9)
- u_bus_top/u_local_bus_slve_cis/reg59_syn_113.f[0] cell (LUT2) 0.262 r 4.418
- scan_start_diff/a_ex_frame_en_reg_syn_5.sr (BUSY_MIPI_sync_d0_i_syn_8) net (fanout = 3) 0.729 r 5.147 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
- scan_start_diff/a_ex_frame_en_reg_syn_5 path2reg 0.143 5.290
- Arrival time 5.290 (1 lvl)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 14) 3.051 r 5.473 ../../../../hg_mp/cdc/cdc_sync.v(9)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.262 r 5.735
+ scan_start_diff/reg2_syn_21.sr (BUSY_MIPI_sync_d0_i_syn_9) net (fanout = 16) 0.819 r 6.554 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
+ scan_start_diff/reg2_syn_21 path2reg 0.143 6.697
+ Arrival time 6.697 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
- scan_start_diff/a_ex_frame_en_reg_syn_5.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ scan_start_diff/reg2_syn_21.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4)
capture clock edge 166.664 168.709
---------------------------------------------------------------------------------------------------------
cell recovery -0.300 168.409
clock uncertainty -0.000 168.409
- clock recovergence pessimism 0.167 168.576
- Required time 168.576
+ clock recovergence pessimism 0.095 168.504
+ Required time 168.504
---------------------------------------------------------------------------------------------------------
- Slack 163.286ns
+ Slack 161.807ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_data_tmp[53]_syn_20 (1 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (recovery check): 161.807 ns
+ Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_data_tmp[53]_syn_20.sr (rising edge triggered by clock clk_adc)
+ Clock group: clock_source
+ Process: Slow
+ Data Path Delay: 4.421ns (logic 0.551ns, net 3.870ns, 12% logic)
+ Logic Levels: 1 ( LUT2=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[4] 0.000 0.000
+ clkubus_rstn_reg_syn_8.clk (exdev_ctl_a/clk_adc) net 2.276 2.276 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ launch clock edge 0.000 2.276
+---------------------------------------------------------------------------------------------------------
+ clkubus_rstn_reg_syn_8.q[0] clk2q 0.146 r 2.422
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 14) 3.051 r 5.473 ../../../../hg_mp/cdc/cdc_sync.v(9)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.262 r 5.735
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_data_tmp[53]_syn_20.sr (BUSY_MIPI_sync_d0_i_syn_9) net (fanout = 16) 0.819 r 6.554 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_data_tmp[53]_syn_20 path2reg 0.143 6.697
+ Arrival time 6.697 (1 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[4] 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_data_tmp[53]_syn_20.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ capture clock edge 166.664 168.709
+---------------------------------------------------------------------------------------------------------
+ cell recovery -0.300 168.409
+ clock uncertainty -0.000 168.409
+ clock recovergence pessimism 0.095 168.504
+ Required time 168.504
+---------------------------------------------------------------------------------------------------------
+ Slack 161.807ns
---------------------------------------------------------------------------------------------------------
Paths for end point scan_start_diff/reg2_syn_19 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (recovery check): 163.371 ns
+ Slack (recovery check): 161.970 ns
Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc)
End Point: scan_start_diff/reg2_syn_19.sr (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Slow
- Data Path Delay: 2.929ns (logic 0.494ns, net 2.435ns, 16% logic)
+ Data Path Delay: 4.258ns (logic 0.551ns, net 3.707ns, 12% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
@@ -3850,11 +3750,11 @@ Paths for end point scan_start_diff/reg2_syn_19 (1 paths)
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
clkubus_rstn_reg_syn_8.q[0] clk2q 0.146 r 2.422
- scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 15) 1.524 r 3.946 ../../../../hg_mp/cdc/cdc_sync.v(9)
- scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.205 r 4.151
- scan_start_diff/reg2_syn_19.sr (BUSY_MIPI_sync_d0_i_syn_6) net (fanout = 9) 0.911 r 5.062 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
- scan_start_diff/reg2_syn_19 path2reg 0.143 5.205
- Arrival time 5.205 (1 lvl)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 14) 3.051 r 5.473 ../../../../hg_mp/cdc/cdc_sync.v(9)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.262 r 5.735
+ scan_start_diff/reg2_syn_19.sr (BUSY_MIPI_sync_d0_i_syn_9) net (fanout = 16) 0.656 r 6.391 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
+ scan_start_diff/reg2_syn_19 path2reg 0.143 6.534
+ Arrival time 6.534 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
@@ -3863,61 +3763,23 @@ Paths for end point scan_start_diff/reg2_syn_19 (1 paths)
---------------------------------------------------------------------------------------------------------
cell recovery -0.300 168.409
clock uncertainty -0.000 168.409
- clock recovergence pessimism 0.167 168.576
- Required time 168.576
+ clock recovergence pessimism 0.095 168.504
+ Required time 168.504
---------------------------------------------------------------------------------------------------------
- Slack 163.371ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point scan_start_diff/a_ex_frame_reg_syn_5 (1 paths)
----------------------------------------------------------------------------------------------------------
- Slack (recovery check): 163.489 ns
- Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc)
- End Point: scan_start_diff/a_ex_frame_reg_syn_5.sr (rising edge triggered by clock clk_adc)
- Clock group: clock_source
- Process: Slow
- Data Path Delay: 2.811ns (logic 0.494ns, net 2.317ns, 17% logic)
- Logic Levels: 1 ( LUT2=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[4] 0.000 0.000
- clkubus_rstn_reg_syn_8.clk (exdev_ctl_a/clk_adc) net 2.276 2.276 ../../../../hg_mp/fe/exdev_ctl.v(4)
- launch clock edge 0.000 2.276
----------------------------------------------------------------------------------------------------------
- clkubus_rstn_reg_syn_8.q[0] clk2q 0.146 r 2.422
- scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 15) 1.524 r 3.946 ../../../../hg_mp/cdc/cdc_sync.v(9)
- scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.205 r 4.151
- scan_start_diff/a_ex_frame_reg_syn_5.sr (BUSY_MIPI_sync_d0_i_syn_6) net (fanout = 9) 0.793 r 4.944 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
- scan_start_diff/a_ex_frame_reg_syn_5 path2reg 0.143 5.087
- Arrival time 5.087 (1 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[4] 0.000 0.000
- scan_start_diff/a_ex_frame_reg_syn_5.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4)
- capture clock edge 166.664 168.709
----------------------------------------------------------------------------------------------------------
- cell recovery -0.300 168.409
- clock uncertainty -0.000 168.409
- clock recovergence pessimism 0.167 168.576
- Required time 168.576
----------------------------------------------------------------------------------------------------------
- Slack 163.489ns
+ Slack 161.970ns
---------------------------------------------------------------------------------------------------------
Removal checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point scan_start_diff/reg1_syn_18 (1 paths)
+Paths for end point scan_start_diff/a_ex_frame_reg_syn_5 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (removal check): 1.456 ns
+ Slack (removal check): 2.526 ns
Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc)
- End Point: scan_start_diff/reg1_syn_18.sr (rising edge triggered by clock clk_adc)
+ End Point: scan_start_diff/a_ex_frame_reg_syn_5.sr (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Fast
- Data Path Delay: 1.754ns (logic 0.322ns, net 1.432ns, 18% logic)
+ Data Path Delay: 2.887ns (logic 0.375ns, net 2.512ns, 12% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
@@ -3928,34 +3790,34 @@ Paths for end point scan_start_diff/reg1_syn_18 (1 paths)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
clkubus_rstn_reg_syn_8.q[0] clk2q 0.109 r 2.047
- scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 15) 1.091 r 3.138 ../../../../hg_mp/cdc/cdc_sync.v(9)
- scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.126 r 3.264
- scan_start_diff/reg1_syn_18.sr (BUSY_MIPI_sync_d0_i_syn_6) net (fanout = 9) 0.341 r 3.605 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
- scan_start_diff/reg1_syn_18 path2reg 0.087 3.692
- Arrival time 3.692 (1 lvl)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 14) 2.171 r 4.218 ../../../../hg_mp/cdc/cdc_sync.v(9)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.179 r 4.397
+ scan_start_diff/a_ex_frame_reg_syn_5.sr (BUSY_MIPI_sync_d0_i_syn_9) net (fanout = 16) 0.341 r 4.738 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
+ scan_start_diff/a_ex_frame_reg_syn_5 path2reg 0.087 4.825
+ Arrival time 4.825 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
- scan_start_diff/reg1_syn_18.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ scan_start_diff/a_ex_frame_reg_syn_5.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell removal 0.253 2.383
clock uncertainty 0.000 2.383
- clock recovergence pessimism -0.147 2.236
- Required time 2.236
+ clock recovergence pessimism -0.084 2.299
+ Required time 2.299
---------------------------------------------------------------------------------------------------------
- Slack 1.456ns
+ Slack 2.526ns
---------------------------------------------------------------------------------------------------------
-Paths for end point scan_start_diff/reg1_syn_21 (1 paths)
+Paths for end point scan_start_diff/a_ex_frame_en_reg_syn_5 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (removal check): 1.562 ns
+ Slack (removal check): 2.537 ns
Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc)
- End Point: scan_start_diff/reg1_syn_21.sr (rising edge triggered by clock clk_adc)
+ End Point: scan_start_diff/a_ex_frame_en_reg_syn_5.sr (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Fast
- Data Path Delay: 1.860ns (logic 0.322ns, net 1.538ns, 17% logic)
+ Data Path Delay: 2.898ns (logic 0.375ns, net 2.523ns, 12% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
@@ -3966,34 +3828,34 @@ Paths for end point scan_start_diff/reg1_syn_21 (1 paths)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
clkubus_rstn_reg_syn_8.q[0] clk2q 0.109 r 2.047
- scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 15) 1.091 r 3.138 ../../../../hg_mp/cdc/cdc_sync.v(9)
- scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.126 r 3.264
- scan_start_diff/reg1_syn_21.sr (BUSY_MIPI_sync_d0_i_syn_6) net (fanout = 9) 0.447 r 3.711 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
- scan_start_diff/reg1_syn_21 path2reg 0.087 3.798
- Arrival time 3.798 (1 lvl)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 14) 2.171 r 4.218 ../../../../hg_mp/cdc/cdc_sync.v(9)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.179 r 4.397
+ scan_start_diff/a_ex_frame_en_reg_syn_5.sr (BUSY_MIPI_sync_d0_i_syn_9) net (fanout = 16) 0.352 r 4.749 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
+ scan_start_diff/a_ex_frame_en_reg_syn_5 path2reg 0.087 4.836
+ Arrival time 4.836 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
- scan_start_diff/reg1_syn_21.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ scan_start_diff/a_ex_frame_en_reg_syn_5.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell removal 0.253 2.383
clock uncertainty 0.000 2.383
- clock recovergence pessimism -0.147 2.236
- Required time 2.236
+ clock recovergence pessimism -0.084 2.299
+ Required time 2.299
---------------------------------------------------------------------------------------------------------
- Slack 1.562ns
+ Slack 2.537ns
---------------------------------------------------------------------------------------------------------
-Paths for end point scan_start_diff/enable_from_arm_rog_reg_syn_5 (1 paths)
+Paths for end point scan_start_diff/reg2_syn_19 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (removal check): 1.579 ns
+ Slack (removal check): 2.627 ns
Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc)
- End Point: scan_start_diff/enable_from_arm_rog_reg_syn_5.sr (rising edge triggered by clock clk_adc)
+ End Point: scan_start_diff/reg2_syn_19.sr (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Fast
- Data Path Delay: 1.877ns (logic 0.322ns, net 1.555ns, 17% logic)
+ Data Path Delay: 2.988ns (logic 0.375ns, net 2.613ns, 12% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
@@ -4004,23 +3866,23 @@ Paths for end point scan_start_diff/enable_from_arm_rog_reg_syn_5 (1 paths)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
clkubus_rstn_reg_syn_8.q[0] clk2q 0.109 r 2.047
- scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 15) 1.091 r 3.138 ../../../../hg_mp/cdc/cdc_sync.v(9)
- scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.126 r 3.264
- scan_start_diff/enable_from_arm_rog_reg_syn_5.sr (BUSY_MIPI_sync_d0_i_syn_6) net (fanout = 9) 0.464 r 3.728 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
- scan_start_diff/enable_from_arm_rog_reg_syn_5 path2reg 0.087 3.815
- Arrival time 3.815 (1 lvl)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 14) 2.171 r 4.218 ../../../../hg_mp/cdc/cdc_sync.v(9)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.179 r 4.397
+ scan_start_diff/reg2_syn_19.sr (BUSY_MIPI_sync_d0_i_syn_9) net (fanout = 16) 0.442 r 4.839 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
+ scan_start_diff/reg2_syn_19 path2reg 0.087 4.926
+ Arrival time 4.926 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
- scan_start_diff/enable_from_arm_rog_reg_syn_5.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ scan_start_diff/reg2_syn_19.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell removal 0.253 2.383
clock uncertainty 0.000 2.383
- clock recovergence pessimism -0.147 2.236
- Required time 2.236
+ clock recovergence pessimism -0.084 2.299
+ Required time 2.299
---------------------------------------------------------------------------------------------------------
- Slack 1.579ns
+ Slack 2.627ns
---------------------------------------------------------------------------------------------------------
@@ -4029,19 +3891,19 @@ Paths for end point scan_start_diff/enable_from_arm_rog_reg_syn_5 (1 paths)
Timing constraint: clock: S_clk_x2
Clock = S_clk_x2, period 4.629ns, rising at 0ns, falling at 2.314ns
-78 endpoints analyzed totally, and 144 paths analyzed
+80 endpoints analyzed totally, and 146 paths analyzed
0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 2.179ns
+Minimum period is 2.561ns
---------------------------------------------------------------------------------------------------------
-Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 (2 paths)
+Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 (2 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 2.450 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add12_syn_69.clk (rising edge triggered by clock S_clk)
- End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.b[0] (rising edge triggered by clock S_clk_x2)
+ Slack (setup check): 2.068 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add32_syn_70.clk (rising edge triggered by clock S_clk)
+ End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[0] (rising edge triggered by clock S_clk_x2)
Clock group: clock_source
Process: Slow
- Data Path Delay: 1.819ns (logic 0.695ns, net 1.124ns, 38% logic)
+ Data Path Delay: 2.201ns (logic 0.695ns, net 1.506ns, 31% logic)
Logic Levels: 1 ( LUT3=1 )
Point Type Incr Path Info
@@ -4050,17 +3912,17 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapp
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add12_syn_69.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add32_syn_70.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add12_syn_69.q[1] clk2q 0.146 r 2.556
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.b[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[1]) net (fanout = 1) 1.124 r 3.680 encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 path2reg0 (LUT3) 0.549 4.229
- Arrival time 4.229 (1 lvl)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add32_syn_70.q[0] clk2q 0.146 r 2.556
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0]) net (fanout = 1) 1.506 r 4.062 encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 path2reg0 (LUT3) 0.549 4.611
+ Arrival time 4.611 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
capture clock edge 4.629 6.795
---------------------------------------------------------------------------------------------------------
cell setup -0.116 6.679
@@ -4068,16 +3930,16 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapp
clock recovergence pessimism 0.000 6.679
Required time 6.679
---------------------------------------------------------------------------------------------------------
- Slack 2.450ns
+ Slack 2.068ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 2.457 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add29_syn_70.clk (rising edge triggered by clock S_clk)
- End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.c[0] (rising edge triggered by clock S_clk_x2)
+ Slack (setup check): 2.526 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.clk (rising edge triggered by clock S_clk)
+ End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[0] (rising edge triggered by clock S_clk_x2)
Clock group: clock_source
Process: Slow
- Data Path Delay: 1.812ns (logic 0.612ns, net 1.200ns, 33% logic)
+ Data Path Delay: 1.743ns (logic 0.612ns, net 1.131ns, 35% logic)
Logic Levels: 1 ( LUT3=1 )
Point Type Incr Path Info
@@ -4086,17 +3948,17 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapp
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add29_syn_70.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add29_syn_70.q[0] clk2q 0.146 r 2.556
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.c[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[5]) net (fanout = 1) 1.200 r 3.756 encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 path2reg0 (LUT3) 0.466 4.222
- Arrival time 4.222 (1 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.q[1] clk2q 0.146 r 2.556
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4]) net (fanout = 1) 1.131 r 3.687 encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 path2reg0 (LUT3) 0.466 4.153
+ Arrival time 4.153 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
capture clock edge 4.629 6.795
---------------------------------------------------------------------------------------------------------
cell setup -0.116 6.679
@@ -4104,18 +3966,18 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapp
clock recovergence pessimism 0.000 6.679
Required time 6.679
---------------------------------------------------------------------------------------------------------
- Slack 2.457ns
+ Slack 2.526ns
---------------------------------------------------------------------------------------------------------
-Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2 (2 paths)
+Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 (2 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 2.518 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk (rising edge triggered by clock S_clk)
- End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.b[1] (rising edge triggered by clock S_clk_x2)
+ Slack (setup check): 2.297 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_39_syn_2.clk (rising edge triggered by clock S_clk)
+ End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[1] (rising edge triggered by clock S_clk_x2)
Clock group: clock_source
Process: Slow
- Data Path Delay: 1.751ns (logic 0.695ns, net 1.056ns, 39% logic)
+ Data Path Delay: 1.972ns (logic 0.695ns, net 1.277ns, 35% logic)
Logic Levels: 1 ( LUT3=1 )
Point Type Incr Path Info
@@ -4124,17 +3986,17 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapp
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_39_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.q[1] clk2q 0.146 r 2.556
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.b[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3]) net (fanout = 1) 1.056 r 3.612 encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2 path2reg1 (LUT3) 0.549 4.161
- Arrival time 4.161 (1 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_39_syn_2.q[0] clk2q 0.146 r 2.556
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[1]) net (fanout = 1) 1.277 r 3.833 encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 path2reg1 (LUT3) 0.549 4.382
+ Arrival time 4.382 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
capture clock edge 4.629 6.795
---------------------------------------------------------------------------------------------------------
cell setup -0.116 6.679
@@ -4142,16 +4004,16 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapp
clock recovergence pessimism 0.000 6.679
Required time 6.679
---------------------------------------------------------------------------------------------------------
- Slack 2.518ns
+ Slack 2.297ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 2.611 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk (rising edge triggered by clock S_clk)
- End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.c[1] (rising edge triggered by clock S_clk_x2)
+ Slack (setup check): 2.367 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_43_syn_2.clk (rising edge triggered by clock S_clk)
+ End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[1] (rising edge triggered by clock S_clk_x2)
Clock group: clock_source
Process: Slow
- Data Path Delay: 1.658ns (logic 0.612ns, net 1.046ns, 36% logic)
+ Data Path Delay: 1.902ns (logic 0.612ns, net 1.290ns, 32% logic)
Logic Levels: 1 ( LUT3=1 )
Point Type Incr Path Info
@@ -4160,17 +4022,17 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapp
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_43_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.q[0] clk2q 0.146 r 2.556
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.c[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[7]) net (fanout = 1) 1.046 r 3.602 encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2 path2reg1 (LUT3) 0.466 4.068
- Arrival time 4.068 (1 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_43_syn_2.q[1] clk2q 0.146 r 2.556
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[5]) net (fanout = 1) 1.290 r 3.846 encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 path2reg1 (LUT3) 0.466 4.312
+ Arrival time 4.312 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
capture clock edge 4.629 6.795
---------------------------------------------------------------------------------------------------------
cell setup -0.116 6.679
@@ -4178,18 +4040,18 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapp
clock recovergence pessimism 0.000 6.679
Required time 6.679
---------------------------------------------------------------------------------------------------------
- Slack 2.611ns
+ Slack 2.367ns
---------------------------------------------------------------------------------------------------------
-Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2 (2 paths)
+Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 (2 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 2.518 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_35_syn_2.clk (rising edge triggered by clock S_clk)
- End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.b[0] (rising edge triggered by clock S_clk_x2)
+ Slack (setup check): 2.443 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47.clk (rising edge triggered by clock S_clk)
+ End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.b[0] (rising edge triggered by clock S_clk_x2)
Clock group: clock_source
Process: Slow
- Data Path Delay: 1.751ns (logic 0.695ns, net 1.056ns, 39% logic)
+ Data Path Delay: 1.826ns (logic 0.695ns, net 1.131ns, 38% logic)
Logic Levels: 1 ( LUT3=1 )
Point Type Incr Path Info
@@ -4198,17 +4060,17 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapp
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_35_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_35_syn_2.q[1] clk2q 0.146 r 2.556
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.b[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0]) net (fanout = 1) 1.056 r 3.612 encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2 path2reg0 (LUT3) 0.549 4.161
- Arrival time 4.161 (1 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47.q[0] clk2q 0.146 r 2.556
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.b[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[2]) net (fanout = 1) 1.131 r 3.687 encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 path2reg0 (LUT3) 0.549 4.236
+ Arrival time 4.236 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
capture clock edge 4.629 6.795
---------------------------------------------------------------------------------------------------------
cell setup -0.116 6.679
@@ -4216,16 +4078,16 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapp
clock recovergence pessimism 0.000 6.679
Required time 6.679
---------------------------------------------------------------------------------------------------------
- Slack 2.518ns
+ Slack 2.443ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 2.761 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_43_syn_2.clk (rising edge triggered by clock S_clk)
- End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.c[0] (rising edge triggered by clock S_clk_x2)
+ Slack (setup check): 2.532 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk (rising edge triggered by clock S_clk)
+ End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.c[0] (rising edge triggered by clock S_clk_x2)
Clock group: clock_source
Process: Slow
- Data Path Delay: 1.508ns (logic 0.612ns, net 0.896ns, 40% logic)
+ Data Path Delay: 1.737ns (logic 0.612ns, net 1.125ns, 35% logic)
Logic Levels: 1 ( LUT3=1 )
Point Type Incr Path Info
@@ -4234,17 +4096,17 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapp
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_43_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_43_syn_2.q[1] clk2q 0.146 r 2.556
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.c[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4]) net (fanout = 1) 0.896 r 3.452 encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2 path2reg0 (LUT3) 0.466 3.918
- Arrival time 3.918 (1 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.q[1] clk2q 0.146 r 2.556
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.c[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[6]) net (fanout = 1) 1.125 r 3.681 encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 path2reg0 (LUT3) 0.466 4.147
+ Arrival time 4.147 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
capture clock edge 4.629 6.795
---------------------------------------------------------------------------------------------------------
cell setup -0.116 6.679
@@ -4252,20 +4114,20 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapp
clock recovergence pessimism 0.000 6.679
Required time 6.679
---------------------------------------------------------------------------------------------------------
- Slack 2.761ns
+ Slack 2.532ns
---------------------------------------------------------------------------------------------------------
Hold checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5 (1 paths)
+Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add7_syn_69 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.158 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6_syn_2.clk (rising edge triggered by clock S_clk)
- End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5.mi[0] (rising edge triggered by clock S_clk_x2)
+ Slack (hold check): 0.167 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6.clk (rising edge triggered by clock S_clk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add7_syn_69.mi[0] (rising edge triggered by clock S_clk_x2)
Clock group: clock_source
Process: Fast
- Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic)
+ Data Path Delay: 0.429ns (logic 0.204ns, net 0.225ns, 47% logic)
Logic Levels: 0
Point Type Incr Path Info
@@ -4274,17 +4136,17 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapp
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6_syn_2.q[0] clk2q 0.109 r 2.138
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d) net (fanout = 1) 0.216 r 2.354 encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5 path2reg0 0.095 2.449
- Arrival time 2.449 (0 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6.q[0] clk2q 0.109 r 2.138
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add7_syn_69.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d) net (fanout = 1) 0.225 r 2.363 encrypted_text(0)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add7_syn_69 path2reg0 0.095 2.458
+ Arrival time 2.458 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add7_syn_69.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
cell hold 0.061 2.291
@@ -4292,18 +4154,18 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapp
clock recovergence pessimism 0.000 2.291
Required time 2.291
---------------------------------------------------------------------------------------------------------
- Slack 0.158ns
+ Slack 0.167ns
---------------------------------------------------------------------------------------------------------
-Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5 (1 paths)
+Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_3d_reg_syn_5 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.274 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.clk (rising edge triggered by clock S_clk)
- End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.mi[1] (rising edge triggered by clock S_clk_x2)
+ Slack (hold check): 0.281 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d_reg_syn_6_syn_2.clk (rising edge triggered by clock S_clk)
+ End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_3d_reg_syn_5.mi[0] (rising edge triggered by clock S_clk_x2)
Clock group: clock_source
Process: Fast
- Data Path Delay: 0.536ns (logic 0.204ns, net 0.332ns, 38% logic)
+ Data Path Delay: 0.543ns (logic 0.204ns, net 0.339ns, 37% logic)
Logic Levels: 0
Point Type Incr Path Info
@@ -4312,17 +4174,17 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d_reg_syn_6_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.q[1] clk2q 0.109 r 2.138
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.mi[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d) net (fanout = 1) 0.332 r 2.470 encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5 path2reg1 0.095 2.565
- Arrival time 2.565 (0 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d_reg_syn_6_syn_2.q[0] clk2q 0.109 r 2.138
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_3d_reg_syn_5.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d) net (fanout = 5) 0.339 r 2.477 encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_3d_reg_syn_5 path2reg0 0.095 2.572
+ Arrival time 2.572 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_3d_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
cell hold 0.061 2.291
@@ -4330,18 +4192,18 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_
clock recovergence pessimism 0.000 2.291
Required time 2.291
---------------------------------------------------------------------------------------------------------
- Slack 0.274ns
+ Slack 0.281ns
---------------------------------------------------------------------------------------------------------
-Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5 (1 paths)
+Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.274 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.clk (rising edge triggered by clock S_clk)
- End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.mi[0] (rising edge triggered by clock S_clk_x2)
+ Slack (hold check): 0.306 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_reg_syn_10_syn_2.clk (rising edge triggered by clock S_clk)
+ End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5.mi[0] (rising edge triggered by clock S_clk_x2)
Clock group: clock_source
Process: Fast
- Data Path Delay: 0.536ns (logic 0.204ns, net 0.332ns, 38% logic)
+ Data Path Delay: 0.568ns (logic 0.204ns, net 0.364ns, 35% logic)
Logic Levels: 0
Point Type Incr Path Info
@@ -4350,17 +4212,17 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_reg_syn_10_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.q[0] clk2q 0.109 r 2.138
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_1d) net (fanout = 2) 0.332 r 2.470 encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5 path2reg0 0.095 2.565
- Arrival time 2.565 (0 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_reg_syn_10_syn_2.q[0] clk2q 0.109 r 2.138
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en) net (fanout = 12) 0.364 r 2.502 encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5 path2reg0 0.095 2.597
+ Arrival time 2.597 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
cell hold 0.061 2.291
@@ -4368,7 +4230,7 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_
clock recovergence pessimism 0.000 2.291
Required time 2.291
---------------------------------------------------------------------------------------------------------
- Slack 0.274ns
+ Slack 0.306ns
---------------------------------------------------------------------------------------------------------
@@ -4379,34 +4241,34 @@ Clock = S_clk_x4, period 2.314ns, rising at 0ns, falling at 1.157ns
8 endpoints analyzed totally, and 32 paths analyzed
0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 1.563ns
+Minimum period is 1.438ns
---------------------------------------------------------------------------------------------------------
-Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
+Paths for end point O_data_hs_p[0]_syn_2 (4 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 0.751 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[3]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
+ Slack (setup check): 0.876 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[0]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
Clock group: clock_source
Process: Slow
- Data Path Delay: 0.949ns (logic 0.146ns, net 0.803ns, 15% logic)
+ Data Path Delay: 0.824ns (logic 0.146ns, net 0.678ns, 17% logic)
Logic Levels: 0
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[1] clk2q 0.146 r 2.556
- O_data_hs_p[3]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.803 r 3.359 encrypted_text(0)
- O_data_hs_p[3]_syn_2 path2reg 0.000 3.359
- Arrival time 3.359 (0 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q 0.146 r 2.556
+ O_data_hs_p[0]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.678 r 3.234 encrypted_text(0)
+ O_data_hs_p[0]_syn_2 path2reg 0.000 3.234
+ Arrival time 3.234 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[3]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
capture clock edge 2.314 4.171
---------------------------------------------------------------------------------------------------------
cell setup -0.061 4.110
@@ -4414,16 +4276,190 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
clock recovergence pessimism 0.000 4.110
Required time 4.110
---------------------------------------------------------------------------------------------------------
- Slack 0.751ns
+ Slack 0.876ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 0.751 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[3]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
+ Slack (setup check): 0.952 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[0]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
Clock group: clock_source
Process: Slow
- Data Path Delay: 0.949ns (logic 0.146ns, net 0.803ns, 15% logic)
+ Data Path Delay: 0.748ns (logic 0.146ns, net 0.602ns, 19% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge 0.000 2.410
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.146 r 2.556
+ O_data_hs_p[0]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.602 r 3.158 encrypted_text(0)
+ O_data_hs_p[0]_syn_2 path2reg 0.000 3.158
+ Arrival time 3.158 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[2] 0.000 0.000
+ O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge 2.314 4.171
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.061 4.110
+ clock uncertainty -0.000 4.110
+ clock recovergence pessimism 0.000 4.110
+ Required time 4.110
+---------------------------------------------------------------------------------------------------------
+ Slack 0.952ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check): 1.028 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[0]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
+ Clock group: clock_source
+ Process: Slow
+ Data Path Delay: 0.672ns (logic 0.146ns, net 0.526ns, 21% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge 0.000 2.410
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[0] clk2q 0.146 r 2.556
+ O_data_hs_p[0]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.526 r 3.082 encrypted_text(0)
+ O_data_hs_p[0]_syn_2 path2reg 0.000 3.082
+ Arrival time 3.082 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[2] 0.000 0.000
+ O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge 2.314 4.171
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.061 4.110
+ clock uncertainty -0.000 4.110
+ clock recovergence pessimism 0.000 4.110
+ Required time 4.110
+---------------------------------------------------------------------------------------------------------
+ Slack 1.028ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check): 0.925 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[1]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
+ Clock group: clock_source
+ Process: Slow
+ Data Path Delay: 0.775ns (logic 0.146ns, net 0.629ns, 18% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge 0.000 2.410
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q 0.146 r 2.556
+ O_data_hs_p[1]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.629 r 3.185 encrypted_text(0)
+ O_data_hs_p[1]_syn_2 path2reg 0.000 3.185
+ Arrival time 3.185 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[2] 0.000 0.000
+ O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge 2.314 4.171
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.061 4.110
+ clock uncertainty -0.000 4.110
+ clock recovergence pessimism 0.000 4.110
+ Required time 4.110
+---------------------------------------------------------------------------------------------------------
+ Slack 0.925ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check): 0.952 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[1]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
+ Clock group: clock_source
+ Process: Slow
+ Data Path Delay: 0.748ns (logic 0.146ns, net 0.602ns, 19% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge 0.000 2.410
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q 0.146 r 2.556
+ O_data_hs_p[1]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.602 r 3.158 encrypted_text(0)
+ O_data_hs_p[1]_syn_2 path2reg 0.000 3.158
+ Arrival time 3.158 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[2] 0.000 0.000
+ O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge 2.314 4.171
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.061 4.110
+ clock uncertainty -0.000 4.110
+ clock recovergence pessimism 0.000 4.110
+ Required time 4.110
+---------------------------------------------------------------------------------------------------------
+ Slack 0.952ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check): 0.952 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[1]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
+ Clock group: clock_source
+ Process: Slow
+ Data Path Delay: 0.748ns (logic 0.146ns, net 0.602ns, 19% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge 0.000 2.410
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[0] clk2q 0.146 r 2.556
+ O_data_hs_p[1]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.602 r 3.158 encrypted_text(0)
+ O_data_hs_p[1]_syn_2 path2reg 0.000 3.158
+ Arrival time 3.158 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[2] 0.000 0.000
+ O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge 2.314 4.171
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.061 4.110
+ clock uncertainty -0.000 4.110
+ clock recovergence pessimism 0.000 4.110
+ Required time 4.110
+---------------------------------------------------------------------------------------------------------
+ Slack 0.952ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check): 0.928 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[3]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
+ Clock group: clock_source
+ Process: Slow
+ Data Path Delay: 0.772ns (logic 0.146ns, net 0.626ns, 18% logic)
Logic Levels: 0
Point Type Incr Path Info
@@ -4434,9 +4470,9 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.146 r 2.556
- O_data_hs_p[3]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.803 r 3.359 encrypted_text(0)
- O_data_hs_p[3]_syn_2 path2reg 0.000 3.359
- Arrival time 3.359 (0 lvl)
+ O_data_hs_p[3]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.626 r 3.182 encrypted_text(0)
+ O_data_hs_p[3]_syn_2 path2reg 0.000 3.182
+ Arrival time 3.182 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[2] 0.000 0.000
@@ -4448,7 +4484,7 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
clock recovergence pessimism 0.000 4.110
Required time 4.110
---------------------------------------------------------------------------------------------------------
- Slack 0.751ns
+ Slack 0.928ns
---------------------------------------------------------------------------------------------------------
@@ -4486,31 +4522,29 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
---------------------------------------------------------------------------------------------------------
-Paths for end point O_data_hs_p[0]_syn_2 (4 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check): 1.028 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[0]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
+ Slack (setup check): 0.952 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[3]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
Clock group: clock_source
Process: Slow
- Data Path Delay: 0.672ns (logic 0.146ns, net 0.526ns, 21% logic)
+ Data Path Delay: 0.748ns (logic 0.146ns, net 0.602ns, 19% logic)
Logic Levels: 0
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[1] clk2q 0.146 r 2.556
- O_data_hs_p[0]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.526 r 3.082 encrypted_text(0)
- O_data_hs_p[0]_syn_2 path2reg 0.000 3.082
- Arrival time 3.082 (0 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[1] clk2q 0.146 r 2.556
+ O_data_hs_p[3]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.602 r 3.158 encrypted_text(0)
+ O_data_hs_p[3]_syn_2 path2reg 0.000 3.158
+ Arrival time 3.158 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ O_data_hs_p[3]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
capture clock edge 2.314 4.171
---------------------------------------------------------------------------------------------------------
cell setup -0.061 4.110
@@ -4518,364 +4552,20 @@ Paths for end point O_data_hs_p[0]_syn_2 (4 paths)
clock recovergence pessimism 0.000 4.110
Required time 4.110
---------------------------------------------------------------------------------------------------------
- Slack 1.028ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check): 1.028 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[0]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
- Clock group: clock_source
- Process: Slow
- Data Path Delay: 0.672ns (logic 0.146ns, net 0.526ns, 21% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge 0.000 2.410
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.146 r 2.556
- O_data_hs_p[0]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.526 r 3.082 encrypted_text(0)
- O_data_hs_p[0]_syn_2 path2reg 0.000 3.082
- Arrival time 3.082 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge 2.314 4.171
----------------------------------------------------------------------------------------------------------
- cell setup -0.061 4.110
- clock uncertainty -0.000 4.110
- clock recovergence pessimism 0.000 4.110
- Required time 4.110
----------------------------------------------------------------------------------------------------------
- Slack 1.028ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check): 1.072 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[0]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
- Clock group: clock_source
- Process: Slow
- Data Path Delay: 0.628ns (logic 0.146ns, net 0.482ns, 23% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge 0.000 2.410
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q 0.146 r 2.556
- O_data_hs_p[0]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.482 r 3.038 encrypted_text(0)
- O_data_hs_p[0]_syn_2 path2reg 0.000 3.038
- Arrival time 3.038 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge 2.314 4.171
----------------------------------------------------------------------------------------------------------
- cell setup -0.061 4.110
- clock uncertainty -0.000 4.110
- clock recovergence pessimism 0.000 4.110
- Required time 4.110
----------------------------------------------------------------------------------------------------------
- Slack 1.072ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check): 1.072 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[1]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
- Clock group: clock_source
- Process: Slow
- Data Path Delay: 0.628ns (logic 0.146ns, net 0.482ns, 23% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge 0.000 2.410
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[1] clk2q 0.146 r 2.556
- O_data_hs_p[1]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.482 r 3.038 encrypted_text(0)
- O_data_hs_p[1]_syn_2 path2reg 0.000 3.038
- Arrival time 3.038 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge 2.314 4.171
----------------------------------------------------------------------------------------------------------
- cell setup -0.061 4.110
- clock uncertainty -0.000 4.110
- clock recovergence pessimism 0.000 4.110
- Required time 4.110
----------------------------------------------------------------------------------------------------------
- Slack 1.072ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check): 1.072 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[1]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
- Clock group: clock_source
- Process: Slow
- Data Path Delay: 0.628ns (logic 0.146ns, net 0.482ns, 23% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge 0.000 2.410
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.146 r 2.556
- O_data_hs_p[1]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.482 r 3.038 encrypted_text(0)
- O_data_hs_p[1]_syn_2 path2reg 0.000 3.038
- Arrival time 3.038 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge 2.314 4.171
----------------------------------------------------------------------------------------------------------
- cell setup -0.061 4.110
- clock uncertainty -0.000 4.110
- clock recovergence pessimism 0.000 4.110
- Required time 4.110
----------------------------------------------------------------------------------------------------------
- Slack 1.072ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check): 1.072 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[1]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
- Clock group: clock_source
- Process: Slow
- Data Path Delay: 0.628ns (logic 0.146ns, net 0.482ns, 23% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge 0.000 2.410
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q 0.146 r 2.556
- O_data_hs_p[1]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.482 r 3.038 encrypted_text(0)
- O_data_hs_p[1]_syn_2 path2reg 0.000 3.038
- Arrival time 3.038 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge 2.314 4.171
----------------------------------------------------------------------------------------------------------
- cell setup -0.061 4.110
- clock uncertainty -0.000 4.110
- clock recovergence pessimism 0.000 4.110
- Required time 4.110
----------------------------------------------------------------------------------------------------------
- Slack 1.072ns
+ Slack 0.952ns
---------------------------------------------------------------------------------------------------------
Hold checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point O_data_hs_p[2]_syn_2 (4 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.507 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[2]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
- Clock group: clock_source
- Process: Fast
- Data Path Delay: 0.440ns (logic 0.109ns, net 0.331ns, 24% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge 0.000 2.029
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q 0.109 r 2.138
- O_data_hs_p[2]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.331 r 2.469 encrypted_text(0)
- O_data_hs_p[2]_syn_2 path2reg 0.000 2.469
- Arrival time 2.469 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[2]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge 0.000 1.965
----------------------------------------------------------------------------------------------------------
- cell hold -0.003 1.962
- clock uncertainty 0.000 1.962
- clock recovergence pessimism 0.000 1.962
- Required time 1.962
----------------------------------------------------------------------------------------------------------
- Slack 0.507ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check): 0.508 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[2]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
- Clock group: clock_source
- Process: Fast
- Data Path Delay: 0.441ns (logic 0.109ns, net 0.332ns, 24% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge 0.000 2.029
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.109 r 2.138
- O_data_hs_p[2]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.332 r 2.470 encrypted_text(0)
- O_data_hs_p[2]_syn_2 path2reg 0.000 2.470
- Arrival time 2.470 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[2]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge 0.000 1.965
----------------------------------------------------------------------------------------------------------
- cell hold -0.003 1.962
- clock uncertainty 0.000 1.962
- clock recovergence pessimism 0.000 1.962
- Required time 1.962
----------------------------------------------------------------------------------------------------------
- Slack 0.508ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check): 0.508 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[2]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
- Clock group: clock_source
- Process: Fast
- Data Path Delay: 0.441ns (logic 0.109ns, net 0.332ns, 24% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge 0.000 2.029
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q 0.109 r 2.138
- O_data_hs_p[2]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.332 r 2.470 encrypted_text(0)
- O_data_hs_p[2]_syn_2 path2reg 0.000 2.470
- Arrival time 2.470 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[2]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge 0.000 1.965
----------------------------------------------------------------------------------------------------------
- cell hold -0.003 1.962
- clock uncertainty 0.000 1.962
- clock recovergence pessimism 0.000 1.962
- Required time 1.962
----------------------------------------------------------------------------------------------------------
- Slack 0.508ns
-
----------------------------------------------------------------------------------------------------------
-
Paths for end point O_data_hs_p[0]_syn_2 (4 paths)
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.517 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[0]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
- Clock group: clock_source
- Process: Fast
- Data Path Delay: 0.450ns (logic 0.109ns, net 0.341ns, 24% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge 0.000 2.029
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q 0.109 r 2.138
- O_data_hs_p[0]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.341 r 2.479 encrypted_text(0)
- O_data_hs_p[0]_syn_2 path2reg 0.000 2.479
- Arrival time 2.479 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge 0.000 1.965
----------------------------------------------------------------------------------------------------------
- cell hold -0.003 1.962
- clock uncertainty 0.000 1.962
- clock recovergence pessimism 0.000 1.962
- Required time 1.962
----------------------------------------------------------------------------------------------------------
- Slack 0.517ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check): 0.517 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[0]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
- Clock group: clock_source
- Process: Fast
- Data Path Delay: 0.450ns (logic 0.109ns, net 0.341ns, 24% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge 0.000 2.029
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q 0.109 r 2.138
- O_data_hs_p[0]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.341 r 2.479 encrypted_text(0)
- O_data_hs_p[0]_syn_2 path2reg 0.000 2.479
- Arrival time 2.479 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge 0.000 1.965
----------------------------------------------------------------------------------------------------------
- cell hold -0.003 1.962
- clock uncertainty 0.000 1.962
- clock recovergence pessimism 0.000 1.962
- Required time 1.962
----------------------------------------------------------------------------------------------------------
- Slack 0.517ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check): 0.546 ns
+ Slack (hold check): 0.401 ns
Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
End Point: O_data_hs_p[0]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
Clock group: clock_source
Process: Fast
- Data Path Delay: 0.479ns (logic 0.109ns, net 0.370ns, 22% logic)
+ Data Path Delay: 0.334ns (logic 0.109ns, net 0.225ns, 32% logic)
Logic Levels: 0
Point Type Incr Path Info
@@ -4886,7 +4576,41 @@ Paths for end point O_data_hs_p[0]_syn_2 (4 paths)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[1] clk2q 0.109 r 2.138
- O_data_hs_p[0]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.370 r 2.508 encrypted_text(0)
+ O_data_hs_p[0]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.225 r 2.363 encrypted_text(0)
+ O_data_hs_p[0]_syn_2 path2reg 0.000 2.363
+ Arrival time 2.363 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[2] 0.000 0.000
+ O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge 0.000 1.965
+---------------------------------------------------------------------------------------------------------
+ cell hold -0.003 1.962
+ clock uncertainty 0.000 1.962
+ clock recovergence pessimism 0.000 1.962
+ Required time 1.962
+---------------------------------------------------------------------------------------------------------
+ Slack 0.401ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check): 0.546 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[0]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
+ Clock group: clock_source
+ Process: Fast
+ Data Path Delay: 0.479ns (logic 0.109ns, net 0.370ns, 22% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge 0.000 2.029
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[0] clk2q 0.109 r 2.138
+ O_data_hs_p[0]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.370 r 2.508 encrypted_text(0)
O_data_hs_p[0]_syn_2 path2reg 0.000 2.508
Arrival time 2.508 (0 lvl)
@@ -4904,31 +4628,29 @@ Paths for end point O_data_hs_p[0]_syn_2 (4 paths)
---------------------------------------------------------------------------------------------------------
-Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.517 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[1]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
+ Slack (hold check): 0.583 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[0]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
Clock group: clock_source
Process: Fast
- Data Path Delay: 0.450ns (logic 0.109ns, net 0.341ns, 24% logic)
+ Data Path Delay: 0.516ns (logic 0.109ns, net 0.407ns, 21% logic)
Logic Levels: 0
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[1] clk2q 0.109 r 2.138
- O_data_hs_p[1]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.341 r 2.479 encrypted_text(0)
- O_data_hs_p[1]_syn_2 path2reg 0.000 2.479
- Arrival time 2.479 (0 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.109 r 2.138
+ O_data_hs_p[0]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.407 r 2.545 encrypted_text(0)
+ O_data_hs_p[0]_syn_2 path2reg 0.000 2.545
+ Arrival time 2.545 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
capture clock edge 0.000 1.965
---------------------------------------------------------------------------------------------------------
cell hold -0.003 1.962
@@ -4936,29 +4658,31 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
clock recovergence pessimism 0.000 1.962
Required time 1.962
---------------------------------------------------------------------------------------------------------
- Slack 0.517ns
+ Slack 0.583ns
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.517 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
+Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.401 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2)
End Point: O_data_hs_p[1]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
Clock group: clock_source
Process: Fast
- Data Path Delay: 0.450ns (logic 0.109ns, net 0.341ns, 24% logic)
+ Data Path Delay: 0.334ns (logic 0.109ns, net 0.225ns, 32% logic)
Logic Levels: 0
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.109 r 2.138
- O_data_hs_p[1]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.341 r 2.479 encrypted_text(0)
- O_data_hs_p[1]_syn_2 path2reg 0.000 2.479
- Arrival time 2.479 (0 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[1] clk2q 0.109 r 2.138
+ O_data_hs_p[1]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.225 r 2.363 encrypted_text(0)
+ O_data_hs_p[1]_syn_2 path2reg 0.000 2.363
+ Arrival time 2.363 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[2] 0.000 0.000
@@ -4970,16 +4694,16 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
clock recovergence pessimism 0.000 1.962
Required time 1.962
---------------------------------------------------------------------------------------------------------
- Slack 0.517ns
+ Slack 0.401ns
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.517 ns
+ Slack (hold check): 0.583 ns
Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[1]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
+ End Point: O_data_hs_p[1]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
Clock group: clock_source
Process: Fast
- Data Path Delay: 0.450ns (logic 0.109ns, net 0.341ns, 24% logic)
+ Data Path Delay: 0.516ns (logic 0.109ns, net 0.407ns, 21% logic)
Logic Levels: 0
Point Type Incr Path Info
@@ -4990,9 +4714,9 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q 0.109 r 2.138
- O_data_hs_p[1]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.341 r 2.479 encrypted_text(0)
- O_data_hs_p[1]_syn_2 path2reg 0.000 2.479
- Arrival time 2.479 (0 lvl)
+ O_data_hs_p[1]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.407 r 2.545 encrypted_text(0)
+ O_data_hs_p[1]_syn_2 path2reg 0.000 2.545
+ Arrival time 2.545 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[2] 0.000 0.000
@@ -5004,7 +4728,145 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
clock recovergence pessimism 0.000 1.962
Required time 1.962
---------------------------------------------------------------------------------------------------------
- Slack 0.517ns
+ Slack 0.583ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check): 0.583 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[1]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
+ Clock group: clock_source
+ Process: Fast
+ Data Path Delay: 0.516ns (logic 0.109ns, net 0.407ns, 21% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge 0.000 2.029
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[0] clk2q 0.109 r 2.138
+ O_data_hs_p[1]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.407 r 2.545 encrypted_text(0)
+ O_data_hs_p[1]_syn_2 path2reg 0.000 2.545
+ Arrival time 2.545 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[2] 0.000 0.000
+ O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge 0.000 1.965
+---------------------------------------------------------------------------------------------------------
+ cell hold -0.003 1.962
+ clock uncertainty 0.000 1.962
+ clock recovergence pessimism 0.000 1.962
+ Required time 1.962
+---------------------------------------------------------------------------------------------------------
+ Slack 0.583ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.401 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[3]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
+ Clock group: clock_source
+ Process: Fast
+ Data Path Delay: 0.334ns (logic 0.109ns, net 0.225ns, 32% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge 0.000 2.029
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[0] clk2q 0.109 r 2.138
+ O_data_hs_p[3]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.225 r 2.363 encrypted_text(0)
+ O_data_hs_p[3]_syn_2 path2reg 0.000 2.363
+ Arrival time 2.363 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[2] 0.000 0.000
+ O_data_hs_p[3]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge 0.000 1.965
+---------------------------------------------------------------------------------------------------------
+ cell hold -0.003 1.962
+ clock uncertainty 0.000 1.962
+ clock recovergence pessimism 0.000 1.962
+ Required time 1.962
+---------------------------------------------------------------------------------------------------------
+ Slack 0.401ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check): 0.583 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[3]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
+ Clock group: clock_source
+ Process: Fast
+ Data Path Delay: 0.516ns (logic 0.109ns, net 0.407ns, 21% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge 0.000 2.029
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q 0.109 r 2.138
+ O_data_hs_p[3]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.407 r 2.545 encrypted_text(0)
+ O_data_hs_p[3]_syn_2 path2reg 0.000 2.545
+ Arrival time 2.545 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[2] 0.000 0.000
+ O_data_hs_p[3]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge 0.000 1.965
+---------------------------------------------------------------------------------------------------------
+ cell hold -0.003 1.962
+ clock uncertainty 0.000 1.962
+ clock recovergence pessimism 0.000 1.962
+ Required time 1.962
+---------------------------------------------------------------------------------------------------------
+ Slack 0.583ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check): 0.583 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[3]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
+ Clock group: clock_source
+ Process: Fast
+ Data Path Delay: 0.516ns (logic 0.109ns, net 0.407ns, 21% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge 0.000 2.029
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[1] clk2q 0.109 r 2.138
+ O_data_hs_p[3]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.407 r 2.545 encrypted_text(0)
+ O_data_hs_p[3]_syn_2 path2reg 0.000 2.545
+ Arrival time 2.545 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[2] 0.000 0.000
+ O_data_hs_p[3]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge 0.000 1.965
+---------------------------------------------------------------------------------------------------------
+ cell hold -0.003 1.962
+ clock uncertainty 0.000 1.962
+ clock recovergence pessimism 0.000 1.962
+ Required time 1.962
+---------------------------------------------------------------------------------------------------------
+ Slack 0.583ns
---------------------------------------------------------------------------------------------------------
@@ -5014,18 +4876,18 @@ Timing constraint: clock: S_clk_x4_90d
Clock = S_clk_x4_90d, period 2.314ns, rising at 0.578ns, falling at 1.735ns
2 endpoints analyzed totally, and 4 paths analyzed
-2 errors detected : 2 setup errors (TNS = -0.661), 0 hold errors (TNS = 0.000)
-Minimum period is 2.975ns
+2 errors detected : 2 setup errors (TNS = -0.811), 0 hold errors (TNS = 0.000)
+Minimum period is 3.125ns
---------------------------------------------------------------------------------------------------------
Paths for end point O_clk_hs_p_syn_2 (2 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): -0.661 ns
+ Slack (setup check): -0.811 ns
Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (rising edge triggered by clock S_clk_x2)
End Point: O_clk_hs_p_syn_2.do[2] (rising edge triggered by clock S_clk_x4_90d)
Clock group: clock_source
Process: Slow
- Data Path Delay: 0.625ns (logic 0.146ns, net 0.479ns, 23% logic)
+ Data Path Delay: 0.775ns (logic 0.146ns, net 0.629ns, 18% logic)
Logic Levels: 0
Point Type Incr Path Info
@@ -5036,9 +4898,9 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[1] clk2q 0.146 r 2.556
- O_clk_hs_p_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net (fanout = 2) 0.479 r 3.035 encrypted_text(0)
- O_clk_hs_p_syn_2 path2reg 0.000 3.035
- Arrival time 3.035 (0 lvl)
+ O_clk_hs_p_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net (fanout = 2) 0.629 r 3.185 encrypted_text(0)
+ O_clk_hs_p_syn_2 path2reg 0.000 3.185
+ Arrival time 3.185 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[3] 0.000 0.000
@@ -5050,16 +4912,16 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths)
clock recovergence pessimism 0.000 2.374
Required time 2.374
---------------------------------------------------------------------------------------------------------
- Slack -0.661ns
+ Slack -0.811ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): -0.658 ns
+ Slack (setup check): -0.810 ns
Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (rising edge triggered by clock S_clk_x2)
End Point: O_clk_hs_p_syn_2.do[0] (rising edge triggered by clock S_clk_x4_90d)
Clock group: clock_source
Process: Slow
- Data Path Delay: 0.622ns (logic 0.146ns, net 0.476ns, 23% logic)
+ Data Path Delay: 0.774ns (logic 0.146ns, net 0.628ns, 18% logic)
Logic Levels: 0
Point Type Incr Path Info
@@ -5070,9 +4932,9 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[1] clk2q 0.146 r 2.556
- O_clk_hs_p_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net (fanout = 2) 0.476 r 3.032 encrypted_text(0)
- O_clk_hs_p_syn_2 path2reg 0.000 3.032
- Arrival time 3.032 (0 lvl)
+ O_clk_hs_p_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net (fanout = 2) 0.628 r 3.184 encrypted_text(0)
+ O_clk_hs_p_syn_2 path2reg 0.000 3.184
+ Arrival time 3.184 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[3] 0.000 0.000
@@ -5084,7 +4946,7 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths)
clock recovergence pessimism 0.000 2.374
Required time 2.374
---------------------------------------------------------------------------------------------------------
- Slack -0.658ns
+ Slack -0.810ns
---------------------------------------------------------------------------------------------------------
@@ -5092,46 +4954,12 @@ Hold checks:
---------------------------------------------------------------------------------------------------------
Paths for end point O_clk_hs_p_syn_2 (2 paths)
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 2.243 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_clk_hs_p_syn_2.do[0] (rising edge triggered by clock S_clk_x4_90d)
- Clock group: clock_source
- Process: Fast
- Data Path Delay: 0.440ns (logic 0.109ns, net 0.331ns, 24% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge 0.000 2.029
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[1] clk2q 0.109 r 2.138
- O_clk_hs_p_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net (fanout = 2) 0.331 r 2.469 encrypted_text(0)
- O_clk_hs_p_syn_2 path2reg 0.000 2.469
- Arrival time 2.469 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[3] 0.000 0.000
- O_clk_hs_p_syn_2.osclk (u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(20)
- capture clock edge -1.736 0.229
----------------------------------------------------------------------------------------------------------
- cell hold -0.003 0.226
- clock uncertainty 0.000 0.226
- clock recovergence pessimism 0.000 0.226
- Required time 0.226
----------------------------------------------------------------------------------------------------------
- Slack 2.243ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check): 2.244 ns
+ Slack (hold check): 2.359 ns
Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (rising edge triggered by clock S_clk_x2)
End Point: O_clk_hs_p_syn_2.do[2] (rising edge triggered by clock S_clk_x4_90d)
Clock group: clock_source
Process: Fast
- Data Path Delay: 0.441ns (logic 0.109ns, net 0.332ns, 24% logic)
+ Data Path Delay: 0.556ns (logic 0.109ns, net 0.447ns, 19% logic)
Logic Levels: 0
Point Type Incr Path Info
@@ -5142,9 +4970,9 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[1] clk2q 0.109 r 2.138
- O_clk_hs_p_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net (fanout = 2) 0.332 r 2.470 encrypted_text(0)
- O_clk_hs_p_syn_2 path2reg 0.000 2.470
- Arrival time 2.470 (0 lvl)
+ O_clk_hs_p_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net (fanout = 2) 0.447 r 2.585 encrypted_text(0)
+ O_clk_hs_p_syn_2 path2reg 0.000 2.585
+ Arrival time 2.585 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[3] 0.000 0.000
@@ -5156,7 +4984,41 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths)
clock recovergence pessimism 0.000 0.226
Required time 0.226
---------------------------------------------------------------------------------------------------------
- Slack 2.244ns
+ Slack 2.359ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check): 2.359 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_clk_hs_p_syn_2.do[0] (rising edge triggered by clock S_clk_x4_90d)
+ Clock group: clock_source
+ Process: Fast
+ Data Path Delay: 0.556ns (logic 0.109ns, net 0.447ns, 19% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge 0.000 2.029
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[1] clk2q 0.109 r 2.138
+ O_clk_hs_p_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net (fanout = 2) 0.447 r 2.585 encrypted_text(0)
+ O_clk_hs_p_syn_2 path2reg 0.000 2.585
+ Arrival time 2.585 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[3] 0.000 0.000
+ O_clk_hs_p_syn_2.osclk (u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(20)
+ capture clock edge -1.736 0.229
+---------------------------------------------------------------------------------------------------------
+ cell hold -0.003 0.226
+ clock uncertainty 0.000 0.226
+ clock recovergence pessimism 0.000 0.226
+ Required time 0.226
+---------------------------------------------------------------------------------------------------------
+ Slack 2.359ns
---------------------------------------------------------------------------------------------------------
@@ -5164,22 +5026,22 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths)
=========================================================================================================
Timing summary:
---------------------------------------------------------------------------------------------------------
-Constraint path number: 370860 (STA coverage = 91.86%)
+Constraint path number: 357308 (STA coverage = 91.87%)
Timing violations: 5 setup errors, and 0 hold errors.
-Minimal setup slack: -1.797, minimal hold slack: 0.067
+Minimal setup slack: -1.945, minimal hold slack: 0.067
Timing group statistics:
Clock constraints:
Clock Name Min Period Max Freq Skew Fanout TNS
- S_clk (108.0MHz) 9.150ns 109.290MHz 0.326ns 1795 0.000ns
- a_pclk (48.0MHz) 13.964ns 71.613MHz 0.326ns 1417 0.000ns
- b_pclk (48.0MHz) 10.242ns 97.637MHz 0.326ns 1355 0.000ns
- clk_adc (6.0MHz) 168.461ns 5.936MHz 0.326ns 967 -3.307ns
- b_sclk (168.0MHz) 1.853ns 539.665MHz 0.326ns 70 0.000ns
- a_sclk (168.0MHz) 2.239ns 446.628MHz 0.326ns 69 0.000ns
- S_clk_x2 (216.0MHz) 2.179ns 458.926MHz 0.480ns 20 0.000ns
- S_clk_x4 (432.0MHz) 1.563ns 639.795MHz 0.018ns 4 0.000ns
- S_clk_x4_90d (432.0MHz) 2.975ns 336.000MHz 0.000ns 1 -0.661ns
+ S_clk (108.0MHz) 9.050ns 110.497MHz 0.326ns 1810 0.000ns
+ a_pclk (48.0MHz) 12.299ns 81.307MHz 0.326ns 1425 0.000ns
+ b_pclk (48.0MHz) 10.093ns 99.079MHz 0.326ns 1358 0.000ns
+ clk_adc (6.0MHz) 168.609ns 5.931MHz 0.326ns 942 -3.279ns
+ a_sclk (168.0MHz) 2.172ns 460.405MHz 0.254ns 69 0.000ns
+ b_sclk (168.0MHz) 2.158ns 463.392MHz 0.326ns 69 0.000ns
+ S_clk_x2 (216.0MHz) 2.561ns 390.472MHz 0.480ns 22 0.000ns
+ S_clk_x4 (432.0MHz) 1.438ns 695.410MHz 0.018ns 4 0.000ns
+ S_clk_x4_90d (432.0MHz) 3.125ns 320.000MHz 0.000ns 1 -0.811ns
Minimum input arrival time before clock: no constraint path
Maximum output required time after clock: no constraint path
Maximum combinational path delay: no constraint path
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.tsm b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.tsm
index 1e7ca45..1295a84 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.tsm
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.tsm
@@ -1,1377 +1,1319 @@
eagle_s20
-13 5165 3533 2973 25612 370860 5 0
--1.797 0.067 huagao_mipi_top eagle_s20 EG4D20EG176 Detail NA 38 12
+13 5027 3393 2877 25626 357308 5 0
+-1.945 0.067 huagao_mipi_top eagle_s20 EG4D20EG176 Detail NA 38 12
clock: a_lvds_clk_p
15 0 0 0
clock: a_pclk
-23 105934 6230 2
+23 103438 6218 2
Setup check
33 3
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
-33 6.869000 691 3
+33 8.534000 691 3
Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
-35 6.869000 22.857000 15.988000 7 9
-sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4] U_rgb_to_csi_pakage/mult0_syn_4.a[12]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_pixel_cdc/reg6_syn_65.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pixel_cdc/reg6_syn_67.b[0]
+35 8.534000 22.857000 14.323000 7 7
+sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[14]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6] sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_396.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239 u_pic_cnt/reg1_syn_384.a[0]
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1]
Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
-89 6.869000 22.857000 15.988000 7 9
-sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4] U_rgb_to_csi_pakage/mult0_syn_4.a[12]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_pixel_cdc/reg6_syn_65.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pixel_cdc/reg6_syn_67.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[0]
-
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
-sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
-143 6.875000 22.857000 15.982000 7 10
+85 8.534000 22.857000 14.323000 7 7
sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4] U_rgb_to_csi_pakage/mult0_syn_4.a[12]
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_pixel_cdc/reg6_syn_65.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pixel_cdc/reg6_syn_67.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6] sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_396.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239 u_pic_cnt/reg1_syn_384.a[0]
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1]
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
+sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
+135 8.534000 22.857000 14.323000 7 7
+sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[14]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6] sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_396.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239 u_pic_cnt/reg1_syn_384.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[0]
+
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
-199 7.164000 659 3
+185 8.641000 659 3
Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
-201 7.164000 22.857000 15.693000 7 9
-sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4] U_rgb_to_csi_pakage/mult0_syn_4.a[12]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_pixel_cdc/reg6_syn_65.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pixel_cdc/reg6_syn_67.b[0]
+187 8.641000 22.929000 14.288000 7 7
+sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[14]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6] sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_396.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239 u_pic_cnt/reg1_syn_384.a[0]
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1]
Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
-255 7.164000 22.857000 15.693000 7 9
-sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4] U_rgb_to_csi_pakage/mult0_syn_4.a[12]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_pixel_cdc/reg6_syn_65.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pixel_cdc/reg6_syn_67.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[0]
-
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
-sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
-309 7.170000 22.857000 15.687000 7 10
+237 8.641000 22.929000 14.288000 7 7
sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4] U_rgb_to_csi_pakage/mult0_syn_4.a[12]
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_pixel_cdc/reg6_syn_65.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pixel_cdc/reg6_syn_67.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6] sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_396.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239 u_pic_cnt/reg1_syn_384.a[0]
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1]
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
+sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
+287 8.641000 22.929000 14.288000 7 7
+sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[14]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6] sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_396.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239 u_pic_cnt/reg1_syn_384.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[0]
-Endpoint: exdev_ctl_a/u_gen_sp/reg0_syn_81
-365 12.294000 217 3
-Timing path: exdev_ctl_a/u_gen_sp/reg9_syn_103.clk->exdev_ctl_a/u_gen_sp/reg0_syn_81
-exdev_ctl_a/u_gen_sp/reg9_syn_103.clk
-exdev_ctl_a/u_gen_sp/reg0_syn_81
-367 12.294000 22.786000 10.492000 7 9
-exdev_ctl_a/u_gen_sp/sp_t_d1[3] exdev_ctl_a/u_gen_sp/sub1_syn_103.a[0]
-exdev_ctl_a/u_gen_sp/sub1_syn_91 exdev_ctl_a/u_gen_sp/sub1_syn_104.fci
-exdev_ctl_a/u_gen_sp/sub1_syn_95 exdev_ctl_a/u_gen_sp/sub1_syn_105.fci
-exdev_ctl_a/u_gen_sp/cnt_one_line_b5[12] exdev_ctl_a/reg8_syn_103.a[1]
-exdev_ctl_a/u_gen_sp/mux31_syn_140 exdev_ctl_b/reg6_syn_103.a[1]
-exdev_ctl_a/u_gen_sp/mux31_syn_142 u_bus_top/reg5_syn_196.a[0]
-exdev_ctl_a/u_gen_sp/mux31_syn_150 exdev_ctl_a/reg8_syn_103.a[0]
-exdev_ctl_a/u_gen_sp/cnt_one_line_b3_n1 exdev_ctl_a/reg8_syn_109.d[1]
-exdev_ctl_a/u_gen_sp/mux31_syn_19 exdev_ctl_a/u_gen_sp/reg0_syn_81.sr
-Timing path: exdev_ctl_a/u_gen_sp/reg9_syn_100.clk->exdev_ctl_a/u_gen_sp/reg0_syn_81
-exdev_ctl_a/u_gen_sp/reg9_syn_100.clk
-exdev_ctl_a/u_gen_sp/reg0_syn_81
-421 12.405000 22.786000 10.381000 7 9
-exdev_ctl_a/u_gen_sp/sp_t_d1[4] exdev_ctl_a/u_gen_sp/sub1_syn_103.b[0]
-exdev_ctl_a/u_gen_sp/sub1_syn_91 exdev_ctl_a/u_gen_sp/sub1_syn_104.fci
-exdev_ctl_a/u_gen_sp/sub1_syn_95 exdev_ctl_a/u_gen_sp/sub1_syn_105.fci
-exdev_ctl_a/u_gen_sp/cnt_one_line_b5[12] exdev_ctl_a/reg8_syn_103.a[1]
-exdev_ctl_a/u_gen_sp/mux31_syn_140 exdev_ctl_b/reg6_syn_103.a[1]
-exdev_ctl_a/u_gen_sp/mux31_syn_142 u_bus_top/reg5_syn_196.a[0]
-exdev_ctl_a/u_gen_sp/mux31_syn_150 exdev_ctl_a/reg8_syn_103.a[0]
-exdev_ctl_a/u_gen_sp/cnt_one_line_b3_n1 exdev_ctl_a/reg8_syn_109.d[1]
-exdev_ctl_a/u_gen_sp/mux31_syn_19 exdev_ctl_a/u_gen_sp/reg0_syn_81.sr
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14
+337 12.509000 85 3
+Timing path: scan_start_diff/trigger_syn_7099.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14
+scan_start_diff/trigger_syn_7099.clk
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14
+339 12.509000 22.929000 10.420000 6 6
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[1] sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_244.c[1]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_39 sampling_fe_a/u_sort/reg2_syn_54.b[1]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_3656 sampling_fe_a/u_sort/reg0_syn_58.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_2 sampling_fe_a/u_sort/reg0_syn_58.c[1]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_4 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_712.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[24]_syn_2 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.c[0]
-Timing path: exdev_ctl_a/u_gen_sp/reg9_syn_100.clk->exdev_ctl_a/u_gen_sp/reg0_syn_81
-exdev_ctl_a/u_gen_sp/reg9_syn_100.clk
-exdev_ctl_a/u_gen_sp/reg0_syn_81
-475 12.598000 22.786000 10.188000 7 8
-exdev_ctl_a/u_gen_sp/sp_t_d1[7] exdev_ctl_a/u_gen_sp/sub1_syn_104.a[0]
-exdev_ctl_a/u_gen_sp/sub1_syn_95 exdev_ctl_a/u_gen_sp/sub1_syn_105.fci
-exdev_ctl_a/u_gen_sp/cnt_one_line_b5[12] exdev_ctl_a/reg8_syn_103.a[1]
-exdev_ctl_a/u_gen_sp/mux31_syn_140 exdev_ctl_b/reg6_syn_103.a[1]
-exdev_ctl_a/u_gen_sp/mux31_syn_142 u_bus_top/reg5_syn_196.a[0]
-exdev_ctl_a/u_gen_sp/mux31_syn_150 exdev_ctl_a/reg8_syn_103.a[0]
-exdev_ctl_a/u_gen_sp/cnt_one_line_b3_n1 exdev_ctl_a/reg8_syn_109.d[1]
-exdev_ctl_a/u_gen_sp/mux31_syn_19 exdev_ctl_a/u_gen_sp/reg0_syn_81.sr
+Timing path: scan_start_diff/trigger_syn_7101.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14
+scan_start_diff/trigger_syn_7101.clk
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14
+387 12.523000 22.929000 10.406000 6 6
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[0] sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_244.d[1]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_39 sampling_fe_a/u_sort/reg2_syn_54.b[1]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_3656 sampling_fe_a/u_sort/reg0_syn_58.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_2 sampling_fe_a/u_sort/reg0_syn_58.c[1]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_4 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_712.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[24]_syn_2 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.c[0]
+
+Timing path: scan_start_diff/trigger_syn_7099.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14
+scan_start_diff/trigger_syn_7099.clk
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14
+435 12.660000 22.929000 10.269000 6 6
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[1] sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_244.c[1]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_39 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[84]_syn_62.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_4756 sampling_fe_a/u_sort/reg0_syn_58.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_2 sampling_fe_a/u_sort/reg0_syn_58.c[1]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_4 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_712.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[24]_syn_2 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.c[0]
Hold check
-527 3
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1
-529 0.114000 10 3
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_741.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_741.clk
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1
-531 0.114000 2.183000 2.297000 1 1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[34] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.addra[7]
+483 3
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1
+485 0.089000 10 3
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[75]_syn_8.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[75]_syn_8.clk
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1
+487 0.089000 2.183000 2.272000 1 1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[65] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.addra[8]
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_652.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_652.clk
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1
-569 0.234000 2.183000 2.417000 1 1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[32] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.addra[5]
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[95]_syn_22.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[95]_syn_22.clk
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1
+525 0.195000 2.183000 2.378000 1 1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[60] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.addra[3]
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_648.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_648.clk
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1
-607 0.311000 2.183000 2.494000 1 1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[39] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.addra[12]
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_735.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_735.clk
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1
+563 0.196000 2.183000 2.379000 1 1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[66] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.addra[9]
-Endpoint: u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_333
-645 0.183000 1 1
-Timing path: u_bus_top/u_local_bus_slve_cis/reg29_syn_227.clk->u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_333
-u_bus_top/u_local_bus_slve_cis/reg29_syn_227.clk
-u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_333
-647 0.183000 2.191000 2.374000 0 1
-u_pixel_cdc/u_clk_cis_frame_num/signal_from[4] u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_333.mi[0]
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1
+601 0.114000 8 3
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_547.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_547.clk
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1
+603 0.114000 2.183000 2.297000 1 1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_data[21] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dia[5]
+
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_549.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_549.clk
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1
+641 0.218000 2.183000 2.401000 1 1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_data[19] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dia[3]
+
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_512.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_512.clk
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1
+679 0.311000 2.183000 2.494000 1 1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_data[22] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dia[6]
-Endpoint: exdev_ctl_a/reg6_syn_89
-683 0.183000 1 1
-Timing path: u_bus_top/u_local_bus_slve_cis/reg40_syn_204.clk->exdev_ctl_a/reg6_syn_89
-u_bus_top/u_local_bus_slve_cis/reg40_syn_204.clk
-exdev_ctl_a/reg6_syn_89
-685 0.183000 2.191000 2.374000 0 1
-u_bus_top/u_local_bus_slve_cis/reg1[18] exdev_ctl_a/reg6_syn_89.mi[0]
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1
+717 0.114000 8 3
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add8_syn_69.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add8_syn_69.clk
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1
+719 0.114000 2.183000 2.297000 1 1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_data[17] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dia[1]
+
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_549.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_549.clk
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1
+757 0.196000 2.183000 2.379000 1 1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_data[19] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dia[3]
+
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_548.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_548.clk
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1
+795 0.234000 2.183000 2.417000 1 1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_data[16] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dia[0]
clock: a_sclk
-721 722 282 2
+833 706 282 2
Setup check
-731 3
-Endpoint: ua_lvds_rx/reg14_syn_64
-731 3.713000 7 3
-Timing path: ua_lvds_rx/reg7_syn_33.clk->ua_lvds_rx/reg14_syn_64
-ua_lvds_rx/reg7_syn_33.clk
-ua_lvds_rx/reg14_syn_64
-733 3.713000 8.076000 4.363000 2 2
-ua_lvds_rx/rx_clk_sft[1] ua_lvds_rx/reg14_syn_62.b[0]
-ua_lvds_rx/rx_clk_sync_n_syn_2 ua_lvds_rx/reg14_syn_64.d[0]
+843 3
+Endpoint: ua_lvds_rx/rx_clk_sync_reg_syn_5
+843 3.780000 7 3
+Timing path: ua_lvds_rx/reg7_syn_44.clk->ua_lvds_rx/rx_clk_sync_reg_syn_5
+ua_lvds_rx/reg7_syn_44.clk
+ua_lvds_rx/rx_clk_sync_reg_syn_5
+845 3.780000 8.210000 4.430000 2 2
+ua_lvds_rx/rx_clk_sft[0] ua_lvds_rx/rx_clk_sync_reg_syn_5.a[0]
+ua_lvds_rx/rx_clk_sync_n_syn_2 ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1]
-Timing path: ua_lvds_rx/reg7_syn_28.clk->ua_lvds_rx/reg14_syn_64
-ua_lvds_rx/reg7_syn_28.clk
-ua_lvds_rx/reg14_syn_64
-769 3.811000 8.076000 4.265000 2 2
-ua_lvds_rx/rx_clk_sft[2] ua_lvds_rx/reg14_syn_62.c[0]
-ua_lvds_rx/rx_clk_sync_n_syn_2 ua_lvds_rx/reg14_syn_64.d[0]
+Timing path: ua_lvds_rx/reg7_syn_47.clk->ua_lvds_rx/rx_clk_sync_reg_syn_5
+ua_lvds_rx/reg7_syn_47.clk
+ua_lvds_rx/rx_clk_sync_reg_syn_5
+881 3.815000 8.210000 4.395000 2 2
+ua_lvds_rx/rx_clk_sft[3] ua_lvds_rx/rx_clk_sync_reg_syn_5.d[0]
+ua_lvds_rx/rx_clk_sync_n_syn_2 ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1]
-Timing path: ua_lvds_rx/reg7_syn_25.clk->ua_lvds_rx/reg14_syn_64
-ua_lvds_rx/reg7_syn_25.clk
-ua_lvds_rx/reg14_syn_64
-805 3.988000 8.076000 4.088000 2 2
-ua_lvds_rx/rx_clk_sft[4] ua_lvds_rx/reg14_syn_62.e[0]
-ua_lvds_rx/rx_clk_sync_n_syn_2 ua_lvds_rx/reg14_syn_64.d[0]
+Timing path: ua_lvds_rx/reg7_syn_38.clk->ua_lvds_rx/rx_clk_sync_reg_syn_5
+ua_lvds_rx/reg7_syn_38.clk
+ua_lvds_rx/rx_clk_sync_reg_syn_5
+917 3.849000 8.210000 4.361000 2 2
+ua_lvds_rx/rx_clk_sft[2] ua_lvds_rx/rx_clk_sync_reg_syn_5.c[0]
+ua_lvds_rx/rx_clk_sync_n_syn_2 ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1]
-Endpoint: ua_lvds_rx/reg8_syn_155
-841 4.003000 9 3
-Timing path: ua_lvds_rx/reg8_syn_161.clk->ua_lvds_rx/reg8_syn_155
-ua_lvds_rx/reg8_syn_161.clk
-ua_lvds_rx/reg8_syn_155
-843 4.003000 8.076000 4.073000 1 1
-ua_lvds_rx/rx_data[37] ua_lvds_rx/reg8_syn_155.c[1]
+Endpoint: ua_lvds_rx/reg8_syn_145
+953 4.058000 9 3
+Timing path: ua_lvds_rx/sync0_reg_syn_4.clk->ua_lvds_rx/reg8_syn_145
+ua_lvds_rx/sync0_reg_syn_4.clk
+ua_lvds_rx/reg8_syn_145
+955 4.058000 8.182000 4.124000 1 1
+ua_lvds_rx/sync0 ua_lvds_rx/reg8_syn_145.d[1]
-Timing path: ua_lvds_rx/reg8_syn_161.clk->ua_lvds_rx/reg8_syn_155
-ua_lvds_rx/reg8_syn_161.clk
-ua_lvds_rx/reg8_syn_155
-877 4.003000 8.076000 4.073000 1 1
-ua_lvds_rx/rx_data[37] ua_lvds_rx/reg8_syn_155.c[0]
+Timing path: ua_lvds_rx/sync0_reg_syn_4.clk->ua_lvds_rx/reg8_syn_145
+ua_lvds_rx/sync0_reg_syn_4.clk
+ua_lvds_rx/reg8_syn_145
+989 4.058000 8.182000 4.124000 1 1
+ua_lvds_rx/sync0 ua_lvds_rx/reg8_syn_145.d[0]
-Timing path: ua_lvds_rx/reg8_syn_166.clk->ua_lvds_rx/reg8_syn_155
-ua_lvds_rx/reg8_syn_166.clk
-ua_lvds_rx/reg8_syn_155
-911 4.125000 8.076000 3.951000 1 1
-ua_lvds_rx/sync0 ua_lvds_rx/reg8_syn_155.d[1]
+Timing path: ua_lvds_rx/reg8_syn_145.clk->ua_lvds_rx/reg8_syn_145
+ua_lvds_rx/reg8_syn_145.clk
+ua_lvds_rx/reg8_syn_145
+1023 4.198000 8.182000 3.984000 1 1
+ua_lvds_rx/para_data[2] ua_lvds_rx/reg8_syn_145.a[1]
-Endpoint: ua_lvds_rx/reg3_syn_198
-945 4.009000 5 3
-Timing path: ua_lvds_rx/reg8_syn_161.clk->ua_lvds_rx/reg3_syn_198
-ua_lvds_rx/reg8_syn_161.clk
-ua_lvds_rx/reg3_syn_198
-947 4.009000 8.076000 4.067000 1 1
-ua_lvds_rx/rx_data[37] ua_lvds_rx/reg3_syn_198.b[0]
+Endpoint: ua_lvds_rx/reg8_syn_157
+1057 4.092000 9 3
+Timing path: ua_lvds_rx/sync0_reg_syn_4.clk->ua_lvds_rx/reg8_syn_157
+ua_lvds_rx/sync0_reg_syn_4.clk
+ua_lvds_rx/reg8_syn_157
+1059 4.092000 8.182000 4.090000 1 1
+ua_lvds_rx/sync0 ua_lvds_rx/reg8_syn_157.d[1]
-Timing path: ua_lvds_rx/reg8_syn_198.clk->ua_lvds_rx/reg3_syn_198
-ua_lvds_rx/reg8_syn_198.clk
-ua_lvds_rx/reg3_syn_198
-981 4.454000 8.076000 3.622000 1 1
-ua_lvds_rx/rx_data[38] ua_lvds_rx/reg3_syn_198.c[0]
+Timing path: ua_lvds_rx/sync0_reg_syn_4.clk->ua_lvds_rx/reg8_syn_157
+ua_lvds_rx/sync0_reg_syn_4.clk
+ua_lvds_rx/reg8_syn_157
+1093 4.092000 8.182000 4.090000 1 1
+ua_lvds_rx/sync0 ua_lvds_rx/reg8_syn_157.d[0]
-Timing path: ua_lvds_rx/reg14_syn_62.clk->ua_lvds_rx/reg3_syn_198
-ua_lvds_rx/reg14_syn_62.clk
-ua_lvds_rx/reg3_syn_198
-1015 4.486000 8.076000 3.590000 1 1
-ua_lvds_rx/sync1 ua_lvds_rx/reg3_syn_198.e[0]
+Timing path: ua_lvds_rx/sync0_reg_syn_4.clk->ua_lvds_rx/reg8_syn_157
+ua_lvds_rx/sync0_reg_syn_4.clk
+ua_lvds_rx/reg8_syn_157
+1127 4.387000 8.182000 3.795000 1 1
+ua_lvds_rx/sync1 ua_lvds_rx/reg8_syn_157.mi[0]
Hold check
-1049 3
-Endpoint: ua_lvds_rx/ramread0_syn_32
-1051 0.092000 2 2
-Timing path: ua_lvds_rx/reg3_syn_190.clk->ua_lvds_rx/ramread0_syn_32
-ua_lvds_rx/reg3_syn_190.clk
-ua_lvds_rx/ramread0_syn_32
-1053 0.092000 2.066000 2.158000 1 1
-ua_lvds_rx/para_data[6] ua_lvds_rx/ramread0_syn_32.c[1]
-
-Timing path: ua_lvds_rx/reg16_syn_31.clk->ua_lvds_rx/ramread0_syn_32
-ua_lvds_rx/reg16_syn_31.clk
-ua_lvds_rx/ramread0_syn_32
-1087 0.369000 2.066000 2.435000 1 1
-ua_lvds_rx/wcnt[2] ua_lvds_rx/ramread0_syn_32.c[0]
-
-
+1161 3
Endpoint: ua_lvds_rx/ramread0_syn_102
-1121 0.114000 2 2
-Timing path: ua_lvds_rx/reg16_syn_33.clk->ua_lvds_rx/ramread0_syn_102
-ua_lvds_rx/reg16_syn_33.clk
+1163 0.092000 2 2
+Timing path: ua_lvds_rx/reg3_syn_184.clk->ua_lvds_rx/ramread0_syn_102
+ua_lvds_rx/reg3_syn_184.clk
ua_lvds_rx/ramread0_syn_102
-1123 0.114000 2.066000 2.180000 1 1
-ua_lvds_rx/wcnt[1] ua_lvds_rx/ramread0_syn_102.b[0]
-
-Timing path: ua_lvds_rx/reg8_syn_147.clk->ua_lvds_rx/ramread0_syn_102
-ua_lvds_rx/reg8_syn_147.clk
-ua_lvds_rx/ramread0_syn_102
-1157 0.289000 2.066000 2.355000 1 1
+1165 0.092000 2.157000 2.249000 1 1
ua_lvds_rx/para_data[25] ua_lvds_rx/ramread0_syn_102.b[1]
+Timing path: ua_lvds_rx/reg16_syn_31.clk->ua_lvds_rx/ramread0_syn_102
+ua_lvds_rx/reg16_syn_31.clk
+ua_lvds_rx/ramread0_syn_102
+1199 0.409000 2.157000 2.566000 1 1
+ua_lvds_rx/wcnt[1] ua_lvds_rx/ramread0_syn_102.b[0]
+
Endpoint: ua_lvds_rx/ramread0_syn_116
-1191 0.167000 2 2
-Timing path: ua_lvds_rx/reg3_syn_198.clk->ua_lvds_rx/ramread0_syn_116
-ua_lvds_rx/reg3_syn_198.clk
+1233 0.167000 2 2
+Timing path: ua_lvds_rx/reg14_syn_62.clk->ua_lvds_rx/ramread0_syn_116
+ua_lvds_rx/reg14_syn_62.clk
ua_lvds_rx/ramread0_syn_116
-1193 0.167000 2.096000 2.263000 1 1
+1235 0.167000 2.187000 2.354000 1 1
ua_lvds_rx/para_data[34] ua_lvds_rx/ramread0_syn_116.c[1]
Timing path: ua_lvds_rx/reg16_syn_31.clk->ua_lvds_rx/ramread0_syn_116
ua_lvds_rx/reg16_syn_31.clk
ua_lvds_rx/ramread0_syn_116
-1227 0.415000 2.096000 2.511000 1 1
+1269 0.345000 2.187000 2.532000 1 1
ua_lvds_rx/wcnt[2] ua_lvds_rx/ramread0_syn_116.c[0]
+Endpoint: ua_lvds_rx/ramread0_syn_116
+1303 0.167000 2 2
+Timing path: ua_lvds_rx/reg3_syn_195.clk->ua_lvds_rx/ramread0_syn_116
+ua_lvds_rx/reg3_syn_195.clk
+ua_lvds_rx/ramread0_syn_116
+1305 0.167000 2.187000 2.354000 1 1
+ua_lvds_rx/para_data[32] ua_lvds_rx/ramread0_syn_116.a[1]
+
+Timing path: ua_lvds_rx/reg16_syn_33.clk->ua_lvds_rx/ramread0_syn_116
+ua_lvds_rx/reg16_syn_33.clk
+ua_lvds_rx/ramread0_syn_116
+1339 0.586000 2.187000 2.773000 1 1
+ua_lvds_rx/wcnt[0] ua_lvds_rx/ramread0_syn_116.a[0]
+
+
clock: b_lvds_clk_p
-1263 0 0 0
+1375 0 0 0
clock: b_pclk
-1271 105758 5876 2
+1383 101266 5874 2
Setup check
-1281 3
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23
-1281 10.591000 171 3
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23
+1393 3
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25
+1393 10.740000 70 3
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23
-1283 10.591000 22.929000 12.338000 6 6
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7] u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238 sampling_fe_a/reg1_syn_61.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.a[1]
-
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23
-1331 10.591000 22.929000 12.338000 6 6
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7] u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238 sampling_fe_a/reg1_syn_61.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.a[0]
-
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23
-1379 10.598000 22.929000 12.331000 6 7
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25
+1395 10.740000 22.857000 12.117000 6 9
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7] u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238 sampling_fe_a/reg1_syn_61.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.a[1]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg3_syn_167.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0]
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514
-1429 10.711000 70 3
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514
-1431 10.711000 22.929000 12.218000 6 6
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7] u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238 sampling_fe_a/reg1_syn_61.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25
+1449 10.763000 22.857000 12.094000 6 7
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[7] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg3_syn_167.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0]
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514
-1479 10.718000 22.929000 12.211000 6 7
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25
+1499 10.810000 22.857000 12.047000 6 6
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[10] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.a[1]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg3_syn_167.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0]
+
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
+1547 10.755000 171 3
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
+1549 10.755000 22.857000 12.102000 6 9
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7] u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238 sampling_fe_a/reg1_syn_61.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg3_syn_167.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1]
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514
-1529 10.783000 22.929000 12.146000 6 6
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[6] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[1]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
+1603 10.755000 22.857000 12.102000 6 9
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7] u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238 sampling_fe_a/reg1_syn_61.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg3_syn_167.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[0]
+
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
+1657 10.778000 22.857000 12.079000 6 7
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[7] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg3_syn_167.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1]
-Endpoint: exdev_ctl_b/u_gen_sp/reg0_syn_74
-1577 11.561000 214 3
-Timing path: exdev_ctl_b/u_gen_sp/reg9_syn_89.clk->exdev_ctl_b/u_gen_sp/reg0_syn_74
-exdev_ctl_b/u_gen_sp/reg9_syn_89.clk
-exdev_ctl_b/u_gen_sp/reg0_syn_74
-1579 11.561000 22.858000 11.297000 8 11
+Endpoint: exdev_ctl_b/u_gen_sp/reg0_syn_77
+1707 12.253000 214 3
+Timing path: exdev_ctl_b/u_gen_sp/reg9_syn_78.clk->exdev_ctl_b/u_gen_sp/reg0_syn_77
+exdev_ctl_b/u_gen_sp/reg9_syn_78.clk
+exdev_ctl_b/u_gen_sp/reg0_syn_77
+1709 12.253000 22.858000 10.605000 7 8
+exdev_ctl_b/u_gen_sp/sp_t_d1[7] exdev_ctl_b/u_gen_sp/sub1_syn_104.a[0]
+exdev_ctl_b/u_gen_sp/sub1_syn_95 exdev_ctl_b/u_gen_sp/sub1_syn_105.fci
+exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12] u_pixel_cdc/u_clkb_mipi_total_num/reg1_syn_415.a[1]
+exdev_ctl_b/u_gen_sp/mux31_syn_138 exdev_ctl_b/u_gen_sp/reg9_syn_69.a[0]
+exdev_ctl_b/u_gen_sp/mux31_syn_140 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_464.a[1]
+exdev_ctl_b/u_gen_sp/mux31_syn_148 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_456.a[1]
+exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_517.c[0]
+exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_77.sr
+
+Timing path: exdev_ctl_b/u_gen_sp/reg9_syn_92.clk->exdev_ctl_b/u_gen_sp/reg0_syn_77
+exdev_ctl_b/u_gen_sp/reg9_syn_92.clk
+exdev_ctl_b/u_gen_sp/reg0_syn_77
+1761 12.379000 22.858000 10.479000 7 10
exdev_ctl_b/u_gen_sp/sp_t_d1[1] exdev_ctl_b/u_gen_sp/sub1_syn_102.a[1]
exdev_ctl_b/u_gen_sp/sub1_syn_87 exdev_ctl_b/u_gen_sp/sub1_syn_103.fci
exdev_ctl_b/u_gen_sp/sub1_syn_91 exdev_ctl_b/u_gen_sp/sub1_syn_104.fci
exdev_ctl_b/u_gen_sp/sub1_syn_95 exdev_ctl_b/u_gen_sp/sub1_syn_105.fci
-exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12] u_a_sp_sampling/reg0_syn_27.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_139 exdev_ctl_b/u_gen_sp/reg9_syn_103.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_141 sampling_fe_a/u_ad_sampling/sp_1d_reg_syn_8.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_149 u_bus_top/u_local_bus_slve_cis/reg53_syn_51.a[0]
-exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 u_bus_top/u_local_bus_slve_cis/reg54_syn_47.a[0]
-exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2 u_bus_top/u_local_bus_slve_cis/reg55_syn_42.a[1]
-exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_74.sr
+exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12] u_pixel_cdc/u_clkb_mipi_total_num/reg1_syn_415.a[1]
+exdev_ctl_b/u_gen_sp/mux31_syn_138 exdev_ctl_b/u_gen_sp/reg9_syn_69.a[0]
+exdev_ctl_b/u_gen_sp/mux31_syn_140 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_464.a[1]
+exdev_ctl_b/u_gen_sp/mux31_syn_148 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_456.a[1]
+exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_517.c[0]
+exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_77.sr
-Timing path: exdev_ctl_b/u_gen_sp/reg8_syn_107.clk->exdev_ctl_b/u_gen_sp/reg0_syn_74
-exdev_ctl_b/u_gen_sp/reg8_syn_107.clk
-exdev_ctl_b/u_gen_sp/reg0_syn_74
-1637 11.662000 22.858000 11.196000 8 9
-exdev_ctl_b/u_gen_sp/sp_t_d1[9] exdev_ctl_b/u_gen_sp/sub1_syn_104.a[1]
-exdev_ctl_b/u_gen_sp/sub1_syn_95 exdev_ctl_b/u_gen_sp/sub1_syn_105.fci
-exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12] u_a_sp_sampling/reg0_syn_27.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_139 exdev_ctl_b/u_gen_sp/reg9_syn_103.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_141 sampling_fe_a/u_ad_sampling/sp_1d_reg_syn_8.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_149 u_bus_top/u_local_bus_slve_cis/reg53_syn_51.a[0]
-exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 u_bus_top/u_local_bus_slve_cis/reg54_syn_47.a[0]
-exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2 u_bus_top/u_local_bus_slve_cis/reg55_syn_42.a[1]
-exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_74.sr
-
-Timing path: exdev_ctl_b/u_gen_sp/reg9_syn_106.clk->exdev_ctl_b/u_gen_sp/reg0_syn_74
-exdev_ctl_b/u_gen_sp/reg9_syn_106.clk
-exdev_ctl_b/u_gen_sp/reg0_syn_74
-1691 11.726000 22.858000 11.132000 8 11
+Timing path: exdev_ctl_b/u_gen_sp/reg9_syn_90.clk->exdev_ctl_b/u_gen_sp/reg0_syn_77
+exdev_ctl_b/u_gen_sp/reg9_syn_90.clk
+exdev_ctl_b/u_gen_sp/reg0_syn_77
+1817 12.427000 22.858000 10.431000 7 10
exdev_ctl_b/u_gen_sp/sp_t_d1[0] exdev_ctl_b/u_gen_sp/sub1_syn_102.b[0]
exdev_ctl_b/u_gen_sp/sub1_syn_87 exdev_ctl_b/u_gen_sp/sub1_syn_103.fci
exdev_ctl_b/u_gen_sp/sub1_syn_91 exdev_ctl_b/u_gen_sp/sub1_syn_104.fci
exdev_ctl_b/u_gen_sp/sub1_syn_95 exdev_ctl_b/u_gen_sp/sub1_syn_105.fci
-exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12] u_a_sp_sampling/reg0_syn_27.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_139 exdev_ctl_b/u_gen_sp/reg9_syn_103.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_141 sampling_fe_a/u_ad_sampling/sp_1d_reg_syn_8.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_149 u_bus_top/u_local_bus_slve_cis/reg53_syn_51.a[0]
-exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 u_bus_top/u_local_bus_slve_cis/reg54_syn_47.a[0]
-exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2 u_bus_top/u_local_bus_slve_cis/reg55_syn_42.a[1]
-exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_74.sr
+exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12] u_pixel_cdc/u_clkb_mipi_total_num/reg1_syn_415.a[1]
+exdev_ctl_b/u_gen_sp/mux31_syn_138 exdev_ctl_b/u_gen_sp/reg9_syn_69.a[0]
+exdev_ctl_b/u_gen_sp/mux31_syn_140 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_464.a[1]
+exdev_ctl_b/u_gen_sp/mux31_syn_148 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_456.a[1]
+exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_517.c[0]
+exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_77.sr
Hold check
-1749 3
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
-1751 0.080000 10 3
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_663.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_663.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
-1753 0.080000 2.183000 2.263000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[100] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.addra[3]
+1873 3
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1
+1875 0.114000 10 3
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_719.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_719.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1
+1877 0.114000 2.183000 2.297000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[39] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[12]
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_625.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_625.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
-1791 0.089000 2.183000 2.272000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[103] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.addra[6]
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_721.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_721.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1
+1915 0.114000 2.183000 2.297000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[38] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[11]
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_665.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_665.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
-1829 0.234000 2.183000 2.417000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[101] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.addra[4]
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_719.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_719.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1
+1953 0.195000 2.183000 2.378000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[30] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[3]
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
-1867 0.080000 8 3
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_27.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_27.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
-1869 0.080000 2.183000 2.263000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[80] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.dia[0]
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1
+1991 0.147000 8 3
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_624.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_624.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1
+1993 0.147000 2.183000 2.330000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[12] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.dia[4]
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_666.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_666.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
-1907 0.130000 2.183000 2.313000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[82] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.dia[2]
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_606.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_606.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1
+2031 0.186000 2.183000 2.369000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[15] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.dia[7]
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_543.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_543.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
-1945 0.186000 2.183000 2.369000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[87] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.dia[7]
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_606.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_606.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1
+2069 0.186000 2.183000 2.369000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[13] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.dia[5]
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1
-1983 0.114000 10 3
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_712.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_712.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1
-1985 0.114000 2.183000 2.297000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[68] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.addra[11]
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
+2107 0.186000 8 3
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_582.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_582.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
+2109 0.186000 2.183000 2.369000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[47] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[7]
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_712.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_712.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1
-2023 0.205000 2.183000 2.388000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[67] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.addra[10]
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_574.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_574.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
+2147 0.311000 2.183000 2.494000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[41] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[1]
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_703.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_703.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1
-2061 0.302000 2.183000 2.485000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[66] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.addra[9]
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_525.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_525.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
+2185 0.411000 2.183000 2.594000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[45] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[5]
clock: b_sclk
-2099 690 282 2
+2223 706 282 2
Setup check
-2109 3
+2233 3
Endpoint: ub_lvds_rx/rx_clk_sync_reg_syn_5
-2109 4.099000 7 3
-Timing path: ub_lvds_rx/reg7_syn_32.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5
-ub_lvds_rx/reg7_syn_32.clk
+2233 3.794000 7 3
+Timing path: ub_lvds_rx/reg7_syn_33.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5
+ub_lvds_rx/reg7_syn_33.clk
ub_lvds_rx/rx_clk_sync_reg_syn_5
-2111 4.099000 8.210000 4.111000 2 2
-ub_lvds_rx/rx_clk_sft[0] ub_lvds_rx/rx_clk_sync_reg_syn_5.a[0]
+2235 3.794000 8.076000 4.282000 2 2
+ub_lvds_rx/rx_clk_sft[1] ub_lvds_rx/rx_clk_sync_reg_syn_5.b[0]
ub_lvds_rx/rx_clk_sync_n_syn_2 ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1]
Timing path: ub_lvds_rx/reg7_syn_25.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5
ub_lvds_rx/reg7_syn_25.clk
ub_lvds_rx/rx_clk_sync_reg_syn_5
-2147 4.175000 8.210000 4.035000 2 2
+2271 4.018000 8.076000 4.058000 2 2
ub_lvds_rx/rx_clk_sft[2] ub_lvds_rx/rx_clk_sync_reg_syn_5.c[0]
ub_lvds_rx/rx_clk_sync_n_syn_2 ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1]
-Timing path: ub_lvds_rx/reg7_syn_32.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5
-ub_lvds_rx/reg7_syn_32.clk
+Timing path: ub_lvds_rx/reg7_syn_25.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5
+ub_lvds_rx/reg7_syn_25.clk
ub_lvds_rx/rx_clk_sync_reg_syn_5
-2183 4.364000 8.210000 3.846000 2 2
-ub_lvds_rx/rx_clk_sft[1] ub_lvds_rx/rx_clk_sync_reg_syn_5.b[0]
+2307 4.087000 8.076000 3.989000 2 2
+ub_lvds_rx/rx_clk_sft[4] ub_lvds_rx/rx_clk_sync_reg_syn_5.e[0]
ub_lvds_rx/rx_clk_sync_n_syn_2 ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1]
-Endpoint: ub_lvds_rx/reg8_syn_145
-2219 4.145000 9 3
-Timing path: ub_lvds_rx/reg8_syn_145.clk->ub_lvds_rx/reg8_syn_145
-ub_lvds_rx/reg8_syn_145.clk
-ub_lvds_rx/reg8_syn_145
-2221 4.145000 8.246000 4.101000 1 1
-ub_lvds_rx/para_data[25] ub_lvds_rx/reg8_syn_145.a[1]
+Endpoint: ub_lvds_rx/reg16_syn_31
+2343 4.143000 4 3
+Timing path: ub_lvds_rx/para_en_reg_syn_5.clk->ub_lvds_rx/reg16_syn_31
+ub_lvds_rx/para_en_reg_syn_5.clk
+ub_lvds_rx/reg16_syn_31
+2345 4.143000 8.091000 3.948000 1 1
+ub_lvds_rx/para_en ub_lvds_rx/reg16_syn_31.a[0]
-Timing path: ub_lvds_rx/reg8_syn_143.clk->ub_lvds_rx/reg8_syn_145
-ub_lvds_rx/reg8_syn_143.clk
-ub_lvds_rx/reg8_syn_145
-2255 4.156000 8.246000 4.090000 1 1
-ub_lvds_rx/rx_data[28] ub_lvds_rx/reg8_syn_145.b[1]
+Timing path: ub_lvds_rx/reg16_syn_33.clk->ub_lvds_rx/reg16_syn_31
+ub_lvds_rx/reg16_syn_33.clk
+ub_lvds_rx/reg16_syn_31
+2379 4.403000 8.091000 3.688000 1 1
+ub_lvds_rx/wcnt[0] ub_lvds_rx/reg16_syn_31.b[0]
-Timing path: ub_lvds_rx/reg8_syn_143.clk->ub_lvds_rx/reg8_syn_145
-ub_lvds_rx/reg8_syn_143.clk
-ub_lvds_rx/reg8_syn_145
-2289 4.156000 8.246000 4.090000 1 1
-ub_lvds_rx/rx_data[28] ub_lvds_rx/reg8_syn_145.b[0]
+Timing path: ub_lvds_rx/reg16_syn_31.clk->ub_lvds_rx/reg16_syn_31
+ub_lvds_rx/reg16_syn_31.clk
+ub_lvds_rx/reg16_syn_31
+2413 4.442000 8.091000 3.649000 1 1
+ub_lvds_rx/wcnt[1] ub_lvds_rx/reg16_syn_31.c[0]
-Endpoint: ub_lvds_rx/reg8_syn_149
-2323 4.166000 9 3
-Timing path: ub_lvds_rx/reg8_syn_131.clk->ub_lvds_rx/reg8_syn_149
-ub_lvds_rx/reg8_syn_131.clk
-ub_lvds_rx/reg8_syn_149
-2325 4.166000 8.182000 4.016000 1 1
-ub_lvds_rx/rx_data[24] ub_lvds_rx/reg8_syn_149.b[1]
+Endpoint: ub_lvds_rx/reg8_syn_147
+2447 4.145000 9 3
+Timing path: ub_lvds_rx/reg8_syn_147.clk->ub_lvds_rx/reg8_syn_147
+ub_lvds_rx/reg8_syn_147.clk
+ub_lvds_rx/reg8_syn_147
+2449 4.145000 8.112000 3.967000 1 1
+ub_lvds_rx/para_data[11] ub_lvds_rx/reg8_syn_147.a[1]
-Timing path: ub_lvds_rx/reg8_syn_131.clk->ub_lvds_rx/reg8_syn_149
-ub_lvds_rx/reg8_syn_131.clk
-ub_lvds_rx/reg8_syn_149
-2359 4.166000 8.182000 4.016000 1 1
-ub_lvds_rx/rx_data[24] ub_lvds_rx/reg8_syn_149.b[0]
+Timing path: ub_lvds_rx/reg12_syn_17.clk->ub_lvds_rx/reg8_syn_147
+ub_lvds_rx/reg12_syn_17.clk
+ub_lvds_rx/reg8_syn_147
+2483 4.294000 8.112000 3.818000 1 1
+ub_lvds_rx/sync0 ub_lvds_rx/reg8_syn_147.d[1]
-Timing path: ub_lvds_rx/sync0_reg_syn_4.clk->ub_lvds_rx/reg8_syn_149
-ub_lvds_rx/sync0_reg_syn_4.clk
-ub_lvds_rx/reg8_syn_149
-2393 4.324000 8.182000 3.858000 1 1
-ub_lvds_rx/sync0 ub_lvds_rx/reg8_syn_149.d[1]
+Timing path: ub_lvds_rx/reg12_syn_17.clk->ub_lvds_rx/reg8_syn_147
+ub_lvds_rx/reg12_syn_17.clk
+ub_lvds_rx/reg8_syn_147
+2517 4.294000 8.112000 3.818000 1 1
+ub_lvds_rx/sync0 ub_lvds_rx/reg8_syn_147.d[0]
Hold check
-2427 3
-Endpoint: ub_lvds_rx/ramread0_syn_74
-2429 0.104000 2 2
-Timing path: ub_lvds_rx/reg3_syn_180.clk->ub_lvds_rx/ramread0_syn_74
-ub_lvds_rx/reg3_syn_180.clk
-ub_lvds_rx/ramread0_syn_74
-2431 0.104000 2.250000 2.354000 1 1
-ub_lvds_rx/para_data[18] ub_lvds_rx/ramread0_syn_74.c[1]
+2551 3
+Endpoint: ub_lvds_rx/ramread0_syn_102
+2553 0.167000 2 2
+Timing path: ub_lvds_rx/reg8_syn_161.clk->ub_lvds_rx/ramread0_syn_102
+ub_lvds_rx/reg8_syn_161.clk
+ub_lvds_rx/ramread0_syn_102
+2555 0.167000 2.096000 2.263000 1 1
+ub_lvds_rx/para_data[26] ub_lvds_rx/ramread0_syn_102.c[1]
-Timing path: ub_lvds_rx/reg16_syn_31.clk->ub_lvds_rx/ramread0_syn_74
+Timing path: ub_lvds_rx/reg16_syn_31.clk->ub_lvds_rx/ramread0_syn_102
ub_lvds_rx/reg16_syn_31.clk
-ub_lvds_rx/ramread0_syn_74
-2465 0.199000 2.250000 2.449000 1 1
-ub_lvds_rx/wcnt[2] ub_lvds_rx/ramread0_syn_74.c[0]
+ub_lvds_rx/ramread0_syn_102
+2589 0.345000 2.096000 2.441000 1 1
+ub_lvds_rx/wcnt[2] ub_lvds_rx/ramread0_syn_102.c[0]
+
+
+Endpoint: ub_lvds_rx/ramread0_syn_18
+2623 0.167000 2 2
+Timing path: ub_lvds_rx/reg3_syn_163.clk->ub_lvds_rx/ramread0_syn_18
+ub_lvds_rx/reg3_syn_163.clk
+ub_lvds_rx/ramread0_syn_18
+2625 0.167000 2.096000 2.263000 1 1
+ub_lvds_rx/para_data[2] ub_lvds_rx/ramread0_syn_18.c[1]
+
+Timing path: ub_lvds_rx/reg16_syn_31.clk->ub_lvds_rx/ramread0_syn_18
+ub_lvds_rx/reg16_syn_31.clk
+ub_lvds_rx/ramread0_syn_18
+2659 0.199000 2.096000 2.295000 1 1
+ub_lvds_rx/wcnt[2] ub_lvds_rx/ramread0_syn_18.c[0]
Endpoint: ub_lvds_rx/ramread0_syn_102
-2499 0.113000 2 2
-Timing path: ub_lvds_rx/reg3_syn_175.clk->ub_lvds_rx/ramread0_syn_102
-ub_lvds_rx/reg3_syn_175.clk
+2693 0.176000 1 1
+Timing path: ub_lvds_rx/reg3_syn_185.clk->ub_lvds_rx/ramread0_syn_102
+ub_lvds_rx/reg3_syn_185.clk
ub_lvds_rx/ramread0_syn_102
-2501 0.113000 2.250000 2.363000 1 1
-ub_lvds_rx/para_data[24] ub_lvds_rx/ramread0_syn_102.a[1]
-
-Timing path: ub_lvds_rx/reg16_syn_33.clk->ub_lvds_rx/ramread0_syn_102
-ub_lvds_rx/reg16_syn_33.clk
-ub_lvds_rx/ramread0_syn_102
-2535 0.345000 2.250000 2.595000 1 1
-ub_lvds_rx/wcnt[0] ub_lvds_rx/ramread0_syn_102.a[0]
-
-
-Endpoint: ub_lvds_rx/ramread0_syn_74
-2569 0.113000 1 1
-Timing path: ub_lvds_rx/reg3_syn_180.clk->ub_lvds_rx/ramread0_syn_74
-ub_lvds_rx/reg3_syn_180.clk
-ub_lvds_rx/ramread0_syn_74
-2571 0.113000 2.250000 2.363000 1 1
-ub_lvds_rx/para_data[19] ub_lvds_rx/ramread0_syn_74.d[1]
+2695 0.176000 2.096000 2.272000 1 1
+ub_lvds_rx/para_data[27] ub_lvds_rx/ramread0_syn_102.d[1]
clock: clock_source
-2607 0 0 0
+2731 0 0 0
clock: S_clk
-2615 111938 8572 5
+2739 107786 8640 5
Setup check
-2625 3
-Endpoint: reg7_syn_149
-2625 0.108000 188 3
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb->reg7_syn_149
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb
-reg7_syn_149
-2627 0.108000 11.488000 11.380000 7 7
-sampling_fe_a/u_sort/u_data_prebuffer/dou_i[1][18] adj_datao_b1[2]_syn_73.b[1]
-adj_datao_b1[2]_syn_16 adj_datao_b1[2]_syn_79.a[1]
-adj_datao_b1[2]_syn_18 sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_79.a[1]
-adj_datao_b1[2]_syn_32 sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_488.a[1]
-sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[2] sampling_fe_a/u_sort/u_transfer_300_to_200/reg10_syn_128.b[0]
-adj_datao_b1[2]_syn_39 sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_59.a[0]
-adj_datao_b1[2]_syn_43 reg7_syn_149.a[0]
-
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb->reg7_syn_149
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb
-reg7_syn_149
-2677 0.108000 11.488000 11.380000 7 7
-sampling_fe_a/u_sort/u_data_prebuffer/dou_i[1][18] adj_datao_b1[2]_syn_73.b[1]
-adj_datao_b1[2]_syn_16 adj_datao_b1[2]_syn_79.a[1]
-adj_datao_b1[2]_syn_18 sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_79.a[1]
-adj_datao_b1[2]_syn_32 sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_488.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[2] sampling_fe_a/u_sort/u_transfer_300_to_200/reg10_syn_128.b[0]
-adj_datao_b1[2]_syn_39 sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_59.a[0]
-adj_datao_b1[2]_syn_43 reg7_syn_149.a[0]
-
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb->reg7_syn_149
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb
-reg7_syn_149
-2727 0.415000 11.488000 11.073000 7 7
-sampling_fe_a/u_sort/u_data_prebuffer/dou_i[0][18] adj_datao_b1[2]_syn_73.a[1]
-adj_datao_b1[2]_syn_16 adj_datao_b1[2]_syn_79.a[1]
-adj_datao_b1[2]_syn_18 sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_79.a[1]
-adj_datao_b1[2]_syn_32 sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_488.a[1]
-sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[2] sampling_fe_a/u_sort/u_transfer_300_to_200/reg10_syn_128.b[0]
-adj_datao_b1[2]_syn_39 sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_59.a[0]
-adj_datao_b1[2]_syn_43 reg7_syn_149.a[0]
+2749 3
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/add9_syn_86
+2749 0.208000 1 1
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/add9_syn_86
+sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/add9_syn_86
+2751 0.208000 4.317000 4.109000 1 2
+sampling_fe_b/u_sort/u_data_prebuffer_rev/raw_switch[0] sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_49.b[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_13 sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/add9_syn_86.mi[0]
-Endpoint: reg7_syn_152
-2777 0.309000 114 3
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clkb->reg7_syn_152
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clkb
-reg7_syn_152
-2779 0.309000 11.488000 11.179000 7 7
-sampling_fe_a/u_sort/u_data_prebuffer/dou_i[1][45] reg6_syn_164.b[0]
-adj_datao_b1[21]_syn_22 adj_datao_b1[21]_syn_70.a[1]
-adj_datao_b1[21]_syn_26 u_bus_top/u_local_bus_slve_cis/sel23_syn_6787.a[0]
-adj_datao_b1[5]_syn_20 sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_491.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[5] u_bus_top/reg15_syn_186.a[1]
-adj_datao_b1[5]_syn_27 sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_56.a[1]
-adj_datao_b1[5]_syn_31 reg7_syn_152.a[0]
-
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb->reg7_syn_152
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb
-reg7_syn_152
-2829 0.591000 11.488000 10.897000 7 7
-sampling_fe_a/u_sort/u_data_prebuffer/dou_i[0][21] clkmipi_rstn_reg_syn_13.d[0]
-adj_datao_b1[21]_syn_24 adj_datao_b1[21]_syn_70.b[1]
-adj_datao_b1[21]_syn_26 u_bus_top/u_local_bus_slve_cis/sel23_syn_6787.a[0]
-adj_datao_b1[5]_syn_20 sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_491.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[5] u_bus_top/reg15_syn_186.a[1]
-adj_datao_b1[5]_syn_27 sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_56.a[1]
-adj_datao_b1[5]_syn_31 reg7_syn_152.a[0]
-
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst_syn_1.clkb->reg7_syn_152
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst_syn_1.clkb
-reg7_syn_152
-2879 0.607000 11.488000 10.881000 7 7
-sampling_fe_a/u_sort/u_data_prebuffer/dou_i[0][45] reg6_syn_164.a[0]
-adj_datao_b1[21]_syn_22 adj_datao_b1[21]_syn_70.a[1]
-adj_datao_b1[21]_syn_26 u_bus_top/u_local_bus_slve_cis/sel23_syn_6787.a[0]
-adj_datao_b1[5]_syn_20 sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_491.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[5] u_bus_top/reg15_syn_186.a[1]
-adj_datao_b1[5]_syn_27 sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_56.a[1]
-adj_datao_b1[5]_syn_31 reg7_syn_152.a[0]
-
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_97
-2929 0.353000 1 1
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk->sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_97
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2
+2791 0.279000 1 1
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk->sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2
sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk
-sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_97
-2931 0.353000 4.317000 3.964000 1 2
-sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0] sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_75.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13 sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_97.mi[0]
+sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2
+2793 0.279000 4.317000 4.038000 1 2
+sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0] sampling_fe_a/u_sort/u_transfer_300_to_200/data_f_b4_n87_syn_28.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13 sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2.mi[0]
+
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2
+2833 0.279000 1 1
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk->sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2
+sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk
+sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2
+2835 0.279000 4.317000 4.038000 1 2
+sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0] sampling_fe_a/u_sort/u_transfer_300_to_200/data_f_b4_n87_syn_28.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13 sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2.mi[1]
Hold check
-2971 3
-Endpoint: u_mipi_sot_min/reg1_syn_265
-2973 0.067000 1 1
-Timing path: u_bus_top/reg19_syn_84.clk->u_mipi_sot_min/reg1_syn_265
-u_bus_top/reg19_syn_84.clk
-u_mipi_sot_min/reg1_syn_265
-2975 0.067000 2.291000 2.358000 0 1
-u_mipi_sot_min/signal_from[3] u_mipi_sot_min/reg1_syn_265.mi[1]
+2875 3
+Endpoint: u_mipi_eot_min/reg1_syn_275
+2877 0.067000 1 1
+Timing path: u_bus_top/reg18_syn_74.clk->u_mipi_eot_min/reg1_syn_275
+u_bus_top/reg18_syn_74.clk
+u_mipi_eot_min/reg1_syn_275
+2879 0.067000 2.291000 2.358000 0 1
+u_mipi_eot_min/signal_from[1] u_mipi_eot_min/reg1_syn_275.mi[1]
-Endpoint: u_mipi_sot_min/reg1_syn_283
-3011 0.067000 1 1
-Timing path: u_bus_top/reg18_syn_72.clk->u_mipi_sot_min/reg1_syn_283
-u_bus_top/reg18_syn_72.clk
-u_mipi_sot_min/reg1_syn_283
-3013 0.067000 2.291000 2.358000 0 1
-u_mipi_sot_min/signal_from[2] u_mipi_sot_min/reg1_syn_283.mi[1]
+Endpoint: add0_syn_146
+2915 0.067000 1 1
+Timing path: reg36_syn_118.clk->add0_syn_146
+reg36_syn_118.clk
+add0_syn_146
+2917 0.067000 2.291000 2.358000 0 1
+u_pic_cnt/signal_from[9] add0_syn_146.mi[0]
-Endpoint: reg13_syn_43
-3049 0.075000 1 1
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/channelPart/wr_end_reg_syn_8.clk->reg13_syn_43
-sampling_fe_a/u_sort/u_data_prebuffer/channelPart/wr_end_reg_syn_8.clk
-reg13_syn_43
-3051 0.075000 2.291000 2.366000 0 1
-sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/u0_rdsoft_n/signal_from[0] reg13_syn_43.mi[0]
+Endpoint: u_pic_cnt/reg1_syn_465
+2953 0.067000 1 1
+Timing path: reg36_syn_130.clk->u_pic_cnt/reg1_syn_465
+reg36_syn_130.clk
+u_pic_cnt/reg1_syn_465
+2955 0.067000 2.291000 2.358000 0 1
+u_pic_cnt/signal_from[4] u_pic_cnt/reg1_syn_465.mi[0]
Recovery check
-3089 3
-Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070
-3091 5.584000 2 2
-Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070
+2991 3
+Endpoint: U_rgb_to_csi_pakage/reg10_syn_53_syn_2
+2993 5.512000 1 1
+Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/reg10_syn_53_syn_2
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070
-3093 5.584000 11.304000 5.720000 2 3
-U_rgb_to_csi_pakage/S_global_en reg21_syn_52_syn_2.d[0]
-U_rgb_to_csi_pakage/S_rst_n U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.d[0]
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070.sr
-
-Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070
-adj_vsynco_reg_syn_5.clk
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070
-3135 5.858000 11.304000 5.446000 1 2
-U_rgb_to_csi_pakage/I_rgb_vsync U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.c[0]
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070.sr
+U_rgb_to_csi_pakage/reg10_syn_53_syn_2
+2995 5.512000 11.304000 5.792000 1 2
+U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/S_frame_start_delay_n_edge_1d_reg_syn_6_syn_2.d[0]
+U_rgb_to_csi_pakage/S_rst_n_dup_1 U_rgb_to_csi_pakage/reg10_syn_53_syn_2.sr
-Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2
-3175 6.014000 2 2
-Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2
+Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2
+3035 5.735000 2 2
+Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2
-3177 6.014000 11.304000 5.290000 2 3
-U_rgb_to_csi_pakage/S_global_en reg21_syn_52_syn_2.d[0]
-U_rgb_to_csi_pakage/S_rst_n U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.d[0]
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2.sr
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2
+3037 5.735000 11.304000 5.569000 2 3
+U_rgb_to_csi_pakage/S_global_en reg20_syn_64_syn_2.d[0]
+U_rgb_to_csi_pakage/S_rst_n_dup_5 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_620.d[0]
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2.sr
-Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2
+Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2
adj_vsynco_reg_syn_5.clk
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2
-3219 6.288000 11.304000 5.016000 1 2
-U_rgb_to_csi_pakage/I_rgb_vsync U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.c[0]
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2.sr
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2
+3079 6.339000 11.304000 4.965000 1 2
+U_rgb_to_csi_pakage/I_rgb_vsync sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_620.c[0]
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2.sr
-Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2
-3259 6.026000 2 2
-Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2
+Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
+3119 5.754000 2 2
+Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2
-3261 6.026000 11.304000 5.278000 2 3
-U_rgb_to_csi_pakage/S_global_en reg21_syn_52_syn_2.d[0]
-U_rgb_to_csi_pakage/S_rst_n U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.d[0]
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2.sr
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
+3121 5.754000 11.304000 5.550000 2 3
+U_rgb_to_csi_pakage/S_global_en reg20_syn_64_syn_2.d[0]
+U_rgb_to_csi_pakage/S_rst_n_dup_5 U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_34_syn_2.d[1]
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.sr
-Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2
+Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
adj_vsynco_reg_syn_5.clk
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2
-3303 6.300000 11.304000 5.004000 1 2
-U_rgb_to_csi_pakage/I_rgb_vsync U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.c[0]
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2.sr
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
+3163 6.319000 11.304000 4.985000 1 2
+U_rgb_to_csi_pakage/I_rgb_vsync U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_34_syn_2.c[1]
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.sr
Removal check
-3343 3
-Endpoint: U_rgb_to_csi_pakage/reg7_syn_145_syn_2
-3345 0.773000 1 1
-Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/reg7_syn_145_syn_2
+3203 3
+Endpoint: U_rgb_to_csi_pakage/reg12_syn_73_syn_2
+3205 0.685000 1 1
+Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/reg12_syn_73_syn_2
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
-U_rgb_to_csi_pakage/reg7_syn_145_syn_2
-3347 0.773000 2.327000 3.100000 1 2
-U_rgb_to_csi_pakage/S_global_en reg21_syn_54_syn_2.d[0]
-U_rgb_to_csi_pakage/S_rst_n_dup_4 U_rgb_to_csi_pakage/reg7_syn_145_syn_2.sr
+U_rgb_to_csi_pakage/reg12_syn_73_syn_2
+3207 0.685000 2.311000 2.996000 1 2
+U_rgb_to_csi_pakage/S_global_en reg20_syn_54_syn_2.d[0]
+U_rgb_to_csi_pakage/S_rst_n_dup_2 U_rgb_to_csi_pakage/reg12_syn_73_syn_2.sr
-Endpoint: U_rgb_to_csi_pakage/reg13_syn_67_syn_2
-3387 0.775000 1 1
-Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/reg13_syn_67_syn_2
+Endpoint: U_rgb_to_csi_pakage/reg12_syn_69_syn_2
+3247 0.685000 1 1
+Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/reg12_syn_69_syn_2
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
-U_rgb_to_csi_pakage/reg13_syn_67_syn_2
-3389 0.775000 2.327000 3.102000 1 2
-U_rgb_to_csi_pakage/S_global_en reg21_syn_52_syn_2.d[0]
-U_rgb_to_csi_pakage/S_rst_n U_rgb_to_csi_pakage/reg13_syn_67_syn_2.sr
+U_rgb_to_csi_pakage/reg12_syn_69_syn_2
+3249 0.685000 2.311000 2.996000 1 2
+U_rgb_to_csi_pakage/S_global_en reg20_syn_54_syn_2.d[0]
+U_rgb_to_csi_pakage/S_rst_n_dup_2 U_rgb_to_csi_pakage/reg12_syn_69_syn_2.sr
-Endpoint: U_rgb_to_csi_pakage/reg13_syn_79_syn_2
-3429 0.805000 1 1
-Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/reg13_syn_79_syn_2
+Endpoint: U_rgb_to_csi_pakage/reg7_syn_151_syn_2
+3289 0.781000 1 1
+Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/reg7_syn_151_syn_2
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
-U_rgb_to_csi_pakage/reg13_syn_79_syn_2
-3431 0.805000 2.327000 3.132000 1 2
-U_rgb_to_csi_pakage/S_global_en reg21_syn_52_syn_2.d[0]
-U_rgb_to_csi_pakage/S_rst_n U_rgb_to_csi_pakage/reg13_syn_79_syn_2.sr
+U_rgb_to_csi_pakage/reg7_syn_151_syn_2
+3291 0.781000 2.327000 3.108000 1 2
+U_rgb_to_csi_pakage/S_global_en reg20_syn_54_syn_2.d[0]
+U_rgb_to_csi_pakage/S_rst_n_dup_2 U_rgb_to_csi_pakage/reg7_syn_151_syn_2.sr
Period check
-3471 48
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst_syn_1.clkb
-3475 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst_syn_1.clkb
-3476 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst_syn_1.clkb
-3477 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.clkb
-3478 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst_syn_1.clkb
-3479 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.clkb
-3480 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst_syn_1.clkb
-3481 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.clkb
-3482 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst_syn_1.clkb
-3483 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst_syn_1.clkb
-3484 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst_syn_1.clkb
-3485 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.clkb
-3486 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst_syn_1.clkb
-3487 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst_syn_1.clkb
-3488 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst_syn_1.clkb
-3489 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.clkb
-3490 5.858000 1 0
-
+3331 48
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst_syn_1.clkb
-3491 5.858000 1 0
+3335 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.clkb
-3492 5.858000 1 0
+3336 5.858000 1 0
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clkb
-3493 5.858000 1 0
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.clkb
+3337 5.858000 1 0
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clkb
-3494 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst_syn_1.clkb
-3495 5.858000 1 0
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst_syn_1.clkb
+3338 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst_syn_1.clkb
-3496 5.858000 1 0
+3339 5.858000 1 0
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.clkb
-3497 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb
-3498 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.clkb
-3499 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.clkb
-3500 5.858000 1 0
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst_syn_1.clkb
+3340 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst_syn_1.clkb
-3501 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst_syn_1.clkb
-3502 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst_syn_1.clkb
-3503 5.858000 1 0
+3341 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst_syn_1.clkb
-3504 5.858000 1 0
+3342 5.858000 1 0
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst_syn_1.clkb
-3505 5.858000 1 0
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.clkb
+3343 5.858000 1 0
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.clkb
-3506 5.858000 1 0
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst_syn_1.clkb
+3344 5.858000 1 0
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst_syn_1.clkb
-3507 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst_syn_1.clkb
-3508 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst_syn_1.clkb
-3509 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst_syn_1.clkb
-3510 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.clkb
-3511 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst_syn_1.clkb
-3512 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1.clkb
-3513 5.858000 1 0
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clkb
+3345 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1.clkb
-3514 5.858000 1 0
+3346 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst_syn_1.clkb
+3347 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.clkb
+3348 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst_syn_1.clkb
+3349 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.clkb
+3350 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst_syn_1.clkb
+3351 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst_syn_1.clkb
+3352 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.clkb
+3353 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst_syn_1.clkb
+3354 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst_syn_1.clkb
+3355 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.clkb
+3356 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst_syn_1.clkb
+3357 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.clkb
+3358 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.clkb
+3359 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clkb
+3360 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.clkb
+3361 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst_syn_1.clkb
+3362 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.clkb
+3363 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb
+3364 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst_syn_1.clkb
+3365 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst_syn_1.clkb
+3366 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst_syn_1.clkb
+3367 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst_syn_1.clkb
+3368 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst_syn_1.clkb
+3369 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst_syn_1.clkb
+3370 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst_syn_1.clkb
+3371 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst_syn_1.clkb
+3372 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1.clkb
+3373 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb
-3515 5.858000 1 0
+3374 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst_syn_1.clkb
+3375 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst_syn_1.clkb
-3516 5.858000 1 0
+3376 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.clkb
-3517 5.858000 1 0
+3377 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1.clkb
-3518 5.858000 1 0
-
-Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw
-3519 5.958000 1 0
+3378 5.858000 1 0
Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw
-3520 5.958000 1 0
+3379 5.958000 1 0
-Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw
-3521 5.958000 1 0
+Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw
+3380 5.958000 1 0
Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw
-3522 5.958000 1 0
+3381 5.958000 1 0
+
+Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw
+3382 5.958000 1 0
clock: clk_adc
-3523 45638 4282 4
+3383 43224 4240 4
Setup check
-3533 3
-Endpoint: reg40_syn_14
-3533 -1.797000 2 2
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk->reg40_syn_14
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk
-reg40_syn_14
-3535 -1.797000 1.949000 3.746000 1 2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d reg29_syn_16.c[0]
-O_clk_lp_n_dup_1 reg40_syn_14.mi[0]
+3393 3
+Endpoint: reg40_syn_12
+3393 -1.945000 2 2
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add18_syn_70.clk->reg40_syn_12
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add18_syn_70.clk
+reg40_syn_12
+3395 -1.945000 1.949000 3.894000 1 2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d reg29_syn_13.d[0]
+O_clk_lp_n_dup_1 reg40_syn_12.mi[1]
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk->reg40_syn_14
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk
-reg40_syn_14
-3571 -1.738000 1.949000 3.687000 1 2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d reg29_syn_16.d[0]
-O_clk_lp_n_dup_1 reg40_syn_14.mi[0]
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1_syn_69.clk->reg40_syn_12
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1_syn_69.clk
+reg40_syn_12
+3431 -1.844000 1.949000 3.793000 1 2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d reg29_syn_13.c[0]
+O_clk_lp_n_dup_1 reg40_syn_12.mi[1]
-Endpoint: reg41_syn_15
-3607 -1.510000 1 1
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk->reg41_syn_15
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk
-reg41_syn_15
-3609 -1.510000 1.949000 3.459000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d reg41_syn_15.mi[0]
+Endpoint: reg40_syn_12
+3467 -1.334000 1 1
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1_syn_69.clk->reg40_syn_12
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1_syn_69.clk
+reg40_syn_12
+3469 -1.334000 1.949000 3.283000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d reg40_syn_12.mi[0]
-Endpoint: u_bus_top/reg13_syn_216
-3643 6.926000 1 1
-Timing path: reg26_syn_241.clk->u_bus_top/reg13_syn_216
-reg26_syn_241.clk
-u_bus_top/reg13_syn_216
-3645 6.926000 11.187000 4.261000 0 1
-lv_cnt_a[31] u_bus_top/reg13_syn_216.mi[0]
+Endpoint: u_bus_top/reg15_syn_166
+3503 7.526000 1 1
+Timing path: reg27_syn_214.clk->u_bus_top/reg15_syn_166
+reg27_syn_214.clk
+u_bus_top/reg15_syn_166
+3505 7.526000 11.187000 3.661000 0 1
+lv_cnt_b[12] u_bus_top/reg15_syn_166.mi[1]
Hold check
-3681 3
-Endpoint: u_bus_top/reg5_syn_190
-3683 0.251000 1 1
-Timing path: u_bus_top/reg4_syn_178.clk->u_bus_top/reg5_syn_190
-u_bus_top/reg4_syn_178.clk
-u_bus_top/reg5_syn_190
-3685 0.251000 2.107000 2.358000 0 1
-u_bus_top/adc_cfg_data_o_sync2d_8m[2] u_bus_top/reg5_syn_190.mi[0]
+3541 3
+Endpoint: u_bus_top/reg9_syn_165
+3543 0.258000 1 1
+Timing path: reg25_syn_115.clk->u_bus_top/reg9_syn_165
+reg25_syn_115.clk
+u_bus_top/reg9_syn_165
+3545 0.258000 2.191000 2.449000 0 1
+lv_cnt2bus[6] u_bus_top/reg9_syn_165.mi[1]
-Endpoint: u_bus_top/reg0_syn_220
-3719 0.258000 1 1
-Timing path: reg1_syn_184.clk->u_bus_top/reg0_syn_220
-reg1_syn_184.clk
-u_bus_top/reg0_syn_220
-3721 0.258000 2.191000 2.449000 0 1
-S_hs_data_reg[19] u_bus_top/reg0_syn_220.mi[1]
+Endpoint: u_bus_top/reg9_syn_165
+3581 0.258000 1 1
+Timing path: reg25_syn_127.clk->u_bus_top/reg9_syn_165
+reg25_syn_127.clk
+u_bus_top/reg9_syn_165
+3583 0.258000 2.191000 2.449000 0 1
+lv_cnt2bus[8] u_bus_top/reg9_syn_165.mi[0]
-Endpoint: u_bus_top/reg0_syn_217
-3757 0.258000 1 1
-Timing path: reg1_syn_181.clk->u_bus_top/reg0_syn_217
-reg1_syn_181.clk
-u_bus_top/reg0_syn_217
-3759 0.258000 2.191000 2.449000 0 1
-S_hs_data_reg[25] u_bus_top/reg0_syn_217.mi[0]
+Endpoint: u_bus_top/reg9_syn_152
+3619 0.258000 1 1
+Timing path: reg25_syn_133.clk->u_bus_top/reg9_syn_152
+reg25_syn_133.clk
+u_bus_top/reg9_syn_152
+3621 0.258000 2.191000 2.449000 0 1
+lv_cnt2bus[3] u_bus_top/reg9_syn_152.mi[1]
Recovery check
-3795 3
-Endpoint: scan_start_diff/a_ex_frame_en_reg_syn_5
-3797 163.286000 1 1
-Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/a_ex_frame_en_reg_syn_5
+3657 3
+Endpoint: scan_start_diff/reg2_syn_21
+3659 161.807000 1 1
+Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg2_syn_21
clkubus_rstn_reg_syn_8.clk
-scan_start_diff/a_ex_frame_en_reg_syn_5
-3799 163.286000 168.576000 5.290000 1 2
-u_softrst_fan_ctrl/signal_from[0] u_bus_top/u_local_bus_slve_cis/reg59_syn_113.d[0]
-BUSY_MIPI_sync_d0_i_syn_8 scan_start_diff/a_ex_frame_en_reg_syn_5.sr
+scan_start_diff/reg2_syn_21
+3661 161.807000 168.504000 6.697000 1 2
+u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
+BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/reg2_syn_21.sr
+
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_data_tmp[53]_syn_20
+3697 161.807000 1 1
+Timing path: clkubus_rstn_reg_syn_8.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_data_tmp[53]_syn_20
+clkubus_rstn_reg_syn_8.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_data_tmp[53]_syn_20
+3699 161.807000 168.504000 6.697000 1 2
+u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
+BUSY_MIPI_sync_d0_i_syn_9 sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_data_tmp[53]_syn_20.sr
Endpoint: scan_start_diff/reg2_syn_19
-3835 163.371000 1 1
+3735 161.970000 1 1
Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg2_syn_19
clkubus_rstn_reg_syn_8.clk
scan_start_diff/reg2_syn_19
-3837 163.371000 168.576000 5.205000 1 2
+3737 161.970000 168.504000 6.534000 1 2
u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
-BUSY_MIPI_sync_d0_i_syn_6 scan_start_diff/reg2_syn_19.sr
-
-
-Endpoint: scan_start_diff/a_ex_frame_reg_syn_5
-3873 163.489000 1 1
-Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/a_ex_frame_reg_syn_5
-clkubus_rstn_reg_syn_8.clk
-scan_start_diff/a_ex_frame_reg_syn_5
-3875 163.489000 168.576000 5.087000 1 2
-u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
-BUSY_MIPI_sync_d0_i_syn_6 scan_start_diff/a_ex_frame_reg_syn_5.sr
+BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/reg2_syn_19.sr
Removal check
-3911 3
-Endpoint: scan_start_diff/reg1_syn_18
-3913 1.456000 1 1
-Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg1_syn_18
+3773 3
+Endpoint: scan_start_diff/a_ex_frame_reg_syn_5
+3775 2.526000 1 1
+Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/a_ex_frame_reg_syn_5
clkubus_rstn_reg_syn_8.clk
-scan_start_diff/reg1_syn_18
-3915 1.456000 2.236000 3.692000 1 2
+scan_start_diff/a_ex_frame_reg_syn_5
+3777 2.526000 2.299000 4.825000 1 2
u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
-BUSY_MIPI_sync_d0_i_syn_6 scan_start_diff/reg1_syn_18.sr
+BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/a_ex_frame_reg_syn_5.sr
-Endpoint: scan_start_diff/reg1_syn_21
-3951 1.562000 1 1
-Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg1_syn_21
+Endpoint: scan_start_diff/a_ex_frame_en_reg_syn_5
+3813 2.537000 1 1
+Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/a_ex_frame_en_reg_syn_5
clkubus_rstn_reg_syn_8.clk
-scan_start_diff/reg1_syn_21
-3953 1.562000 2.236000 3.798000 1 2
+scan_start_diff/a_ex_frame_en_reg_syn_5
+3815 2.537000 2.299000 4.836000 1 2
u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
-BUSY_MIPI_sync_d0_i_syn_6 scan_start_diff/reg1_syn_21.sr
+BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/a_ex_frame_en_reg_syn_5.sr
-Endpoint: scan_start_diff/enable_from_arm_rog_reg_syn_5
-3989 1.579000 1 1
-Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/enable_from_arm_rog_reg_syn_5
+Endpoint: scan_start_diff/reg2_syn_19
+3851 2.627000 1 1
+Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg2_syn_19
clkubus_rstn_reg_syn_8.clk
-scan_start_diff/enable_from_arm_rog_reg_syn_5
-3991 1.579000 2.236000 3.815000 1 2
+scan_start_diff/reg2_syn_19
+3853 2.627000 2.299000 4.926000 1 2
u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
-BUSY_MIPI_sync_d0_i_syn_6 scan_start_diff/enable_from_arm_rog_reg_syn_5.sr
+BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/reg2_syn_19.sr
clock: S_clk_x2
-4027 144 78 2
+3889 146 80 2
Setup check
-4037 3
-Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
-4037 2.450000 2 2
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add12_syn_69.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add12_syn_69.clk
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
-4039 2.450000 6.679000 4.229000 1 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[1] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.b[0]
+3899 3
+Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
+3899 2.068000 2 2
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add32_syn_70.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add32_syn_70.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
+3901 2.068000 6.679000 4.611000 1 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[0]
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add29_syn_70.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add29_syn_70.clk
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
-4075 2.457000 6.679000 4.222000 1 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[5] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.c[0]
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
+3937 2.526000 6.679000 4.153000 1 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[0]
-Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2
-4111 2.518000 2 2
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2
-4113 2.518000 6.679000 4.161000 1 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.b[1]
+Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
+3973 2.297000 2 2
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_39_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_39_syn_2.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
+3975 2.297000 6.679000 4.382000 1 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[1] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[1]
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2
-4149 2.611000 6.679000 4.068000 1 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[7] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.c[1]
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_43_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_43_syn_2.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
+4011 2.367000 6.679000 4.312000 1 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[5] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[1]
-Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2
-4185 2.518000 2 2
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_35_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_35_syn_2.clk
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2
-4187 2.518000 6.679000 4.161000 1 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.b[0]
+Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
+4047 2.443000 2 2
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
+4049 2.443000 6.679000 4.236000 1 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[2] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.b[0]
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_43_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_43_syn_2.clk
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2
-4223 2.761000 6.679000 3.918000 1 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.c[0]
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
+4085 2.532000 6.679000 4.147000 1 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[6] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.c[0]
Hold check
-4259 3
-Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5
-4261 0.158000 1 1
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6_syn_2.clk
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5
-4263 0.158000 2.291000 2.449000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5.mi[0]
+4121 3
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add7_syn_69
+4123 0.167000 1 1
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add7_syn_69
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6.clk
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add7_syn_69
+4125 0.167000 2.291000 2.458000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add7_syn_69.mi[0]
-Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5
-4299 0.274000 1 1
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.clk
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5
-4301 0.274000 2.291000 2.565000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.mi[1]
+Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_3d_reg_syn_5
+4161 0.281000 1 1
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d_reg_syn_6_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_3d_reg_syn_5
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d_reg_syn_6_syn_2.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_3d_reg_syn_5
+4163 0.281000 2.291000 2.572000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_3d_reg_syn_5.mi[0]
-Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5
-4337 0.274000 1 1
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.clk
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5
-4339 0.274000 2.291000 2.565000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_1d u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.mi[0]
+Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5
+4199 0.306000 1 1
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_reg_syn_10_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_reg_syn_10_syn_2.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5
+4201 0.306000 2.291000 2.597000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5.mi[0]
clock: S_clk_x4
-4375 32 8 2
+4237 32 8 2
Setup check
-4385 3
-Endpoint: O_data_hs_p[3]_syn_2
-4385 0.751000 4 3
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[3]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
-O_data_hs_p[3]_syn_2
-4387 0.751000 4.110000 3.359000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[3]_syn_2.do[2]
+4247 3
+Endpoint: O_data_hs_p[0]_syn_2
+4247 0.876000 4 3
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[0]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
+O_data_hs_p[0]_syn_2
+4249 0.876000 4.110000 3.234000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[0]_syn_2.do[3]
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[0]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
+O_data_hs_p[0]_syn_2
+4283 0.952000 4.110000 3.158000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[0]_syn_2.do[0]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[0]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
+O_data_hs_p[0]_syn_2
+4317 1.028000 4.110000 3.082000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[0]_syn_2.do[1]
+
+
+Endpoint: O_data_hs_p[1]_syn_2
+4351 0.925000 4 3
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[1]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
+O_data_hs_p[1]_syn_2
+4353 0.925000 4.110000 3.185000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[1]_syn_2.do[2]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[1]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
+O_data_hs_p[1]_syn_2
+4387 0.952000 4.110000 3.158000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[1]_syn_2.do[3]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[1]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
+O_data_hs_p[1]_syn_2
+4421 0.952000 4.110000 3.158000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[1]_syn_2.do[0]
+
+
+Endpoint: O_data_hs_p[3]_syn_2
+4455 0.928000 4 3
Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[3]_syn_2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
O_data_hs_p[3]_syn_2
-4421 0.751000 4.110000 3.359000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[3]_syn_2.do[1]
+4457 0.928000 4.110000 3.182000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[3]_syn_2.do[2]
Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[3]_syn_2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
O_data_hs_p[3]_syn_2
-4455 0.952000 4.110000 3.158000 0 1
+4491 0.952000 4.110000 3.158000 0 1
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[3]_syn_2.do[3]
-
-Endpoint: O_data_hs_p[0]_syn_2
-4489 1.028000 4 3
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[0]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
-O_data_hs_p[0]_syn_2
-4491 1.028000 4.110000 3.082000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[0]_syn_2.do[2]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[0]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
-O_data_hs_p[0]_syn_2
-4525 1.028000 4.110000 3.082000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[0]_syn_2.do[1]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[0]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
-O_data_hs_p[0]_syn_2
-4559 1.072000 4.110000 3.038000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[0]_syn_2.do[3]
-
-
-Endpoint: O_data_hs_p[1]_syn_2
-4593 1.072000 4 3
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[1]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
-O_data_hs_p[1]_syn_2
-4595 1.072000 4.110000 3.038000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[1]_syn_2.do[2]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[1]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
-O_data_hs_p[1]_syn_2
-4629 1.072000 4.110000 3.038000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[1]_syn_2.do[1]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[1]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
-O_data_hs_p[1]_syn_2
-4663 1.072000 4.110000 3.038000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[1]_syn_2.do[0]
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[3]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
+O_data_hs_p[3]_syn_2
+4525 0.952000 4.110000 3.158000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[3]_syn_2.do[1]
Hold check
-4697 3
-Endpoint: O_data_hs_p[2]_syn_2
-4699 0.507000 4 3
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[2]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
-O_data_hs_p[2]_syn_2
-4701 0.507000 1.962000 2.469000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[2]_syn_2.do[3]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[2]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
-O_data_hs_p[2]_syn_2
-4735 0.508000 1.962000 2.470000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[2]_syn_2.do[1]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[2]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
-O_data_hs_p[2]_syn_2
-4769 0.508000 1.962000 2.470000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[2]_syn_2.do[0]
-
-
+4559 3
Endpoint: O_data_hs_p[0]_syn_2
-4803 0.517000 4 3
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[0]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
+4561 0.401000 4 3
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[0]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
O_data_hs_p[0]_syn_2
-4805 0.517000 1.962000 2.479000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[0]_syn_2.do[3]
+4563 0.401000 1.962000 2.363000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[0]_syn_2.do[2]
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[0]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[0]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
O_data_hs_p[0]_syn_2
-4839 0.517000 1.962000 2.479000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[0]_syn_2.do[0]
+4597 0.546000 1.962000 2.508000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[0]_syn_2.do[1]
Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[0]_syn_2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
O_data_hs_p[0]_syn_2
-4873 0.546000 1.962000 2.508000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[0]_syn_2.do[2]
+4631 0.583000 1.962000 2.545000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[0]_syn_2.do[0]
Endpoint: O_data_hs_p[1]_syn_2
-4907 0.517000 4 3
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[1]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
+4665 0.401000 4 3
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[1]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
O_data_hs_p[1]_syn_2
-4909 0.517000 1.962000 2.479000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[1]_syn_2.do[2]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[1]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
-O_data_hs_p[1]_syn_2
-4943 0.517000 1.962000 2.479000 0 1
+4667 0.401000 1.962000 2.363000 0 1
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[1]_syn_2.do[1]
Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[1]_syn_2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
O_data_hs_p[1]_syn_2
-4977 0.517000 1.962000 2.479000 0 1
+4701 0.583000 1.962000 2.545000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[1]_syn_2.do[3]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[1]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
+O_data_hs_p[1]_syn_2
+4735 0.583000 1.962000 2.545000 0 1
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[1]_syn_2.do[0]
+Endpoint: O_data_hs_p[3]_syn_2
+4769 0.401000 4 3
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[3]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
+O_data_hs_p[3]_syn_2
+4771 0.401000 1.962000 2.363000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[3]_syn_2.do[0]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[3]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
+O_data_hs_p[3]_syn_2
+4805 0.583000 1.962000 2.545000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[3]_syn_2.do[3]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[3]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
+O_data_hs_p[3]_syn_2
+4839 0.583000 1.962000 2.545000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[3]_syn_2.do[1]
+
+
clock: S_clk_x4_90d
-5011 4 2 2
+4873 4 2 2
Setup check
-5021 1
+4883 1
Endpoint: O_clk_hs_p_syn_2
-5021 -0.661000 2 2
+4883 -0.811000 2 2
Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk->O_clk_hs_p_syn_2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk
O_clk_hs_p_syn_2
-5023 -0.661000 2.374000 3.035000 0 1
+4885 -0.811000 2.374000 3.185000 0 1
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[2]
Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk->O_clk_hs_p_syn_2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk
O_clk_hs_p_syn_2
-5057 -0.658000 2.374000 3.032000 0 1
+4919 -0.810000 2.374000 3.184000 0 1
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[0]
Hold check
-5091 1
+4953 1
Endpoint: O_clk_hs_p_syn_2
-5093 2.243000 2 2
+4955 2.359000 2 2
Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk->O_clk_hs_p_syn_2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk
O_clk_hs_p_syn_2
-5095 2.243000 0.226000 2.469000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[0]
+4957 2.359000 0.226000 2.585000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[2]
Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk->O_clk_hs_p_syn_2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk
O_clk_hs_p_syn_2
-5129 2.244000 0.226000 2.470000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[2]
+4991 2.359000 0.226000 2.585000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[0]
@@ -1380,15 +1322,15 @@ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_cl
Timing group statistics:
Clock constraints:
Clock Name Min Period Max Freq Skew Fanout TNS
- S_clk (108.0MHz) 9.150ns 109.290MHz 0.326ns 1795 0.000ns
- a_pclk (48.0MHz) 13.964ns 71.613MHz 0.326ns 1417 0.000ns
- b_pclk (48.0MHz) 10.242ns 97.637MHz 0.326ns 1355 0.000ns
- clk_adc (6.0MHz) 168.461ns 5.936MHz 0.326ns 967 -3.307ns
- b_sclk (168.0MHz) 1.853ns 539.665MHz 0.326ns 70 0.000ns
- a_sclk (168.0MHz) 2.239ns 446.628MHz 0.326ns 69 0.000ns
- S_clk_x2 (216.0MHz) 2.179ns 458.926MHz 0.480ns 20 0.000ns
- S_clk_x4 (432.0MHz) 1.563ns 639.795MHz 0.018ns 4 0.000ns
- S_clk_x4_90d (432.0MHz) 2.975ns 336.000MHz 0.000ns 1 -0.661ns
+ S_clk (108.0MHz) 9.050ns 110.497MHz 0.326ns 1810 0.000ns
+ a_pclk (48.0MHz) 12.299ns 81.307MHz 0.326ns 1425 0.000ns
+ b_pclk (48.0MHz) 10.093ns 99.079MHz 0.326ns 1358 0.000ns
+ clk_adc (6.0MHz) 168.609ns 5.931MHz 0.326ns 942 -3.279ns
+ a_sclk (168.0MHz) 2.172ns 460.405MHz 0.254ns 69 0.000ns
+ b_sclk (168.0MHz) 2.158ns 463.392MHz 0.326ns 69 0.000ns
+ S_clk_x2 (216.0MHz) 2.561ns 390.472MHz 0.480ns 22 0.000ns
+ S_clk_x4 (432.0MHz) 1.438ns 695.410MHz 0.018ns 4 0.000ns
+ S_clk_x4_90d (432.0MHz) 3.125ns 320.000MHz 0.000ns 1 -0.811ns
Minimum input arrival time before clock: no constraint path
Maximum output required time after clock: no constraint path
Maximum combinational path delay: no constraint path
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db
index 0b89331..15a41f1 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db and b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db
index 00432b3..ea2170c 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db and b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/run.log b/src/prj/td_project/hg_anlogic_Runs/phy_1/run.log
index eb5e064..e4626a9 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/run.log
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/run.log
@@ -4,7 +4,7 @@
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
Built at = 20:34:38 Mar 21 2023
Run by = holdtecs
- Run Date = Sun Feb 18 16:12:24 2024
+ Run Date = Mon Feb 19 10:57:51 2024
Run on = DESKTOP-5MQL5VE
============================================================
@@ -86,7 +86,7 @@ HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
-HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
@@ -163,27 +163,27 @@ HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
-HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
-HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
-HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
-HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
-HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
-HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
-HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
-HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
-HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
-HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
-HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
-HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
@@ -207,9 +207,9 @@ RUN-1001 : Import timing constraints
RUN-1001 : Import IO constraints
RUN-1001 : Import Inst constraints
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
-RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.252502s wall, 2.234375s user + 0.015625s system = 2.250000s CPU (99.9%)
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.171020s wall, 2.093750s user + 0.078125s system = 2.171875s CPU (100.0%)
-RUN-1004 : used memory is 337 MB, reserved memory is 315 MB, peak memory is 341 MB
+RUN-1004 : used memory is 336 MB, reserved memory is 314 MB, peak memory is 340 MB
RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
RUN-1002 : start command "get_ports clock_source"
RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
@@ -308,7 +308,7 @@ SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be m
SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
SYN-5055 Similar messages will be suppressed.
RUN-1002 : start command "phys_opt -simplify_lut"
-SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2945 clock/control pins, 1 other pins).
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
@@ -346,15 +346,15 @@ SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to
SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
PHY-1001 : Populate physical database on model huagao_mipi_top.
-RUN-1001 : There are total 17703 instances
-RUN-0007 : 7440 luts, 9040 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
-RUN-1001 : There are total 20281 nets
+RUN-1001 : There are total 17673 instances
+RUN-0007 : 7407 luts, 9043 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20251 nets
RUN-6004 WARNING: There are 20 nets with only 1 pin.
-RUN-1001 : 13180 nets have 2 pins
-RUN-1001 : 5799 nets have [3 - 5] pins
-RUN-1001 : 882 nets have [6 - 10] pins
-RUN-1001 : 171 nets have [11 - 20] pins
-RUN-1001 : 175 nets have [21 - 99] pins
+RUN-1001 : 13316 nets have 2 pins
+RUN-1001 : 5518 nets have [3 - 5] pins
+RUN-1001 : 1004 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 177 nets have [21 - 99] pins
RUN-1001 : 54 nets have 100+ pins
PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
RUN-1001 : Report Control nets information:
@@ -362,9 +362,9 @@ RUN-1001 : DFF Distribution
RUN-1001 : ----------------------------------
RUN-1001 : CE | SSR | ASR | DFF Count
RUN-1001 : ----------------------------------
-RUN-1001 : No | No | No | 789
+RUN-1001 : No | No | No | 793
RUN-1001 : No | No | Yes | 1968
-RUN-1001 : No | Yes | No | 3474
+RUN-1001 : No | Yes | No | 3473
RUN-1001 : Yes | No | No | 64
RUN-1001 : Yes | No | Yes | 72
RUN-1001 : Yes | Yes | No | 2673
@@ -373,24 +373,24 @@ RUN-0007 : Control Group Statistic
RUN-0007 : ---------------------------
RUN-0007 : #CLK | #CE | #SSR/ASR
RUN-0007 : ---------------------------
-RUN-0007 : 12 | 76 | 56
+RUN-0007 : 12 | 76 | 57
RUN-0007 : ---------------------------
-RUN-0007 : Control Set = 141
+RUN-0007 : Control Set = 142
PHY-3001 : Initial placement ...
-PHY-3001 : design contains 17701 instances, 7440 luts, 9040 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1179 with 5915 pins
+PHY-3001 : design contains 17671 instances, 7407 luts, 9043 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5897 pins
PHY-0007 : Cell area utilization is 48%
PHY-3001 : Start timing update ...
RUN-1002 : start command "start_timer -report"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84691, tnet num: 20103, tinst num: 17701, tnode num: 114767, tedge num: 135907.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in 1.209763s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (99.5%)
+RUN-1003 : finish command "start_timer -report" in 1.161753s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (100.9%)
-RUN-1004 : used memory is 529 MB, reserved memory is 514 MB, peak memory is 529 MB
+RUN-1004 : used memory is 528 MB, reserved memory is 512 MB, peak memory is 528 MB
TMR-2503 : Start to update net delay, extr mode = 2.
-TMR-2504 : Update delay of 20103 nets completely.
+TMR-2504 : Update delay of 20073 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 2.
TMR-3001 : Initiate 12 clocks from SDC.
TMR-3004 : Map sdc constraints, there are 6 constraints in total.
@@ -401,342 +401,387 @@ TMR-3003 : Constraints initiated successfully.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update; 2.034946s wall, 2.015625s user + 0.015625s system = 2.031250s CPU (99.8%)
+PHY-3001 : End timing update; 1.976174s wall, 1.968750s user + 0.015625s system = 1.984375s CPU (100.4%)
-PHY-3001 : Found 1228 cells with 2 region constraints.
+PHY-3001 : Found 1227 cells with 2 region constraints.
PHY-3001 : Global placement ...
-PHY-3001 : Initial: Len = 3.80961e+06
+PHY-3001 : Initial: Len = 4.09967e+06
PHY-3001 : Clustering ...
-PHY-3001 : Level 0 #clusters 17701.
-PHY-3001 : Level 1 #clusters 2034.
-PHY-3001 : End clustering; 0.139674s wall, 0.125000s user + 0.015625s system = 0.140625s CPU (100.7%)
+PHY-3001 : Level 0 #clusters 17671.
+PHY-3001 : Level 1 #clusters 2000.
+PHY-3001 : End clustering; 0.125609s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (136.8%)
PHY-3001 : Run with size of 4
PHY-3001 : Cell area utilization is 48%
PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
-PHY-3002 : Step(1): len = 1.28216e+06, overlap = 479.625
-PHY-3002 : Step(2): len = 1.16629e+06, overlap = 466.594
-PHY-3002 : Step(3): len = 879184, overlap = 563.188
-PHY-3002 : Step(4): len = 778763, overlap = 603.531
-PHY-3002 : Step(5): len = 610007, overlap = 698.5
-PHY-3002 : Step(6): len = 553353, overlap = 793.531
-PHY-3002 : Step(7): len = 483397, overlap = 865.125
-PHY-3002 : Step(8): len = 428045, overlap = 948.875
-PHY-3002 : Step(9): len = 387650, overlap = 1027.94
-PHY-3002 : Step(10): len = 347429, overlap = 1091.44
-PHY-3002 : Step(11): len = 320060, overlap = 1115.94
-PHY-3002 : Step(12): len = 291839, overlap = 1155.03
-PHY-3002 : Step(13): len = 261286, overlap = 1162.31
-PHY-3002 : Step(14): len = 241329, overlap = 1257.91
-PHY-3002 : Step(15): len = 218162, overlap = 1327.19
-PHY-3002 : Step(16): len = 201977, overlap = 1380.91
-PHY-3002 : Step(17): len = 188610, overlap = 1409.34
-PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.17875e-06
-PHY-3002 : Step(18): len = 192522, overlap = 1393.97
-PHY-3002 : Step(19): len = 219286, overlap = 1267.19
-PHY-3002 : Step(20): len = 216608, overlap = 1219.03
-PHY-3002 : Step(21): len = 221491, overlap = 1189.69
-PHY-3002 : Step(22): len = 217335, overlap = 1176.91
-PHY-3002 : Step(23): len = 213907, overlap = 1169
-PHY-3002 : Step(24): len = 207477, overlap = 1155.03
-PHY-3002 : Step(25): len = 204839, overlap = 1121.84
-PHY-3002 : Step(26): len = 201758, overlap = 1095.22
-PHY-3002 : Step(27): len = 199103, overlap = 1074.72
-PHY-3002 : Step(28): len = 195864, overlap = 1068.25
-PHY-3002 : Step(29): len = 194181, overlap = 1056.53
-PHY-3002 : Step(30): len = 190914, overlap = 1055.34
-PHY-3002 : Step(31): len = 190364, overlap = 1063.09
-PHY-3002 : Step(32): len = 189352, overlap = 1080.78
-PHY-3002 : Step(33): len = 188271, overlap = 1086.03
-PHY-3002 : Step(34): len = 187676, overlap = 1096.19
-PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.35749e-06
-PHY-3002 : Step(35): len = 191338, overlap = 1089.16
-PHY-3002 : Step(36): len = 206908, overlap = 1048.03
-PHY-3002 : Step(37): len = 212447, overlap = 1036.25
-PHY-3002 : Step(38): len = 216650, overlap = 1013.75
-PHY-3002 : Step(39): len = 217121, overlap = 1007.72
-PHY-3002 : Step(40): len = 218523, overlap = 984.438
-PHY-3002 : Step(41): len = 218264, overlap = 975.406
-PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.71498e-06
-PHY-3002 : Step(42): len = 226950, overlap = 968.812
-PHY-3002 : Step(43): len = 245710, overlap = 872.906
-PHY-3002 : Step(44): len = 257664, overlap = 797.438
-PHY-3002 : Step(45): len = 266586, overlap = 762.031
-PHY-3002 : Step(46): len = 271617, overlap = 731.906
-PHY-3002 : Step(47): len = 274607, overlap = 691.5
-PHY-3002 : Step(48): len = 276377, overlap = 653.438
-PHY-3002 : Step(49): len = 276817, overlap = 646.938
-PHY-3002 : Step(50): len = 276581, overlap = 660.125
-PHY-3002 : Step(51): len = 276637, overlap = 682.438
-PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.42996e-06
-PHY-3002 : Step(52): len = 292794, overlap = 631.031
-PHY-3002 : Step(53): len = 315192, overlap = 541.281
-PHY-3002 : Step(54): len = 325580, overlap = 488.906
-PHY-3002 : Step(55): len = 330349, overlap = 470.656
-PHY-3002 : Step(56): len = 330984, overlap = 479.5
-PHY-3002 : Step(57): len = 329740, overlap = 469.5
-PHY-3002 : Step(58): len = 328432, overlap = 476.188
-PHY-3002 : Step(59): len = 329101, overlap = 476
-PHY-3002 : Step(60): len = 327860, overlap = 473.656
-PHY-3002 : Step(61): len = 327626, overlap = 460.375
-PHY-3002 : Step(62): len = 326421, overlap = 465.219
-PHY-3002 : Step(63): len = 326449, overlap = 460.844
-PHY-3002 : Step(64): len = 325947, overlap = 463.781
-PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.88599e-05
-PHY-3002 : Step(65): len = 345594, overlap = 405.844
-PHY-3002 : Step(66): len = 358504, overlap = 380.375
-PHY-3002 : Step(67): len = 361349, overlap = 342.25
-PHY-3002 : Step(68): len = 363338, overlap = 326.031
-PHY-3002 : Step(69): len = 363377, overlap = 309.844
-PHY-3002 : Step(70): len = 364627, overlap = 326.219
-PHY-3002 : Step(71): len = 365087, overlap = 328.219
-PHY-3002 : Step(72): len = 365792, overlap = 333.594
-PHY-3002 : Step(73): len = 364897, overlap = 330.188
-PHY-3002 : Step(74): len = 365206, overlap = 329.875
-PHY-3002 : Step(75): len = 363871, overlap = 332.094
-PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.77199e-05
-PHY-3002 : Step(76): len = 383140, overlap = 311.875
-PHY-3002 : Step(77): len = 395177, overlap = 289.969
-PHY-3002 : Step(78): len = 395172, overlap = 281.938
-PHY-3002 : Step(79): len = 396342, overlap = 263.188
-PHY-3002 : Step(80): len = 399773, overlap = 272.594
-PHY-3002 : Step(81): len = 403999, overlap = 252.812
-PHY-3002 : Step(82): len = 402545, overlap = 237.156
-PHY-3002 : Step(83): len = 402877, overlap = 213.281
-PHY-3002 : Step(84): len = 404121, overlap = 220.188
-PHY-3002 : Step(85): len = 405404, overlap = 208.75
-PHY-3002 : Step(86): len = 404198, overlap = 210.375
-PHY-3002 : Step(87): len = 404719, overlap = 206.062
-PHY-3002 : Step(88): len = 405666, overlap = 203.531
-PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.54397e-05
-PHY-3002 : Step(89): len = 422768, overlap = 199
-PHY-3002 : Step(90): len = 433682, overlap = 201.625
-PHY-3002 : Step(91): len = 431641, overlap = 196.031
-PHY-3002 : Step(92): len = 430725, overlap = 188.062
-PHY-3002 : Step(93): len = 432978, overlap = 187.25
-PHY-3002 : Step(94): len = 435457, overlap = 191.875
-PHY-3002 : Step(95): len = 433279, overlap = 195.875
-PHY-3002 : Step(96): len = 435016, overlap = 188.656
-PHY-3002 : Step(97): len = 438049, overlap = 188.688
-PHY-3002 : Step(98): len = 438940, overlap = 184.656
-PHY-3002 : Step(99): len = 437194, overlap = 189.844
-PHY-3002 : Step(100): len = 437650, overlap = 189.219
-PHY-3002 : Step(101): len = 438669, overlap = 183.594
-PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000150879
-PHY-3002 : Step(102): len = 451568, overlap = 191.656
-PHY-3002 : Step(103): len = 458537, overlap = 182.375
-PHY-3002 : Step(104): len = 458416, overlap = 164.906
-PHY-3002 : Step(105): len = 459084, overlap = 159.875
-PHY-3002 : Step(106): len = 460562, overlap = 160.438
-PHY-3002 : Step(107): len = 461926, overlap = 168.562
-PHY-3002 : Step(108): len = 460202, overlap = 162.594
-PHY-3002 : Step(109): len = 461085, overlap = 163.625
-PHY-3002 : Step(110): len = 463855, overlap = 157.969
-PHY-3002 : Step(111): len = 466293, overlap = 153.281
-PHY-3002 : Step(112): len = 465161, overlap = 163.906
-PHY-3002 : Step(113): len = 465966, overlap = 159.062
-PHY-3002 : Step(114): len = 468286, overlap = 147.875
-PHY-3002 : Step(115): len = 469272, overlap = 143.812
-PHY-3002 : Step(116): len = 467852, overlap = 146.781
-PHY-3002 : Step(117): len = 468130, overlap = 146.781
-PHY-3002 : Step(118): len = 470349, overlap = 145.562
-PHY-3002 : Step(119): len = 471970, overlap = 149.188
-PHY-3002 : Step(120): len = 470240, overlap = 150.781
-PHY-3002 : Step(121): len = 470218, overlap = 152.906
-PHY-3002 : Step(122): len = 471502, overlap = 158.875
-PHY-3002 : Step(123): len = 472437, overlap = 157
-PHY-3002 : Step(124): len = 471668, overlap = 161.594
-PHY-3002 : Step(125): len = 471740, overlap = 160.219
-PHY-3002 : Step(126): len = 472430, overlap = 161.719
-PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000301759
-PHY-3002 : Step(127): len = 481561, overlap = 157.75
-PHY-3002 : Step(128): len = 491291, overlap = 148.5
-PHY-3002 : Step(129): len = 495046, overlap = 138.031
-PHY-3002 : Step(130): len = 496710, overlap = 134.188
-PHY-3002 : Step(131): len = 498607, overlap = 129.844
-PHY-3002 : Step(132): len = 499874, overlap = 130.438
-PHY-3002 : Step(133): len = 498023, overlap = 130.094
-PHY-3002 : Step(134): len = 497863, overlap = 133
-PHY-3002 : Step(135): len = 499555, overlap = 133
-PHY-3002 : Step(136): len = 500548, overlap = 124.969
-PHY-3002 : Step(137): len = 499129, overlap = 125.719
-PHY-3002 : Step(138): len = 498751, overlap = 127
-PHY-3002 : Step(139): len = 499579, overlap = 130.312
-PHY-3002 : Step(140): len = 500234, overlap = 129.875
-PHY-3002 : Step(141): len = 499512, overlap = 130.406
-PHY-3002 : Step(142): len = 499876, overlap = 132.219
-PHY-3002 : Step(143): len = 501054, overlap = 132.281
-PHY-3002 : Step(144): len = 501728, overlap = 135.094
-PHY-3002 : Step(145): len = 500931, overlap = 129.344
-PHY-3002 : Step(146): len = 500875, overlap = 130.469
-PHY-3002 : Step(147): len = 501276, overlap = 127.719
-PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000595753
-PHY-3002 : Step(148): len = 508170, overlap = 120.156
-PHY-3002 : Step(149): len = 513247, overlap = 115.562
-PHY-3002 : Step(150): len = 513677, overlap = 112.656
-PHY-3002 : Step(151): len = 514601, overlap = 115.906
-PHY-3002 : Step(152): len = 515876, overlap = 109.062
-PHY-3002 : Step(153): len = 517064, overlap = 110.969
-PHY-3002 : Step(154): len = 517158, overlap = 109.438
-PHY-3002 : Step(155): len = 517550, overlap = 115.094
-PHY-3002 : Step(156): len = 518867, overlap = 109.156
-PHY-3002 : Step(157): len = 519944, overlap = 101.531
-PHY-3002 : Step(158): len = 519809, overlap = 102.156
-PHY-3002 : Step(159): len = 519917, overlap = 104.344
-PHY-3002 : Step(160): len = 519662, overlap = 104.531
-PHY-3002 : Step(161): len = 519991, overlap = 106
-PHY-3002 : Step(162): len = 520598, overlap = 107.938
-PHY-3002 : Step(163): len = 521229, overlap = 101.469
-PHY-3002 : Step(164): len = 520862, overlap = 102.031
-PHY-3002 : Step(165): len = 520876, overlap = 102.094
-PHY-3002 : Step(166): len = 520991, overlap = 99.8438
-PHY-3002 : Step(167): len = 521046, overlap = 102.344
-PHY-3002 : Step(168): len = 520694, overlap = 104.531
-PHY-3002 : Step(169): len = 521123, overlap = 105.562
-PHY-3002 : Step(170): len = 521670, overlap = 103.312
-PHY-3002 : Step(171): len = 521936, overlap = 103.594
-PHY-3002 : Step(172): len = 521952, overlap = 101.719
-PHY-3002 : Step(173): len = 522327, overlap = 104.531
-PHY-3002 : Step(174): len = 522609, overlap = 104.156
-PHY-3002 : Step(175): len = 522585, overlap = 104.156
-PHY-3002 : Step(176): len = 521950, overlap = 103.969
-PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00101933
-PHY-3002 : Step(177): len = 524620, overlap = 106.344
-PHY-3002 : Step(178): len = 527198, overlap = 104.719
-PHY-3002 : Step(179): len = 528003, overlap = 102.719
-PHY-3002 : Step(180): len = 528529, overlap = 101.5
-PHY-3002 : Step(181): len = 529519, overlap = 101.969
-PHY-3002 : Step(182): len = 529809, overlap = 102
-PHY-3002 : Step(183): len = 529605, overlap = 102.531
+PHY-3002 : Step(1): len = 1.28668e+06, overlap = 484.094
+PHY-3002 : Step(2): len = 1.18318e+06, overlap = 557.375
+PHY-3002 : Step(3): len = 843931, overlap = 601.625
+PHY-3002 : Step(4): len = 791874, overlap = 624.344
+PHY-3002 : Step(5): len = 609615, overlap = 754.969
+PHY-3002 : Step(6): len = 529112, overlap = 805.719
+PHY-3002 : Step(7): len = 456874, overlap = 912.031
+PHY-3002 : Step(8): len = 425331, overlap = 995.844
+PHY-3002 : Step(9): len = 378282, overlap = 1057.66
+PHY-3002 : Step(10): len = 340965, overlap = 1115.97
+PHY-3002 : Step(11): len = 297218, overlap = 1185.28
+PHY-3002 : Step(12): len = 272422, overlap = 1214.28
+PHY-3002 : Step(13): len = 251103, overlap = 1252.66
+PHY-3002 : Step(14): len = 233830, overlap = 1297.31
+PHY-3002 : Step(15): len = 207240, overlap = 1327.09
+PHY-3002 : Step(16): len = 192315, overlap = 1358.84
+PHY-3002 : Step(17): len = 174239, overlap = 1404.44
+PHY-3002 : Step(18): len = 162009, overlap = 1423.03
+PHY-3002 : Step(19): len = 147685, overlap = 1465.97
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.2036e-06
+PHY-3002 : Step(20): len = 148424, overlap = 1423.66
+PHY-3002 : Step(21): len = 179191, overlap = 1304.53
+PHY-3002 : Step(22): len = 190294, overlap = 1232.22
+PHY-3002 : Step(23): len = 199319, overlap = 1189.78
+PHY-3002 : Step(24): len = 198566, overlap = 1179.34
+PHY-3002 : Step(25): len = 198247, overlap = 1163.12
+PHY-3002 : Step(26): len = 195020, overlap = 1157.25
+PHY-3002 : Step(27): len = 194648, overlap = 1158.09
+PHY-3002 : Step(28): len = 193918, overlap = 1142.66
+PHY-3002 : Step(29): len = 192851, overlap = 1149.03
+PHY-3002 : Step(30): len = 191764, overlap = 1148.06
+PHY-3002 : Step(31): len = 190566, overlap = 1168.28
+PHY-3002 : Step(32): len = 188829, overlap = 1145.56
+PHY-3002 : Step(33): len = 188125, overlap = 1149.47
+PHY-3002 : Step(34): len = 187128, overlap = 1136
+PHY-3002 : Step(35): len = 186806, overlap = 1099.56
+PHY-3002 : Step(36): len = 184419, overlap = 1073.5
+PHY-3002 : Step(37): len = 183688, overlap = 1074.06
+PHY-3002 : Step(38): len = 181963, overlap = 1075.84
+PHY-3002 : Step(39): len = 180821, overlap = 1100.16
+PHY-3002 : Step(40): len = 180049, overlap = 1107.62
+PHY-3002 : Step(41): len = 178563, overlap = 1115.78
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.40721e-06
+PHY-3002 : Step(42): len = 182212, overlap = 1088.72
+PHY-3002 : Step(43): len = 192003, overlap = 1041.94
+PHY-3002 : Step(44): len = 195313, overlap = 996.5
+PHY-3002 : Step(45): len = 200502, overlap = 971.938
+PHY-3002 : Step(46): len = 203704, overlap = 964.062
+PHY-3002 : Step(47): len = 207043, overlap = 946.125
+PHY-3002 : Step(48): len = 207363, overlap = 916.281
+PHY-3002 : Step(49): len = 207868, overlap = 907.031
+PHY-3002 : Step(50): len = 206820, overlap = 918.844
+PHY-3002 : Step(51): len = 206254, overlap = 931.125
+PHY-3002 : Step(52): len = 204603, overlap = 938.312
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.81441e-06
+PHY-3002 : Step(53): len = 211487, overlap = 931
+PHY-3002 : Step(54): len = 228174, overlap = 895.562
+PHY-3002 : Step(55): len = 237150, overlap = 803.812
+PHY-3002 : Step(56): len = 242854, overlap = 767.344
+PHY-3002 : Step(57): len = 244809, overlap = 750.625
+PHY-3002 : Step(58): len = 247200, overlap = 746.219
+PHY-3002 : Step(59): len = 246762, overlap = 749.906
+PHY-3002 : Step(60): len = 246476, overlap = 758.188
+PHY-3002 : Step(61): len = 245504, overlap = 776.312
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.62883e-06
+PHY-3002 : Step(62): len = 259270, overlap = 736.844
+PHY-3002 : Step(63): len = 280310, overlap = 622.125
+PHY-3002 : Step(64): len = 289452, overlap = 594.688
+PHY-3002 : Step(65): len = 292950, overlap = 596.625
+PHY-3002 : Step(66): len = 291834, overlap = 562.719
+PHY-3002 : Step(67): len = 289272, overlap = 547.375
+PHY-3002 : Step(68): len = 287091, overlap = 546.344
+PHY-3002 : Step(69): len = 287110, overlap = 528.281
+PHY-3002 : Step(70): len = 287591, overlap = 509.438
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.92577e-05
+PHY-3002 : Step(71): len = 306070, overlap = 487.531
+PHY-3002 : Step(72): len = 321535, overlap = 471.406
+PHY-3002 : Step(73): len = 327807, overlap = 437.219
+PHY-3002 : Step(74): len = 332649, overlap = 431.281
+PHY-3002 : Step(75): len = 331947, overlap = 424.094
+PHY-3002 : Step(76): len = 332519, overlap = 428.656
+PHY-3002 : Step(77): len = 332226, overlap = 415.594
+PHY-3002 : Step(78): len = 331189, overlap = 397.969
+PHY-3002 : Step(79): len = 330580, overlap = 386.438
+PHY-3002 : Step(80): len = 331430, overlap = 383.438
+PHY-3002 : Step(81): len = 332546, overlap = 365.906
+PHY-3002 : Step(82): len = 332833, overlap = 367.281
+PHY-3002 : Step(83): len = 331822, overlap = 367.219
+PHY-3002 : Step(84): len = 332233, overlap = 356.375
+PHY-3002 : Step(85): len = 331344, overlap = 344.094
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.85153e-05
+PHY-3002 : Step(86): len = 350518, overlap = 322.5
+PHY-3002 : Step(87): len = 360328, overlap = 306.594
+PHY-3002 : Step(88): len = 357880, overlap = 317.406
+PHY-3002 : Step(89): len = 358822, overlap = 305.344
+PHY-3002 : Step(90): len = 363911, overlap = 302.406
+PHY-3002 : Step(91): len = 367835, overlap = 304.938
+PHY-3002 : Step(92): len = 363522, overlap = 317.188
+PHY-3002 : Step(93): len = 365018, overlap = 310.875
+PHY-3002 : Step(94): len = 367761, overlap = 310.25
+PHY-3002 : Step(95): len = 369860, overlap = 319.094
+PHY-3002 : Step(96): len = 365177, overlap = 314.25
+PHY-3002 : Step(97): len = 363436, overlap = 316.188
+PHY-3002 : Step(98): len = 364963, overlap = 322.094
+PHY-3002 : Step(99): len = 366885, overlap = 314
+PHY-3002 : Step(100): len = 363632, overlap = 313.844
+PHY-3002 : Step(101): len = 363549, overlap = 310.25
+PHY-3002 : Step(102): len = 364192, overlap = 304.562
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.70306e-05
+PHY-3002 : Step(103): len = 382186, overlap = 300.719
+PHY-3002 : Step(104): len = 393320, overlap = 290.438
+PHY-3002 : Step(105): len = 390061, overlap = 265.469
+PHY-3002 : Step(106): len = 389428, overlap = 253.938
+PHY-3002 : Step(107): len = 394384, overlap = 237.344
+PHY-3002 : Step(108): len = 399627, overlap = 227.5
+PHY-3002 : Step(109): len = 397812, overlap = 236.219
+PHY-3002 : Step(110): len = 399415, overlap = 243.656
+PHY-3002 : Step(111): len = 402607, overlap = 242.125
+PHY-3002 : Step(112): len = 404322, overlap = 239.312
+PHY-3002 : Step(113): len = 400761, overlap = 240.844
+PHY-3002 : Step(114): len = 399368, overlap = 243.125
+PHY-3002 : Step(115): len = 401595, overlap = 233.938
+PHY-3002 : Step(116): len = 404676, overlap = 239.812
+PHY-3002 : Step(117): len = 400962, overlap = 247.219
+PHY-3002 : Step(118): len = 400739, overlap = 247.281
+PHY-3002 : Step(119): len = 402377, overlap = 239.938
+PHY-3002 : Step(120): len = 404242, overlap = 244.781
+PHY-3002 : Step(121): len = 401723, overlap = 248.594
+PHY-3002 : Step(122): len = 401871, overlap = 252.375
+PHY-3002 : Step(123): len = 404195, overlap = 251.375
+PHY-3002 : Step(124): len = 406140, overlap = 257.312
+PHY-3002 : Step(125): len = 403540, overlap = 259.656
+PHY-3002 : Step(126): len = 403245, overlap = 259.188
+PHY-3002 : Step(127): len = 403984, overlap = 258
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000154061
+PHY-3002 : Step(128): len = 419164, overlap = 244.906
+PHY-3002 : Step(129): len = 428463, overlap = 233.125
+PHY-3002 : Step(130): len = 426829, overlap = 217.812
+PHY-3002 : Step(131): len = 427102, overlap = 211.844
+PHY-3002 : Step(132): len = 429947, overlap = 210.938
+PHY-3002 : Step(133): len = 431921, overlap = 206.281
+PHY-3002 : Step(134): len = 429822, overlap = 204.156
+PHY-3002 : Step(135): len = 430225, overlap = 212.344
+PHY-3002 : Step(136): len = 432285, overlap = 210.5
+PHY-3002 : Step(137): len = 434226, overlap = 207.281
+PHY-3002 : Step(138): len = 433644, overlap = 199.531
+PHY-3002 : Step(139): len = 434785, overlap = 208.406
+PHY-3002 : Step(140): len = 436011, overlap = 203.75
+PHY-3002 : Step(141): len = 437222, overlap = 200.469
+PHY-3002 : Step(142): len = 436221, overlap = 201.188
+PHY-3002 : Step(143): len = 436724, overlap = 207.406
+PHY-3002 : Step(144): len = 437985, overlap = 207.875
+PHY-3002 : Step(145): len = 439045, overlap = 207.375
+PHY-3002 : Step(146): len = 437923, overlap = 207.281
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000297449
+PHY-3002 : Step(147): len = 447213, overlap = 201.406
+PHY-3002 : Step(148): len = 454452, overlap = 203.656
+PHY-3002 : Step(149): len = 454959, overlap = 198.281
+PHY-3002 : Step(150): len = 455780, overlap = 191
+PHY-3002 : Step(151): len = 458270, overlap = 186.562
+PHY-3002 : Step(152): len = 459849, overlap = 184
+PHY-3002 : Step(153): len = 458838, overlap = 186.688
+PHY-3002 : Step(154): len = 459485, overlap = 181.969
+PHY-3002 : Step(155): len = 461789, overlap = 184.562
+PHY-3002 : Step(156): len = 463496, overlap = 173.094
+PHY-3002 : Step(157): len = 462326, overlap = 171.438
+PHY-3002 : Step(158): len = 462656, overlap = 170.656
+PHY-3002 : Step(159): len = 464690, overlap = 167.469
+PHY-3002 : Step(160): len = 466201, overlap = 171.656
+PHY-3002 : Step(161): len = 465166, overlap = 165.188
+PHY-3002 : Step(162): len = 465218, overlap = 167.594
+PHY-3002 : Step(163): len = 466623, overlap = 165.719
+PHY-3002 : Step(164): len = 467287, overlap = 162.25
+PHY-3002 : Step(165): len = 466412, overlap = 161.688
+PHY-3002 : Step(166): len = 466327, overlap = 158.469
+PHY-3002 : Step(167): len = 467295, overlap = 161.75
+PHY-3002 : Step(168): len = 468354, overlap = 160.594
+PHY-3002 : Step(169): len = 468124, overlap = 155.656
+PHY-3002 : Step(170): len = 468614, overlap = 159.062
+PHY-3002 : Step(171): len = 469394, overlap = 153.281
+PHY-3002 : Step(172): len = 469789, overlap = 151.75
+PHY-3002 : Step(173): len = 470169, overlap = 135.656
+PHY-3002 : Step(174): len = 471663, overlap = 137.594
+PHY-3002 : Step(175): len = 472466, overlap = 133.844
+PHY-3002 : Step(176): len = 473025, overlap = 132.812
+PHY-3002 : Step(177): len = 472951, overlap = 135.25
+PHY-3002 : Step(178): len = 473084, overlap = 136.938
+PHY-3002 : Step(179): len = 473356, overlap = 135.25
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000566962
+PHY-3002 : Step(180): len = 479949, overlap = 132.312
+PHY-3002 : Step(181): len = 485650, overlap = 134
+PHY-3002 : Step(182): len = 486958, overlap = 125.781
+PHY-3002 : Step(183): len = 488201, overlap = 126
+PHY-3002 : Step(184): len = 490404, overlap = 126.844
+PHY-3002 : Step(185): len = 492125, overlap = 131.5
+PHY-3002 : Step(186): len = 492854, overlap = 128.094
+PHY-3002 : Step(187): len = 494116, overlap = 125.406
+PHY-3002 : Step(188): len = 496340, overlap = 126.312
+PHY-3002 : Step(189): len = 497988, overlap = 123.688
+PHY-3002 : Step(190): len = 498041, overlap = 122.812
+PHY-3002 : Step(191): len = 498102, overlap = 120.5
+PHY-3002 : Step(192): len = 498689, overlap = 124.594
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00109183
+PHY-3002 : Step(193): len = 502699, overlap = 120.406
+PHY-3002 : Step(194): len = 508726, overlap = 117.844
+PHY-3002 : Step(195): len = 511069, overlap = 114.281
+PHY-3002 : Step(196): len = 512644, overlap = 114.906
+PHY-3002 : Step(197): len = 513979, overlap = 114.875
+PHY-3002 : Step(198): len = 515197, overlap = 112.781
+PHY-3002 : Step(199): len = 515367, overlap = 112.906
+PHY-3002 : Step(200): len = 515820, overlap = 108.875
+PHY-3002 : Step(201): len = 516704, overlap = 111.188
+PHY-3002 : Step(202): len = 517142, overlap = 112.75
+PHY-3002 : Step(203): len = 517073, overlap = 107.688
+PHY-3002 : Step(204): len = 517115, overlap = 107.688
+PHY-3002 : Step(205): len = 517492, overlap = 112
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00191502
+PHY-3002 : Step(206): len = 520575, overlap = 107.125
+PHY-3002 : Step(207): len = 525493, overlap = 102.531
+PHY-3002 : Step(208): len = 526615, overlap = 100.969
+PHY-3002 : Step(209): len = 527208, overlap = 101.75
+PHY-3002 : Step(210): len = 528067, overlap = 102.562
+PHY-3002 : Step(211): len = 529197, overlap = 104.125
+PHY-3002 : Step(212): len = 530271, overlap = 102.125
+PHY-3002 : Step(213): len = 532302, overlap = 102.125
+PHY-3002 : Step(214): len = 533399, overlap = 103.219
+PHY-3002 : Step(215): len = 533896, overlap = 100.969
+PHY-3002 : Step(216): len = 534380, overlap = 98.9375
+PHY-3002 : Step(217): len = 534814, overlap = 96.5
+PHY-3002 : Step(218): len = 535308, overlap = 96.6875
PHY-3001 : Legalization ...
-PHY-3001 : End legalization; 0.019461s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (80.3%)
+PHY-3001 : End legalization; 0.014083s wall, 0.031250s user + 0.015625s system = 0.046875s CPU (332.8%)
PHY-3001 : Run with size of 4
-PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Cell area utilization is 55%
PHY-3001 : Analyzing congestion ...
RUN-1001 : Generating global routing grids ...
RUN-1001 : Building simple global routing graph ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 0/20281.
+PHY-1001 : Reuse net number 0/20251.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 683856, over cnt = 1540(4%), over = 6849, worst = 32
-PHY-1001 : End global iterations; 0.806200s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (133.7%)
+PHY-1002 : len = 705016, over cnt = 1536(4%), over = 7270, worst = 58
+PHY-1001 : End global iterations; 0.697043s wall, 1.015625s user + 0.046875s system = 1.062500s CPU (152.4%)
-PHY-1001 : Congestion index: top1 = 72.93, top5 = 56.93, top10 = 49.43, top15 = 44.73.
-PHY-3001 : End congestion estimation; 1.057142s wall, 1.312500s user + 0.015625s system = 1.328125s CPU (125.6%)
+PHY-1001 : Congestion index: top1 = 78.64, top5 = 60.55, top10 = 51.46, top15 = 45.82.
+PHY-3001 : End congestion estimation; 0.923953s wall, 1.265625s user + 0.046875s system = 1.312500s CPU (142.1%)
PHY-3001 : Update density targets...
PHY-3001 : Update congestion history...
PHY-3001 : Update timing in global mode ...
TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 20103 nets completely.
+TMR-2504 : Update delay of 20073 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 5.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update; 0.906378s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (100.0%)
+PHY-3001 : End timing update; 0.844461s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (99.9%)
-PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000117893
-PHY-3002 : Step(184): len = 619912, overlap = 37.3125
-PHY-3002 : Step(185): len = 625258, overlap = 40.3438
-PHY-3002 : Step(186): len = 619999, overlap = 41.1875
-PHY-3002 : Step(187): len = 618039, overlap = 46.5
-PHY-3002 : Step(188): len = 619855, overlap = 48.0625
-PHY-3002 : Step(189): len = 617680, overlap = 44.5625
-PHY-3002 : Step(190): len = 615660, overlap = 44.2812
-PHY-3002 : Step(191): len = 615121, overlap = 38.375
-PHY-3002 : Step(192): len = 613095, overlap = 32.5625
-PHY-3002 : Step(193): len = 612369, overlap = 32.7812
-PHY-3002 : Step(194): len = 609716, overlap = 31.7812
-PHY-3002 : Step(195): len = 608656, overlap = 30.7188
-PHY-3002 : Step(196): len = 606789, overlap = 31.4062
-PHY-3002 : Step(197): len = 606288, overlap = 31.5938
-PHY-3002 : Step(198): len = 604330, overlap = 28.7188
-PHY-3002 : Step(199): len = 603101, overlap = 25.875
-PHY-3002 : Step(200): len = 601975, overlap = 24.9062
-PHY-3002 : Step(201): len = 601508, overlap = 23.7188
-PHY-3002 : Step(202): len = 601148, overlap = 23.3125
-PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000235786
-PHY-3002 : Step(203): len = 602900, overlap = 22.1875
-PHY-3002 : Step(204): len = 605450, overlap = 21.625
-PHY-3002 : Step(205): len = 610775, overlap = 20.875
-PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000463887
-PHY-3002 : Step(206): len = 619828, overlap = 19.5625
-PHY-3002 : Step(207): len = 630216, overlap = 18.0312
-PHY-3002 : Step(208): len = 635697, overlap = 17.0938
-PHY-3002 : Step(209): len = 638971, overlap = 16.0625
-PHY-3002 : Step(210): len = 643006, overlap = 15.0312
-PHY-3002 : Step(211): len = 644334, overlap = 13.4062
-PHY-3002 : Step(212): len = 646449, overlap = 14
-PHY-3002 : Step(213): len = 648472, overlap = 12.4375
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000143207
+PHY-3002 : Step(219): len = 646213, overlap = 36.1875
+PHY-3002 : Step(220): len = 644319, overlap = 34.0938
+PHY-3002 : Step(221): len = 639708, overlap = 39.3438
+PHY-3002 : Step(222): len = 639697, overlap = 46.5312
+PHY-3002 : Step(223): len = 642009, overlap = 48.0312
+PHY-3002 : Step(224): len = 641422, overlap = 47.8125
+PHY-3002 : Step(225): len = 640251, overlap = 44.2188
+PHY-3002 : Step(226): len = 638069, overlap = 35.5625
+PHY-3002 : Step(227): len = 635262, overlap = 23.5
+PHY-3002 : Step(228): len = 631544, overlap = 27.6875
+PHY-3002 : Step(229): len = 628555, overlap = 28.2812
+PHY-3002 : Step(230): len = 626551, overlap = 29.0312
+PHY-3002 : Step(231): len = 624331, overlap = 32.0312
+PHY-3002 : Step(232): len = 622629, overlap = 37.5625
+PHY-3002 : Step(233): len = 620279, overlap = 34.2812
+PHY-3002 : Step(234): len = 620152, overlap = 34.7812
+PHY-3002 : Step(235): len = 617309, overlap = 36.5625
+PHY-3002 : Step(236): len = 615563, overlap = 38.2188
+PHY-3002 : Step(237): len = 614250, overlap = 37.7812
+PHY-3002 : Step(238): len = 613568, overlap = 37.75
+PHY-3002 : Step(239): len = 611804, overlap = 36.5
+PHY-3002 : Step(240): len = 610938, overlap = 38.875
+PHY-3002 : Step(241): len = 609379, overlap = 39.9062
+PHY-3002 : Step(242): len = 608310, overlap = 39.2812
+PHY-3002 : Step(243): len = 607656, overlap = 40.0312
+PHY-3002 : Step(244): len = 605710, overlap = 41.8438
+PHY-3002 : Step(245): len = 605011, overlap = 44.0625
+PHY-3002 : Step(246): len = 603058, overlap = 43.3438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000286414
+PHY-3002 : Step(247): len = 605841, overlap = 43.4688
+PHY-3002 : Step(248): len = 609140, overlap = 42.8438
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000469768
+PHY-3002 : Step(249): len = 613099, overlap = 42.2188
+PHY-3002 : Step(250): len = 620558, overlap = 41.125
+PHY-3002 : Step(251): len = 635556, overlap = 34.5938
+PHY-3002 : Step(252): len = 638311, overlap = 33.125
+PHY-3002 : Step(253): len = 640895, overlap = 31.9375
+PHY-3002 : Step(254): len = 642045, overlap = 32.5625
PHY-3001 : Run with size of 2
-PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Cell area utilization is 55%
PHY-3001 : Analyzing congestion ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 73/20281.
+PHY-1001 : Reuse net number 40/20251.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 735472, over cnt = 2714(7%), over = 12154, worst = 36
-PHY-1001 : End global iterations; 1.745193s wall, 2.343750s user + 0.031250s system = 2.375000s CPU (136.1%)
+PHY-1002 : len = 731656, over cnt = 2654(7%), over = 12250, worst = 64
+PHY-1001 : End global iterations; 1.758166s wall, 2.359375s user + 0.046875s system = 2.406250s CPU (136.9%)
-PHY-1001 : Congestion index: top1 = 80.47, top5 = 65.06, top10 = 57.39, top15 = 52.62.
-PHY-3001 : End congestion estimation; 2.034568s wall, 2.640625s user + 0.031250s system = 2.671875s CPU (131.3%)
+PHY-1001 : Congestion index: top1 = 85.02, top5 = 66.04, top10 = 57.79, top15 = 52.68.
+PHY-3001 : End congestion estimation; 2.028716s wall, 2.640625s user + 0.046875s system = 2.687500s CPU (132.5%)
PHY-3001 : Update density targets...
PHY-3001 : Update congestion history...
PHY-3001 : Update timing in global mode ...
TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 20103 nets completely.
+TMR-2504 : Update delay of 20073 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 5.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update; 0.926961s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (99.5%)
+PHY-3001 : End timing update; 1.066492s wall, 1.031250s user + 0.031250s system = 1.062500s CPU (99.6%)
-PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000126876
-PHY-3002 : Step(214): len = 641840, overlap = 242.125
-PHY-3002 : Step(215): len = 643778, overlap = 194.875
-PHY-3002 : Step(216): len = 636240, overlap = 186.906
-PHY-3002 : Step(217): len = 631784, overlap = 173.156
-PHY-3002 : Step(218): len = 627649, overlap = 166.156
-PHY-3002 : Step(219): len = 625175, overlap = 157.625
-PHY-3002 : Step(220): len = 620478, overlap = 156.344
-PHY-3002 : Step(221): len = 617497, overlap = 143.594
-PHY-3002 : Step(222): len = 614855, overlap = 138.469
-PHY-3002 : Step(223): len = 610915, overlap = 137.188
-PHY-3002 : Step(224): len = 608956, overlap = 135.125
-PHY-3002 : Step(225): len = 606719, overlap = 138.219
-PHY-3002 : Step(226): len = 603712, overlap = 136.312
-PHY-3002 : Step(227): len = 602610, overlap = 126.375
-PHY-3002 : Step(228): len = 599637, overlap = 126.562
-PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000253752
-PHY-3002 : Step(229): len = 601163, overlap = 119.375
-PHY-3002 : Step(230): len = 602373, overlap = 117.344
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00012412
+PHY-3002 : Step(255): len = 634493, overlap = 218.594
+PHY-3002 : Step(256): len = 633945, overlap = 186.656
+PHY-3002 : Step(257): len = 624281, overlap = 182.938
+PHY-3002 : Step(258): len = 620956, overlap = 176.469
+PHY-3002 : Step(259): len = 616979, overlap = 157.156
+PHY-3002 : Step(260): len = 613520, overlap = 135.344
+PHY-3002 : Step(261): len = 609779, overlap = 127.906
+PHY-3002 : Step(262): len = 608368, overlap = 127.469
+PHY-3002 : Step(263): len = 603987, overlap = 124.812
+PHY-3002 : Step(264): len = 601816, overlap = 126.906
+PHY-3002 : Step(265): len = 599563, overlap = 125.969
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00024824
+PHY-3002 : Step(266): len = 599695, overlap = 121.312
+PHY-3002 : Step(267): len = 601392, overlap = 118.5
+PHY-3002 : Step(268): len = 603887, overlap = 117.031
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000496481
+PHY-3002 : Step(269): len = 610653, overlap = 103.031
+PHY-3002 : Step(270): len = 617658, overlap = 96.375
+PHY-3002 : Step(271): len = 621957, overlap = 93.625
+PHY-3002 : Step(272): len = 624159, overlap = 89.5625
+PHY-3002 : Step(273): len = 623537, overlap = 89.2188
OPT-1001 : Start physical optimization ...
RUN-1002 : start command "start_timer -report"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84691, tnet num: 20103, tinst num: 17701, tnode num: 114767, tedge num: 135907.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in 1.566564s wall, 1.484375s user + 0.078125s system = 1.562500s CPU (99.7%)
+RUN-1003 : finish command "start_timer -report" in 1.458795s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (100.7%)
-RUN-1004 : used memory is 574 MB, reserved memory is 563 MB, peak memory is 709 MB
-OPT-1001 : Total overflow 449.03 peak overflow 8.34
+RUN-1004 : used memory is 572 MB, reserved memory is 561 MB, peak memory is 708 MB
+OPT-1001 : Total overflow 402.84 peak overflow 2.69
OPT-1001 : Start high-fanout net optimization ...
OPT-1001 : Update timing in global mode
PHY-1001 : Start incremental global routing, caller is place ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 857/20281.
+PHY-1001 : Reuse net number 966/20251.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 699552, over cnt = 2835(8%), over = 10043, worst = 25
-PHY-1001 : End global iterations; 1.393356s wall, 1.921875s user + 0.031250s system = 1.953125s CPU (140.2%)
+PHY-1002 : len = 725272, over cnt = 2983(8%), over = 10954, worst = 26
+PHY-1001 : End global iterations; 1.163434s wall, 1.734375s user + 0.015625s system = 1.750000s CPU (150.4%)
-PHY-1001 : Congestion index: top1 = 66.31, top5 = 55.55, top10 = 50.15, top15 = 46.60.
-PHY-1001 : End incremental global routing; 1.754026s wall, 2.281250s user + 0.031250s system = 2.312500s CPU (131.8%)
+PHY-1001 : Congestion index: top1 = 65.78, top5 = 55.57, top10 = 50.32, top15 = 46.98.
+PHY-1001 : End incremental global routing; 1.485633s wall, 2.062500s user + 0.015625s system = 2.078125s CPU (139.9%)
TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 20103 nets completely.
+TMR-2504 : Update delay of 20073 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 5.
TMR-3001 : Initiate 12 clocks from SDC.
TMR-3004 : Map sdc constraints, there are 6 constraints in total.
@@ -747,46 +792,46 @@ TMR-3003 : Constraints initiated successfully.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update; 1.143365s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (98.4%)
+OPT-1001 : End timing update; 0.906483s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (100.0%)
-OPT-1001 : 49 high-fanout net processed.
+OPT-1001 : 51 high-fanout net processed.
PHY-3001 : Start incremental placement ...
PHY-1001 : Populate physical database on model huagao_mipi_top.
PHY-3001 : Initial placement ...
PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
-PHY-3001 : eco cells: 17567 has valid locations, 322 needs to be replaced
-PHY-3001 : design contains 17974 instances, 7534 luts, 9219 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1179 with 6039 pins
-PHY-3001 : Found 1242 cells with 2 region constraints.
+PHY-3001 : eco cells: 17535 has valid locations, 332 needs to be replaced
+PHY-3001 : design contains 17952 instances, 7503 luts, 9228 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6004 pins
+PHY-3001 : Found 1238 cells with 2 region constraints.
PHY-3001 : Global placement ...
-PHY-3001 : Initial: Len = 625679
+PHY-3001 : Initial: Len = 648311
PHY-3001 : Run with size of 4
PHY-3001 : Cell area utilization is 56%
PHY-3001 : Analyzing congestion ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 16052/20554.
+PHY-1001 : Reuse net number 16555/20532.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 714888, over cnt = 2876(8%), over = 10033, worst = 26
-PHY-1001 : End global iterations; 0.257696s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (121.3%)
+PHY-1002 : len = 741400, over cnt = 3040(8%), over = 11005, worst = 23
+PHY-1001 : End global iterations; 0.250345s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (156.0%)
-PHY-1001 : Congestion index: top1 = 66.66, top5 = 55.46, top10 = 50.11, top15 = 46.70.
-PHY-3001 : End congestion estimation; 0.515356s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (112.2%)
+PHY-1001 : Congestion index: top1 = 66.03, top5 = 56.05, top10 = 50.69, top15 = 47.27.
+PHY-3001 : End congestion estimation; 0.525617s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (124.9%)
PHY-3001 : Update density targets...
PHY-3001 : Update congestion history...
PHY-3001 : Update timing in global mode ...
RUN-1002 : start command "start_timer -report"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85780, tnet num: 20376, tinst num: 17974, tnode num: 116409, tedge num: 137539.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85749, tnet num: 20354, tinst num: 17952, tnode num: 116398, tedge num: 137520.
TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in 1.515021s wall, 1.468750s user + 0.046875s system = 1.515625s CPU (100.0%)
+RUN-1003 : finish command "start_timer -report" in 1.456048s wall, 1.421875s user + 0.031250s system = 1.453125s CPU (99.8%)
-RUN-1004 : used memory is 618 MB, reserved memory is 621 MB, peak memory is 713 MB
+RUN-1004 : used memory is 616 MB, reserved memory is 619 MB, peak memory is 710 MB
TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 20376 nets completely.
+TMR-2504 : Update delay of 20354 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 5.
TMR-3001 : Initiate 12 clocks from SDC.
TMR-3004 : Map sdc constraints, there are 6 constraints in total.
@@ -797,145 +842,141 @@ TMR-3003 : Constraints initiated successfully.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update; 2.511787s wall, 2.468750s user + 0.046875s system = 2.515625s CPU (100.2%)
+PHY-3001 : End timing update; 2.402078s wall, 2.343750s user + 0.062500s system = 2.406250s CPU (100.2%)
PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
-PHY-3002 : Step(231): len = 624841, overlap = 1.84375
-PHY-3002 : Step(232): len = 624485, overlap = 1.875
-PHY-3002 : Step(233): len = 624208, overlap = 1.9375
+PHY-3002 : Step(274): len = 647207, overlap = 0.4375
+PHY-3002 : Step(275): len = 646813, overlap = 0.4375
+PHY-3002 : Step(276): len = 646562, overlap = 0.4375
+PHY-3002 : Step(277): len = 646329, overlap = 0.4375
PHY-3001 : Run with size of 2
PHY-3001 : Cell area utilization is 56%
PHY-3001 : Analyzing congestion ...
PHY-1001 : Generate routing nets ...
PHY-1001 : Incremental mode ON
-PHY-1001 : Reuse net number 16167/20554.
+PHY-1001 : Reuse net number 16669/20532.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 712584, over cnt = 2884(8%), over = 10123, worst = 26
-PHY-1001 : End global iterations; 0.214491s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (109.3%)
+PHY-1002 : len = 738224, over cnt = 3040(8%), over = 11020, worst = 23
+PHY-1001 : End global iterations; 0.232955s wall, 0.296875s user + 0.015625s system = 0.312500s CPU (134.1%)
-PHY-1001 : Congestion index: top1 = 67.16, top5 = 55.92, top10 = 50.46, top15 = 46.96.
-PHY-3001 : End congestion estimation; 0.497612s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (103.6%)
+PHY-1001 : Congestion index: top1 = 66.44, top5 = 56.30, top10 = 50.96, top15 = 47.56.
+PHY-3001 : End congestion estimation; 0.494469s wall, 0.546875s user + 0.015625s system = 0.562500s CPU (113.8%)
PHY-3001 : Update density targets...
PHY-3001 : Update congestion history...
PHY-3001 : Update timing in global mode ...
TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 20376 nets completely.
+TMR-2504 : Update delay of 20354 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 5.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update; 0.982352s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (100.2%)
+PHY-3001 : End timing update; 1.000311s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (100.0%)
-PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000234242
-PHY-3002 : Step(234): len = 624067, overlap = 118.844
-PHY-3002 : Step(235): len = 624142, overlap = 118.875
-PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000468484
-PHY-3002 : Step(236): len = 624150, overlap = 119.438
-PHY-3002 : Step(237): len = 624515, overlap = 119.781
-PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000936969
-PHY-3002 : Step(238): len = 624747, overlap = 119.469
-PHY-3002 : Step(239): len = 625394, overlap = 119.125
-PHY-3001 : Final: Len = 625394, Over = 119.125
-PHY-3001 : End incremental placement; 5.297590s wall, 5.406250s user + 0.156250s system = 5.562500s CPU (105.0%)
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000327438
+PHY-3002 : Step(278): len = 646336, overlap = 91.7812
+PHY-3002 : Step(279): len = 646431, overlap = 91.4062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000654876
+PHY-3002 : Step(280): len = 646360, overlap = 90.7812
+PHY-3002 : Step(281): len = 646751, overlap = 91.4375
+PHY-3001 : Final: Len = 646751, Over = 91.4375
+PHY-3001 : End incremental placement; 5.153788s wall, 5.734375s user + 0.234375s system = 5.968750s CPU (115.8%)
-OPT-1001 : Total overflow 455.03 peak overflow 8.34
-OPT-1001 : End high-fanout net optimization; 8.784785s wall, 9.484375s user + 0.187500s system = 9.671875s CPU (110.1%)
+OPT-1001 : Total overflow 409.66 peak overflow 2.69
+OPT-1001 : End high-fanout net optimization; 8.186217s wall, 9.406250s user + 0.265625s system = 9.671875s CPU (118.1%)
-OPT-1001 : Current memory(MB): used = 715, reserve = 710, peak = 733.
+OPT-1001 : Current memory(MB): used = 715, reserve = 709, peak = 732.
OPT-1001 : Start global optimization ...
OPT-1001 : Start congestion update ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 16083/20554.
+PHY-1001 : Reuse net number 16602/20532.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 715384, over cnt = 2806(7%), over = 9025, worst = 25
-PHY-1002 : len = 749816, over cnt = 2175(6%), over = 5692, worst = 18
-PHY-1002 : len = 797800, over cnt = 922(2%), over = 2171, worst = 15
-PHY-1002 : len = 829904, over cnt = 103(0%), over = 176, worst = 10
-PHY-1002 : len = 833304, over cnt = 8(0%), over = 8, worst = 1
-PHY-1001 : End global iterations; 1.858928s wall, 2.453125s user + 0.093750s system = 2.546875s CPU (137.0%)
+PHY-1002 : len = 740224, over cnt = 2991(8%), over = 9937, worst = 20
+PHY-1002 : len = 794184, over cnt = 2008(5%), over = 4860, worst = 18
+PHY-1002 : len = 828048, over cnt = 869(2%), over = 1996, worst = 17
+PHY-1002 : len = 852104, over cnt = 293(0%), over = 560, worst = 11
+PHY-1002 : len = 861664, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.010204s wall, 2.765625s user + 0.015625s system = 2.781250s CPU (138.4%)
-PHY-1001 : Congestion index: top1 = 56.66, top5 = 49.86, top10 = 46.49, top15 = 44.26.
-OPT-1001 : End congestion update; 2.143489s wall, 2.734375s user + 0.093750s system = 2.828125s CPU (131.9%)
+PHY-1001 : Congestion index: top1 = 55.04, top5 = 49.28, top10 = 45.86, top15 = 43.68.
+OPT-1001 : End congestion update; 2.319261s wall, 3.093750s user + 0.015625s system = 3.109375s CPU (134.1%)
OPT-1001 : Update timing in Manhattan mode
TMR-2503 : Start to update net delay, extr mode = 3.
-TMR-2504 : Update delay of 20376 nets completely.
+TMR-2504 : Update delay of 20354 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 3.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update; 0.845385s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (99.8%)
+OPT-1001 : End timing update; 0.814386s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.8%)
-OPT-0007 : Start: WNS -1068 TNS -1528 NUM_FEPS 2
-OPT-0007 : Iter 1: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 69 cells processed and 4172 slack improved
-OPT-0007 : Iter 2: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 37 cells processed and 2642 slack improved
-OPT-0007 : Iter 3: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 18 cells processed and 1540 slack improved
-OPT-0007 : Iter 4: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 8 cells processed and 700 slack improved
-OPT-1001 : End global optimization; 3.028918s wall, 3.609375s user + 0.109375s system = 3.718750s CPU (122.8%)
+OPT-0007 : Start: WNS -1018 TNS -1565 NUM_FEPS 3
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1565 NUM_FEPS 3 with 96 cells processed and 6778 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1565 NUM_FEPS 3 with 7 cells processed and 350 slack improved
+OPT-1001 : End global optimization; 3.178466s wall, 3.953125s user + 0.015625s system = 3.968750s CPU (124.9%)
-OPT-1001 : Current memory(MB): used = 693, reserve = 692, peak = 733.
-OPT-1001 : End physical optimization; 14.149479s wall, 15.406250s user + 0.406250s system = 15.812500s CPU (111.8%)
+OPT-1001 : Current memory(MB): used = 695, reserve = 693, peak = 732.
+OPT-1001 : End physical optimization; 13.329156s wall, 15.296875s user + 0.296875s system = 15.593750s CPU (117.0%)
PHY-3001 : Start packing ...
SYN-4007 : Packing 0 MUX to BLE ...
SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
-SYN-4007 : Packing 7534 LUT to BLE ...
-SYN-4008 : Packed 7534 LUT and 3081 SEQ to BLE.
-SYN-4003 : Packing 6138 remaining SEQ's ...
-SYN-4005 : Packed 3728 SEQ with LUT/SLICE
-SYN-4006 : 1033 single LUT's are left
-SYN-4006 : 2410 single SEQ's are left
-SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9944/13675 primitive instances ...
-PHY-3001 : End packing; 1.768773s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (99.8%)
+SYN-4007 : Packing 7503 LUT to BLE ...
+SYN-4008 : Packed 7503 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6095 remaining SEQ's ...
+SYN-4005 : Packed 3693 SEQ with LUT/SLICE
+SYN-4006 : 969 single LUT's are left
+SYN-4006 : 2402 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9905/13636 primitive instances ...
+PHY-3001 : End packing; 1.652991s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (100.2%)
PHY-1001 : Populate physical database on model huagao_mipi_top.
-RUN-1001 : There are total 6908 instances
-RUN-1001 : 3380 mslices, 3380 lslices, 75 pads, 58 brams, 3 dsps
-RUN-1001 : There are total 17605 nets
+RUN-1001 : There are total 6890 instances
+RUN-1001 : 3371 mslices, 3371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17530 nets
RUN-6004 WARNING: There are 20 nets with only 1 pin.
-RUN-1001 : 9882 nets have 2 pins
-RUN-1001 : 6039 nets have [3 - 5] pins
-RUN-1001 : 996 nets have [6 - 10] pins
-RUN-1001 : 319 nets have [11 - 20] pins
-RUN-1001 : 336 nets have [21 - 99] pins
-RUN-1001 : 13 nets have 100+ pins
-PHY-3001 : design contains 6906 instances, 6760 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1179 with 3598 pins
-PHY-3001 : Found 489 cells with 2 region constraints.
+RUN-1001 : 9969 nets have 2 pins
+RUN-1001 : 5758 nets have [3 - 5] pins
+RUN-1001 : 1123 nets have [6 - 10] pins
+RUN-1001 : 308 nets have [11 - 20] pins
+RUN-1001 : 340 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6888 instances, 6742 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3560 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
PHY-3001 : Cell area utilization is 74%
-PHY-3001 : After packing: Len = 639903, Over = 311.75
+PHY-3001 : After packing: Len = 657912, Over = 251
PHY-3001 : Run with size of 2
PHY-3001 : Cell area utilization is 74%
PHY-3001 : Analyzing congestion ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 7236/17605.
+PHY-1001 : Reuse net number 7593/17530.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 789120, over cnt = 1925(5%), over = 3253, worst = 8
-PHY-1002 : len = 798072, over cnt = 1216(3%), over = 1800, worst = 7
-PHY-1002 : len = 811296, over cnt = 503(1%), over = 716, worst = 6
-PHY-1002 : len = 820752, over cnt = 125(0%), over = 177, worst = 6
-PHY-1002 : len = 824224, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations; 1.739831s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (143.7%)
+PHY-1002 : len = 813888, over cnt = 1952(5%), over = 3148, worst = 7
+PHY-1002 : len = 821784, over cnt = 1230(3%), over = 1767, worst = 6
+PHY-1002 : len = 830520, over cnt = 722(2%), over = 1019, worst = 6
+PHY-1002 : len = 837008, over cnt = 475(1%), over = 681, worst = 6
+PHY-1002 : len = 845584, over cnt = 109(0%), over = 150, worst = 6
+PHY-1001 : End global iterations; 1.493644s wall, 2.187500s user + 0.000000s system = 2.187500s CPU (146.5%)
-PHY-1001 : Congestion index: top1 = 57.07, top5 = 50.13, top10 = 46.41, top15 = 44.00.
-PHY-3001 : End congestion estimation; 2.153004s wall, 2.921875s user + 0.000000s system = 2.921875s CPU (135.7%)
+PHY-1001 : Congestion index: top1 = 57.65, top5 = 50.04, top10 = 45.96, top15 = 43.38.
+PHY-3001 : End congestion estimation; 1.895549s wall, 2.578125s user + 0.000000s system = 2.578125s CPU (136.0%)
PHY-3001 : Update density targets...
PHY-3001 : Update congestion history...
PHY-3001 : Update timing in global mode ...
RUN-1002 : start command "start_timer -report"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74010, tnet num: 17427, tinst num: 6906, tnode num: 96499, tedge num: 124264.
-TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73751, tnet num: 17352, tinst num: 6888, tnode num: 96233, tedge num: 123821.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in 1.721909s wall, 1.703125s user + 0.015625s system = 1.718750s CPU (99.8%)
+RUN-1003 : finish command "start_timer -report" in 1.663680s wall, 1.656250s user + 0.015625s system = 1.671875s CPU (100.5%)
-RUN-1004 : used memory is 611 MB, reserved memory is 612 MB, peak memory is 733 MB
+RUN-1004 : used memory is 608 MB, reserved memory is 603 MB, peak memory is 732 MB
TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 17427 nets completely.
+TMR-2504 : Update delay of 17352 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 5.
TMR-3001 : Initiate 12 clocks from SDC.
TMR-3004 : Map sdc constraints, there are 6 constraints in total.
@@ -945,116 +986,114 @@ TMR-3003 : Constraints initiated successfully.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update; 2.682779s wall, 2.656250s user + 0.015625s system = 2.671875s CPU (99.6%)
+PHY-3001 : End timing update; 2.524608s wall, 2.500000s user + 0.031250s system = 2.531250s CPU (100.3%)
-PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.06879e-05
-PHY-3002 : Step(240): len = 631140, overlap = 311.75
-PHY-3002 : Step(241): len = 627745, overlap = 297.5
-PHY-3002 : Step(242): len = 626822, overlap = 291.5
-PHY-3002 : Step(243): len = 626753, overlap = 288.75
-PHY-3002 : Step(244): len = 626765, overlap = 289
-PHY-3002 : Step(245): len = 625140, overlap = 294.75
-PHY-3002 : Step(246): len = 623501, overlap = 289.75
-PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.13758e-05
-PHY-3002 : Step(247): len = 625054, overlap = 285.75
-PHY-3002 : Step(248): len = 628153, overlap = 280.5
-PHY-3002 : Step(249): len = 629867, overlap = 274.25
-PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000162752
-PHY-3002 : Step(250): len = 636527, overlap = 270.25
-PHY-3002 : Step(251): len = 646126, overlap = 260.75
-PHY-3002 : Step(252): len = 647192, overlap = 257
-PHY-3002 : Step(253): len = 648901, overlap = 249.75
-PHY-3002 : Step(254): len = 650656, overlap = 243.75
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.75783e-05
+PHY-3002 : Step(282): len = 645888, overlap = 249.75
+PHY-3002 : Step(283): len = 639979, overlap = 245.5
+PHY-3002 : Step(284): len = 636462, overlap = 252.5
+PHY-3002 : Step(285): len = 633658, overlap = 252.5
+PHY-3002 : Step(286): len = 630887, overlap = 260.75
+PHY-3002 : Step(287): len = 627447, overlap = 264
+PHY-3002 : Step(288): len = 624149, overlap = 268
+PHY-3002 : Step(289): len = 621609, overlap = 270.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.51567e-05
+PHY-3002 : Step(290): len = 624770, overlap = 262
+PHY-3002 : Step(291): len = 629314, overlap = 250.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000190313
+PHY-3002 : Step(292): len = 633723, overlap = 244
+PHY-3002 : Step(293): len = 645927, overlap = 215.75
+PHY-3002 : Step(294): len = 648474, overlap = 213.5
+PHY-3002 : Step(295): len = 649771, overlap = 210.25
PHY-3001 : Legalization ...
-PHY-3001 : End legalization; 0.373026s wall, 0.328125s user + 0.546875s system = 0.875000s CPU (234.6%)
+PHY-3001 : End legalization; 0.398554s wall, 0.328125s user + 0.453125s system = 0.781250s CPU (196.0%)
-PHY-3001 : Trial Legalized: Len = 743394
+PHY-3001 : Trial Legalized: Len = 725964
PHY-3001 : Run with size of 2
-PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Cell area utilization is 73%
PHY-3001 : Analyzing congestion ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 860/17605.
+PHY-1001 : Reuse net number 759/17530.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 863992, over cnt = 2790(7%), over = 4770, worst = 9
-PHY-1002 : len = 879488, over cnt = 1790(5%), over = 2791, worst = 9
-PHY-1002 : len = 898056, over cnt = 932(2%), over = 1462, worst = 9
-PHY-1002 : len = 915752, over cnt = 266(0%), over = 437, worst = 5
-PHY-1002 : len = 922712, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations; 2.471592s wall, 3.671875s user + 0.015625s system = 3.687500s CPU (149.2%)
+PHY-1002 : len = 840944, over cnt = 2673(7%), over = 4537, worst = 8
+PHY-1002 : len = 859824, over cnt = 1524(4%), over = 2187, worst = 7
+PHY-1002 : len = 878400, over cnt = 481(1%), over = 720, worst = 7
+PHY-1002 : len = 886200, over cnt = 114(0%), over = 174, worst = 7
+PHY-1002 : len = 888632, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.310098s wall, 3.468750s user + 0.031250s system = 3.500000s CPU (151.5%)
-PHY-1001 : Congestion index: top1 = 55.62, top5 = 50.45, top10 = 47.79, top15 = 45.92.
-PHY-3001 : End congestion estimation; 2.962224s wall, 4.171875s user + 0.015625s system = 4.187500s CPU (141.4%)
+PHY-1001 : Congestion index: top1 = 53.23, top5 = 48.36, top10 = 45.74, top15 = 43.97.
+PHY-3001 : End congestion estimation; 2.768120s wall, 3.921875s user + 0.031250s system = 3.953125s CPU (142.8%)
PHY-3001 : Update density targets...
PHY-3001 : Update congestion history...
PHY-3001 : Update timing in global mode ...
TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 17427 nets completely.
+TMR-2504 : Update delay of 17352 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 5.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update; 0.933765s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (100.4%)
+PHY-3001 : End timing update; 0.857966s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (98.3%)
-PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000164287
-PHY-3002 : Step(255): len = 712986, overlap = 53.5
-PHY-3002 : Step(256): len = 696944, overlap = 79.75
-PHY-3002 : Step(257): len = 682333, overlap = 116
-PHY-3002 : Step(258): len = 674623, overlap = 137.75
-PHY-3002 : Step(259): len = 668996, overlap = 153.25
-PHY-3002 : Step(260): len = 665196, overlap = 165.5
-PHY-3002 : Step(261): len = 663411, overlap = 179.25
-PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000328575
-PHY-3002 : Step(262): len = 669297, overlap = 175.25
-PHY-3002 : Step(263): len = 675703, overlap = 176
-PHY-3002 : Step(264): len = 679816, overlap = 173.5
-PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00065715
-PHY-3002 : Step(265): len = 684396, overlap = 170
-PHY-3002 : Step(266): len = 694418, overlap = 160.25
-PHY-3002 : Step(267): len = 698782, overlap = 155
-PHY-3002 : Step(268): len = 701898, overlap = 155.75
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000160038
+PHY-3002 : Step(296): len = 699842, overlap = 38.5
+PHY-3002 : Step(297): len = 685178, overlap = 66.25
+PHY-3002 : Step(298): len = 673051, overlap = 91.75
+PHY-3002 : Step(299): len = 666043, overlap = 117.25
+PHY-3002 : Step(300): len = 661142, overlap = 139.5
+PHY-3002 : Step(301): len = 658978, overlap = 146.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000320077
+PHY-3002 : Step(302): len = 665134, overlap = 141.75
+PHY-3002 : Step(303): len = 670968, overlap = 139.75
+PHY-3002 : Step(304): len = 671541, overlap = 147.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00063987
+PHY-3002 : Step(305): len = 676138, overlap = 148.5
+PHY-3002 : Step(306): len = 686491, overlap = 145
+PHY-3002 : Step(307): len = 691560, overlap = 146.25
+PHY-3002 : Step(308): len = 692892, overlap = 151.75
PHY-3001 : Legalization ...
-PHY-3001 : End legalization; 0.037784s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (82.7%)
+PHY-3001 : End legalization; 0.035092s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (89.1%)
-PHY-3001 : Legalized: Len = 730065, Over = 0
-PHY-3001 : Spreading special nets. 447 overflows in 2952 tiles.
-PHY-3001 : End spreading; 0.109370s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (100.0%)
+PHY-3001 : Legalized: Len = 721430, Over = 0
+PHY-3001 : Spreading special nets. 418 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.110096s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (99.3%)
-PHY-3001 : 660 instances has been re-located, deltaX = 210, deltaY = 407, maxDist = 2.
-PHY-3001 : Final: Len = 740629, Over = 0
+PHY-3001 : 612 instances has been re-located, deltaX = 269, deltaY = 342, maxDist = 3.
+PHY-3001 : Final: Len = 732202, Over = 0
PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
OPT-1001 : Start physical optimization ...
RUN-1002 : start command "start_timer -report"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74010, tnet num: 17427, tinst num: 6909, tnode num: 96499, tedge num: 124264.
-TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73751, tnet num: 17352, tinst num: 6891, tnode num: 96233, tedge num: 123821.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in 1.972104s wall, 1.937500s user + 0.031250s system = 1.968750s CPU (99.8%)
+RUN-1003 : finish command "start_timer -report" in 1.874554s wall, 1.859375s user + 0.015625s system = 1.875000s CPU (100.0%)
-RUN-1004 : used memory is 635 MB, reserved memory is 653 MB, peak memory is 733 MB
+RUN-1004 : used memory is 612 MB, reserved memory is 607 MB, peak memory is 732 MB
OPT-1001 : Total overflow 0.00 peak overflow 0.00
OPT-1001 : Start high-fanout net optimization ...
OPT-1001 : Update timing in global mode
PHY-1001 : Start incremental global routing, caller is place ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 3203/17605.
+PHY-1001 : Reuse net number 3456/17530.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 874136, over cnt = 2608(7%), over = 4302, worst = 9
-PHY-1002 : len = 888584, over cnt = 1473(4%), over = 2234, worst = 7
-PHY-1002 : len = 905280, over cnt = 568(1%), over = 888, worst = 7
-PHY-1002 : len = 919032, over cnt = 51(0%), over = 69, worst = 5
-PHY-1002 : len = 920176, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations; 2.311184s wall, 3.625000s user + 0.000000s system = 3.625000s CPU (156.8%)
+PHY-1002 : len = 859832, over cnt = 2564(7%), over = 4193, worst = 8
+PHY-1002 : len = 875568, over cnt = 1522(4%), over = 2156, worst = 6
+PHY-1002 : len = 887848, over cnt = 801(2%), over = 1128, worst = 6
+PHY-1002 : len = 899448, over cnt = 263(0%), over = 372, worst = 5
+PHY-1002 : len = 905456, over cnt = 12(0%), over = 15, worst = 2
+PHY-1001 : End global iterations; 1.903423s wall, 2.906250s user + 0.031250s system = 2.937500s CPU (154.3%)
-PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.41, top10 = 46.68, top15 = 44.80.
-PHY-1001 : End incremental global routing; 2.720139s wall, 4.031250s user + 0.000000s system = 4.031250s CPU (148.2%)
+PHY-1001 : Congestion index: top1 = 53.38, top5 = 48.42, top10 = 45.65, top15 = 43.88.
+PHY-1001 : End incremental global routing; 2.274139s wall, 3.281250s user + 0.046875s system = 3.328125s CPU (146.3%)
TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 17427 nets completely.
+TMR-2504 : Update delay of 17352 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 5.
TMR-3001 : Initiate 12 clocks from SDC.
TMR-3004 : Map sdc constraints, there are 6 constraints in total.
@@ -1062,7 +1101,7 @@ TMR-3003 : Constraints initiated successfully.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update; 0.945794s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.1%)
+OPT-1001 : End timing update; 0.862982s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.6%)
OPT-1001 : 5 high-fanout net processed.
PHY-3001 : Start incremental placement ...
@@ -1070,42 +1109,41 @@ PHY-1001 : Populate physical database on model huagao_mipi_top.
PHY-3001 : Initial placement ...
PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
-PHY-3001 : eco cells: 6816 has valid locations, 26 needs to be replaced
-PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
-PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : eco cells: 6798 has valid locations, 27 needs to be replaced
+PHY-3001 : design contains 6913 instances, 6764 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3639 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
PHY-3001 : Global placement ...
-PHY-3001 : Initial: Len = 744426
+PHY-3001 : Initial: Len = 735387
PHY-3001 : Run with size of 4
PHY-3001 : Cell area utilization is 74%
PHY-3001 : Analyzing congestion ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 16034/17630.
+PHY-1001 : Reuse net number 15975/17552.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 924200, over cnt = 82(0%), over = 95, worst = 3
-PHY-1002 : len = 924280, over cnt = 38(0%), over = 39, worst = 2
-PHY-1002 : len = 924576, over cnt = 15(0%), over = 15, worst = 1
-PHY-1002 : len = 924704, over cnt = 4(0%), over = 4, worst = 1
-PHY-1002 : len = 924736, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations; 0.828284s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (111.3%)
+PHY-1002 : len = 909520, over cnt = 90(0%), over = 105, worst = 5
+PHY-1002 : len = 909704, over cnt = 43(0%), over = 44, worst = 2
+PHY-1002 : len = 910104, over cnt = 19(0%), over = 19, worst = 1
+PHY-1002 : len = 910456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.622373s wall, 0.656250s user + 0.015625s system = 0.671875s CPU (108.0%)
-PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.39, top10 = 46.67, top15 = 44.80.
-PHY-3001 : End congestion estimation; 1.163709s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (107.4%)
+PHY-1001 : Congestion index: top1 = 53.36, top5 = 48.44, top10 = 45.71, top15 = 43.96.
+PHY-3001 : End congestion estimation; 0.931666s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (105.7%)
PHY-3001 : Update density targets...
PHY-3001 : Update congestion history...
PHY-3001 : Update timing in global mode ...
RUN-1002 : start command "start_timer -report"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74216, tnet num: 17452, tinst num: 6930, tnode num: 96760, tedge num: 124559.
-TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73989, tnet num: 17374, tinst num: 6913, tnode num: 96516, tedge num: 124127.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in 1.993424s wall, 1.984375s user + 0.015625s system = 2.000000s CPU (100.3%)
+RUN-1003 : finish command "start_timer -report" in 1.842906s wall, 1.812500s user + 0.031250s system = 1.843750s CPU (100.0%)
-RUN-1004 : used memory is 645 MB, reserved memory is 641 MB, peak memory is 733 MB
+RUN-1004 : used memory is 661 MB, reserved memory is 665 MB, peak memory is 732 MB
TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 17452 nets completely.
+TMR-2504 : Update delay of 17374 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 5.
TMR-3001 : Initiate 12 clocks from SDC.
TMR-3004 : Map sdc constraints, there are 6 constraints in total.
@@ -1113,361 +1151,149 @@ TMR-3003 : Constraints initiated successfully.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update; 2.971579s wall, 2.937500s user + 0.031250s system = 2.968750s CPU (99.9%)
+PHY-3001 : End timing update; 2.732448s wall, 2.671875s user + 0.062500s system = 2.734375s CPU (100.1%)
PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
-PHY-3002 : Step(269): len = 743276, overlap = 0
-PHY-3002 : Step(270): len = 742723, overlap = 0
-PHY-3002 : Step(271): len = 742706, overlap = 0
+PHY-3002 : Step(309): len = 734474, overlap = 0
+PHY-3002 : Step(310): len = 734081, overlap = 0
PHY-3001 : Run with size of 2
PHY-3001 : Cell area utilization is 74%
PHY-3001 : Analyzing congestion ...
PHY-1001 : Generate routing nets ...
PHY-1001 : Incremental mode ON
-PHY-1001 : Reuse net number 16022/17630.
+PHY-1001 : Reuse net number 15963/17552.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 921320, over cnt = 94(0%), over = 112, worst = 5
-PHY-1002 : len = 921496, over cnt = 44(0%), over = 48, worst = 4
-PHY-1002 : len = 922000, over cnt = 10(0%), over = 10, worst = 1
-PHY-1002 : len = 922184, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations; 0.657432s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (104.6%)
+PHY-1002 : len = 908160, over cnt = 75(0%), over = 95, worst = 4
+PHY-1002 : len = 908296, over cnt = 39(0%), over = 42, worst = 2
+PHY-1002 : len = 908824, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 908920, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.653769s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (112.3%)
-PHY-1001 : Congestion index: top1 = 55.04, top5 = 49.39, top10 = 46.68, top15 = 44.83.
-PHY-3001 : End congestion estimation; 1.000205s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (103.1%)
+PHY-1001 : Congestion index: top1 = 53.30, top5 = 48.44, top10 = 45.71, top15 = 43.95.
+PHY-3001 : End congestion estimation; 0.987356s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (107.6%)
PHY-3001 : Update density targets...
PHY-3001 : Update congestion history...
PHY-3001 : Update timing in global mode ...
TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 17452 nets completely.
+TMR-2504 : Update delay of 17374 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 5.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update; 0.919630s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (100.2%)
+PHY-3001 : End timing update; 0.862313s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.7%)
-PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00045968
-PHY-3002 : Step(272): len = 742691, overlap = 1.75
-PHY-3002 : Step(273): len = 742734, overlap = 1.5
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000333503
+PHY-3002 : Step(311): len = 734109, overlap = 1.5
+PHY-3002 : Step(312): len = 734482, overlap = 1.5
PHY-3001 : Legalization ...
-PHY-3001 : End legalization; 0.005744s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+PHY-3001 : End legalization; 0.005911s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
-PHY-3001 : Legalized: Len = 742783, Over = 0
-PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
-PHY-3001 : End spreading; 0.067353s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (92.8%)
+PHY-3001 : Legalized: Len = 734542, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059822s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (78.4%)
-PHY-3001 : 2 instances has been re-located, deltaX = 4, deltaY = 0, maxDist = 2.
-PHY-3001 : Final: Len = 742827, Over = 0
-PHY-3001 : End incremental placement; 6.623341s wall, 6.890625s user + 0.093750s system = 6.984375s CPU (105.5%)
+PHY-3001 : 14 instances has been re-located, deltaX = 13, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 734724, Over = 0
+PHY-3001 : End incremental placement; 5.993245s wall, 6.046875s user + 0.171875s system = 6.218750s CPU (103.8%)
OPT-1001 : Total overflow 0.00 peak overflow 0.00
-OPT-1001 : End high-fanout net optimization; 10.816412s wall, 12.390625s user + 0.093750s system = 12.484375s CPU (115.4%)
+OPT-1001 : End high-fanout net optimization; 9.612886s wall, 10.796875s user + 0.218750s system = 11.015625s CPU (114.6%)
-OPT-1001 : Current memory(MB): used = 739, reserve = 742, peak = 743.
+OPT-1001 : Current memory(MB): used = 736, reserve = 736, peak = 742.
OPT-1001 : Start path based optimization ...
OPT-1001 : Start congestion update ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 16016/17630.
+PHY-1001 : Reuse net number 15926/17552.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 922168, over cnt = 57(0%), over = 74, worst = 4
-PHY-1002 : len = 922344, over cnt = 24(0%), over = 27, worst = 2
-PHY-1002 : len = 922616, over cnt = 8(0%), over = 8, worst = 1
-PHY-1002 : len = 922736, over cnt = 1(0%), over = 1, worst = 1
-PHY-1002 : len = 922752, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations; 0.912525s wall, 1.000000s user + 0.015625s system = 1.015625s CPU (111.3%)
+PHY-1002 : len = 909344, over cnt = 69(0%), over = 91, worst = 7
+PHY-1002 : len = 909360, over cnt = 28(0%), over = 28, worst = 1
+PHY-1002 : len = 909488, over cnt = 18(0%), over = 18, worst = 1
+PHY-1002 : len = 909728, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 909752, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.805598s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (106.7%)
-PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.38, top10 = 46.62, top15 = 44.79.
-OPT-1001 : End congestion update; 1.275360s wall, 1.359375s user + 0.015625s system = 1.375000s CPU (107.8%)
+PHY-1001 : Congestion index: top1 = 53.19, top5 = 48.37, top10 = 45.65, top15 = 43.90.
+OPT-1001 : End congestion update; 1.116446s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (103.6%)
OPT-1001 : Update timing in Manhattan mode
TMR-2503 : Start to update net delay, extr mode = 3.
-TMR-2504 : Update delay of 17452 nets completely.
+TMR-2504 : Update delay of 17374 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 3.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update; 0.774240s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (98.9%)
+OPT-1001 : End timing update; 0.721944s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.6%)
-OPT-0007 : Start: WNS -1086 TNS -1721 NUM_FEPS 2
+OPT-0007 : Start: WNS -1040 TNS -1754 NUM_FEPS 3
PHY-3001 : Start incremental legalization ...
PHY-1001 : Populate physical database on model huagao_mipi_top.
PHY-3001 : Initial placement ...
PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
-PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
-PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
-PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : eco cells: 6825 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6913 instances, 6764 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3639 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
PHY-3001 : Cell area utilization is 74%
-PHY-3001 : Initial: Len = 746757, Over = 0
-PHY-3001 : Spreading special nets. 28 overflows in 2952 tiles.
-PHY-3001 : End spreading; 0.078671s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (99.3%)
+PHY-3001 : Initial: Len = 739128, Over = 0
+PHY-3001 : Spreading special nets. 19 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063330s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.7%)
-PHY-3001 : 35 instances has been re-located, deltaX = 19, deltaY = 20, maxDist = 6.
-PHY-3001 : Final: Len = 747093, Over = 0
-PHY-3001 : End incremental legalization; 0.451923s wall, 0.437500s user + 0.015625s system = 0.453125s CPU (100.3%)
+PHY-3001 : 29 instances has been re-located, deltaX = 25, deltaY = 15, maxDist = 3.
+PHY-3001 : Final: Len = 739360, Over = 0
+PHY-3001 : End incremental legalization; 0.392123s wall, 0.375000s user + 0.031250s system = 0.406250s CPU (103.6%)
-OPT-0007 : Iter 1: improved WNS -986 TNS -1521 NUM_FEPS 2 with 53 cells processed and 9773 slack improved
-PHY-3001 : Start incremental legalization ...
-PHY-1001 : Populate physical database on model huagao_mipi_top.
-PHY-3001 : Initial placement ...
-PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
-PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
-PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
-PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
-PHY-3001 : Found 492 cells with 2 region constraints.
-PHY-3001 : Cell area utilization is 74%
-PHY-3001 : Initial: Len = 747839, Over = 0
-PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
-PHY-3001 : End spreading; 0.067305s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (92.9%)
+OPT-0007 : Iter 1: improved WNS -990 TNS -1625 NUM_FEPS 2 with 35 cells processed and 11554 slack improved
+OPT-0007 : Iter 2: improved WNS -990 TNS -1625 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.369147s wall, 2.390625s user + 0.031250s system = 2.421875s CPU (102.2%)
-PHY-3001 : 15 instances has been re-located, deltaX = 9, deltaY = 10, maxDist = 5.
-PHY-3001 : Final: Len = 747939, Over = 0
-PHY-3001 : End incremental legalization; 0.449954s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.7%)
-
-OPT-0007 : Iter 2: improved WNS -936 TNS -1471 NUM_FEPS 2 with 20 cells processed and 1573 slack improved
-PHY-3001 : Start incremental legalization ...
-PHY-1001 : Populate physical database on model huagao_mipi_top.
-PHY-3001 : Initial placement ...
-PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
-PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
-PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
-PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
-PHY-3001 : Found 492 cells with 2 region constraints.
-PHY-3001 : Cell area utilization is 74%
-PHY-3001 : Initial: Len = 748129, Over = 0
-PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles.
-PHY-3001 : End spreading; 0.064779s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.5%)
-
-PHY-3001 : 15 instances has been re-located, deltaX = 12, deltaY = 7, maxDist = 7.
-PHY-3001 : Final: Len = 747949, Over = 0
-PHY-3001 : End incremental legalization; 0.418141s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.9%)
-
-OPT-0007 : Iter 3: improved WNS -936 TNS -1471 NUM_FEPS 2 with 15 cells processed and 349 slack improved
-OPT-1001 : End path based optimization; 3.906012s wall, 3.953125s user + 0.046875s system = 4.000000s CPU (102.4%)
-
-OPT-1001 : Current memory(MB): used = 739, reserve = 742, peak = 743.
+OPT-1001 : Current memory(MB): used = 736, reserve = 736, peak = 742.
OPT-1001 : Update timing in Manhattan mode
TMR-2503 : Start to update net delay, extr mode = 3.
-TMR-2504 : Update delay of 17452 nets completely.
+TMR-2504 : Update delay of 17374 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 3.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update; 0.806124s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (96.9%)
+OPT-1001 : End timing update; 0.726593s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (101.1%)
OPT-1001 : Start pin optimization...
OPT-1001 : skip pin optimization...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 15705/17630.
+PHY-1001 : Reuse net number 15842/17552.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 926848, over cnt = 191(0%), over = 258, worst = 4
-PHY-1002 : len = 927192, over cnt = 104(0%), over = 111, worst = 2
-PHY-1002 : len = 927784, over cnt = 33(0%), over = 34, worst = 2
-PHY-1002 : len = 928328, over cnt = 3(0%), over = 3, worst = 1
-PHY-1002 : len = 928456, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations; 0.961342s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (102.4%)
+PHY-1002 : len = 913768, over cnt = 81(0%), over = 92, worst = 4
+PHY-1002 : len = 913880, over cnt = 38(0%), over = 40, worst = 2
+PHY-1002 : len = 914048, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 914240, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 914256, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.816002s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (109.1%)
-PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.55, top10 = 46.70, top15 = 44.82.
+PHY-1001 : Congestion index: top1 = 53.56, top5 = 48.50, top10 = 45.71, top15 = 43.94.
OPT-1001 : Update timing in Manhattan mode
TMR-2503 : Start to update net delay, extr mode = 3.
-TMR-2504 : Update delay of 17452 nets completely.
+TMR-2504 : Update delay of 17374 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 3.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update; 0.787686s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.2%)
+OPT-1001 : End timing update; 0.719422s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.9%)
RUN-1001 : QoR Analysis:
-OPT-0007 : WNS -986 TNS -1571 NUM_FEPS 2
-RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.482759
+OPT-0007 : WNS -1040 TNS -1725 NUM_FEPS 2
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 53.103448
RUN-1001 : Top critical paths
-RUN-1001 : #1 path slack -986ps with logic level 2
-RUN-1001 : #2 path slack -940ps with logic level 2
-RUN-1001 : extra opt step will be enabled to improve QoR
-RUN-1001 : 0 HFN exist on timing critical paths out of 17630 nets
-RUN-1001 : 0 long nets exist on timing critical paths out of 17630 nets
-PHY-3001 : Start incremental legalization ...
-PHY-1001 : Populate physical database on model huagao_mipi_top.
-PHY-3001 : Initial placement ...
-PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
-PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
-PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
-PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
-PHY-3001 : Found 492 cells with 2 region constraints.
-PHY-3001 : Cell area utilization is 74%
-PHY-3001 : Initial: Len = 747949, Over = 0
-PHY-3001 : End spreading; 0.065259s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.8%)
+RUN-1001 : #1 path slack -1040ps with logic level 2
+RUN-1001 : 0 HFN exist on timing critical paths out of 17552 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 17552 nets
+OPT-1001 : End physical optimization; 16.807141s wall, 18.046875s user + 0.281250s system = 18.328125s CPU (109.0%)
-PHY-3001 : Final: Len = 747949, Over = 0
-PHY-3001 : End incremental legalization; 0.421445s wall, 0.515625s user + 0.031250s system = 0.546875s CPU (129.8%)
+RUN-1003 : finish command "place" in 59.234187s wall, 88.281250s user + 5.921875s system = 94.203125s CPU (159.0%)
-OPT-1001 : Update timing in Manhattan mode
-TMR-2503 : Start to update net delay, extr mode = 3.
-TMR-2504 : Update delay of 17452 nets completely.
-TMR-2502 : Annotate delay completely, extr mode = 3.
-TMR-3501 : Forward propagation: start to calculate arrival time...
-TMR-3502 : Backward propagation: start to calculate required time...
-TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update; 0.805812s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (100.8%)
-
-OPT-1001 : Start path based optimization ...
-OPT-1001 : Start congestion update ...
-RUN-1001 : Generating global routing grids ...
-PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 16057/17630.
-PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 928456, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations; 0.141990s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.0%)
-
-PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.55, top10 = 46.70, top15 = 44.82.
-OPT-1001 : End congestion update; 0.475537s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (98.6%)
-
-OPT-1001 : Update timing in Manhattan mode
-TMR-2503 : Start to update net delay, extr mode = 3.
-TMR-2504 : Update delay of 17452 nets completely.
-TMR-2502 : Annotate delay completely, extr mode = 3.
-TMR-3501 : Forward propagation: start to calculate arrival time...
-TMR-3502 : Backward propagation: start to calculate required time...
-TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update; 0.760751s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.6%)
-
-OPT-0007 : Start: WNS -986 TNS -1571 NUM_FEPS 2
-PHY-3001 : Start incremental legalization ...
-PHY-1001 : Populate physical database on model huagao_mipi_top.
-PHY-3001 : Initial placement ...
-PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
-PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
-PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
-PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
-PHY-3001 : Found 492 cells with 2 region constraints.
-PHY-3001 : Cell area utilization is 74%
-PHY-3001 : Initial: Len = 747889, Over = 0
-PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
-PHY-3001 : End spreading; 0.075859s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (103.0%)
-
-PHY-3001 : 3 instances has been re-located, deltaX = 3, deltaY = 0, maxDist = 1.
-PHY-3001 : Final: Len = 747949, Over = 0
-PHY-3001 : End incremental legalization; 0.485966s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (135.0%)
-
-OPT-0007 : Iter 1: improved WNS -936 TNS -1471 NUM_FEPS 2 with 3 cells processed and 150 slack improved
-OPT-0007 : Iter 2: improved WNS -936 TNS -1471 NUM_FEPS 2 with 0 cells processed and 0 slack improved
-OPT-1001 : End path based optimization; 1.855841s wall, 2.093750s user + 0.000000s system = 2.093750s CPU (112.8%)
-
-OPT-1001 : Current memory(MB): used = 739, reserve = 742, peak = 743.
-OPT-1001 : Start bottleneck based optimization ...
-OPT-1001 : Start congestion update ...
-RUN-1001 : Generating global routing grids ...
-PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 16057/17630.
-PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 928456, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations; 0.169442s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (92.2%)
-
-PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.55, top10 = 46.70, top15 = 44.82.
-OPT-1001 : End congestion update; 0.590557s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (97.9%)
-
-OPT-1001 : Update timing in Manhattan mode
-TMR-2503 : Start to update net delay, extr mode = 3.
-TMR-2504 : Update delay of 17452 nets completely.
-TMR-2502 : Annotate delay completely, extr mode = 3.
-TMR-3501 : Forward propagation: start to calculate arrival time...
-TMR-3502 : Backward propagation: start to calculate required time...
-TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update; 0.833191s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (101.3%)
-
-OPT-0007 : Start: WNS -986 TNS -1571 NUM_FEPS 2
-PHY-3001 : Start incremental legalization ...
-PHY-1001 : Populate physical database on model huagao_mipi_top.
-PHY-3001 : Initial placement ...
-PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
-PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
-PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
-PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
-PHY-3001 : Found 492 cells with 2 region constraints.
-PHY-3001 : Cell area utilization is 74%
-PHY-3001 : Initial: Len = 747909, Over = 0
-PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
-PHY-3001 : End spreading; 0.066075s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.6%)
-
-PHY-3001 : 2 instances has been re-located, deltaX = 2, deltaY = 0, maxDist = 1.
-PHY-3001 : Final: Len = 747949, Over = 0
-PHY-3001 : End incremental legalization; 0.428158s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (124.1%)
-
-OPT-0007 : Iter 1: improved WNS -936 TNS -1471 NUM_FEPS 2 with 2 cells processed and 100 slack improved
-PHY-3001 : Start incremental legalization ...
-PHY-1001 : Populate physical database on model huagao_mipi_top.
-PHY-3001 : Initial placement ...
-PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
-PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
-PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
-PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
-PHY-3001 : Found 492 cells with 2 region constraints.
-PHY-3001 : Cell area utilization is 74%
-PHY-3001 : Initial: Len = 747909, Over = 0
-PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
-PHY-3001 : End spreading; 0.064488s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.9%)
-
-PHY-3001 : 2 instances has been re-located, deltaX = 2, deltaY = 0, maxDist = 1.
-PHY-3001 : Final: Len = 747949, Over = 0
-PHY-3001 : End incremental legalization; 0.424749s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (125.1%)
-
-OPT-0007 : Iter 2: improved WNS -936 TNS -1471 NUM_FEPS 2 with 2 cells processed and 0 slack improved
-OPT-0007 : Iter 3: improved WNS -936 TNS -1471 NUM_FEPS 2 with 0 cells processed and 0 slack improved
-OPT-1001 : End bottleneck based optimization; 2.628235s wall, 2.812500s user + 0.000000s system = 2.812500s CPU (107.0%)
-
-OPT-1001 : Current memory(MB): used = 739, reserve = 742, peak = 743.
-OPT-1001 : Update timing in Manhattan mode
-TMR-2503 : Start to update net delay, extr mode = 3.
-TMR-2504 : Update delay of 17452 nets completely.
-TMR-2502 : Annotate delay completely, extr mode = 3.
-TMR-3501 : Forward propagation: start to calculate arrival time...
-TMR-3502 : Backward propagation: start to calculate required time...
-TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update; 0.803381s wall, 0.781250s user + 0.015625s system = 0.796875s CPU (99.2%)
-
-OPT-1001 : Start pin optimization...
-OPT-1001 : skip pin optimization...
-OPT-1001 : Current memory(MB): used = 739, reserve = 742, peak = 743.
-OPT-1001 : Start congestion recovery ...
-RUN-1002 : start command "set_param place ofv 80"
-OPT-1001 : Update timing in Manhattan mode
-TMR-2503 : Start to update net delay, extr mode = 3.
-TMR-2504 : Update delay of 17452 nets completely.
-TMR-2502 : Annotate delay completely, extr mode = 3.
-TMR-3501 : Forward propagation: start to calculate arrival time...
-TMR-3502 : Backward propagation: start to calculate required time...
-TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update; 1.128367s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.7%)
-
-RUN-1001 : Start congestion update ...
-RUN-1001 : Generating global routing grids ...
-PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 16057/17630.
-PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 928456, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations; 0.145366s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.7%)
-
-PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.55, top10 = 46.70, top15 = 44.82.
-RUN-1001 : End congestion update; 0.482550s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (97.1%)
-
-RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
-OPT-1001 : End congestion recovery; 1.614286s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.7%)
-
-OPT-1001 : Current memory(MB): used = 739, reserve = 742, peak = 743.
-OPT-1001 : End physical optimization; 28.258080s wall, 30.453125s user + 0.250000s system = 30.703125s CPU (108.7%)
-
-RUN-1003 : finish command "place" in 71.802909s wall, 100.937500s user + 5.593750s system = 106.531250s CPU (148.4%)
-
-RUN-1004 : used memory is 611 MB, reserved memory is 619 MB, peak memory is 743 MB
+RUN-1004 : used memory is 604 MB, reserved memory is 617 MB, peak memory is 742 MB
RUN-1002 : start command "export_db hg_anlogic_place.db"
RUN-1001 : Exported /
RUN-1001 : Exported flow parameters
@@ -1484,9 +1310,9 @@ RUN-1001 : Exported violations
RUN-1001 : Exported timing constraints
RUN-1001 : Exported IO constraints
RUN-1001 : Exported Inst constraints
-RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.768222s wall, 3.109375s user + 0.015625s system = 3.125000s CPU (176.7%)
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.701880s wall, 2.968750s user + 0.015625s system = 2.984375s CPU (175.4%)
-RUN-1004 : used memory is 611 MB, reserved memory is 620 MB, peak memory is 743 MB
+RUN-1004 : used memory is 605 MB, reserved memory is 618 MB, peak memory is 742 MB
RUN-1002 : start command "route"
RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
RUN-1001 : Print Global Property
@@ -1511,27 +1337,27 @@ RUN-1001 : priority | timing | timing |
RUN-1001 : swap_pin | on | on |
RUN-1001 : -------------------------------------------------------
PHY-1001 : Route runs in 8 thread(s)
-RUN-1001 : There are total 6932 instances
-RUN-1001 : 3392 mslices, 3389 lslices, 75 pads, 58 brams, 3 dsps
-RUN-1001 : There are total 17630 nets
+RUN-1001 : There are total 6915 instances
+RUN-1001 : 3380 mslices, 3384 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17552 nets
RUN-6004 WARNING: There are 20 nets with only 1 pin.
-RUN-1001 : 9886 nets have 2 pins
-RUN-1001 : 6040 nets have [3 - 5] pins
-RUN-1001 : 1001 nets have [6 - 10] pins
-RUN-1001 : 321 nets have [11 - 20] pins
-RUN-1001 : 354 nets have [21 - 99] pins
+RUN-1001 : 9969 nets have 2 pins
+RUN-1001 : 5757 nets have [3 - 5] pins
+RUN-1001 : 1125 nets have [6 - 10] pins
+RUN-1001 : 318 nets have [11 - 20] pins
+RUN-1001 : 355 nets have [21 - 99] pins
RUN-1001 : 8 nets have 100+ pins
RUN-1002 : start command "start_timer -report"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74216, tnet num: 17452, tinst num: 6930, tnode num: 96760, tedge num: 124559.
-TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73989, tnet num: 17374, tinst num: 6913, tnode num: 96516, tedge num: 124127.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in 1.769299s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (99.8%)
+RUN-1003 : finish command "start_timer -report" in 1.725273s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (99.6%)
-RUN-1004 : used memory is 604 MB, reserved memory is 605 MB, peak memory is 743 MB
-PHY-1001 : 3392 mslices, 3389 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1004 : used memory is 601 MB, reserved memory is 611 MB, peak memory is 742 MB
+PHY-1001 : 3380 mslices, 3384 lslices, 75 pads, 58 brams, 3 dsps
TMR-2503 : Start to update net delay, extr mode = 3.
-TMR-2504 : Update delay of 17452 nets completely.
+TMR-2504 : Update delay of 17374 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 3.
TMR-3001 : Initiate 12 clocks from SDC.
TMR-3004 : Map sdc constraints, there are 6 constraints in total.
@@ -1543,18 +1369,18 @@ PHY-1001 : Start global routing, caller is route ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 861432, over cnt = 2754(7%), over = 4563, worst = 8
-PHY-1002 : len = 876872, over cnt = 1730(4%), over = 2557, worst = 6
-PHY-1002 : len = 899896, over cnt = 526(1%), over = 774, worst = 6
-PHY-1002 : len = 912264, over cnt = 3(0%), over = 3, worst = 1
-PHY-1002 : len = 912440, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations; 3.203294s wall, 4.343750s user + 0.078125s system = 4.421875s CPU (138.0%)
+PHY-1002 : len = 847752, over cnt = 2759(7%), over = 4572, worst = 8
+PHY-1002 : len = 866784, over cnt = 1589(4%), over = 2268, worst = 8
+PHY-1002 : len = 884376, over cnt = 660(1%), over = 927, worst = 6
+PHY-1002 : len = 898472, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 898536, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.878729s wall, 3.984375s user + 0.078125s system = 4.062500s CPU (141.1%)
-PHY-1001 : Congestion index: top1 = 54.20, top5 = 49.29, top10 = 46.64, top15 = 44.74.
-PHY-1001 : End global routing; 3.574955s wall, 4.718750s user + 0.078125s system = 4.796875s CPU (134.2%)
+PHY-1001 : Congestion index: top1 = 53.28, top5 = 48.37, top10 = 45.59, top15 = 43.67.
+PHY-1001 : End global routing; 3.212755s wall, 4.296875s user + 0.093750s system = 4.390625s CPU (136.7%)
PHY-1001 : Start detail routing ...
-PHY-1001 : Current memory(MB): used = 710, reserve = 717, peak = 743.
+PHY-1001 : Current memory(MB): used = 711, reserve = 715, peak = 742.
PHY-1001 : Detailed router is running in normal mode.
PHY-1001 : Generate detailed routing grids ...
PHY-1001 : Generate nets ...
@@ -1584,131 +1410,131 @@ PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock me
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
-PHY-1001 : Current memory(MB): used = 985, reserve = 991, peak = 985.
-PHY-1001 : End build detailed router design. 4.285590s wall, 4.250000s user + 0.046875s system = 4.296875s CPU (100.3%)
+PHY-1001 : Current memory(MB): used = 988, reserve = 993, peak = 988.
+PHY-1001 : End build detailed router design. 3.992463s wall, 3.984375s user + 0.015625s system = 4.000000s CPU (100.2%)
PHY-1001 : Detail Route ...
PHY-1001 : ===== Detail Route Phase 1 =====
PHY-1001 : Clock net routing.....
PHY-1001 : Routed 0% nets.
-PHY-1022 : len = 266520, over cnt = 4(0%), over = 4, worst = 1, crit = 0
-PHY-1001 : End initial clock net routed; 5.543466s wall, 5.515625s user + 0.000000s system = 5.515625s CPU (99.5%)
+PHY-1022 : len = 267120, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.309327s wall, 5.281250s user + 0.015625s system = 5.296875s CPU (99.8%)
PHY-1001 : Ripup-reroute.....
PHY-1001 : ===== DR Iter 1 =====
-PHY-1022 : len = 266576, over cnt = 0(0%), over = 0, worst = 0, crit = 0
-PHY-1001 : End DR Iter 1; 0.456184s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (102.8%)
+PHY-1022 : len = 267176, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.431956s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.3%)
-PHY-1001 : Current memory(MB): used = 1021, reserve = 1028, peak = 1021.
-PHY-1001 : End phase 1; 6.012081s wall, 5.984375s user + 0.000000s system = 5.984375s CPU (99.5%)
+PHY-1001 : Current memory(MB): used = 1024, reserve = 1030, peak = 1024.
+PHY-1001 : End phase 1; 5.753878s wall, 5.734375s user + 0.015625s system = 5.750000s CPU (99.9%)
PHY-1001 : ===== Detail Route Phase 2 =====
PHY-1001 : Initial routing.....
PHY-1001 : Routed 44% nets.
-PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 51% nets.
PHY-1001 : Routed 61% nets.
PHY-1001 : Routed 73% nets.
PHY-1001 : Routed 93% nets.
-PHY-1022 : len = 2.38544e+06, over cnt = 1940(0%), over = 1945, worst = 2, crit = 0
-PHY-1001 : Current memory(MB): used = 1038, reserve = 1042, peak = 1038.
-PHY-1001 : End initial routed; 31.065055s wall, 66.125000s user + 0.296875s system = 66.421875s CPU (213.8%)
+PHY-1022 : len = 2.31459e+06, over cnt = 1958(0%), over = 1962, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1042, reserve = 1047, peak = 1042.
+PHY-1001 : End initial routed; 22.886717s wall, 57.109375s user + 0.343750s system = 57.453125s CPU (251.0%)
PHY-1001 : Update timing.....
-PHY-1001 : 11/16553(0%) critical/total net(s).
+PHY-1001 : 4/16475(0%) critical/total net(s).
RUN-1001 : --------------------------------------
RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
RUN-1001 : --------------------------------------
-RUN-1001 : Setup | -1.799 | -4.467 | 4
+RUN-1001 : Setup | -2.084 | -4.275 | 3
RUN-1001 : Hold | 0.067 | 0.000 | 0
RUN-1001 : --------------------------------------
-PHY-1001 : End update timing; 3.475285s wall, 3.468750s user + 0.000000s system = 3.468750s CPU (99.8%)
+PHY-1001 : End update timing; 3.376894s wall, 3.359375s user + 0.015625s system = 3.375000s CPU (99.9%)
-PHY-1001 : Current memory(MB): used = 1054, reserve = 1059, peak = 1054.
-PHY-1001 : End phase 2; 34.540448s wall, 69.593750s user + 0.296875s system = 69.890625s CPU (202.3%)
+PHY-1001 : Current memory(MB): used = 1045, reserve = 1047, peak = 1045.
+PHY-1001 : End phase 2; 26.263678s wall, 60.468750s user + 0.359375s system = 60.828125s CPU (231.6%)
PHY-1001 : ===== Detail Route Phase 3 =====
PHY-1001 : Optimize timing.....
PHY-1001 : ===== OPT Iter 1 =====
-PHY-1001 : Processed 4 pins with SWNS -1.797ns STNS -3.968ns FEP 3.
-PHY-1001 : End OPT Iter 1; 0.160822s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (106.9%)
+PHY-1001 : Processed 4 pins with SWNS -1.945ns STNS -4.090ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.147381s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (106.0%)
-PHY-1022 : len = 2.38541e+06, over cnt = 1942(0%), over = 1947, worst = 2, crit = 0
-PHY-1001 : End optimize timing; 0.456183s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (102.8%)
+PHY-1022 : len = 2.31459e+06, over cnt = 1960(0%), over = 1964, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.412433s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (98.5%)
PHY-1001 : Ripup-reroute.....
PHY-1001 : ===== DR Iter 1 =====
-PHY-1022 : len = 2.35104e+06, over cnt = 800(0%), over = 801, worst = 2, crit = 0
-PHY-1001 : End DR Iter 1; 2.258916s wall, 4.187500s user + 0.000000s system = 4.187500s CPU (185.4%)
+PHY-1022 : len = 2.28119e+06, over cnt = 722(0%), over = 722, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.359431s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (183.9%)
PHY-1001 : ===== DR Iter 2 =====
-PHY-1022 : len = 2.34865e+06, over cnt = 253(0%), over = 254, worst = 2, crit = 0
-PHY-1001 : End DR Iter 2; 0.761614s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (141.6%)
+PHY-1022 : len = 2.27972e+06, over cnt = 191(0%), over = 191, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.616469s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (167.3%)
PHY-1001 : ===== DR Iter 3 =====
-PHY-1022 : len = 2.34642e+06, over cnt = 33(0%), over = 33, worst = 1, crit = 0
-PHY-1001 : End DR Iter 3; 0.752782s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (128.7%)
+PHY-1022 : len = 2.28086e+06, over cnt = 22(0%), over = 22, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.482993s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (119.7%)
PHY-1001 : ===== DR Iter 4 =====
-PHY-1022 : len = 2.34658e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
-PHY-1001 : End DR Iter 4; 0.332144s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (98.8%)
+PHY-1022 : len = 2.28087e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.237032s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (105.5%)
PHY-1001 : ===== DR Iter 5 =====
-PHY-1022 : len = 2.34667e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
-PHY-1001 : End DR Iter 5; 0.188044s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.7%)
+PHY-1022 : len = 2.28094e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.207754s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (105.3%)
PHY-1001 : Update timing.....
-PHY-1001 : 4/16553(0%) critical/total net(s).
+PHY-1001 : 4/16475(0%) critical/total net(s).
RUN-1001 : --------------------------------------
RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
RUN-1001 : --------------------------------------
-RUN-1001 : Setup | -1.797 | -3.968 | 3
+RUN-1001 : Setup | -1.945 | -4.090 | 3
RUN-1001 : Hold | 0.067 | 0.000 | 0
RUN-1001 : --------------------------------------
-PHY-1001 : End update timing; 3.491980s wall, 3.484375s user + 0.000000s system = 3.484375s CPU (99.8%)
+PHY-1001 : End update timing; 3.278177s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (100.1%)
PHY-1001 : Commit to database.....
-PHY-1001 : 586 feed throughs used by 421 nets
-PHY-1001 : End commit to database; 2.400501s wall, 2.406250s user + 0.000000s system = 2.406250s CPU (100.2%)
+PHY-1001 : 589 feed throughs used by 429 nets
+PHY-1001 : End commit to database; 2.281274s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (100.0%)
-PHY-1001 : Current memory(MB): used = 1157, reserve = 1166, peak = 1157.
-PHY-1001 : End phase 3; 11.067591s wall, 13.500000s user + 0.000000s system = 13.500000s CPU (122.0%)
+PHY-1001 : Current memory(MB): used = 1153, reserve = 1160, peak = 1153.
+PHY-1001 : End phase 3; 9.283671s wall, 10.937500s user + 0.000000s system = 10.937500s CPU (117.8%)
PHY-1001 : ===== Detail Route Phase 4 =====
PHY-1001 : Optimize timing.....
PHY-1001 : ===== OPT Iter 1 =====
-PHY-1001 : Processed 3 pins with SWNS -1.797ns STNS -3.968ns FEP 3.
-PHY-1001 : End OPT Iter 1; 0.151432s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (103.2%)
+PHY-1001 : Processed 3 pins with SWNS -1.945ns STNS -4.090ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.157822s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.0%)
-PHY-1022 : len = 2.34667e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
-PHY-1001 : End optimize timing; 0.409648s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.2%)
+PHY-1022 : len = 2.28094e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.431752s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.7%)
-PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.797ns, -3.968ns, 3}
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.945ns, -4.090ns, 3}
PHY-1001 : Update timing.....
-PHY-1001 : 4/16553(0%) critical/total net(s).
+PHY-1001 : 4/16475(0%) critical/total net(s).
RUN-1001 : --------------------------------------
RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
RUN-1001 : --------------------------------------
-RUN-1001 : Setup | -1.797 | -3.968 | 3
+RUN-1001 : Setup | -1.945 | -4.090 | 3
RUN-1001 : Hold | 0.067 | 0.000 | 0
RUN-1001 : --------------------------------------
-PHY-1001 : End update timing; 3.554722s wall, 3.562500s user + 0.000000s system = 3.562500s CPU (100.2%)
+PHY-1001 : End update timing; 3.367672s wall, 3.359375s user + 0.000000s system = 3.359375s CPU (99.8%)
PHY-1001 : Commit to database.....
-PHY-1001 : 586 feed throughs used by 421 nets
-PHY-1001 : End commit to database; 2.510793s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (99.6%)
+PHY-1001 : 589 feed throughs used by 429 nets
+PHY-1001 : End commit to database; 2.325026s wall, 2.328125s user + 0.000000s system = 2.328125s CPU (100.1%)
-PHY-1001 : Current memory(MB): used = 1166, reserve = 1175, peak = 1166.
-PHY-1001 : End phase 4; 6.505379s wall, 6.500000s user + 0.000000s system = 6.500000s CPU (99.9%)
+PHY-1001 : Current memory(MB): used = 1162, reserve = 1169, peak = 1162.
+PHY-1001 : End phase 4; 6.151986s wall, 6.156250s user + 0.000000s system = 6.156250s CPU (100.1%)
-PHY-1003 : Routed, final wirelength = 2.34667e+06
-PHY-1001 : Current memory(MB): used = 1169, reserve = 1177, peak = 1169.
-PHY-1001 : End export database. 0.065920s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.8%)
+PHY-1003 : Routed, final wirelength = 2.28094e+06
+PHY-1001 : Current memory(MB): used = 1165, reserve = 1172, peak = 1165.
+PHY-1001 : End export database. 0.144027s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.6%)
-PHY-1001 : End detail routing; 62.899885s wall, 100.312500s user + 0.343750s system = 100.656250s CPU (160.0%)
+PHY-1001 : End detail routing; 51.989670s wall, 87.828125s user + 0.390625s system = 88.218750s CPU (169.7%)
-RUN-1003 : finish command "route" in 69.437223s wall, 107.968750s user + 0.453125s system = 108.421875s CPU (156.1%)
+RUN-1003 : finish command "route" in 57.995979s wall, 94.890625s user + 0.484375s system = 95.375000s CPU (164.5%)
-RUN-1004 : used memory is 1090 MB, reserved memory is 1098 MB, peak memory is 1169 MB
+RUN-1004 : used memory is 1093 MB, reserved memory is 1105 MB, peak memory is 1165 MB
RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
RUN-1001 : standard
***Report Model: huagao_mipi_top Device: EG4D20EG176***
@@ -1720,12 +1546,12 @@ IO Statistics
#inout 0
Utilization Statistics
-#lut 10320 out of 19600 52.65%
-#reg 9363 out of 19600 47.77%
-#le 12661
- #lut only 3298 out of 12661 26.05%
- #reg only 2341 out of 12661 18.49%
- #lut® 7022 out of 12661 55.46%
+#lut 10273 out of 19600 52.41%
+#reg 9368 out of 19600 47.80%
+#le 12618
+ #lut only 3250 out of 12618 25.76%
+ #reg only 2345 out of 12618 18.58%
+ #lut® 7023 out of 12618 55.66%
#dsp 3 out of 29 10.34%
#bram 54 out of 64 84.38%
#bram9k 50
@@ -1733,24 +1559,24 @@ Utilization Statistics
#bram32k 4 out of 16 25.00%
#pad 75 out of 130 57.69%
#ireg 13
- #oreg 18
+ #oreg 19
#treg 0
#pll 3 out of 4 75.00%
#gclk 6 out of 16 37.50%
Clock Resource Statistics
Index ClockNet Type DriverType Driver Fanout
-#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1795
-#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1417
-#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1355
-#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 967
-#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 139
-#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70
-#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
-#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1810
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1425
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1358
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 942
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 143
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
-#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg42_syn_219.f1 3
-#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_b/u_ADconfig/reg1_syn_191.f0 2
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_277.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/reg10_syn_122.f1 3
#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
@@ -1760,36 +1586,36 @@ Index ClockNet Type
Detailed IO Report
Name Direction Location IOStandard DriveStrength PullType PackReg
- a_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
- a_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
- a_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
- b_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
- b_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
- b_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
- onoff_in INPUT P133 LVCMOS33 N/A N/A NONE
- paper_in INPUT P4 LVCMOS25 N/A N/A NONE
+ onoff_in INPUT P148 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P106 LVCMOS25 N/A N/A NONE
rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
@@ -1811,85 +1637,85 @@ Detailed IO Report
O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
- a_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
- a_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
- a_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
- a_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
- a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
- b_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
- b_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
- b_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
- b_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P25 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
- debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
- debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
- debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
- fan_pwm OUTPUT P138 LVCMOS33 8 N/A NONE
- frame_indicator OUTPUT P16 LVCMOS25 8 N/A OREG
- onoff_out OUTPUT P152 LVCMOS33 8 N/A NONE
- paper_out OUTPUT P17 LVCMOS25 8 N/A NONE
- scan_out OUTPUT P15 LVCMOS25 8 N/A NONE
- sys_initial_done OUTPUT P104 LVCMOS25 8 N/A NONE
+ fan_pwm OUTPUT P139 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P107 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P169 LVCMOS33 8 N/A NONE
+ paper_out OUTPUT P91 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P66 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P39 LVCMOS25 8 N/A NONE
txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
Report Hierarchy Area:
+---------------------------------------------------------------------------------------------------------+
|Instance |Module |le |lut |ripple |seq |bram |dsp |
+---------------------------------------------------------------------------------------------------------+
-|top |huagao_mipi_top |12661 |9293 |1027 |9394 |58 |3 |
-| U_rgb_to_csi_pakage |rgb_to_csi_pakage |545 |451 |23 |442 |4 |1 |
-| U_fifo_w32_d8192 |fifo_w32_d8192 |98 |83 |4 |90 |4 |0 |
-| U_crc16_24b |crc16_24b |29 |29 |0 |19 |0 |0 |
-| U_ecc_gen |ecc_gen |14 |14 |0 |10 |0 |0 |
-| exdev_ctl_a |exdev_ctl |767 |373 |96 |581 |0 |0 |
-| u_ADconfig |AD_config |188 |139 |25 |142 |0 |0 |
-| u_gen_sp |gen_sp |263 |160 |71 |123 |0 |0 |
-| exdev_ctl_b |exdev_ctl |752 |423 |96 |556 |0 |0 |
-| u_ADconfig |AD_config |178 |140 |25 |126 |0 |0 |
-| u_gen_sp |gen_sp |262 |168 |71 |118 |0 |0 |
-| sampling_fe_a |sampling_fe |3094 |2433 |306 |2032 |25 |0 |
+|top |huagao_mipi_top |12618 |9246 |1027 |9400 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |561 |454 |23 |449 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |110 |93 |4 |93 |4 |0 |
+| U_crc16_24b |crc16_24b |32 |32 |0 |22 |0 |0 |
+| U_ecc_gen |ecc_gen |12 |12 |0 |9 |0 |0 |
+| exdev_ctl_a |exdev_ctl |781 |337 |96 |583 |0 |0 |
+| u_ADconfig |AD_config |191 |118 |25 |142 |0 |0 |
+| u_gen_sp |gen_sp |269 |158 |71 |120 |0 |0 |
+| exdev_ctl_b |exdev_ctl |743 |379 |96 |554 |0 |0 |
+| u_ADconfig |AD_config |177 |129 |25 |125 |0 |0 |
+| u_gen_sp |gen_sp |259 |144 |71 |122 |0 |0 |
+| sampling_fe_a |sampling_fe |3071 |2501 |306 |2076 |25 |0 |
| u0_soft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
-| u_ad_sampling |ad_sampling |183 |97 |17 |141 |0 |0 |
-| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
-| u_sort |sort |2875 |2311 |289 |1855 |25 |0 |
-| rddpram_ctl |rddpram_ctl |5 |5 |0 |5 |0 |0 |
-| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
-| u0_rdsoft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
-| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
-| u_data_prebuffer |data_prebuffer |2499 |2063 |253 |1538 |22 |0 |
-| channelPart |channel_part_8478 |133 |130 |3 |122 |0 |0 |
-| fifo_adc |fifo_adc |62 |53 |9 |44 |0 |0 |
-| ram_switch |ram_switch |1994 |1633 |197 |1144 |0 |0 |
-| adc_addr_gen |adc_addr_gen |244 |217 |27 |114 |0 |0 |
-| [0]$ch_addr_gen |ch_addr_gen |8 |5 |3 |4 |0 |0 |
-| [1]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
-| [2]$ch_addr_gen |ch_addr_gen |29 |26 |3 |14 |0 |0 |
-| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
-| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
-| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
-| [6]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
-| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
-| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |9 |0 |0 |
-| insert |insert |953 |620 |170 |654 |0 |0 |
-| ram_switch_state |ram_switch_state |797 |796 |0 |376 |0 |0 |
-| read_ram_i |read_ram |265 |209 |44 |186 |0 |0 |
-| read_ram_addr |read_ram_addr |213 |173 |40 |147 |0 |0 |
-| read_ram_data |read_ram_data |51 |35 |4 |38 |0 |0 |
-| u0_rdsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u_ad_sampling |ad_sampling |180 |137 |17 |133 |0 |0 |
+| u0_soft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_sort |sort |2855 |2346 |289 |1907 |25 |0 |
+| rddpram_ctl |rddpram_ctl |2 |1 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |9 |4 |0 |9 |0 |0 |
+| u0_wrsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2407 |1999 |253 |1544 |22 |0 |
+| channelPart |channel_part_8478 |143 |136 |3 |126 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |41 |0 |0 |
+| ram_switch |ram_switch |1870 |1532 |197 |1149 |0 |0 |
+| adc_addr_gen |adc_addr_gen |247 |220 |27 |123 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |5 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |29 |26 |3 |15 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |31 |28 |3 |17 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |27 |24 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |25 |22 |3 |10 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| insert |insert |965 |654 |170 |661 |0 |0 |
+| ram_switch_state |ram_switch_state |658 |658 |0 |365 |0 |0 |
+| read_ram_i |read_ram |300 |255 |44 |195 |0 |0 |
+| read_ram_addr |read_ram_addr |240 |200 |40 |155 |0 |0 |
+| read_ram_data |read_ram_data |56 |51 |4 |36 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
@@ -1897,42 +1723,41 @@ Report Hierarchy Area:
| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_b_5 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u_transfer_300_to_200 |transfer_300_to_200 |339 |233 |36 |280 |3 |0 |
-| u0_soft_n |cdc_sync |7 |7 |0 |7 |0 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |337 |245 |36 |283 |3 |0 |
+| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
-| sampling_fe_b |sampling_fe_rev |3367 |2648 |349 |2114 |25 |1 |
-| u0_soft_n |cdc_sync |6 |1 |0 |6 |0 |0 |
-| u_ad_sampling |ad_sampling |166 |113 |17 |130 |0 |0 |
-| u0_soft_n |cdc_sync |6 |1 |0 |6 |0 |0 |
-| u_sort |sort_rev |3165 |2522 |332 |1948 |25 |1 |
-| rddpram_ctl |rddpram_ctl_rev |4 |3 |0 |4 |0 |0 |
-| u0_rdsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
-| u0_rdsoft_n |cdc_sync |7 |2 |0 |7 |0 |0 |
-| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
-| u_data_prebuffer_rev |data_prebuffer_rev |2731 |2228 |290 |1587 |22 |1 |
-| channelPart |channel_part_8478 |238 |235 |3 |135 |0 |0 |
-| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
-| ram_switch |ram_switch |1983 |1621 |197 |1142 |0 |0 |
-| adc_addr_gen |adc_addr_gen |221 |194 |27 |105 |0 |0 |
-| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |6 |0 |0 |
-| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
-| [2]$ch_addr_gen |ch_addr_gen |30 |27 |3 |18 |0 |0 |
-| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
-| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
-| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |8 |0 |0 |
-| [6]$ch_addr_gen |ch_addr_gen |21 |18 |3 |10 |0 |0 |
-| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
-| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
-| insert |insert |974 |641 |170 |669 |0 |0 |
-| ram_switch_state |ram_switch_state |788 |786 |0 |368 |0 |0 |
-| read_ram_i |read_ram_rev |424 |303 |81 |240 |0 |0 |
-| read_ram_addr |read_ram_addr_rev |291 |206 |73 |159 |0 |0 |
-| read_ram_data |read_ram_data_rev |133 |97 |8 |81 |0 |0 |
+| sampling_fe_b |sampling_fe_rev |3397 |2743 |349 |2088 |25 |1 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_ad_sampling |ad_sampling |189 |127 |17 |147 |0 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_sort |sort_rev |3178 |2597 |332 |1911 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2741 |2251 |290 |1561 |22 |1 |
+| channelPart |channel_part_8478 |243 |238 |3 |137 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |43 |0 |1 |
+| ram_switch |ram_switch |2023 |1671 |197 |1132 |0 |0 |
+| adc_addr_gen |adc_addr_gen |219 |192 |27 |98 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |19 |16 |3 |6 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| insert |insert |982 |658 |170 |674 |0 |0 |
+| ram_switch_state |ram_switch_state |822 |821 |0 |360 |0 |0 |
+| read_ram_i |read_ram_rev |378 |263 |81 |214 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |311 |226 |73 |165 |0 |0 |
+| read_ram_data |read_ram_data_rev |67 |37 |8 |49 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
@@ -1941,6 +1766,7 @@ Report Hierarchy Area:
| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|...... |...... |- |- |- |- |- |- |
+---------------------------------------------------------------------------------------------------------+
@@ -1948,15 +1774,15 @@ Report Hierarchy Area:
DataNet Average Fanout:
Index Fanout Nets
- #1 1 9824
- #2 2 3937
- #3 3 1458
- #4 4 642
- #5 5-10 1062
- #6 11-50 587
- #7 51-100 24
+ #1 1 9907
+ #2 2 3801
+ #3 3 1374
+ #4 4 579
+ #5 5-10 1189
+ #6 11-50 584
+ #7 51-100 22
#8 >500 1
- Average 2.91
+ Average 2.92
RUN-1002 : start command "export_db hg_anlogic_pr.db"
RUN-1001 : Exported /
@@ -1974,20 +1800,20 @@ RUN-1001 : Exported violations
RUN-1001 : Exported timing constraints
RUN-1001 : Exported IO constraints
RUN-1001 : Exported Inst constraints
-RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.179280s wall, 3.765625s user + 0.015625s system = 3.781250s CPU (173.5%)
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.104425s wall, 3.593750s user + 0.000000s system = 3.593750s CPU (170.8%)
-RUN-1004 : used memory is 1091 MB, reserved memory is 1099 MB, peak memory is 1169 MB
+RUN-1004 : used memory is 1094 MB, reserved memory is 1106 MB, peak memory is 1165 MB
RUN-1002 : start command "start_timer"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74216, tnet num: 17452, tinst num: 6930, tnode num: 96760, tedge num: 124559.
-TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73989, tnet num: 17374, tinst num: 6913, tnode num: 96516, tedge num: 124127.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer" in 1.739411s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (100.6%)
+RUN-1003 : finish command "start_timer" in 1.643211s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (100.8%)
-RUN-1004 : used memory is 1096 MB, reserved memory is 1104 MB, peak memory is 1169 MB
+RUN-1004 : used memory is 1098 MB, reserved memory is 1110 MB, peak memory is 1165 MB
RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
TMR-2503 : Start to update net delay, extr mode = 6.
-TMR-2504 : Update delay of 17452 nets completely.
+TMR-2504 : Update delay of 17374 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 6.
TMR-3001 : Initiate 12 clocks from SDC.
TMR-3004 : Map sdc constraints, there are 6 constraints in total.
@@ -2003,27 +1829,27 @@ TMR-5009 WARNING: No clock constraint on 3 clock net(s):
exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
TMR-3508 : Export timing summary.
TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
-RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.583424s wall, 1.562500s user + 0.015625s system = 1.578125s CPU (99.7%)
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.458982s wall, 1.437500s user + 0.015625s system = 1.453125s CPU (99.6%)
-RUN-1004 : used memory is 1099 MB, reserved memory is 1106 MB, peak memory is 1169 MB
+RUN-1004 : used memory is 1102 MB, reserved memory is 1114 MB, peak memory is 1165 MB
RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
PRG-1000 :
RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
BIT-1003 : Start to generate bitstream.
BIT-1002 : Init instances with 8 threads.
-BIT-1002 : Init instances completely, inst num: 6930
+BIT-1002 : Init instances completely, inst num: 6913
BIT-1002 : Init pips with 8 threads.
-BIT-1002 : Init pips completely, net num: 17630, pip num: 174550
+BIT-1002 : Init pips completely, net num: 17552, pip num: 172527
BIT-1002 : Init feedthrough with 8 threads.
-BIT-1002 : Init feedthrough completely, num: 586
+BIT-1002 : Init feedthrough completely, num: 589
BIT-1003 : Multithreading accelaration with 8 threads.
-BIT-1003 : Generate bitstream completely, there are 3249 valid insts, and 483475 bits set as '1'.
+BIT-1003 : Generate bitstream completely, there are 3249 valid insts, and 479670 bits set as '1'.
BIT-1004 : the usercode register value: 00000000101110110000000000000000
BIT-1004 : PLL setting string = 1011
BIT-1004 : Generate bits file hg_anlogic.bit.
BIT-1004 : Generate bin file hg_anlogic.bin.
-RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.850289s wall, 64.062500s user + 0.187500s system = 64.250000s CPU (652.3%)
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 10.263146s wall, 65.328125s user + 0.125000s system = 65.453125s CPU (637.7%)
-RUN-1004 : used memory is 1267 MB, reserved memory is 1270 MB, peak memory is 1383 MB
-RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240218_161224.log"
+RUN-1004 : used memory is 1265 MB, reserved memory is 1268 MB, peak memory is 1380 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240219_105751.log"
RUN-1001 : Backing up run's log file succeed.
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_gate.begin.f b/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_gate.begin.f
index 1a9c951..8bc5310 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_gate.begin.f
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_gate.begin.f
@@ -1,5 +1,5 @@
-
+
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_rtl.begin.f b/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_rtl.begin.f
index 1a9c951..8bc5310 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_rtl.begin.f
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_rtl.begin.f
@@ -1,5 +1,5 @@
-
+
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/.read_design.begin.f b/src/prj/td_project/hg_anlogic_Runs/syn_1/.read_design.begin.f
index 1a9c951..8bc5310 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/.read_design.begin.f
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/.read_design.begin.f
@@ -1,5 +1,5 @@
-
+
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic.prj b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic.prj
index 3c08349..11cdc57 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic.prj
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic.prj
@@ -1,5 +1,5 @@
-
+
UTF-8
5.6.71036
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db
index 88fcdd3..7de4c54 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db and b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.area b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.area
index a586c41..3727463 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.area
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.area
@@ -8,16 +8,16 @@ IO Statistics
#inout 0
LUT Statistics
-#Total_luts 9995
- #lut4 5129
- #lut5 2311
+#Total_luts 9962
+ #lut4 5231
+ #lut5 2176
#lut6 0
#lut5_mx41 0
#lut4_alu1b 2555
Utilization Statistics
-#lut 9995 out of 19600 50.99%
-#reg 9170 out of 19600 46.79%
+#lut 9962 out of 19600 50.83%
+#reg 9173 out of 19600 46.80%
#le 0
#dsp 3 out of 29 10.34%
#bram 54 out of 64 84.38%
@@ -27,7 +27,7 @@ Utilization Statistics
#dram 16
#pad 75 out of 130 57.69%
#ireg 13
- #oreg 18
+ #oreg 19
#treg 0
#pll 3 out of 4 75.00%
@@ -35,30 +35,30 @@ Report Hierarchy Area:
+-------------------------------------------------------------------------------------------------+
|Instance |Module |lut |ripple |seq |bram |dsp |
+-------------------------------------------------------------------------------------------------+
-|top |huagao_mipi_top |7440 |2555 |9201 |58 |3 |
-| U_rgb_to_csi_pakage |rgb_to_csi_pakage |339 |81 |441 |4 |1 |
-| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 |
+|top |huagao_mipi_top |7407 |2555 |9205 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |342 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 |
| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
| exdev_ctl_a |exdev_ctl |282 |234 |559 |0 |0 |
| u_ADconfig |AD_config |99 |49 |138 |0 |0 |
| u_gen_sp |gen_sp |125 |185 |104 |0 |0 |
-| exdev_ctl_b |exdev_ctl |279 |234 |546 |0 |0 |
+| exdev_ctl_b |exdev_ctl |274 |234 |546 |0 |0 |
| u_ADconfig |AD_config |91 |49 |125 |0 |0 |
-| u_gen_sp |gen_sp |130 |185 |104 |0 |0 |
-| sampling_fe_a |sampling_fe |2067 |738 |1894 |25 |0 |
+| u_gen_sp |gen_sp |125 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2317 |738 |1919 |25 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
-| u_sort |sort |1997 |691 |1712 |25 |0 |
+| u_sort |sort |2247 |691 |1737 |25 |0 |
| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
-| u_data_prebuffer |data_prebuffer |1868 |615 |1391 |22 |0 |
-| channelPart |channel_part_8478 |147 |11 |144 |0 |0 |
+| u_data_prebuffer |data_prebuffer |1906 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
-| ram_switch |ram_switch |1448 |422 |1023 |0 |0 |
+| ram_switch |ram_switch |1466 |422 |1023 |0 |0 |
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
@@ -70,10 +70,10 @@ Report Hierarchy Area:
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| insert |insert |265 |323 |692 |0 |0 |
-| ram_switch_state |ram_switch_state |1054 |0 |216 |0 |0 |
-| read_ram_i |read_ram |186 |158 |164 |0 |0 |
-| read_ram_addr |read_ram_addr |158 |145 |127 |0 |0 |
-| read_ram_data |read_ram_data |27 |13 |32 |0 |0 |
+| ram_switch_state |ram_switch_state |1072 |0 |216 |0 |0 |
+| read_ram_i |read_ram |207 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |177 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |29 |13 |32 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
@@ -97,22 +97,22 @@ Report Hierarchy Area:
| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
-| u_transfer_300_to_200 |transfer_300_to_200 |122 |76 |276 |3 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
-| sampling_fe_b |sampling_fe_rev |2261 |751 |1958 |25 |1 |
+| sampling_fe_b |sampling_fe_rev |2335 |751 |1936 |25 |1 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
-| u_sort |sort_rev |2191 |704 |1776 |25 |1 |
+| u_sort |sort_rev |2265 |704 |1754 |25 |1 |
| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
-| u_data_prebuffer_rev |data_prebuffer_rev |2066 |628 |1405 |22 |1 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1924 |628 |1408 |22 |1 |
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
-| ram_switch |ram_switch |1441 |422 |1023 |0 |0 |
+| ram_switch |ram_switch |1479 |422 |1023 |0 |0 |
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
@@ -124,10 +124,10 @@ Report Hierarchy Area:
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| insert |insert |265 |323 |692 |0 |0 |
-| ram_switch_state |ram_switch_state |1047 |0 |216 |0 |0 |
-| read_ram_i |read_ram_rev |390 |171 |178 |0 |0 |
-| read_ram_addr |read_ram_addr_rev |176 |145 |136 |0 |0 |
-| read_ram_data |read_ram_data_rev |214 |26 |42 |0 |0 |
+| ram_switch_state |ram_switch_state |1085 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |210 |171 |181 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |181 |145 |139 |0 |0 |
+| read_ram_data |read_ram_data_rev |29 |26 |42 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
@@ -150,7 +150,7 @@ Report Hierarchy Area:
| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
-| u_transfer_300_to_200 |transfer_300_to_200 |120 |76 |276 |3 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
| scan_start_diff |scan_start_diff |30 |0 |12 |0 |0 |
@@ -165,16 +165,16 @@ Report Hierarchy Area:
| u_b_sp_sampling |cdc_sync |1 |0 |5 |0 |0 |
| u_b_sp_sampling_cam |cdc_sync |1 |0 |5 |0 |0 |
| u_b_sp_sampling_last |cdc_sync |1 |0 |5 |0 |0 |
-| u_bus_top |ubus_top |826 |50 |1248 |0 |0 |
-| u_local_bus_slve_cis |local_bus_slve_cis |732 |50 |721 |0 |0 |
-| u_uart_2dsp |uart_2dsp |119 |31 |52 |0 |0 |
+| u_bus_top |ubus_top |805 |50 |1248 |0 |0 |
+| u_local_bus_slve_cis |local_bus_slve_cis |711 |50 |721 |0 |0 |
+| u_uart_2dsp |uart_2dsp |115 |31 |52 |0 |0 |
| u_dpi_mode |cdc_sync |2 |0 |10 |0 |0 |
| u_eot |cdc_sync |1 |0 |5 |0 |0 |
| u_lv_en_flag |cdc_sync |1 |0 |5 |0 |0 |
-| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |170 |61 |226 |4 |0 |
-| u_hs_tx_wrapper |hs_tx_wrapper |111 |61 |198 |4 |0 |
-| [0]$u_data_lane_wrapper |data_lane_wrapper |54 |52 |93 |1 |0 |
-| u_data_hs_generate |data_hs_generate |50 |52 |87 |1 |0 |
+| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |166 |61 |226 |4 |0 |
+| u_hs_tx_wrapper |hs_tx_wrapper |110 |61 |198 |4 |0 |
+| [0]$u_data_lane_wrapper |data_lane_wrapper |52 |52 |93 |1 |0 |
+| u_data_hs_generate |data_hs_generate |48 |52 |87 |1 |0 |
| u_dphy_tx_fifo |dphy_tx_fifo |2 |0 |0 |1 |0 |
| u_d1024_w8_fifo |d1024_w8_fifo |2 |0 |0 |1 |0 |
| u_data_lp_generate |data_lp_generate |4 |0 |6 |0 |0 |
@@ -193,7 +193,7 @@ Report Hierarchy Area:
| u_clk_lane_wrapper |clk_lane_wrapper |3 |0 |8 |0 |0 |
| u_clk_hs_generate |clk_hs_generate |3 |0 |4 |0 |0 |
| u_clk_lp_generate |clk_lp_generate |0 |0 |4 |0 |0 |
-| u_hs_tx_controler |hs_tx_controler |24 |9 |12 |0 |0 |
+| u_hs_tx_controler |hs_tx_controler |25 |9 |12 |0 |0 |
| u_mipi_eot_min |cdc_sync |20 |0 |65 |0 |0 |
| u_mipi_sot_min |cdc_sync |20 |0 |65 |0 |0 |
| u_pic_cnt |cdc_sync |38 |0 |120 |0 |0 |
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.db b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.db
index e433079..5cf4c66 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.db and b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.db differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.area b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.area
index fc61d5a..149becf 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.area
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.area
@@ -8,8 +8,8 @@ IO Statistics
#inout 0
Gate Statistics
-#Basic gates 13930
- #and 2463
+#Basic gates 13950
+ #and 2480
#nand 0
#or 1078
#nor 0
@@ -20,19 +20,19 @@ Gate Statistics
#bufif1 5
#MX21 615
#FADD 0
- #DFF 9090
+ #DFF 9093
#LATCH 6
-#MACRO_ADD 496
+#MACRO_ADD 497
#MACRO_EQ 225
#MACRO_MULT 4
-#MACRO_MUX 4819
+#MACRO_MUX 4813
#MACRO_OTHERS 73
Report Hierarchy Area:
+----------------------------------------------------------------------------+
|Instance |Module |gates |seq |macros |
+----------------------------------------------------------------------------+
-|top |huagao_mipi_top |4834 |9096 |798 |
+|top |huagao_mipi_top |4851 |9099 |799 |
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
| U_crc16_24b |crc16_24b |67 |16 |0 |
| U_ecc_gen |ecc_gen |37 |6 |0 |
@@ -43,16 +43,16 @@ Report Hierarchy Area:
| exdev_ctl_b |exdev_ctl |158 |546 |41 |
| u_ADconfig |AD_config |81 |125 |18 |
| u_gen_sp |gen_sp |76 |104 |19 |
-| sampling_fe_a |sampling_fe |1838 |1894 |269 |
+| sampling_fe_a |sampling_fe |1847 |1919 |269 |
| u0_soft_n |cdc_sync |2 |5 |0 |
| u_ad_sampling |ad_sampling |40 |147 |10 |
| u0_soft_n |cdc_sync |2 |5 |0 |
-| u_sort |sort |1794 |1712 |258 |
+| u_sort |sort |1803 |1737 |258 |
| rddpram_ctl |rddpram_ctl |2 |5 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_wrsoft_n |cdc_sync |2 |5 |0 |
-| u_data_prebuffer |data_prebuffer |1539 |1391 |118 |
+| u_data_prebuffer |data_prebuffer |1548 |1391 |118 |
| channelPart |channel_part_8478 |865 |144 |8 |
| fifo_adc |fifo_adc |112 |41 |4 |
| ram_switch |ram_switch |60 |1023 |52 |
@@ -72,9 +72,9 @@ Report Hierarchy Area:
| mux_addr |mux_e |0 |0 |0 |
| mux_data |mux_e |0 |0 |0 |
| mux_valid |mux_e |0 |0 |0 |
-| read_ram_i |read_ram |112 |164 |32 |
-| read_ram_addr |read_ram_addr |64 |127 |22 |
-| read_ram_data |read_ram_data |46 |32 |10 |
+| read_ram_i |read_ram |121 |164 |32 |
+| read_ram_addr |read_ram_addr |69 |127 |22 |
+| read_ram_data |read_ram_data |50 |32 |10 |
| mux_i |mux_i |0 |0 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
@@ -102,16 +102,16 @@ Report Hierarchy Area:
| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
| u0_soft_n |cdc_sync |2 |5 |0 |
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
-| sampling_fe_b |sampling_fe_rev |1799 |1958 |267 |
+| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 |
| u0_soft_n |cdc_sync |2 |5 |0 |
| u_ad_sampling |ad_sampling |39 |147 |9 |
| u0_soft_n |cdc_sync |2 |5 |0 |
-| u_sort |sort_rev |1757 |1776 |257 |
+| u_sort |sort_rev |1765 |1754 |258 |
| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_wrsoft_n |cdc_sync |2 |5 |0 |
-| u_data_prebuffer_rev |data_prebuffer_rev |1503 |1405 |118 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 |
| channelPart |channel_part_8478 |865 |144 |8 |
| fifo_adc |fifo_adc |112 |41 |4 |
| ram_switch |ram_switch |60 |1023 |52 |
@@ -131,9 +131,9 @@ Report Hierarchy Area:
| mux_addr |mux_e |0 |0 |0 |
| mux_data |mux_e |0 |0 |0 |
| mux_valid |mux_e |0 |0 |0 |
-| read_ram_i |read_ram_rev |82 |178 |32 |
-| read_ram_addr |read_ram_addr_rev |50 |136 |22 |
-| read_ram_data |read_ram_data_rev |32 |42 |10 |
+| read_ram_i |read_ram_rev |90 |181 |33 |
+| read_ram_addr |read_ram_addr_rev |56 |139 |23 |
+| read_ram_data |read_ram_data_rev |34 |42 |10 |
| mux_i |mux_i |0 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db
index dbf23a3..a1308c1 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db and b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/run.log b/src/prj/td_project/hg_anlogic_Runs/syn_1/run.log
index fccedda..ea888d7 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/run.log
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/run.log
@@ -4,7 +4,7 @@
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
Built at = 20:34:38 Mar 21 2023
Run by = holdtecs
- Run Date = Sun Feb 18 16:10:55 2024
+ Run Date = Mon Feb 19 10:56:25 2024
Run on = DESKTOP-5MQL5VE
============================================================
@@ -86,7 +86,7 @@ HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
-HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
@@ -163,27 +163,27 @@ HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
-HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
-HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
-HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
-HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
-HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
-HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
-HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
-HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
-HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
-HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
-HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
-HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
@@ -310,14 +310,14 @@ HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../
HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
-HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
-HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
-HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
-HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
-HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
-HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
-HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(192)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
@@ -345,11 +345,11 @@ HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF
HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
-HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(36)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
-HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
@@ -362,18 +362,18 @@ HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_m
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
-HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
-HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
-HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
-HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
-HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(194)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
-HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(38)
-HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
@@ -422,9 +422,9 @@ HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been re
HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
HDL-1200 : Current top model is huagao_mipi_top
HDL-1100 : Inferred 1 RAMs.
-RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.135611s wall, 1.109375s user + 0.015625s system = 1.125000s CPU (99.1%)
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.112400s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.7%)
-RUN-1004 : used memory is 193 MB, reserved memory is 171 MB, peak memory is 233 MB
+RUN-1004 : used memory is 193 MB, reserved memory is 171 MB, peak memory is 234 MB
RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
RUN-1001 : Exported /
RUN-1001 : Exported flow parameters
@@ -456,28 +456,28 @@ RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; I
RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
-RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
-RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
-RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
@@ -499,6 +499,7 @@ RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy
RUN-1001 : Starting of IO setups legality check.
RUN-1001 : Starting of IO setups legality check.
RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
@@ -508,7 +509,6 @@ USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
-USR-6010 WARNING: ADC constraints: top model pin scan_out has no constraint.
USR-6010 Similar messages will be suppressed.
RUN-1002 : start command "optimize_rtl"
RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
@@ -654,14 +654,14 @@ RUN-1001 : ub_lvds_rx | false | lvds_rx |
RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
RUN-1001 : ------------------------------------------------------------------------------------------------
-SYN-1032 : 53810/19109 useful/useless nets, 20666/1812 useful/useless insts
+SYN-1032 : 53909/19207 useful/useless nets, 20692/1826 useful/useless insts
SYN-1001 : Optimize 156 less-than instances
SYN-1016 : Merged 38313 instances.
SYN-1025 : Merged 24 RAM ports.
SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
-SYN-1032 : 42352/8970 useful/useless nets, 10953/4743 useful/useless insts
+SYN-1032 : 42440/8976 useful/useless nets, 10974/4743 useful/useless insts
SYN-1016 : Merged 1876 instances.
SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
@@ -672,7 +672,7 @@ SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfi
SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
-SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(283) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
@@ -1173,7 +1173,7 @@ SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16
SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
SYN-5014 Similar messages will be suppressed.
SYN-5025 WARNING: Using 0 for all undriven pins and nets
-SYN-1032 : 40025/363 useful/useless nets, 37222/552 useful/useless insts
+SYN-1032 : 40113/363 useful/useless nets, 37310/558 useful/useless insts
SYN-1014 : Optimize round 1
SYN-1017 : Remove 16 const input seq instances
SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
@@ -1195,14 +1195,14 @@ SYN-1002 : reg17_syn_2
SYN-1018 : Transformed 91 mux instances.
SYN-1019 : Optimized 127 mux instances.
SYN-1021 : Optimized 297 onehot mux instances.
-SYN-1020 : Optimized 3817 distributor mux.
+SYN-1020 : Optimized 3951 distributor mux.
SYN-1001 : Optimize 12 less-than instances
SYN-1019 : Optimized 39 mux instances.
-SYN-1016 : Merged 6180 instances.
-SYN-1015 : Optimize round 1, 29670 better
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29880 better
SYN-1014 : Optimize round 2
SYN-1044 : Optimized 15 inv instances.
-SYN-1032 : 25763/1547 useful/useless nets, 23052/7489 useful/useless insts
+SYN-1032 : 25775/1547 useful/useless nets, 23064/7583 useful/useless insts
SYN-1017 : Remove 29 const input seq instances
SYN-1002 : reg18_syn_2
SYN-1002 : reg22_syn_2
@@ -1235,13 +1235,10 @@ SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
SYN-1019 : Optimized 24 mux instances.
SYN-1020 : Optimized 43 distributor mux.
-SYN-1016 : Merged 117 instances.
-SYN-1015 : Optimize round 2, 9332 better
-SYN-1032 : 25515/80 useful/useless nets, 22836/112 useful/useless insts
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25526/80 useful/useless nets, 22847/112 useful/useless insts
SYN-3004 : Optimized 2 const0 DFF(s)
-SYN-3003 : Optimized 1 equivalent DFF(s)
-SYN-3003 : Optimized 1 equivalent DFF(s)
-SYN-3003 : Optimized 1 equivalent DFF(s)
SYN-3004 : Optimized 8 const0 DFF(s)
SYN-3008 : Optimized 1 const1 DFF(s)
SYN-3004 : Optimized 1 const0 DFF(s)
@@ -1307,20 +1304,20 @@ SYN-3003 : Optimized 1 equivalent DFF(s)
SYN-3003 : Optimized 1 equivalent DFF(s)
SYN-3003 : Optimized 1 equivalent DFF(s)
SYN-3004 : Optimized 2 const0 DFF(s)
-SYN-1032 : 25416/99 useful/useless nets, 22750/7 useful/useless insts
+SYN-1032 : 25433/93 useful/useless nets, 22765/6 useful/useless insts
SYN-1014 : Optimize round 1
SYN-1019 : Optimized 228 mux instances.
SYN-1020 : Optimized 2 distributor mux.
SYN-1016 : Merged 3 instances.
SYN-1015 : Optimize round 1, 279 better
SYN-1014 : Optimize round 2
-SYN-1032 : 25138/20 useful/useless nets, 22488/2 useful/useless insts
+SYN-1032 : 25155/20 useful/useless nets, 22503/2 useful/useless insts
SYN-1015 : Optimize round 2, 2 better
SYN-1014 : Optimize round 3
SYN-1015 : Optimize round 3, 0 better
-RUN-1003 : finish command "optimize_rtl" in 19.412269s wall, 17.515625s user + 1.875000s system = 19.390625s CPU (99.9%)
+RUN-1003 : finish command "optimize_rtl" in 18.908404s wall, 16.984375s user + 1.906250s system = 18.890625s CPU (99.9%)
-RUN-1004 : used memory is 330 MB, reserved memory is 302 MB, peak memory is 350 MB
+RUN-1004 : used memory is 331 MB, reserved memory is 303 MB, peak memory is 349 MB
RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
RUN-1001 : standard
***Report Model: huagao_mipi_top Device: EG4D20EG176***
@@ -1332,8 +1329,8 @@ IO Statistics
#inout 0
Gate Statistics
-#Basic gates 13930
- #and 2463
+#Basic gates 13950
+ #and 2480
#nand 0
#or 1078
#nor 0
@@ -1344,19 +1341,19 @@ Gate Statistics
#bufif1 5
#MX21 615
#FADD 0
- #DFF 9090
+ #DFF 9093
#LATCH 6
-#MACRO_ADD 496
+#MACRO_ADD 497
#MACRO_EQ 225
#MACRO_MULT 4
-#MACRO_MUX 4819
+#MACRO_MUX 4813
#MACRO_OTHERS 73
Report Hierarchy Area:
+----------------------------------------------------------------------------+
|Instance |Module |gates |seq |macros |
+----------------------------------------------------------------------------+
-|top |huagao_mipi_top |4834 |9096 |798 |
+|top |huagao_mipi_top |4851 |9099 |799 |
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
| U_crc16_24b |crc16_24b |67 |16 |0 |
| U_ecc_gen |ecc_gen |37 |6 |0 |
@@ -1367,16 +1364,16 @@ Report Hierarchy Area:
| exdev_ctl_b |exdev_ctl |158 |546 |41 |
| u_ADconfig |AD_config |81 |125 |18 |
| u_gen_sp |gen_sp |76 |104 |19 |
-| sampling_fe_a |sampling_fe |1838 |1894 |269 |
+| sampling_fe_a |sampling_fe |1847 |1919 |269 |
| u0_soft_n |cdc_sync |2 |5 |0 |
| u_ad_sampling |ad_sampling |40 |147 |10 |
| u0_soft_n |cdc_sync |2 |5 |0 |
-| u_sort |sort |1794 |1712 |258 |
+| u_sort |sort |1803 |1737 |258 |
| rddpram_ctl |rddpram_ctl |2 |5 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_wrsoft_n |cdc_sync |2 |5 |0 |
-| u_data_prebuffer |data_prebuffer |1539 |1391 |118 |
+| u_data_prebuffer |data_prebuffer |1548 |1391 |118 |
| channelPart |channel_part_8478 |865 |144 |8 |
| fifo_adc |fifo_adc |112 |41 |4 |
| ram_switch |ram_switch |60 |1023 |52 |
@@ -1396,9 +1393,9 @@ Report Hierarchy Area:
| mux_addr |mux_e |0 |0 |0 |
| mux_data |mux_e |0 |0 |0 |
| mux_valid |mux_e |0 |0 |0 |
-| read_ram_i |read_ram |112 |164 |32 |
-| read_ram_addr |read_ram_addr |64 |127 |22 |
-| read_ram_data |read_ram_data |46 |32 |10 |
+| read_ram_i |read_ram |121 |164 |32 |
+| read_ram_addr |read_ram_addr |69 |127 |22 |
+| read_ram_data |read_ram_data |50 |32 |10 |
| mux_i |mux_i |0 |0 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
@@ -1426,16 +1423,16 @@ Report Hierarchy Area:
| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
| u0_soft_n |cdc_sync |2 |5 |0 |
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
-| sampling_fe_b |sampling_fe_rev |1799 |1958 |267 |
+| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 |
| u0_soft_n |cdc_sync |2 |5 |0 |
| u_ad_sampling |ad_sampling |39 |147 |9 |
| u0_soft_n |cdc_sync |2 |5 |0 |
-| u_sort |sort_rev |1757 |1776 |257 |
+| u_sort |sort_rev |1765 |1754 |258 |
| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_wrsoft_n |cdc_sync |2 |5 |0 |
-| u_data_prebuffer_rev |data_prebuffer_rev |1503 |1405 |118 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 |
| channelPart |channel_part_8478 |865 |144 |8 |
| fifo_adc |fifo_adc |112 |41 |4 |
| ram_switch |ram_switch |60 |1023 |52 |
@@ -1455,8 +1452,8 @@ Report Hierarchy Area:
| mux_addr |mux_e |0 |0 |0 |
| mux_data |mux_e |0 |0 |0 |
| mux_valid |mux_e |0 |0 |0 |
-| read_ram_i |read_ram_rev |82 |178 |32 |
-| read_ram_addr |read_ram_addr_rev |50 |136 |22 |
+| read_ram_i |read_ram_rev |90 |181 |33 |
+| read_ram_addr |read_ram_addr_rev |56 |139 |23 |
|...... |...... |- |- |- |
+----------------------------------------------------------------------------+
@@ -1475,9 +1472,9 @@ RUN-1001 : Exported congestions
RUN-1001 : Exported violations
RUN-1001 : Exported IO constraints
RUN-1001 : Exported Inst constraints
-RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.150280s wall, 1.781250s user + 0.015625s system = 1.796875s CPU (156.2%)
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.053069s wall, 1.656250s user + 0.078125s system = 1.734375s CPU (164.7%)
-RUN-1004 : used memory is 339 MB, reserved memory is 312 MB, peak memory is 399 MB
+RUN-1004 : used memory is 326 MB, reserved memory is 301 MB, peak memory is 399 MB
RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
RUN-1002 : start command "get_ports clock_source"
RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
@@ -1567,7 +1564,7 @@ RUN-1001 : report | standard | standard |
RUN-1001 : retiming | off | off |
RUN-1001 : ------------------------------------------------------------------
SYN-2001 : Map 61 IOs to PADs
-SYN-1032 : 25172/24 useful/useless nets, 22537/26 useful/useless insts
+SYN-1032 : 25189/24 useful/useless nets, 22552/26 useful/useless insts
RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
SYN-2501 : Processed 0 LOGIC_BUF instances.
SYN-2501 : 3 BUFG to GCLK
@@ -1631,20 +1628,20 @@ SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
SYN-2571 : Map 4 macro multiplier
SYN-2571 : Optimize after map_dsp, round 1
-SYN-1032 : 25490/670 useful/useless nets, 22871/580 useful/useless insts
+SYN-1032 : 25507/670 useful/useless nets, 22886/580 useful/useless insts
SYN-1016 : Merged 11 instances.
SYN-2571 : Optimize after map_dsp, round 1, 1181 better
SYN-2571 : Optimize after map_dsp, round 2
SYN-2571 : Optimize after map_dsp, round 2, 0 better
-SYN-1001 : Throwback 313 control mux instances
+SYN-1001 : Throwback 317 control mux instances
SYN-1001 : Convert 12 adder
SYN-2501 : Optimize round 1
-SYN-1032 : 28922/338 useful/useless nets, 26304/38 useful/useless insts
+SYN-1032 : 28943/338 useful/useless nets, 26323/38 useful/useless insts
SYN-1016 : Merged 396 instances.
SYN-2501 : Optimize round 1, 1774 better
SYN-2501 : Optimize round 2
SYN-2501 : Optimize round 2, 0 better
-SYN-2501 : Map 497 macro adder
+SYN-2501 : Map 498 macro adder
SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
@@ -1669,18 +1666,18 @@ SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
SYN-2501 : Inferred 22 ROM instances
SYN-1019 : Optimized 9690 mux instances.
-SYN-1016 : Merged 12104 instances.
-SYN-1032 : 36464/295 useful/useless nets, 33740/0 useful/useless insts
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36487/296 useful/useless nets, 33761/0 useful/useless insts
RUN-1002 : start command "start_timer -prepack"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121620, tnet num: 36466, tinst num: 33740, tnode num: 155576, tedge num: 179063.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121685, tnet num: 36489, tinst num: 33761, tnode num: 155649, tedge num: 179150.
TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -prepack" in 1.483913s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (99.0%)
+RUN-1003 : finish command "start_timer -prepack" in 1.303515s wall, 1.281250s user + 0.031250s system = 1.312500s CPU (100.7%)
-RUN-1004 : used memory is 518 MB, reserved memory is 495 MB, peak memory is 518 MB
+RUN-1004 : used memory is 517 MB, reserved memory is 495 MB, peak memory is 517 MB
TMR-2503 : Start to update net delay, extr mode = 2.
-TMR-2504 : Update delay of 36466 nets completely.
+TMR-2504 : Update delay of 36489 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 2.
TMR-3001 : Initiate 12 clocks from SDC.
TMR-3004 : Map sdc constraints, there are 6 constraints in total.
@@ -1689,11 +1686,11 @@ TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
SYN-3001 : Running gate level optimization.
-SYN-2581 : Mapping with K=5, #lut = 7519 (3.86), #lev = 10 (3.15)
+SYN-2581 : Mapping with K=5, #lut = 7497 (3.86), #lev = 10 (3.14)
SYN-2551 : Post LUT mapping optimization.
-SYN-2581 : Mapping with K=5, #lut = 7392 (3.95), #lev = 8 (3.06)
-SYN-3001 : Logic optimization runtime opt = 1.35 sec, map = 0.00 sec
-SYN-3001 : Mapper mapped 18898 instances into 7420 LUTs, name keeping = 59%.
+SYN-2581 : Mapping with K=5, #lut = 7359 (3.96), #lev = 7 (3.05)
+SYN-3001 : Logic optimization runtime opt = 1.20 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 18916 instances into 7387 LUTs, name keeping = 58%.
SYN-3001 : Mapper removed 2 lut buffers
RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
RUN-1001 : standard
@@ -1706,16 +1703,16 @@ IO Statistics
#inout 0
LUT Statistics
-#Total_luts 9995
- #lut4 5129
- #lut5 2311
+#Total_luts 9962
+ #lut4 5231
+ #lut5 2176
#lut6 0
#lut5_mx41 0
#lut4_alu1b 2555
Utilization Statistics
-#lut 9995 out of 19600 50.99%
-#reg 9170 out of 19600 46.79%
+#lut 9962 out of 19600 50.83%
+#reg 9173 out of 19600 46.80%
#le 0
#dsp 3 out of 29 10.34%
#bram 54 out of 64 84.38%
@@ -1725,7 +1722,7 @@ Utilization Statistics
#dram 16
#pad 75 out of 130 57.69%
#ireg 13
- #oreg 18
+ #oreg 19
#treg 0
#pll 3 out of 4 75.00%
@@ -1733,30 +1730,30 @@ Report Hierarchy Area:
+-------------------------------------------------------------------------------------------------+
|Instance |Module |lut |ripple |seq |bram |dsp |
+-------------------------------------------------------------------------------------------------+
-|top |huagao_mipi_top |7440 |2555 |9201 |58 |3 |
-| U_rgb_to_csi_pakage |rgb_to_csi_pakage |339 |81 |441 |4 |1 |
-| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 |
+|top |huagao_mipi_top |7407 |2555 |9205 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |342 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 |
| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
| exdev_ctl_a |exdev_ctl |282 |234 |559 |0 |0 |
| u_ADconfig |AD_config |99 |49 |138 |0 |0 |
| u_gen_sp |gen_sp |125 |185 |104 |0 |0 |
-| exdev_ctl_b |exdev_ctl |279 |234 |546 |0 |0 |
+| exdev_ctl_b |exdev_ctl |274 |234 |546 |0 |0 |
| u_ADconfig |AD_config |91 |49 |125 |0 |0 |
-| u_gen_sp |gen_sp |130 |185 |104 |0 |0 |
-| sampling_fe_a |sampling_fe |2067 |738 |1894 |25 |0 |
+| u_gen_sp |gen_sp |125 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2317 |738 |1919 |25 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
-| u_sort |sort |1997 |691 |1712 |25 |0 |
+| u_sort |sort |2247 |691 |1737 |25 |0 |
| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
-| u_data_prebuffer |data_prebuffer |1868 |615 |1391 |22 |0 |
-| channelPart |channel_part_8478 |147 |11 |144 |0 |0 |
+| u_data_prebuffer |data_prebuffer |1906 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
-| ram_switch |ram_switch |1448 |422 |1023 |0 |0 |
+| ram_switch |ram_switch |1466 |422 |1023 |0 |0 |
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
@@ -1768,10 +1765,10 @@ Report Hierarchy Area:
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| insert |insert |265 |323 |692 |0 |0 |
-| ram_switch_state |ram_switch_state |1054 |0 |216 |0 |0 |
-| read_ram_i |read_ram |186 |158 |164 |0 |0 |
-| read_ram_addr |read_ram_addr |158 |145 |127 |0 |0 |
-| read_ram_data |read_ram_data |27 |13 |32 |0 |0 |
+| ram_switch_state |ram_switch_state |1072 |0 |216 |0 |0 |
+| read_ram_i |read_ram |207 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |177 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |29 |13 |32 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
@@ -1795,22 +1792,22 @@ Report Hierarchy Area:
| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
-| u_transfer_300_to_200 |transfer_300_to_200 |122 |76 |276 |3 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
-| sampling_fe_b |sampling_fe_rev |2261 |751 |1958 |25 |1 |
+| sampling_fe_b |sampling_fe_rev |2335 |751 |1936 |25 |1 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
-| u_sort |sort_rev |2191 |704 |1776 |25 |1 |
+| u_sort |sort_rev |2265 |704 |1754 |25 |1 |
| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
-| u_data_prebuffer_rev |data_prebuffer_rev |2066 |628 |1405 |22 |1 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1924 |628 |1408 |22 |1 |
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
-| ram_switch |ram_switch |1441 |422 |1023 |0 |0 |
+| ram_switch |ram_switch |1479 |422 |1023 |0 |0 |
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
@@ -1822,10 +1819,10 @@ Report Hierarchy Area:
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| insert |insert |265 |323 |692 |0 |0 |
-| ram_switch_state |ram_switch_state |1047 |0 |216 |0 |0 |
-| read_ram_i |read_ram_rev |390 |171 |178 |0 |0 |
-| read_ram_addr |read_ram_addr_rev |176 |145 |136 |0 |0 |
-| read_ram_data |read_ram_data_rev |214 |26 |42 |0 |0 |
+| ram_switch_state |ram_switch_state |1085 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |210 |171 |181 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |181 |145 |139 |0 |0 |
+| read_ram_data |read_ram_data_rev |29 |26 |42 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
@@ -1841,7 +1838,7 @@ SYN-1001 : Packing model "huagao_mipi_top" ...
SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
SYN-1014 : Optimize round 1
SYN-1015 : Optimize round 1, 0 better
-SYN-4002 : Packing 9170 DFF/LATCH to SEQ ...
+SYN-4002 : Packing 9173 DFF/LATCH to SEQ ...
SYN-4009 : Pack 83 carry chain into lslice
SYN-4007 : Packing 1278 adder to BLE ...
SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
@@ -1849,9 +1846,9 @@ SYN-4007 : Packing 0 gate4 to BLE ...
SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
SYN-4012 : Packed 0 FxMUX
SYN-4013 : Packed 16 DRAM and 4 SEQ.
-RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 63.896196s wall, 63.531250s user + 0.296875s system = 63.828125s CPU (99.9%)
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 61.071613s wall, 60.671875s user + 0.375000s system = 61.046875s CPU (100.0%)
-RUN-1004 : used memory is 395 MB, reserved memory is 386 MB, peak memory is 698 MB
+RUN-1004 : used memory is 394 MB, reserved memory is 379 MB, peak memory is 699 MB
RUN-1002 : start command "legalize_phy_inst"
SYN-1011 : Flatten model huagao_mipi_top
SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
@@ -1871,8 +1868,8 @@ RUN-1001 : Exported violations
RUN-1001 : Exported timing constraints
RUN-1001 : Exported IO constraints
RUN-1001 : Exported Inst constraints
-RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.634628s wall, 2.843750s user + 0.031250s system = 2.875000s CPU (175.9%)
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.555646s wall, 2.687500s user + 0.031250s system = 2.718750s CPU (174.8%)
-RUN-1004 : used memory is 401 MB, reserved memory is 385 MB, peak memory is 698 MB
-RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240218_161055.log"
+RUN-1004 : used memory is 403 MB, reserved memory is 384 MB, peak memory is 699 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240219_105625.log"
RUN-1001 : Backing up run's log file succeed.
diff --git a/src/prj/td_project/td_2024-02-18_15-33-24.log b/src/prj/td_project/td_2024-02-18_15-33-24.log
index e69de29..6408f58 100644
--- a/src/prj/td_project/td_2024-02-18_15-33-24.log
+++ b/src/prj/td_project/td_2024-02-18_15-33-24.log
@@ -0,0 +1,249 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sun Feb 18 15:33:24 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.633929s wall, 0.093750s user + 0.328125s system = 0.421875s CPU (2.4%)
+
+RUN-1004 : used memory is 216 MB, reserved memory is 154 MB, peak memory is 248 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.851310s wall, 0.187500s user + 0.359375s system = 0.546875s CPU (3.1%)
+
+RUN-1004 : used memory is 216 MB, reserved memory is 154 MB, peak memory is 248 MB
+GUI-1001 : Downloading succeeded!
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-6001 WARNING: Failed to reset phy_1: some files can't be removed in D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : stop_run syn_1.
+RUN-1001 : reset_run syn_1 -step opt_rtl.
+RUN-1001 : syn_1: run complete.
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 586 feed throughs used by 421 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 12.298790s wall, 12.000000s user + 0.531250s system = 12.531250s CPU (101.9%)
+
+RUN-1004 : used memory is 971 MB, reserved memory is 936 MB, peak memory is 980 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode program_spi -v -spd 7 -sec 64 -cable 0 -flashsize 128"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+PRG-1001 : SPI Flash ID is: ef
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m program_spi -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1003 : finish command "bit_to_vec -chip EAGLE_S20_EG176 -m program_spi -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit" in 1.749765s wall, 1.640625s user + 0.125000s system = 1.765625s CPU (100.9%)
+
+RUN-1004 : used memory is 1325 MB, reserved memory is 1289 MB, peak memory is 1337 MB
+RUN-1002 : start command "program_spi -cable 0 -spd 7"
+RUN-1003 : finish command "program_spi -cable 0 -spd 7" in 109.791801s wall, 3.875000s user + 2.125000s system = 6.000000s CPU (5.5%)
+
+RUN-1004 : used memory is 1326 MB, reserved memory is 1289 MB, peak memory is 1337 MB
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m verify_spi -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -spd 4"
+RUN-1003 : finish command "program -cable 0 -spd 4" in 23.103374s wall, 0.359375s user + 0.625000s system = 0.984375s CPU (4.3%)
+
+RUN-1004 : used memory is 1115 MB, reserved memory is 1079 MB, peak memory is 1337 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode program_spi -v -spd 7 -sec 64 -cable 0 -flashsize 128" in 138.788588s wall, 7.625000s user + 2.968750s system = 10.593750s CPU (7.6%)
+
+RUN-1004 : used memory is 1115 MB, reserved memory is 1079 MB, peak memory is 1337 MB
+GUI-1001 : Downloading succeeded!
+TMR-3509 : Import timing summary.
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 580 feed throughs used by 430 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 9.264628s wall, 9.171875s user + 0.406250s system = 9.578125s CPU (103.4%)
+
+RUN-1004 : used memory is 1195 MB, reserved memory is 1169 MB, peak memory is 1337 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.579945s wall, 0.125000s user + 0.156250s system = 0.281250s CPU (1.6%)
+
+RUN-1004 : used memory is 1201 MB, reserved memory is 1172 MB, peak memory is 1337 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.791400s wall, 0.250000s user + 0.156250s system = 0.406250s CPU (2.3%)
+
+RUN-1004 : used memory is 1201 MB, reserved memory is 1172 MB, peak memory is 1337 MB
+GUI-1001 : Downloading succeeded!
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.603010s wall, 0.203125s user + 0.421875s system = 0.625000s CPU (3.6%)
+
+RUN-1004 : used memory is 1196 MB, reserved memory is 1168 MB, peak memory is 1337 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.817724s wall, 0.343750s user + 0.437500s system = 0.781250s CPU (4.4%)
+
+RUN-1004 : used memory is 1196 MB, reserved memory is 1168 MB, peak memory is 1337 MB
+GUI-1001 : Downloading succeeded!
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 586 feed throughs used by 421 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 9.434136s wall, 9.281250s user + 0.359375s system = 9.640625s CPU (102.2%)
+
+RUN-1004 : used memory is 1226 MB, reserved memory is 1202 MB, peak memory is 1337 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.566477s wall, 0.250000s user + 0.328125s system = 0.578125s CPU (3.3%)
+
+RUN-1004 : used memory is 1229 MB, reserved memory is 1204 MB, peak memory is 1337 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.781757s wall, 0.375000s user + 0.328125s system = 0.703125s CPU (4.0%)
+
+RUN-1004 : used memory is 1229 MB, reserved memory is 1204 MB, peak memory is 1337 MB
+GUI-1001 : Downloading succeeded!
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.542523s wall, 0.140625s user + 0.281250s system = 0.421875s CPU (2.4%)
+
+RUN-1004 : used memory is 1229 MB, reserved memory is 1204 MB, peak memory is 1337 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.759527s wall, 0.265625s user + 0.281250s system = 0.546875s CPU (3.1%)
+
+RUN-1004 : used memory is 1229 MB, reserved memory is 1204 MB, peak memory is 1337 MB
+GUI-1001 : Downloading succeeded!
+TMR-3509 : Import timing summary.
+TMR-3509 : Import timing summary.
diff --git a/src/prj/td_project/td_20240218_153322.log b/src/prj/td_project/td_20240218_153322.log
index e69de29..9d7fdda 100644
--- a/src/prj/td_project/td_20240218_153322.log
+++ b/src/prj/td_project/td_20240218_153322.log
@@ -0,0 +1,207 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sun Feb 18 15:33:22 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-001 : GUI based run...
+RUN-1002 : start command "open_project hg_anlogic.al -update"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/wrdpram_ctl.v
+HDL-1007 : undeclared symbol 'neg_dval_i', assumed default net type 'wire' in ../../hg_mp/fe/wrdpram_ctl.v(375)
+HDL-5007 WARNING: parameter 'DPI300_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(24)
+HDL-5007 WARNING: parameter 'DPI600_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(25)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 63 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.