diff --git a/src/.simvision/33852_liny__autosave.tcl.svcf b/src/.simvision/33852_liny__autosave.tcl.svcf
new file mode 100644
index 0000000..cd6a422
--- /dev/null
+++ b/src/.simvision/33852_liny__autosave.tcl.svcf
@@ -0,0 +1,81 @@
+
+#
+# Preferences
+#
+preferences set toolbar-SimControl-WatchList {
+ usual
+ position -anchor e
+}
+preferences set toolbar-SimControl-SrcBrowser {
+ usual
+ show step_out
+}
+preferences set plugin-enable-svdatabrowser-new 1
+preferences set cursorctl-dont-show-sync-warning 1
+preferences set user-toolbar-list {WatchList {}}
+preferences set toolbar-Standard-Console {
+ usual
+ position -pos 1
+}
+preferences set toolbar-Search-Console {
+ usual
+ position -pos 2
+}
+preferences set toolbar-Standard-WaveWindow {
+ usual
+ position -pos 4
+}
+preferences set plugin-enable-groupscope 0
+preferences set standard-methodology-filtering 1
+preferences set plugin-enable-interleaveandcompare 0
+preferences set plugin-enable-waveformfrequencyplot 0
+preferences set toolbar-Windows-WatchList {
+ usual
+ position -pos 2
+}
+preferences set savedlg-simulator ppe
+preferences set whats-new-dont-show-at-startup 1
+
+#
+# Mnemonic Maps
+#
+mmap new -reuse -name {Boolean as Logic} -radix %b -contents {{%c=FALSE -edgepriority 1 -shape low}
+{%c=TRUE -edgepriority 1 -shape high}}
+mmap new -reuse -name {Example Map} -radix %x -contents {{%b=11???? -bgcolor orange -label REG:%x -linecolor yellow -shape bus}
+{%x=1F -bgcolor red -label ERROR -linecolor white -shape EVENT}
+{%x=2C -bgcolor red -label ERROR -linecolor white -shape EVENT}
+{%x=* -label %x -linecolor gray -shape bus}}
+
+#
+# Waveform windows
+#
+if {[catch {window new WaveWindow -name "Waveform 1" -geometry 2293x828+0+31}] != ""} {
+ window geometry "Waveform 1" 2293x828+0+31
+}
+window target "Waveform 1" on
+waveform using {Waveform 1}
+waveform sidebar select designbrowser
+waveform set \
+ -primarycursor TimeA \
+ -signalnames name \
+ -signalwidth 175 \
+ -units ns \
+ -valuewidth 75
+waveform baseline set -time 0
+
+
+waveform xview limits 0 1000000000ns
+
+#
+# Waveform Window Links
+#
+
+#
+# Console windows
+#
+console set -windowname Console
+window geometry Console 600x250+0+0
+
+#
+# Layout selection
+#
diff --git a/src/hg_mp/drx_top/huagao_mipi_top.v b/src/hg_mp/drx_top/huagao_mipi_top.v
index ebcc18d..800baeb 100644
--- a/src/hg_mp/drx_top/huagao_mipi_top.v
+++ b/src/hg_mp/drx_top/huagao_mipi_top.v
@@ -1695,10 +1695,10 @@ always @(*) begin
end
assign debug[0] = a_vs ;
-assign debug[1] = debug_6 ;
-assign debug[2] = S_hs_valid ;
-assign debug[3] = O_clk_lp_n;
-assign debug[4] = O_clk_lp_p ;
+assign debug[1] = a_ad_sck;
+assign debug[2] = a_ad_sen ;
+assign debug[3] = a_ad_sdi;
+assign debug[4] = a_ad_sdo ;
assign debug[5] = FV_MIPI ;
assign debug[6] = sync_eot ;
assign debug[7] = LV_MIPI;
diff --git a/src/hg_mp/local_bus/ubus_top.v b/src/hg_mp/local_bus/ubus_top.v
index 517e81e..27392aa 100644
--- a/src/hg_mp/local_bus/ubus_top.v
+++ b/src/hg_mp/local_bus/ubus_top.v
@@ -215,7 +215,7 @@ local_bus_slve_cis u_local_bus_slve_cis(
//,.nd2reg_0 ( scan_status_sync3d_8m ) //input [31:0]
,.nd2reg_0 ( adc_cfg_data_o_sync3d_8m) //input [31:0]
- ,.nd2reg_1 ( 32'h000a0001 ) //input [31:0]
+ ,.nd2reg_1 ( 32'h000a0002 ) //input [31:0]
,.nd2reg_2 ( lv_cnt2bus_sync3d ) //input [31:0]
,.nd2reg_3 ( fr_cnt2bus_sync3d ) //input [31:0]
,.nd2reg_4 ( lv_cnt_a_sync3d ) //input [31:0]
diff --git a/src/prj/td_project/hg_anlogic.adc b/src/prj/td_project/hg_anlogic.adc
index 15fde19..0c6d798 100644
--- a/src/prj/td_project/hg_anlogic.adc
+++ b/src/prj/td_project/hg_anlogic.adc
@@ -13,28 +13,28 @@ set_pin_assignment { O_data_lp_p[0] } { LOCATION = P63; IOSTANDARD = LVCMOS25; D
set_pin_assignment { O_data_lp_p[1] } { LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; }
set_pin_assignment { O_data_lp_p[2] } { LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; }
set_pin_assignment { O_data_lp_p[3] } { LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; }
-set_pin_assignment { a_ad_sck } { LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
-set_pin_assignment { a_ad_sdi } { LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
-set_pin_assignment { a_ad_sdo } { LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
-set_pin_assignment { a_ad_sen } { LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
-set_pin_assignment { a_lvds_clk_p } { LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { a_lvds_data_p[0] } { LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { a_lvds_data_p[1] } { LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { a_lvds_data_p[2] } { LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { a_lvds_data_p[3] } { LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { a_lvds_data_p[4] } { LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { a_sp_pad } { LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
-set_pin_assignment { b_ad_sck } { LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
-set_pin_assignment { b_ad_sdi } { LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
-set_pin_assignment { b_ad_sdo } { LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
-set_pin_assignment { b_ad_sen } { LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
-set_pin_assignment { b_lvds_clk_p } { LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { b_lvds_data_p[0] } { LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { b_lvds_data_p[1] } { LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { b_lvds_data_p[2] } { LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { b_lvds_data_p[3] } { LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { b_lvds_data_p[4] } { LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { b_sp_pad } { LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
+set_pin_assignment { b_ad_sck } { LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
+set_pin_assignment { b_ad_sdi } { LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
+set_pin_assignment { b_ad_sdo } { LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
+set_pin_assignment { b_ad_sen } { LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
+set_pin_assignment { b_lvds_clk_p } { LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { b_lvds_data_p[0] } { LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { b_lvds_data_p[1] } { LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { b_lvds_data_p[2] } { LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { b_lvds_data_p[3] } { LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { b_lvds_data_p[4] } { LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { b_sp_pad } { LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
+set_pin_assignment { a_ad_sck } { LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
+set_pin_assignment { a_ad_sdi } { LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
+set_pin_assignment { a_ad_sdo } { LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
+set_pin_assignment { a_ad_sen } { LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
+set_pin_assignment { a_lvds_clk_p } { LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { a_lvds_data_p[0] } { LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { a_lvds_data_p[1] } { LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { a_lvds_data_p[2] } { LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { a_lvds_data_p[3] } { LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { a_lvds_data_p[4] } { LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
+set_pin_assignment { a_sp_pad } { LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { clock_source } { LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
set_pin_assignment { debug[0] } { LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { debug[1] } { LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240123_173017.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240123_173017.log
new file mode 100644
index 0000000..a3fea55
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240123_173017.log
@@ -0,0 +1,2216 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Tue Jan 23 17:30:17 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.229064s wall, 2.109375s user + 0.093750s system = 2.203125s CPU (98.8%)
+
+RUN-1004 : used memory is 336 MB, reserved memory is 315 MB, peak memory is 340 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2946 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17775 instances
+RUN-0007 : 7512 luts, 9040 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20353 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13335 nets have 2 pins
+RUN-1001 : 5559 nets have [3 - 5] pins
+RUN-1001 : 1037 nets have [6 - 10] pins
+RUN-1001 : 172 nets have [11 - 20] pins
+RUN-1001 : 176 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 789
+RUN-1001 : No | No | Yes | 1968
+RUN-1001 : No | Yes | No | 3474
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 56
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 141
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17773 instances, 7512 luts, 9040 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 5912 pins
+PHY-0007 : Cell area utilization is 49%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85140, tnet num: 20175, tinst num: 17773, tnode num: 115222, tedge num: 136661.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.222447s wall, 1.203125s user + 0.015625s system = 1.218750s CPU (99.7%)
+
+RUN-1004 : used memory is 530 MB, reserved memory is 514 MB, peak memory is 530 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20175 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.034517s wall, 2.000000s user + 0.031250s system = 2.031250s CPU (99.8%)
+
+PHY-3001 : Found 1221 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 3.89577e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17773.
+PHY-3001 : Level 1 #clusters 2039.
+PHY-3001 : End clustering; 0.139460s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (78.4%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 49%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.29775e+06, overlap = 467.844
+PHY-3002 : Step(2): len = 1.16311e+06, overlap = 485.25
+PHY-3002 : Step(3): len = 877561, overlap = 599.844
+PHY-3002 : Step(4): len = 778419, overlap = 626.906
+PHY-3002 : Step(5): len = 612678, overlap = 726.906
+PHY-3002 : Step(6): len = 543642, overlap = 805.844
+PHY-3002 : Step(7): len = 465738, overlap = 882.969
+PHY-3002 : Step(8): len = 431485, overlap = 963.031
+PHY-3002 : Step(9): len = 374974, overlap = 1063.75
+PHY-3002 : Step(10): len = 348378, overlap = 1130.62
+PHY-3002 : Step(11): len = 311449, overlap = 1177.72
+PHY-3002 : Step(12): len = 295623, overlap = 1186.78
+PHY-3002 : Step(13): len = 265982, overlap = 1273.25
+PHY-3002 : Step(14): len = 252734, overlap = 1327.22
+PHY-3002 : Step(15): len = 224231, overlap = 1355.06
+PHY-3002 : Step(16): len = 207066, overlap = 1367.88
+PHY-3002 : Step(17): len = 186944, overlap = 1399.12
+PHY-3002 : Step(18): len = 174210, overlap = 1442.97
+PHY-3002 : Step(19): len = 159238, overlap = 1434.12
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.1033e-06
+PHY-3002 : Step(20): len = 161504, overlap = 1428.69
+PHY-3002 : Step(21): len = 195602, overlap = 1305.03
+PHY-3002 : Step(22): len = 197030, overlap = 1200
+PHY-3002 : Step(23): len = 200043, overlap = 1150.44
+PHY-3002 : Step(24): len = 196268, overlap = 1160.94
+PHY-3002 : Step(25): len = 193620, overlap = 1142.69
+PHY-3002 : Step(26): len = 188789, overlap = 1159.41
+PHY-3002 : Step(27): len = 186803, overlap = 1164.84
+PHY-3002 : Step(28): len = 182121, overlap = 1163.31
+PHY-3002 : Step(29): len = 180718, overlap = 1154.84
+PHY-3002 : Step(30): len = 178985, overlap = 1150.12
+PHY-3002 : Step(31): len = 177689, overlap = 1153.38
+PHY-3002 : Step(32): len = 176199, overlap = 1144.84
+PHY-3002 : Step(33): len = 175284, overlap = 1134.81
+PHY-3002 : Step(34): len = 173591, overlap = 1145.19
+PHY-3002 : Step(35): len = 172988, overlap = 1164.09
+PHY-3002 : Step(36): len = 171801, overlap = 1155.81
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.2066e-06
+PHY-3002 : Step(37): len = 176356, overlap = 1119.94
+PHY-3002 : Step(38): len = 188069, overlap = 1104.94
+PHY-3002 : Step(39): len = 192170, overlap = 1096.56
+PHY-3002 : Step(40): len = 196030, overlap = 1090
+PHY-3002 : Step(41): len = 197396, overlap = 1081.38
+PHY-3002 : Step(42): len = 198171, overlap = 1074
+PHY-3002 : Step(43): len = 196506, overlap = 1067.44
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.4132e-06
+PHY-3002 : Step(44): len = 203106, overlap = 1036.72
+PHY-3002 : Step(45): len = 218122, overlap = 957.469
+PHY-3002 : Step(46): len = 227684, overlap = 900.188
+PHY-3002 : Step(47): len = 239318, overlap = 845.938
+PHY-3002 : Step(48): len = 243630, overlap = 847.969
+PHY-3002 : Step(49): len = 246032, overlap = 860.188
+PHY-3002 : Step(50): len = 244907, overlap = 844.312
+PHY-3002 : Step(51): len = 243542, overlap = 844.375
+PHY-3002 : Step(52): len = 242669, overlap = 834.875
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.8264e-06
+PHY-3002 : Step(53): len = 253865, overlap = 787.688
+PHY-3002 : Step(54): len = 276814, overlap = 685.281
+PHY-3002 : Step(55): len = 289447, overlap = 649.094
+PHY-3002 : Step(56): len = 294471, overlap = 597.938
+PHY-3002 : Step(57): len = 295880, overlap = 598.156
+PHY-3002 : Step(58): len = 294873, overlap = 580.812
+PHY-3002 : Step(59): len = 294061, overlap = 571.5
+PHY-3002 : Step(60): len = 294154, overlap = 577.469
+PHY-3002 : Step(61): len = 293644, overlap = 569.094
+PHY-3002 : Step(62): len = 293305, overlap = 567.219
+PHY-3002 : Step(63): len = 293026, overlap = 549.125
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.76528e-05
+PHY-3002 : Step(64): len = 310085, overlap = 497.594
+PHY-3002 : Step(65): len = 325218, overlap = 454.188
+PHY-3002 : Step(66): len = 329763, overlap = 430.969
+PHY-3002 : Step(67): len = 330969, overlap = 430.719
+PHY-3002 : Step(68): len = 331347, overlap = 423.812
+PHY-3002 : Step(69): len = 334865, overlap = 449.656
+PHY-3002 : Step(70): len = 335378, overlap = 455.219
+PHY-3002 : Step(71): len = 336516, overlap = 449.719
+PHY-3002 : Step(72): len = 336660, overlap = 437.938
+PHY-3002 : Step(73): len = 338289, overlap = 424.375
+PHY-3002 : Step(74): len = 339125, overlap = 398.656
+PHY-3002 : Step(75): len = 339805, overlap = 385.219
+PHY-3002 : Step(76): len = 339131, overlap = 384.438
+PHY-3002 : Step(77): len = 338390, overlap = 374.688
+PHY-3002 : Step(78): len = 339968, overlap = 382.812
+PHY-3002 : Step(79): len = 341572, overlap = 387.594
+PHY-3002 : Step(80): len = 340479, overlap = 378.781
+PHY-3002 : Step(81): len = 341589, overlap = 383.906
+PHY-3002 : Step(82): len = 341108, overlap = 379.281
+PHY-3002 : Step(83): len = 341729, overlap = 394.344
+PHY-3002 : Step(84): len = 339926, overlap = 393.062
+PHY-3002 : Step(85): len = 340056, overlap = 396.375
+PHY-3002 : Step(86): len = 338489, overlap = 401.438
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.53056e-05
+PHY-3002 : Step(87): len = 354438, overlap = 380.75
+PHY-3002 : Step(88): len = 364146, overlap = 370.25
+PHY-3002 : Step(89): len = 365312, overlap = 347.312
+PHY-3002 : Step(90): len = 367037, overlap = 334.969
+PHY-3002 : Step(91): len = 368246, overlap = 311.719
+PHY-3002 : Step(92): len = 371822, overlap = 307.188
+PHY-3002 : Step(93): len = 370261, overlap = 297.25
+PHY-3002 : Step(94): len = 371618, overlap = 285.688
+PHY-3002 : Step(95): len = 371338, overlap = 291.344
+PHY-3002 : Step(96): len = 371703, overlap = 291.344
+PHY-3002 : Step(97): len = 369684, overlap = 291.75
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.06112e-05
+PHY-3002 : Step(98): len = 385567, overlap = 278.469
+PHY-3002 : Step(99): len = 397202, overlap = 276.625
+PHY-3002 : Step(100): len = 395877, overlap = 269.969
+PHY-3002 : Step(101): len = 396261, overlap = 270.062
+PHY-3002 : Step(102): len = 399121, overlap = 267.062
+PHY-3002 : Step(103): len = 402470, overlap = 249.531
+PHY-3002 : Step(104): len = 400912, overlap = 247.469
+PHY-3002 : Step(105): len = 402046, overlap = 264.25
+PHY-3002 : Step(106): len = 405764, overlap = 254.75
+PHY-3002 : Step(107): len = 408792, overlap = 264.25
+PHY-3002 : Step(108): len = 406116, overlap = 280.969
+PHY-3002 : Step(109): len = 406664, overlap = 276.312
+PHY-3002 : Step(110): len = 407914, overlap = 267
+PHY-3002 : Step(111): len = 408739, overlap = 256.219
+PHY-3002 : Step(112): len = 406337, overlap = 263.594
+PHY-3002 : Step(113): len = 405988, overlap = 253.375
+PHY-3002 : Step(114): len = 406383, overlap = 257.844
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000141222
+PHY-3002 : Step(115): len = 419171, overlap = 263.438
+PHY-3002 : Step(116): len = 429534, overlap = 252.125
+PHY-3002 : Step(117): len = 429495, overlap = 255.906
+PHY-3002 : Step(118): len = 430343, overlap = 255.312
+PHY-3002 : Step(119): len = 432547, overlap = 243.031
+PHY-3002 : Step(120): len = 434355, overlap = 239.062
+PHY-3002 : Step(121): len = 431975, overlap = 238.906
+PHY-3002 : Step(122): len = 432326, overlap = 230.938
+PHY-3002 : Step(123): len = 435192, overlap = 217.562
+PHY-3002 : Step(124): len = 437882, overlap = 221.438
+PHY-3002 : Step(125): len = 436164, overlap = 226.188
+PHY-3002 : Step(126): len = 436114, overlap = 228.938
+PHY-3002 : Step(127): len = 437979, overlap = 220.375
+PHY-3002 : Step(128): len = 439852, overlap = 216.375
+PHY-3002 : Step(129): len = 438616, overlap = 209.312
+PHY-3002 : Step(130): len = 439209, overlap = 206.781
+PHY-3002 : Step(131): len = 441164, overlap = 202.469
+PHY-3002 : Step(132): len = 442319, overlap = 203.969
+PHY-3002 : Step(133): len = 440303, overlap = 201
+PHY-3002 : Step(134): len = 439933, overlap = 207.5
+PHY-3002 : Step(135): len = 441044, overlap = 202.25
+PHY-3002 : Step(136): len = 442433, overlap = 205.188
+PHY-3002 : Step(137): len = 440954, overlap = 205.312
+PHY-3002 : Step(138): len = 441229, overlap = 202.156
+PHY-3002 : Step(139): len = 442445, overlap = 203.281
+PHY-3002 : Step(140): len = 442910, overlap = 200.312
+PHY-3002 : Step(141): len = 441321, overlap = 200.344
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000259755
+PHY-3002 : Step(142): len = 450154, overlap = 207.938
+PHY-3002 : Step(143): len = 456830, overlap = 207.812
+PHY-3002 : Step(144): len = 457214, overlap = 216.406
+PHY-3002 : Step(145): len = 457609, overlap = 205.844
+PHY-3002 : Step(146): len = 460943, overlap = 210.562
+PHY-3002 : Step(147): len = 463011, overlap = 195.719
+PHY-3002 : Step(148): len = 461498, overlap = 200.812
+PHY-3002 : Step(149): len = 461375, overlap = 198.625
+PHY-3002 : Step(150): len = 464894, overlap = 194.188
+PHY-3002 : Step(151): len = 468248, overlap = 182.406
+PHY-3002 : Step(152): len = 466281, overlap = 192.094
+PHY-3002 : Step(153): len = 465841, overlap = 193.312
+PHY-3002 : Step(154): len = 466407, overlap = 189
+PHY-3002 : Step(155): len = 466621, overlap = 186.531
+PHY-3002 : Step(156): len = 466058, overlap = 188.781
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000448424
+PHY-3002 : Step(157): len = 471253, overlap = 184.438
+PHY-3002 : Step(158): len = 476598, overlap = 179.594
+PHY-3002 : Step(159): len = 477613, overlap = 180.094
+PHY-3002 : Step(160): len = 478831, overlap = 171.125
+PHY-3002 : Step(161): len = 481130, overlap = 168.406
+PHY-3002 : Step(162): len = 482272, overlap = 162.312
+PHY-3002 : Step(163): len = 481376, overlap = 160.906
+PHY-3002 : Step(164): len = 481456, overlap = 165.031
+PHY-3002 : Step(165): len = 483715, overlap = 161.906
+PHY-3002 : Step(166): len = 485097, overlap = 161.188
+PHY-3002 : Step(167): len = 484054, overlap = 160.031
+PHY-3002 : Step(168): len = 483882, overlap = 163.375
+PHY-3002 : Step(169): len = 486044, overlap = 162.719
+PHY-3002 : Step(170): len = 487671, overlap = 162.781
+PHY-3002 : Step(171): len = 486594, overlap = 160.875
+PHY-3002 : Step(172): len = 486372, overlap = 160.938
+PHY-3002 : Step(173): len = 487559, overlap = 160.312
+PHY-3002 : Step(174): len = 488222, overlap = 157.125
+PHY-3002 : Step(175): len = 486767, overlap = 153.5
+PHY-3002 : Step(176): len = 486400, overlap = 151.25
+PHY-3002 : Step(177): len = 488043, overlap = 156.875
+PHY-3002 : Step(178): len = 489293, overlap = 155.5
+PHY-3002 : Step(179): len = 487817, overlap = 160.375
+PHY-3002 : Step(180): len = 487397, overlap = 154.5
+PHY-3002 : Step(181): len = 488680, overlap = 156.5
+PHY-3002 : Step(182): len = 489808, overlap = 156.969
+PHY-3002 : Step(183): len = 488257, overlap = 152.438
+PHY-3002 : Step(184): len = 487927, overlap = 152
+PHY-3002 : Step(185): len = 489442, overlap = 152.062
+PHY-3002 : Step(186): len = 490062, overlap = 153
+PHY-3002 : Step(187): len = 488875, overlap = 147.875
+PHY-3002 : Step(188): len = 488562, overlap = 147.781
+PHY-3002 : Step(189): len = 489660, overlap = 151.531
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000866261
+PHY-3002 : Step(190): len = 494105, overlap = 149.344
+PHY-3002 : Step(191): len = 501395, overlap = 146.781
+PHY-3002 : Step(192): len = 502887, overlap = 143.281
+PHY-3002 : Step(193): len = 503478, overlap = 146.531
+PHY-3002 : Step(194): len = 504288, overlap = 146.25
+PHY-3002 : Step(195): len = 504718, overlap = 145.594
+PHY-3002 : Step(196): len = 504566, overlap = 146.406
+PHY-3002 : Step(197): len = 505186, overlap = 137.719
+PHY-3002 : Step(198): len = 507021, overlap = 141.562
+PHY-3002 : Step(199): len = 508439, overlap = 136.719
+PHY-3002 : Step(200): len = 508625, overlap = 134.938
+PHY-3002 : Step(201): len = 508698, overlap = 134.5
+PHY-3002 : Step(202): len = 508904, overlap = 135.312
+PHY-3002 : Step(203): len = 508977, overlap = 132.844
+PHY-3002 : Step(204): len = 508907, overlap = 136.969
+PHY-3002 : Step(205): len = 508978, overlap = 135.656
+PHY-3002 : Step(206): len = 509484, overlap = 132.656
+PHY-3002 : Step(207): len = 509484, overlap = 132.656
+PHY-3002 : Step(208): len = 509430, overlap = 134.688
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.0014794
+PHY-3002 : Step(209): len = 512389, overlap = 131.5
+PHY-3002 : Step(210): len = 518722, overlap = 130.594
+PHY-3002 : Step(211): len = 519553, overlap = 128.312
+PHY-3002 : Step(212): len = 519925, overlap = 126.156
+PHY-3002 : Step(213): len = 521356, overlap = 120.781
+PHY-3002 : Step(214): len = 522398, overlap = 117.656
+PHY-3002 : Step(215): len = 522369, overlap = 119.844
+PHY-3002 : Step(216): len = 522561, overlap = 120.656
+PHY-3002 : Step(217): len = 523638, overlap = 118.344
+PHY-3002 : Step(218): len = 524158, overlap = 118.656
+PHY-3002 : Step(219): len = 523821, overlap = 121.344
+PHY-3002 : Step(220): len = 523751, overlap = 121.344
+PHY-3002 : Step(221): len = 524262, overlap = 120.875
+PHY-3002 : Step(222): len = 524669, overlap = 120.219
+PHY-3002 : Step(223): len = 524519, overlap = 119.438
+PHY-3002 : Step(224): len = 524554, overlap = 118.562
+PHY-3002 : Step(225): len = 525025, overlap = 119.625
+PHY-3002 : Step(226): len = 525250, overlap = 119.5
+PHY-3002 : Step(227): len = 525343, overlap = 118.625
+PHY-3002 : Step(228): len = 525729, overlap = 113.25
+PHY-3002 : Step(229): len = 526326, overlap = 115
+PHY-3002 : Step(230): len = 526326, overlap = 115
+PHY-3002 : Step(231): len = 526253, overlap = 113.719
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.011539s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20353.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 697032, over cnt = 1578(4%), over = 7283, worst = 59
+PHY-1001 : End global iterations; 0.716414s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (137.4%)
+
+PHY-1001 : Congestion index: top1 = 82.50, top5 = 61.32, top10 = 52.19, top15 = 46.69.
+PHY-3001 : End congestion estimation; 0.943670s wall, 1.156250s user + 0.046875s system = 1.203125s CPU (127.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20175 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.886886s wall, 0.843750s user + 0.046875s system = 0.890625s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000151037
+PHY-3002 : Step(232): len = 631054, overlap = 60.0625
+PHY-3002 : Step(233): len = 637362, overlap = 57.3438
+PHY-3002 : Step(234): len = 633635, overlap = 52.3438
+PHY-3002 : Step(235): len = 629957, overlap = 49.0625
+PHY-3002 : Step(236): len = 627900, overlap = 51.25
+PHY-3002 : Step(237): len = 627655, overlap = 51.3125
+PHY-3002 : Step(238): len = 626002, overlap = 45.3125
+PHY-3002 : Step(239): len = 625218, overlap = 34.1562
+PHY-3002 : Step(240): len = 622385, overlap = 27.9375
+PHY-3002 : Step(241): len = 620786, overlap = 25.8438
+PHY-3002 : Step(242): len = 616946, overlap = 27.9062
+PHY-3002 : Step(243): len = 615018, overlap = 28.5
+PHY-3002 : Step(244): len = 613891, overlap = 27.25
+PHY-3002 : Step(245): len = 612476, overlap = 27.5
+PHY-3002 : Step(246): len = 611599, overlap = 27.8438
+PHY-3002 : Step(247): len = 611643, overlap = 28.125
+PHY-3002 : Step(248): len = 611270, overlap = 26.5938
+PHY-3002 : Step(249): len = 609844, overlap = 25.5312
+PHY-3002 : Step(250): len = 608255, overlap = 22.9062
+PHY-3002 : Step(251): len = 606901, overlap = 23.4062
+PHY-3002 : Step(252): len = 605387, overlap = 26
+PHY-3002 : Step(253): len = 603930, overlap = 30.4062
+PHY-3002 : Step(254): len = 603806, overlap = 34.625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000302073
+PHY-3002 : Step(255): len = 605050, overlap = 32.7812
+PHY-3002 : Step(256): len = 609067, overlap = 30.4688
+PHY-3002 : Step(257): len = 613785, overlap = 28.5938
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000604147
+PHY-3002 : Step(258): len = 620742, overlap = 26.5
+PHY-3002 : Step(259): len = 632388, overlap = 23.4375
+PHY-3002 : Step(260): len = 640631, overlap = 22.9375
+PHY-3002 : Step(261): len = 645095, overlap = 20.7812
+PHY-3002 : Step(262): len = 649226, overlap = 20.0312
+PHY-3002 : Step(263): len = 652579, overlap = 21.0312
+PHY-3002 : Step(264): len = 654670, overlap = 24.4062
+PHY-3002 : Step(265): len = 655013, overlap = 24.3438
+PHY-3002 : Step(266): len = 653591, overlap = 22.9375
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00120829
+PHY-3002 : Step(267): len = 659533, overlap = 21.6562
+PHY-3002 : Step(268): len = 666010, overlap = 21.375
+PHY-3002 : Step(269): len = 668141, overlap = 20.625
+PHY-3002 : Step(270): len = 669197, overlap = 20.625
+PHY-3002 : Step(271): len = 671897, overlap = 18.5938
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 61/20353.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 763680, over cnt = 2909(8%), over = 12572, worst = 42
+PHY-1001 : End global iterations; 1.818722s wall, 2.484375s user + 0.031250s system = 2.515625s CPU (138.3%)
+
+PHY-1001 : Congestion index: top1 = 87.91, top5 = 67.62, top10 = 59.10, top15 = 54.11.
+PHY-3001 : End congestion estimation; 2.103372s wall, 2.765625s user + 0.031250s system = 2.796875s CPU (133.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20175 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.924483s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000151067
+PHY-3002 : Step(272): len = 662376, overlap = 178.906
+PHY-3002 : Step(273): len = 657751, overlap = 139.781
+PHY-3002 : Step(274): len = 648369, overlap = 132.688
+PHY-3002 : Step(275): len = 640058, overlap = 125.781
+PHY-3002 : Step(276): len = 634036, overlap = 118.594
+PHY-3002 : Step(277): len = 628972, overlap = 116.719
+PHY-3002 : Step(278): len = 624030, overlap = 105.281
+PHY-3002 : Step(279): len = 619850, overlap = 95.7812
+PHY-3002 : Step(280): len = 617705, overlap = 95.125
+PHY-3002 : Step(281): len = 613657, overlap = 100.625
+PHY-3002 : Step(282): len = 610909, overlap = 105.344
+PHY-3002 : Step(283): len = 607156, overlap = 108.969
+PHY-3002 : Step(284): len = 603793, overlap = 110.281
+PHY-3002 : Step(285): len = 600817, overlap = 110.594
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000302133
+PHY-3002 : Step(286): len = 601737, overlap = 107
+PHY-3002 : Step(287): len = 603706, overlap = 105.094
+PHY-3002 : Step(288): len = 604197, overlap = 105.125
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000595784
+PHY-3002 : Step(289): len = 610115, overlap = 97.7812
+PHY-3002 : Step(290): len = 618587, overlap = 85.5312
+PHY-3002 : Step(291): len = 620551, overlap = 82.125
+PHY-3002 : Step(292): len = 620294, overlap = 77.9688
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00119157
+PHY-3002 : Step(293): len = 622425, overlap = 75.2812
+PHY-3002 : Step(294): len = 626136, overlap = 69.4375
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85140, tnet num: 20175, tinst num: 17773, tnode num: 115222, tedge num: 136661.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.522602s wall, 1.500000s user + 0.031250s system = 1.531250s CPU (100.6%)
+
+RUN-1004 : used memory is 575 MB, reserved memory is 565 MB, peak memory is 710 MB
+OPT-1001 : Total overflow 394.62 peak overflow 3.28
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 761/20353.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 727480, over cnt = 3010(8%), over = 10385, worst = 21
+PHY-1001 : End global iterations; 1.458419s wall, 1.968750s user + 0.000000s system = 1.968750s CPU (135.0%)
+
+PHY-1001 : Congestion index: top1 = 69.44, top5 = 56.14, top10 = 50.50, top15 = 47.00.
+PHY-1001 : End incremental global routing; 1.826890s wall, 2.343750s user + 0.000000s system = 2.343750s CPU (128.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20175 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.935771s wall, 0.859375s user + 0.046875s system = 0.906250s CPU (96.8%)
+
+OPT-1001 : 48 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17640 has valid locations, 343 needs to be replaced
+PHY-3001 : design contains 18068 instances, 7619 luts, 9228 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 6047 pins
+PHY-3001 : Found 1231 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 651470
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16669/20648.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 743288, over cnt = 3083(8%), over = 10518, worst = 20
+PHY-1001 : End global iterations; 0.277290s wall, 0.406250s user + 0.015625s system = 0.421875s CPU (152.1%)
+
+PHY-1001 : Congestion index: top1 = 68.97, top5 = 56.11, top10 = 50.77, top15 = 47.32.
+PHY-3001 : End congestion estimation; 0.553555s wall, 0.671875s user + 0.015625s system = 0.687500s CPU (124.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86305, tnet num: 20470, tinst num: 18068, tnode num: 116956, tedge num: 138401.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.501481s wall, 1.468750s user + 0.031250s system = 1.500000s CPU (99.9%)
+
+RUN-1004 : used memory is 620 MB, reserved memory is 621 MB, peak memory is 715 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20470 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.522401s wall, 2.468750s user + 0.062500s system = 2.531250s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(295): len = 650382, overlap = 0
+PHY-3002 : Step(296): len = 649834, overlap = 0
+PHY-3002 : Step(297): len = 649581, overlap = 0
+PHY-3002 : Step(298): len = 649334, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16785/20648.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 740728, over cnt = 3073(8%), over = 10581, worst = 20
+PHY-1001 : End global iterations; 0.228364s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (143.7%)
+
+PHY-1001 : Congestion index: top1 = 70.11, top5 = 56.55, top10 = 51.10, top15 = 47.57.
+PHY-3001 : End congestion estimation; 0.518667s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (117.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20470 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.975214s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000418217
+PHY-3002 : Step(299): len = 649219, overlap = 72.4062
+PHY-3002 : Step(300): len = 649255, overlap = 72.9062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000836433
+PHY-3002 : Step(301): len = 649542, overlap = 72.125
+PHY-3002 : Step(302): len = 650099, overlap = 71.9688
+PHY-3001 : Final: Len = 650099, Over = 71.9688
+PHY-3001 : End incremental placement; 5.311694s wall, 5.640625s user + 0.234375s system = 5.875000s CPU (110.6%)
+
+OPT-1001 : Total overflow 400.59 peak overflow 3.28
+OPT-1001 : End high-fanout net optimization; 8.666529s wall, 9.515625s user + 0.296875s system = 9.812500s CPU (113.2%)
+
+OPT-1001 : Current memory(MB): used = 718, reserve = 713, peak = 735.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16736/20648.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 743544, over cnt = 3018(8%), over = 9538, worst = 20
+PHY-1002 : len = 786344, over cnt = 2056(5%), over = 5232, worst = 20
+PHY-1002 : len = 826320, over cnt = 945(2%), over = 2144, worst = 15
+PHY-1002 : len = 848792, over cnt = 309(0%), over = 572, worst = 12
+PHY-1002 : len = 859880, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.801725s wall, 2.406250s user + 0.000000s system = 2.406250s CPU (133.6%)
+
+PHY-1001 : Congestion index: top1 = 56.83, top5 = 49.88, top10 = 46.48, top15 = 44.34.
+OPT-1001 : End congestion update; 2.081082s wall, 2.687500s user + 0.000000s system = 2.687500s CPU (129.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20470 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.944701s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.2%)
+
+OPT-0007 : Start: WNS -1318 TNS -1828 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1268 TNS -1778 NUM_FEPS 2 with 69 cells processed and 2300 slack improved
+OPT-0007 : Iter 2: improved WNS -1268 TNS -1778 NUM_FEPS 2 with 11 cells processed and 500 slack improved
+OPT-0007 : Iter 3: improved WNS -1268 TNS -1778 NUM_FEPS 2 with 3 cells processed and 150 slack improved
+OPT-1001 : End global optimization; 3.069118s wall, 3.671875s user + 0.000000s system = 3.671875s CPU (119.6%)
+
+OPT-1001 : Current memory(MB): used = 695, reserve = 693, peak = 735.
+OPT-1001 : End physical optimization; 13.925665s wall, 15.359375s user + 0.328125s system = 15.687500s CPU (112.7%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7619 LUT to BLE ...
+SYN-4008 : Packed 7619 LUT and 3080 SEQ to BLE.
+SYN-4003 : Packing 6148 remaining SEQ's ...
+SYN-4005 : Packed 3985 SEQ with LUT/SLICE
+SYN-4006 : 856 single LUT's are left
+SYN-4006 : 2163 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9782/13513 primitive instances ...
+PHY-3001 : End packing; 1.757564s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (100.5%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6849 instances
+RUN-1001 : 3350 mslices, 3351 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17700 nets
+RUN-6002 WARNING: There are 2 undriven nets.
+RUN-6004 WARNING: There are 23 nets with only 1 pin.
+RUN-1001 : 10049 nets have 2 pins
+RUN-1001 : 5816 nets have [3 - 5] pins
+RUN-1001 : 1116 nets have [6 - 10] pins
+RUN-1001 : 336 nets have [11 - 20] pins
+RUN-1001 : 348 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6847 instances, 6701 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3598 pins
+PHY-3001 : Found 486 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 661122, Over = 257.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_pakage_en_1d is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7337/17700.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 812616, over cnt = 2031(5%), over = 3350, worst = 8
+PHY-1002 : len = 819976, over cnt = 1402(3%), over = 2064, worst = 6
+PHY-1002 : len = 838528, over cnt = 398(1%), over = 525, worst = 6
+PHY-1002 : len = 844984, over cnt = 88(0%), over = 123, worst = 5
+PHY-1002 : len = 847088, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.805419s wall, 2.562500s user + 0.031250s system = 2.593750s CPU (143.7%)
+
+PHY-1001 : Congestion index: top1 = 55.32, top5 = 49.80, top10 = 46.45, top15 = 44.11.
+PHY-3001 : End congestion estimation; 2.258495s wall, 3.000000s user + 0.031250s system = 3.031250s CPU (134.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74401, tnet num: 17522, tinst num: 6847, tnode num: 96919, tedge num: 124862.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.774114s wall, 1.781250s user + 0.000000s system = 1.781250s CPU (100.4%)
+
+RUN-1004 : used memory is 610 MB, reserved memory is 610 MB, peak memory is 735 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17522 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.717195s wall, 2.703125s user + 0.015625s system = 2.718750s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.61107e-05
+PHY-3002 : Step(303): len = 649289, overlap = 261.25
+PHY-3002 : Step(304): len = 643135, overlap = 254.5
+PHY-3002 : Step(305): len = 640306, overlap = 245
+PHY-3002 : Step(306): len = 638472, overlap = 247.5
+PHY-3002 : Step(307): len = 637232, overlap = 254.5
+PHY-3002 : Step(308): len = 634963, overlap = 254.25
+PHY-3002 : Step(309): len = 633388, overlap = 253
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.22215e-05
+PHY-3002 : Step(310): len = 634504, overlap = 249
+PHY-3002 : Step(311): len = 639625, overlap = 240.75
+PHY-3002 : Step(312): len = 643376, overlap = 239.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000184443
+PHY-3002 : Step(313): len = 650570, overlap = 228
+PHY-3002 : Step(314): len = 661195, overlap = 212.5
+PHY-3002 : Step(315): len = 662888, overlap = 206
+PHY-3002 : Step(316): len = 663949, overlap = 204.75
+PHY-3002 : Step(317): len = 665401, overlap = 205.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.429493s wall, 0.375000s user + 0.687500s system = 1.062500s CPU (247.4%)
+
+PHY-3001 : Trial Legalized: Len = 744012
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_pakage_en_1d is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 844/17700.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 864856, over cnt = 2760(7%), over = 4646, worst = 8
+PHY-1002 : len = 881392, over cnt = 1786(5%), over = 2596, worst = 6
+PHY-1002 : len = 900952, over cnt = 760(2%), over = 1084, worst = 5
+PHY-1002 : len = 914528, over cnt = 200(0%), over = 285, worst = 4
+PHY-1002 : len = 918976, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.603110s wall, 3.734375s user + 0.015625s system = 3.750000s CPU (144.1%)
+
+PHY-1001 : Congestion index: top1 = 54.76, top5 = 49.97, top10 = 47.41, top15 = 45.56.
+PHY-3001 : End congestion estimation; 3.094948s wall, 4.234375s user + 0.015625s system = 4.250000s CPU (137.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17522 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.894734s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (101.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00016069
+PHY-3002 : Step(318): len = 717825, overlap = 49.75
+PHY-3002 : Step(319): len = 702725, overlap = 66.25
+PHY-3002 : Step(320): len = 689305, overlap = 98.5
+PHY-3002 : Step(321): len = 682117, overlap = 116.5
+PHY-3002 : Step(322): len = 676230, overlap = 136
+PHY-3002 : Step(323): len = 672632, overlap = 151.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00032138
+PHY-3002 : Step(324): len = 678972, overlap = 148.75
+PHY-3002 : Step(325): len = 684855, overlap = 146.75
+PHY-3002 : Step(326): len = 688550, overlap = 143
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000642759
+PHY-3002 : Step(327): len = 694181, overlap = 139.5
+PHY-3002 : Step(328): len = 706443, overlap = 140.25
+PHY-3002 : Step(329): len = 710467, overlap = 141.5
+PHY-3002 : Step(330): len = 711819, overlap = 141.25
+PHY-3002 : Step(331): len = 713978, overlap = 148.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.034592s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (90.3%)
+
+PHY-3001 : Legalized: Len = 740576, Over = 0
+PHY-3001 : Spreading special nets. 478 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.111958s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (97.7%)
+
+PHY-3001 : 684 instances has been re-located, deltaX = 238, deltaY = 420, maxDist = 6.
+PHY-3001 : Final: Len = 751936, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74401, tnet num: 17522, tinst num: 6850, tnode num: 96919, tedge num: 124862.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.940111s wall, 1.921875s user + 0.015625s system = 1.937500s CPU (99.9%)
+
+RUN-1004 : used memory is 628 MB, reserved memory is 646 MB, peak memory is 735 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_pakage_en_1d is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3313/17700.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 888352, over cnt = 2638(7%), over = 4290, worst = 6
+PHY-1002 : len = 904200, over cnt = 1404(3%), over = 1992, worst = 6
+PHY-1002 : len = 919592, over cnt = 549(1%), over = 747, worst = 5
+PHY-1002 : len = 928104, over cnt = 149(0%), over = 207, worst = 5
+PHY-1002 : len = 932136, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations; 2.319963s wall, 3.343750s user + 0.000000s system = 3.343750s CPU (144.1%)
+
+PHY-1001 : Congestion index: top1 = 54.35, top5 = 49.83, top10 = 47.18, top15 = 45.21.
+PHY-1001 : End incremental global routing; 2.700651s wall, 3.734375s user + 0.000000s system = 3.734375s CPU (138.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17522 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.932281s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (98.9%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6757 has valid locations, 23 needs to be replaced
+PHY-3001 : design contains 6868 instances, 6719 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3687 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 755541
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_pakage_en_1d is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16135/17725.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 935864, over cnt = 91(0%), over = 95, worst = 2
+PHY-1002 : len = 936040, over cnt = 51(0%), over = 54, worst = 2
+PHY-1002 : len = 936440, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 936480, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 936512, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.804913s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.0%)
+
+PHY-1001 : Congestion index: top1 = 54.35, top5 = 49.84, top10 = 47.23, top15 = 45.27.
+PHY-3001 : End congestion estimation; 1.132911s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74596, tnet num: 17547, tinst num: 6868, tnode num: 97164, tedge num: 125124.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.940752s wall, 1.906250s user + 0.031250s system = 1.937500s CPU (99.8%)
+
+RUN-1004 : used memory is 662 MB, reserved memory is 662 MB, peak memory is 735 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17547 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.886910s wall, 2.828125s user + 0.046875s system = 2.875000s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(332): len = 754564, overlap = 0
+PHY-3002 : Step(333): len = 754017, overlap = 0.5
+PHY-3002 : Step(334): len = 753684, overlap = 0.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_pakage_en_1d is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16126/17725.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 933488, over cnt = 80(0%), over = 101, worst = 5
+PHY-1002 : len = 933848, over cnt = 37(0%), over = 38, worst = 2
+PHY-1002 : len = 934168, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 934248, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.617608s wall, 0.640625s user + 0.031250s system = 0.671875s CPU (108.8%)
+
+PHY-1001 : Congestion index: top1 = 54.44, top5 = 49.91, top10 = 47.25, top15 = 45.26.
+PHY-3001 : End congestion estimation; 0.941446s wall, 0.968750s user + 0.031250s system = 1.000000s CPU (106.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17547 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.908280s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (101.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000338937
+PHY-3002 : Step(335): len = 754135, overlap = 1.75
+PHY-3002 : Step(336): len = 754158, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005848s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (267.2%)
+
+PHY-3001 : Legalized: Len = 754238, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064153s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.4%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 4, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 754290, Over = 0
+PHY-3001 : End incremental placement; 6.433550s wall, 6.500000s user + 0.156250s system = 6.656250s CPU (103.5%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.616434s wall, 11.671875s user + 0.187500s system = 11.859375s CPU (111.7%)
+
+OPT-1001 : Current memory(MB): used = 741, reserve = 744, peak = 745.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_pakage_en_1d is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16113/17725.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 934352, over cnt = 63(0%), over = 74, worst = 5
+PHY-1002 : len = 934552, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 934616, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 934632, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.732285s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (106.7%)
+
+PHY-1001 : Congestion index: top1 = 54.35, top5 = 49.88, top10 = 47.21, top15 = 45.24.
+OPT-1001 : End congestion update; 1.093365s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (105.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17547 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.830481s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.7%)
+
+OPT-0007 : Start: WNS -1436 TNS -2021 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6780 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6868 instances, 6719 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3687 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 759676, Over = 0
+PHY-3001 : Spreading special nets. 21 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063342s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.7%)
+
+PHY-3001 : 31 instances has been re-located, deltaX = 17, deltaY = 15, maxDist = 2.
+PHY-3001 : Final: Len = 760180, Over = 0
+PHY-3001 : End incremental legalization; 0.455440s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (99.5%)
+
+OPT-0007 : Iter 1: improved WNS -886 TNS -1371 NUM_FEPS 2 with 46 cells processed and 10550 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6780 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6868 instances, 6719 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3687 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 762762, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066332s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.2%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 6, deltaY = 7, maxDist = 1.
+PHY-3001 : Final: Len = 763006, Over = 0
+PHY-3001 : End incremental legalization; 0.460984s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (115.2%)
+
+OPT-0007 : Iter 2: improved WNS -986 TNS -1471 NUM_FEPS 2 with 13 cells processed and 3057 slack improved
+OPT-1001 : End path based optimization; 3.215627s wall, 3.531250s user + 0.000000s system = 3.531250s CPU (109.8%)
+
+OPT-1001 : Current memory(MB): used = 741, reserve = 744, peak = 745.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17547 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.789840s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (98.9%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_pakage_en_1d is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15845/17725.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 942744, over cnt = 166(0%), over = 198, worst = 5
+PHY-1002 : len = 942944, over cnt = 76(0%), over = 80, worst = 2
+PHY-1002 : len = 943592, over cnt = 19(0%), over = 20, worst = 2
+PHY-1002 : len = 943792, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 943832, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.012881s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (108.0%)
+
+PHY-1001 : Congestion index: top1 = 54.09, top5 = 49.81, top10 = 47.17, top15 = 45.24.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17547 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.833449s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (97.5%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -986 TNS -1471 NUM_FEPS 2
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 53.620690
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -986ps with logic level 2
+RUN-1001 : #2 path slack -940ps with logic level 2
+RUN-1001 : extra opt step will be enabled to improve QoR
+RUN-1001 : 0 HFN exist on timing critical paths out of 17725 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 17725 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6780 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6868 instances, 6719 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3687 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 763006, Over = 0
+PHY-3001 : End spreading; 0.063514s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (123.0%)
+
+PHY-3001 : Final: Len = 763006, Over = 0
+PHY-3001 : End incremental legalization; 0.436095s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17547 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.764746s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.1%)
+
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Start: WNS -986 TNS -1471 NUM_FEPS 2
+OPT-1001 : Process HFN debug[3]_dup_1 with 3 loads
+OPT-1001 : duplicate driver cell reg29_syn_13_hfnopt2_0 for 1 loads of net debug[3]_dup_1
+OPT-1001 : duplicate driver cell reg29_syn_13_hfnopt2_1 for 1 loads of net debug[3]_dup_1
+OPT-1001 : duplicate driver cell reg29_syn_13_hfnopt2_2 for 1 loads of net debug[3]_dup_1
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6779 has valid locations, 4 needs to be replaced
+PHY-3001 : design contains 6871 instances, 6722 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3690 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 763583
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_pakage_en_1d is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16150/17727.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 944408, over cnt = 1(0%), over = 2, worst = 2
+PHY-1002 : len = 944424, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.273325s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (102.9%)
+
+PHY-1001 : Congestion index: top1 = 54.05, top5 = 49.80, top10 = 47.17, top15 = 45.25.
+PHY-3001 : End congestion estimation; 0.613682s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (99.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74610, tnet num: 17549, tinst num: 6871, tnode num: 97184, tedge num: 125143.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.996745s wall, 1.984375s user + 0.015625s system = 2.000000s CPU (100.2%)
+
+RUN-1004 : used memory is 669 MB, reserved memory is 687 MB, peak memory is 745 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.019229s wall, 2.953125s user + 0.046875s system = 3.000000s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(337): len = 763632, overlap = 0
+PHY-3002 : Step(338): len = 763291, overlap = 0
+PHY-3002 : Step(339): len = 763212, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_pakage_en_1d is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16148/17727.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 944048, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 944040, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 944040, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 944088, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.613255s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (99.4%)
+
+PHY-1001 : Congestion index: top1 = 54.09, top5 = 49.80, top10 = 47.16, top15 = 45.24.
+PHY-3001 : End congestion estimation; 0.955158s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (99.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.914303s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00694352
+PHY-3002 : Step(340): len = 763106, overlap = 0.25
+PHY-3002 : Step(341): len = 763065, overlap = 0.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005398s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (289.4%)
+
+PHY-3001 : Legalized: Len = 763123, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062869s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.4%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 2, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 763155, Over = 0
+PHY-3001 : End incremental placement; 6.014261s wall, 5.953125s user + 0.093750s system = 6.046875s CPU (100.5%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+DBG-001 : Processed HFN with EG_PHY_MSLICE driver reg29_syn_13 fanout #3, crit_level 6, duplicated cnt 3 in non crit mode
+RUN-1001 : HFN opt statistic
+RUN-1001 : ------------------------------------------------------------------------------------
+RUN-1001 : DriverCell type | HFN count | HFN count with highcritlevel | Duplicated count
+RUN-1001 : ------------------------------------------------------------------------------------
+RUN-1001 : LSLICE | 0 | 0 | 0
+RUN-1001 : MSLICE | 0 | 0 | 0
+RUN-1001 : OTHER | 1 | 1 | 3
+RUN-1001 : ------------------------------------------------------------------------------------
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_pakage_en_1d is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16137/17727.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 944032, over cnt = 13(0%), over = 14, worst = 2
+PHY-1002 : len = 944088, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 944120, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.435102s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.6%)
+
+PHY-1001 : Congestion index: top1 = 54.09, top5 = 49.83, top10 = 47.18, top15 = 45.25.
+PHY-1001 : End incremental global routing; 0.760399s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.875819s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.9%)
+
+OPT-1001 : Current memory(MB): used = 742, reserve = 745, peak = 746.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_pakage_en_1d is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16153/17727.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 944120, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.136043s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.9%)
+
+PHY-1001 : Congestion index: top1 = 54.09, top5 = 49.83, top10 = 47.18, top15 = 45.25.
+OPT-1001 : End congestion update; 0.461087s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (98.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.750560s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.9%)
+
+OPT-0007 : Start: WNS -1086 TNS -1571 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6783 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6871 instances, 6722 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3690 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 763259, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062253s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (75.3%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 2, deltaY = 1, maxDist = 3.
+PHY-3001 : Final: Len = 763155, Over = 0
+PHY-3001 : End incremental legalization; 0.407929s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.6%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1421 NUM_FEPS 2 with 1 cells processed and 150 slack improved
+OPT-0007 : Iter 2: improved WNS -936 TNS -1421 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.740164s wall, 1.843750s user + 0.000000s system = 1.843750s CPU (106.0%)
+
+OPT-1001 : Current memory(MB): used = 743, reserve = 745, peak = 746.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_pakage_en_1d is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16153/17727.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 944120, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.136917s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.7%)
+
+PHY-1001 : Congestion index: top1 = 54.09, top5 = 49.83, top10 = 47.18, top15 = 45.25.
+OPT-1001 : End congestion update; 0.468757s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (100.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.744139s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.8%)
+
+OPT-0007 : Start: WNS -1086 TNS -1571 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6783 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6871 instances, 6722 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3690 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 763151, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063377s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.6%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 0, deltaY = 2, maxDist = 1.
+PHY-3001 : Final: Len = 763141, Over = 0
+PHY-3001 : End incremental legalization; 0.436439s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.2%)
+
+OPT-0007 : Iter 1: improved WNS -986 TNS -1471 NUM_FEPS 2 with 1 cells processed and 100 slack improved
+OPT-0007 : Iter 2: improved WNS -986 TNS -1471 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS -986 TNS -1471 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 1.923858s wall, 1.921875s user + 0.000000s system = 1.921875s CPU (99.9%)
+
+OPT-1001 : Current memory(MB): used = 743, reserve = 745, peak = 746.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.785363s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.5%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 743, reserve = 745, peak = 746.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.812926s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (98.0%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_pakage_en_1d is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16148/17727.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 944120, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 944120, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.308130s wall, 0.281250s user + 0.031250s system = 0.312500s CPU (101.4%)
+
+PHY-1001 : Congestion index: top1 = 54.09, top5 = 49.83, top10 = 47.18, top15 = 45.26.
+RUN-1001 : End congestion update; 0.673435s wall, 0.640625s user + 0.031250s system = 0.671875s CPU (99.8%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.492361s wall, 1.453125s user + 0.031250s system = 1.484375s CPU (99.5%)
+
+OPT-1001 : Current memory(MB): used = 743, reserve = 745, peak = 746.
+OPT-1001 : End physical optimization; 34.638074s wall, 36.171875s user + 0.343750s system = 36.515625s CPU (105.4%)
+
+RUN-1003 : finish command "place" in 80.865594s wall, 116.390625s user + 7.500000s system = 123.890625s CPU (153.2%)
+
+RUN-1004 : used memory is 646 MB, reserved memory is 661 MB, peak memory is 746 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.888333s wall, 3.296875s user + 0.015625s system = 3.312500s CPU (175.4%)
+
+RUN-1004 : used memory is 646 MB, reserved memory is 662 MB, peak memory is 746 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6873 instances
+RUN-1001 : 3368 mslices, 3354 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17727 nets
+RUN-6002 WARNING: There are 2 undriven nets.
+RUN-6004 WARNING: There are 23 nets with only 1 pin.
+RUN-1001 : 10059 nets have 2 pins
+RUN-1001 : 5808 nets have [3 - 5] pins
+RUN-1001 : 1125 nets have [6 - 10] pins
+RUN-1001 : 336 nets have [11 - 20] pins
+RUN-1001 : 368 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74610, tnet num: 17549, tinst num: 6871, tnode num: 97184, tedge num: 125143.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.752341s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (99.0%)
+
+RUN-1004 : used memory is 627 MB, reserved memory is 633 MB, peak memory is 746 MB
+PHY-1001 : 3368 mslices, 3354 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_pakage_en_1d is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 876984, over cnt = 2756(7%), over = 4578, worst = 7
+PHY-1002 : len = 895176, over cnt = 1620(4%), over = 2316, worst = 7
+PHY-1002 : len = 909960, over cnt = 825(2%), over = 1163, worst = 7
+PHY-1002 : len = 927856, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 928048, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.300638s wall, 4.500000s user + 0.015625s system = 4.515625s CPU (136.8%)
+
+PHY-1001 : Congestion index: top1 = 53.81, top5 = 49.53, top10 = 46.92, top15 = 44.97.
+PHY-1001 : End global routing; 3.645682s wall, 4.843750s user + 0.015625s system = 4.859375s CPU (133.3%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 719, reserve = 722, peak = 746.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-5010 WARNING: Net S_hs_last is skipped due to 0 input or output
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 988, reserve = 992, peak = 988.
+PHY-1001 : End build detailed router design. 4.342927s wall, 4.250000s user + 0.078125s system = 4.328125s CPU (99.7%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 270528, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 6.017887s wall, 6.015625s user + 0.000000s system = 6.015625s CPU (100.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 270584, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.659252s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (94.8%)
+
+PHY-1001 : Current memory(MB): used = 1024, reserve = 1028, peak = 1024.
+PHY-1001 : End phase 1; 6.689721s wall, 6.640625s user + 0.000000s system = 6.640625s CPU (99.3%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.39322e+06, over cnt = 1897(0%), over = 1900, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1042, reserve = 1047, peak = 1042.
+PHY-1001 : End initial routed; 29.286478s wall, 71.921875s user + 0.328125s system = 72.250000s CPU (246.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 11/16647(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -2.172 | -4.167 | 4
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.468863s wall, 3.468750s user + 0.000000s system = 3.468750s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1055, reserve = 1060, peak = 1055.
+PHY-1001 : End phase 2; 32.755405s wall, 75.390625s user + 0.328125s system = 75.718750s CPU (231.2%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 5 pins with SWNS -2.049ns STNS -3.984ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.159286s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (98.1%)
+
+PHY-1022 : len = 2.39324e+06, over cnt = 1902(0%), over = 1905, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.450005s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.35586e+06, over cnt = 654(0%), over = 656, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.505358s wall, 2.640625s user + 0.000000s system = 2.640625s CPU (175.4%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.35371e+06, over cnt = 128(0%), over = 128, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.837602s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (130.6%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.35454e+06, over cnt = 22(0%), over = 22, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.392748s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (111.4%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.35494e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.232544s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (107.5%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.35496e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.169246s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16647(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -2.049 | -3.984 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.394440s wall, 3.375000s user + 0.000000s system = 3.375000s CPU (99.4%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 613 feed throughs used by 457 nets
+PHY-1001 : End commit to database; 2.412019s wall, 2.359375s user + 0.046875s system = 2.406250s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1159, reserve = 1167, peak = 1159.
+PHY-1001 : End phase 3; 9.806215s wall, 11.203125s user + 0.046875s system = 11.250000s CPU (114.7%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.754ns STNS -3.689ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.146862s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.8%)
+
+PHY-1022 : len = 2.35493e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.412393s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (102.3%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.754ns, -3.689ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16647(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.754 | -3.689 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.423835s wall, 3.421875s user + 0.000000s system = 3.421875s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 614 feed throughs used by 458 nets
+PHY-1001 : End commit to database; 2.459044s wall, 2.468750s user + 0.000000s system = 2.468750s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1168, reserve = 1176, peak = 1168.
+PHY-1001 : End phase 4; 6.324084s wall, 6.328125s user + 0.000000s system = 6.328125s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.35493e+06
+PHY-1001 : Current memory(MB): used = 1170, reserve = 1179, peak = 1170.
+PHY-1001 : End export database. 0.162087s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (106.0%)
+
+PHY-1001 : End detail routing; 60.491528s wall, 104.375000s user + 0.453125s system = 104.828125s CPU (173.3%)
+
+RUN-1003 : finish command "route" in 67.105729s wall, 112.187500s user + 0.468750s system = 112.656250s CPU (167.9%)
+
+RUN-1004 : used memory is 1095 MB, reserved memory is 1105 MB, peak memory is 1170 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10373 out of 19600 52.92%
+#reg 9373 out of 19600 47.82%
+#le 12475
+ #lut only 3102 out of 12475 24.87%
+ #reg only 2102 out of 12475 16.85%
+ #lut® 7271 out of 12475 58.28%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 20
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1822
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1434
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1341
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 951
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 140
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 68
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 25
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_266.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg45_syn_192.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P140 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P2 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P25 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P16 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P152 LVCMOS33 8 N/A NONE
+ paper_out OUTPUT P11 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P17 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P15 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12475 |9346 |1027 |9406 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |537 |458 |23 |437 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |101 |84 |4 |92 |4 |0 |
+| U_ecc_gen |ecc_gen |9 |9 |0 |7 |0 |0 |
+| U_crc16_24b |crc16_24b |39 |39 |0 |19 |0 |0 |
+| exdev_ctl_a |exdev_ctl |780 |382 |96 |588 |0 |0 |
+| u_ADconfig |AD_config |194 |120 |25 |146 |0 |0 |
+| u_gen_sp |gen_sp |266 |160 |71 |122 |0 |0 |
+| exdev_ctl_b |exdev_ctl |730 |400 |96 |539 |0 |0 |
+| u_ADconfig |AD_config |175 |124 |25 |122 |0 |0 |
+| u_gen_sp |gen_sp |252 |164 |71 |114 |0 |0 |
+| sampling_fe_a |sampling_fe |3042 |2468 |306 |2045 |25 |0 |
+| u0_soft_n |cdc_sync |5 |2 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |185 |124 |17 |146 |0 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_sort |sort |2822 |2330 |289 |1864 |25 |0 |
+| rddpram_ctl |rddpram_ctl |5 |2 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |2 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2445 |2073 |253 |1553 |22 |0 |
+| channelPart |channel_part_8478 |163 |159 |3 |126 |0 |0 |
+| fifo_adc |fifo_adc |66 |56 |9 |43 |0 |0 |
+| ram_switch |ram_switch |1902 |1596 |197 |1149 |0 |0 |
+| adc_addr_gen |adc_addr_gen |258 |230 |27 |126 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |15 |11 |3 |10 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |25 |22 |3 |12 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |10 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |27 |24 |3 |12 |0 |0 |
+| insert |insert |962 |686 |170 |653 |0 |0 |
+| ram_switch_state |ram_switch_state |682 |680 |0 |370 |0 |0 |
+| read_ram_i |read_ram |275 |229 |44 |198 |0 |0 |
+| read_ram_addr |read_ram_addr |217 |177 |40 |154 |0 |0 |
+| read_ram_data |read_ram_data |56 |50 |4 |42 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |340 |245 |36 |274 |3 |0 |
+| u0_soft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3277 |2523 |349 |2134 |25 |1 |
+| u0_soft_n |cdc_sync |5 |2 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |186 |94 |17 |148 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort_rev |3056 |2416 |332 |1951 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |6 |6 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2619 |2123 |290 |1576 |22 |1 |
+| channelPart |channel_part_8478 |233 |220 |3 |136 |0 |0 |
+| fifo_adc |fifo_adc |62 |53 |9 |45 |0 |1 |
+| ram_switch |ram_switch |1894 |1526 |197 |1140 |0 |0 |
+| adc_addr_gen |adc_addr_gen |230 |202 |27 |121 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |17 |13 |3 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |14 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |16 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| insert |insert |999 |662 |170 |701 |0 |0 |
+| ram_switch_state |ram_switch_state |665 |662 |0 |318 |0 |0 |
+| read_ram_i |read_ram_rev |392 |290 |81 |217 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |286 |202 |73 |152 |0 |0 |
+| read_ram_data |read_ram_data_rev |106 |88 |8 |65 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9997
+ #2 2 3828
+ #3 3 1408
+ #4 4 569
+ #5 5-10 1197
+ #6 11-50 609
+ #7 51-100 20
+ #8 >500 1
+ Average 2.91
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.159558s wall, 3.703125s user + 0.000000s system = 3.703125s CPU (171.5%)
+
+RUN-1004 : used memory is 1096 MB, reserved memory is 1107 MB, peak memory is 1170 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74610, tnet num: 17549, tinst num: 6871, tnode num: 97184, tedge num: 125143.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.664852s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (99.5%)
+
+RUN-1004 : used memory is 1101 MB, reserved memory is 1111 MB, peak memory is 1170 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.538759s wall, 1.531250s user + 0.000000s system = 1.531250s CPU (99.5%)
+
+RUN-1004 : used memory is 1103 MB, reserved memory is 1113 MB, peak memory is 1170 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6871
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17727, pip num: 176108
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 614
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3251 valid insts, and 485811 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 10.575798s wall, 63.390625s user + 0.203125s system = 63.593750s CPU (601.3%)
+
+RUN-1004 : used memory is 1268 MB, reserved memory is 1272 MB, peak memory is 1383 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240123_173017.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240123_173806.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240123_173806.log
new file mode 100644
index 0000000..0b259a1
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240123_173806.log
@@ -0,0 +1,1894 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Tue Jan 23 17:38:06 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.312477s wall, 2.203125s user + 0.093750s system = 2.296875s CPU (99.3%)
+
+RUN-1004 : used memory is 336 MB, reserved memory is 314 MB, peak memory is 340 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2946 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17751 instances
+RUN-0007 : 7488 luts, 9040 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20329 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13320 nets have 2 pins
+RUN-1001 : 5543 nets have [3 - 5] pins
+RUN-1001 : 1047 nets have [6 - 10] pins
+RUN-1001 : 168 nets have [11 - 20] pins
+RUN-1001 : 177 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 789
+RUN-1001 : No | No | Yes | 1968
+RUN-1001 : No | Yes | No | 3474
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 56
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 141
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17749 instances, 7488 luts, 9040 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 5913 pins
+PHY-0007 : Cell area utilization is 49%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85053, tnet num: 20151, tinst num: 17749, tnode num: 115138, tedge num: 136535.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.242541s wall, 1.203125s user + 0.015625s system = 1.218750s CPU (98.1%)
+
+RUN-1004 : used memory is 529 MB, reserved memory is 514 MB, peak memory is 529 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20151 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.124913s wall, 2.062500s user + 0.046875s system = 2.109375s CPU (99.3%)
+
+PHY-3001 : Found 1221 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 3.87272e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17749.
+PHY-3001 : Level 1 #clusters 1994.
+PHY-3001 : End clustering; 0.144746s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (107.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 49%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.30601e+06, overlap = 474.562
+PHY-3002 : Step(2): len = 1.18493e+06, overlap = 506.281
+PHY-3002 : Step(3): len = 888608, overlap = 546.469
+PHY-3002 : Step(4): len = 760675, overlap = 630.156
+PHY-3002 : Step(5): len = 597521, overlap = 780.781
+PHY-3002 : Step(6): len = 542110, overlap = 875.5
+PHY-3002 : Step(7): len = 477561, overlap = 954.188
+PHY-3002 : Step(8): len = 423131, overlap = 994
+PHY-3002 : Step(9): len = 382447, overlap = 1043.81
+PHY-3002 : Step(10): len = 347359, overlap = 1076.69
+PHY-3002 : Step(11): len = 310049, overlap = 1145.16
+PHY-3002 : Step(12): len = 282647, overlap = 1159.47
+PHY-3002 : Step(13): len = 258010, overlap = 1250.56
+PHY-3002 : Step(14): len = 235004, overlap = 1332.06
+PHY-3002 : Step(15): len = 212533, overlap = 1393.38
+PHY-3002 : Step(16): len = 191032, overlap = 1431.53
+PHY-3002 : Step(17): len = 176467, overlap = 1474.12
+PHY-3002 : Step(18): len = 161078, overlap = 1493.84
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.32138e-07
+PHY-3002 : Step(19): len = 161497, overlap = 1471
+PHY-3002 : Step(20): len = 191425, overlap = 1320.41
+PHY-3002 : Step(21): len = 194383, overlap = 1278.19
+PHY-3002 : Step(22): len = 197916, overlap = 1245.69
+PHY-3002 : Step(23): len = 191835, overlap = 1229.03
+PHY-3002 : Step(24): len = 187214, overlap = 1208.31
+PHY-3002 : Step(25): len = 183936, overlap = 1195.72
+PHY-3002 : Step(26): len = 182483, overlap = 1194.12
+PHY-3002 : Step(27): len = 181134, overlap = 1192.22
+PHY-3002 : Step(28): len = 180886, overlap = 1189.34
+PHY-3002 : Step(29): len = 179762, overlap = 1188.03
+PHY-3002 : Step(30): len = 178349, overlap = 1177.09
+PHY-3002 : Step(31): len = 177243, overlap = 1168.34
+PHY-3002 : Step(32): len = 176445, overlap = 1172.78
+PHY-3002 : Step(33): len = 174887, overlap = 1164.47
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.66428e-06
+PHY-3002 : Step(34): len = 178044, overlap = 1161.06
+PHY-3002 : Step(35): len = 190742, overlap = 1105.47
+PHY-3002 : Step(36): len = 195116, overlap = 1081.25
+PHY-3002 : Step(37): len = 199702, overlap = 1079.12
+PHY-3002 : Step(38): len = 201879, overlap = 1081.72
+PHY-3002 : Step(39): len = 203026, overlap = 1072.66
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.32855e-06
+PHY-3002 : Step(40): len = 208643, overlap = 1038.78
+PHY-3002 : Step(41): len = 222726, overlap = 1013.44
+PHY-3002 : Step(42): len = 229484, overlap = 963.5
+PHY-3002 : Step(43): len = 235024, overlap = 933.188
+PHY-3002 : Step(44): len = 236984, overlap = 913.344
+PHY-3002 : Step(45): len = 237318, overlap = 903.75
+PHY-3002 : Step(46): len = 235368, overlap = 904.75
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 6.65711e-06
+PHY-3002 : Step(47): len = 248210, overlap = 851.719
+PHY-3002 : Step(48): len = 278918, overlap = 737.625
+PHY-3002 : Step(49): len = 294865, overlap = 687.688
+PHY-3002 : Step(50): len = 301984, overlap = 639.062
+PHY-3002 : Step(51): len = 302296, overlap = 618.125
+PHY-3002 : Step(52): len = 298996, overlap = 601.25
+PHY-3002 : Step(53): len = 295627, overlap = 576.25
+PHY-3002 : Step(54): len = 293903, overlap = 572
+PHY-3002 : Step(55): len = 293415, overlap = 574.125
+PHY-3002 : Step(56): len = 294138, overlap = 580.719
+PHY-3002 : Step(57): len = 293661, overlap = 600.375
+PHY-3002 : Step(58): len = 293536, overlap = 604.656
+PHY-3002 : Step(59): len = 292948, overlap = 602.594
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.33142e-05
+PHY-3002 : Step(60): len = 308507, overlap = 550.5
+PHY-3002 : Step(61): len = 324193, overlap = 495.312
+PHY-3002 : Step(62): len = 327686, overlap = 449.531
+PHY-3002 : Step(63): len = 330410, overlap = 425.75
+PHY-3002 : Step(64): len = 330241, overlap = 422.875
+PHY-3002 : Step(65): len = 331715, overlap = 413.938
+PHY-3002 : Step(66): len = 331402, overlap = 424.812
+PHY-3002 : Step(67): len = 332689, overlap = 410.812
+PHY-3002 : Step(68): len = 333251, overlap = 424.719
+PHY-3002 : Step(69): len = 334428, overlap = 416
+PHY-3002 : Step(70): len = 333987, overlap = 411.344
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 2.66284e-05
+PHY-3002 : Step(71): len = 350858, overlap = 395.031
+PHY-3002 : Step(72): len = 366710, overlap = 356.281
+PHY-3002 : Step(73): len = 372324, overlap = 330.531
+PHY-3002 : Step(74): len = 373258, overlap = 322.625
+PHY-3002 : Step(75): len = 374614, overlap = 329.219
+PHY-3002 : Step(76): len = 376600, overlap = 324.75
+PHY-3002 : Step(77): len = 375732, overlap = 315.25
+PHY-3002 : Step(78): len = 375685, overlap = 313.156
+PHY-3002 : Step(79): len = 375713, overlap = 330.125
+PHY-3002 : Step(80): len = 377146, overlap = 328.531
+PHY-3002 : Step(81): len = 377875, overlap = 321.656
+PHY-3002 : Step(82): len = 378086, overlap = 327.344
+PHY-3002 : Step(83): len = 377607, overlap = 329.281
+PHY-3002 : Step(84): len = 378911, overlap = 329.75
+PHY-3002 : Step(85): len = 379833, overlap = 331.062
+PHY-3002 : Step(86): len = 379099, overlap = 325.656
+PHY-3002 : Step(87): len = 377846, overlap = 336
+PHY-3002 : Step(88): len = 379514, overlap = 345.781
+PHY-3002 : Step(89): len = 379723, overlap = 340.781
+PHY-3002 : Step(90): len = 378264, overlap = 328.031
+PHY-3002 : Step(91): len = 376984, overlap = 312.312
+PHY-3002 : Step(92): len = 377082, overlap = 303.562
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 5.32569e-05
+PHY-3002 : Step(93): len = 392649, overlap = 267.156
+PHY-3002 : Step(94): len = 401156, overlap = 257.219
+PHY-3002 : Step(95): len = 399349, overlap = 253.625
+PHY-3002 : Step(96): len = 400584, overlap = 252.25
+PHY-3002 : Step(97): len = 405095, overlap = 243.656
+PHY-3002 : Step(98): len = 407456, overlap = 248.375
+PHY-3002 : Step(99): len = 405200, overlap = 249.156
+PHY-3002 : Step(100): len = 405964, overlap = 241.562
+PHY-3002 : Step(101): len = 408588, overlap = 239.031
+PHY-3002 : Step(102): len = 410648, overlap = 236.75
+PHY-3002 : Step(103): len = 408651, overlap = 253.25
+PHY-3002 : Step(104): len = 409698, overlap = 239.938
+PHY-3002 : Step(105): len = 410964, overlap = 225.375
+PHY-3002 : Step(106): len = 411994, overlap = 224.438
+PHY-3002 : Step(107): len = 410657, overlap = 240.094
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000100885
+PHY-3002 : Step(108): len = 424786, overlap = 192.031
+PHY-3002 : Step(109): len = 433350, overlap = 178.344
+PHY-3002 : Step(110): len = 431515, overlap = 194.531
+PHY-3002 : Step(111): len = 431726, overlap = 195.469
+PHY-3002 : Step(112): len = 433899, overlap = 186.469
+PHY-3002 : Step(113): len = 436013, overlap = 183.812
+PHY-3002 : Step(114): len = 434689, overlap = 184.969
+PHY-3002 : Step(115): len = 435618, overlap = 188.438
+PHY-3002 : Step(116): len = 438352, overlap = 179.25
+PHY-3002 : Step(117): len = 440041, overlap = 177.219
+PHY-3002 : Step(118): len = 437621, overlap = 182.281
+PHY-3002 : Step(119): len = 437311, overlap = 186.656
+PHY-3002 : Step(120): len = 438832, overlap = 188.656
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.00020177
+PHY-3002 : Step(121): len = 452573, overlap = 166.75
+PHY-3002 : Step(122): len = 463883, overlap = 160.531
+PHY-3002 : Step(123): len = 463057, overlap = 164.375
+PHY-3002 : Step(124): len = 463732, overlap = 162.938
+PHY-3002 : Step(125): len = 467568, overlap = 155.625
+PHY-3002 : Step(126): len = 469787, overlap = 147.625
+PHY-3002 : Step(127): len = 467186, overlap = 154.875
+PHY-3002 : Step(128): len = 467498, overlap = 160.344
+PHY-3002 : Step(129): len = 471916, overlap = 159.938
+PHY-3002 : Step(130): len = 476564, overlap = 158.031
+PHY-3002 : Step(131): len = 475316, overlap = 157.656
+PHY-3002 : Step(132): len = 476957, overlap = 151.562
+PHY-3002 : Step(133): len = 480076, overlap = 137.531
+PHY-3002 : Step(134): len = 481577, overlap = 143.375
+PHY-3002 : Step(135): len = 478954, overlap = 144.094
+PHY-3002 : Step(136): len = 478190, overlap = 151.031
+PHY-3002 : Step(137): len = 479214, overlap = 143.906
+PHY-3002 : Step(138): len = 479721, overlap = 136.656
+PHY-3002 : Step(139): len = 477756, overlap = 143.375
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000386982
+PHY-3002 : Step(140): len = 485476, overlap = 141.969
+PHY-3002 : Step(141): len = 490130, overlap = 140.094
+PHY-3002 : Step(142): len = 490142, overlap = 138.562
+PHY-3002 : Step(143): len = 490546, overlap = 138.25
+PHY-3002 : Step(144): len = 493148, overlap = 136.219
+PHY-3002 : Step(145): len = 494805, overlap = 136.406
+PHY-3002 : Step(146): len = 493651, overlap = 134.281
+PHY-3002 : Step(147): len = 494099, overlap = 131.25
+PHY-3002 : Step(148): len = 496842, overlap = 135.188
+PHY-3002 : Step(149): len = 497787, overlap = 131.844
+PHY-3002 : Step(150): len = 496249, overlap = 128.438
+PHY-3002 : Step(151): len = 495742, overlap = 126.25
+PHY-3002 : Step(152): len = 497768, overlap = 128.281
+PHY-3002 : Step(153): len = 500219, overlap = 121.375
+PHY-3002 : Step(154): len = 498341, overlap = 121.656
+PHY-3002 : Step(155): len = 497917, overlap = 120.594
+PHY-3002 : Step(156): len = 498871, overlap = 124.438
+PHY-3002 : Step(157): len = 499321, overlap = 122.438
+PHY-3002 : Step(158): len = 497960, overlap = 120
+PHY-3002 : Step(159): len = 497620, overlap = 119.312
+PHY-3002 : Step(160): len = 498664, overlap = 111.344
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000742668
+PHY-3002 : Step(161): len = 503009, overlap = 114.906
+PHY-3002 : Step(162): len = 509106, overlap = 109.906
+PHY-3002 : Step(163): len = 511173, overlap = 108.875
+PHY-3002 : Step(164): len = 513152, overlap = 111.062
+PHY-3002 : Step(165): len = 515282, overlap = 108.969
+PHY-3002 : Step(166): len = 516304, overlap = 108.844
+PHY-3002 : Step(167): len = 515433, overlap = 105.344
+PHY-3002 : Step(168): len = 515361, overlap = 107.125
+PHY-3002 : Step(169): len = 515851, overlap = 108.031
+PHY-3002 : Step(170): len = 516005, overlap = 107.719
+PHY-3002 : Step(171): len = 516141, overlap = 106.219
+PHY-3002 : Step(172): len = 516523, overlap = 106.594
+PHY-3002 : Step(173): len = 517028, overlap = 106.844
+PHY-3002 : Step(174): len = 517144, overlap = 108.719
+PHY-3002 : Step(175): len = 516992, overlap = 101.969
+PHY-3002 : Step(176): len = 517020, overlap = 102.719
+PHY-3002 : Step(177): len = 517600, overlap = 106.25
+PHY-3002 : Step(178): len = 517953, overlap = 106.625
+PHY-3002 : Step(179): len = 518160, overlap = 104.312
+PHY-3002 : Step(180): len = 518291, overlap = 101.75
+PHY-3002 : Step(181): len = 519237, overlap = 104.812
+PHY-3002 : Step(182): len = 520219, overlap = 108.5
+PHY-3002 : Step(183): len = 520115, overlap = 106.375
+PHY-3002 : Step(184): len = 520095, overlap = 106.312
+PHY-3002 : Step(185): len = 519921, overlap = 106.875
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00124578
+PHY-3002 : Step(186): len = 522739, overlap = 106.906
+PHY-3002 : Step(187): len = 526133, overlap = 105.469
+PHY-3002 : Step(188): len = 526360, overlap = 103.844
+PHY-3002 : Step(189): len = 526641, overlap = 106.594
+PHY-3002 : Step(190): len = 527781, overlap = 107.656
+PHY-3002 : Step(191): len = 528332, overlap = 107.344
+PHY-3002 : Step(192): len = 527947, overlap = 107.625
+PHY-3002 : Step(193): len = 527903, overlap = 106.562
+PHY-3002 : Step(194): len = 529107, overlap = 108.312
+PHY-3002 : Step(195): len = 529741, overlap = 106.438
+PHY-3002 : Step(196): len = 529501, overlap = 106.219
+PHY-3002 : Step(197): len = 529490, overlap = 106.719
+PHY-3002 : Step(198): len = 530139, overlap = 106
+PHY-3002 : Step(199): len = 530782, overlap = 104.594
+PHY-3002 : Step(200): len = 530670, overlap = 105.5
+PHY-3002 : Step(201): len = 530708, overlap = 105.656
+PHY-3002 : Step(202): len = 531472, overlap = 104.75
+PHY-3002 : Step(203): len = 532282, overlap = 105.062
+PHY-3002 : Step(204): len = 532287, overlap = 104.875
+PHY-3002 : Step(205): len = 532448, overlap = 105.25
+PHY-3002 : Step(206): len = 532959, overlap = 100.25
+PHY-3002 : Step(207): len = 533182, overlap = 100.594
+PHY-3002 : Step(208): len = 533715, overlap = 98.4062
+PHY-3002 : Step(209): len = 534982, overlap = 102.031
+PHY-3002 : Step(210): len = 536265, overlap = 99.8125
+PHY-3002 : Step(211): len = 536721, overlap = 97.6875
+PHY-3002 : Step(212): len = 536982, overlap = 100.156
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00203865
+PHY-3002 : Step(213): len = 538210, overlap = 98.1875
+PHY-3002 : Step(214): len = 538767, overlap = 100.219
+PHY-3002 : Step(215): len = 539065, overlap = 100.781
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.015850s wall, 0.015625s user + 0.031250s system = 0.046875s CPU (295.7%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20329.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 703024, over cnt = 1596(4%), over = 7137, worst = 30
+PHY-1001 : End global iterations; 0.768668s wall, 1.109375s user + 0.015625s system = 1.125000s CPU (146.4%)
+
+PHY-1001 : Congestion index: top1 = 77.74, top5 = 59.26, top10 = 50.61, top15 = 45.51.
+PHY-3001 : End congestion estimation; 1.045389s wall, 1.359375s user + 0.046875s system = 1.406250s CPU (134.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20151 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.912527s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (97.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000123338
+PHY-3002 : Step(216): len = 636013, overlap = 55.25
+PHY-3002 : Step(217): len = 643950, overlap = 56.0312
+PHY-3002 : Step(218): len = 640757, overlap = 58.4062
+PHY-3002 : Step(219): len = 641452, overlap = 57.875
+PHY-3002 : Step(220): len = 641226, overlap = 54.8125
+PHY-3002 : Step(221): len = 640747, overlap = 47.6562
+PHY-3002 : Step(222): len = 638327, overlap = 45.625
+PHY-3002 : Step(223): len = 638249, overlap = 39.3438
+PHY-3002 : Step(224): len = 638212, overlap = 36.0312
+PHY-3002 : Step(225): len = 635699, overlap = 34.4062
+PHY-3002 : Step(226): len = 634217, overlap = 33
+PHY-3002 : Step(227): len = 631546, overlap = 32.1562
+PHY-3002 : Step(228): len = 630418, overlap = 34.9688
+PHY-3002 : Step(229): len = 628930, overlap = 33.3438
+PHY-3002 : Step(230): len = 627735, overlap = 31.4688
+PHY-3002 : Step(231): len = 627632, overlap = 30.0625
+PHY-3002 : Step(232): len = 626140, overlap = 33.4688
+PHY-3002 : Step(233): len = 624809, overlap = 29.5938
+PHY-3002 : Step(234): len = 623738, overlap = 30.0625
+PHY-3002 : Step(235): len = 622396, overlap = 28.3438
+PHY-3002 : Step(236): len = 622091, overlap = 27.7812
+PHY-3002 : Step(237): len = 620449, overlap = 25.5938
+PHY-3002 : Step(238): len = 619583, overlap = 26.5
+PHY-3002 : Step(239): len = 618849, overlap = 23.9375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000246677
+PHY-3002 : Step(240): len = 620967, overlap = 23.0625
+PHY-3002 : Step(241): len = 622322, overlap = 23.4375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 87/20329.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 714912, over cnt = 2587(7%), over = 10815, worst = 40
+PHY-1001 : End global iterations; 1.978130s wall, 2.562500s user + 0.031250s system = 2.593750s CPU (131.1%)
+
+PHY-1001 : Congestion index: top1 = 78.66, top5 = 62.56, top10 = 54.88, top15 = 50.20.
+PHY-3001 : End congestion estimation; 2.292968s wall, 2.859375s user + 0.031250s system = 2.890625s CPU (126.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20151 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.973803s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (97.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.60391e-05
+PHY-3002 : Step(242): len = 620665, overlap = 248.531
+PHY-3002 : Step(243): len = 624625, overlap = 204.375
+PHY-3002 : Step(244): len = 622386, overlap = 179.219
+PHY-3002 : Step(245): len = 620594, overlap = 166.312
+PHY-3002 : Step(246): len = 621554, overlap = 154.219
+PHY-3002 : Step(247): len = 617100, overlap = 146.406
+PHY-3002 : Step(248): len = 614371, overlap = 144.625
+PHY-3002 : Step(249): len = 611794, overlap = 143.844
+PHY-3002 : Step(250): len = 608880, overlap = 141.625
+PHY-3002 : Step(251): len = 606596, overlap = 140.75
+PHY-3002 : Step(252): len = 604151, overlap = 142.594
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000192078
+PHY-3002 : Step(253): len = 604228, overlap = 141.25
+PHY-3002 : Step(254): len = 605307, overlap = 139.594
+PHY-3002 : Step(255): len = 608528, overlap = 132.844
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000384156
+PHY-3002 : Step(256): len = 614231, overlap = 120.531
+PHY-3002 : Step(257): len = 620121, overlap = 111.188
+PHY-3002 : Step(258): len = 625256, overlap = 105.062
+PHY-3002 : Step(259): len = 625448, overlap = 101.094
+PHY-3002 : Step(260): len = 626224, overlap = 106.938
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000768313
+PHY-3002 : Step(261): len = 629764, overlap = 100.938
+PHY-3002 : Step(262): len = 637326, overlap = 99
+PHY-3002 : Step(263): len = 643260, overlap = 99.4062
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85053, tnet num: 20151, tinst num: 17749, tnode num: 115138, tedge num: 136535.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.601892s wall, 1.562500s user + 0.031250s system = 1.593750s CPU (99.5%)
+
+RUN-1004 : used memory is 574 MB, reserved memory is 564 MB, peak memory is 710 MB
+OPT-1001 : Total overflow 419.75 peak overflow 3.97
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1271/20329.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 748544, over cnt = 3189(9%), over = 11299, worst = 23
+PHY-1001 : End global iterations; 1.246093s wall, 1.968750s user + 0.015625s system = 1.984375s CPU (159.2%)
+
+PHY-1001 : Congestion index: top1 = 72.18, top5 = 58.80, top10 = 52.44, top15 = 48.48.
+PHY-1001 : End incremental global routing; 1.633084s wall, 2.343750s user + 0.015625s system = 2.359375s CPU (144.5%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20151 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.134482s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.2%)
+
+OPT-1001 : 49 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17615 has valid locations, 323 needs to be replaced
+PHY-3001 : design contains 18023 instances, 7585 luts, 9217 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 6038 pins
+PHY-3001 : Found 1233 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 667488
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16819/20603.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 762024, over cnt = 3226(9%), over = 11355, worst = 23
+PHY-1001 : End global iterations; 0.268635s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (139.6%)
+
+PHY-1001 : Congestion index: top1 = 72.05, top5 = 59.12, top10 = 52.76, top15 = 48.95.
+PHY-3001 : End congestion estimation; 0.532255s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (123.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86155, tnet num: 20425, tinst num: 18023, tnode num: 116775, tedge num: 138191.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.539394s wall, 1.515625s user + 0.015625s system = 1.531250s CPU (99.5%)
+
+RUN-1004 : used memory is 616 MB, reserved memory is 614 MB, peak memory is 713 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20425 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.535007s wall, 2.484375s user + 0.046875s system = 2.531250s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(264): len = 666471, overlap = 0
+PHY-3002 : Step(265): len = 666093, overlap = 0
+PHY-3002 : Step(266): len = 665930, overlap = 0
+PHY-3002 : Step(267): len = 665817, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16917/20603.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 760216, over cnt = 3236(9%), over = 11405, worst = 23
+PHY-1001 : End global iterations; 0.222035s wall, 0.281250s user + 0.015625s system = 0.296875s CPU (133.7%)
+
+PHY-1001 : Congestion index: top1 = 73.12, top5 = 59.60, top10 = 53.11, top15 = 49.15.
+PHY-3001 : End congestion estimation; 0.507671s wall, 0.562500s user + 0.015625s system = 0.578125s CPU (113.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20425 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.966344s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00045159
+PHY-3002 : Step(268): len = 665744, overlap = 102.062
+PHY-3002 : Step(269): len = 665776, overlap = 102.156
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00090318
+PHY-3002 : Step(270): len = 666141, overlap = 102.375
+PHY-3002 : Step(271): len = 666604, overlap = 102.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00176571
+PHY-3002 : Step(272): len = 666761, overlap = 102.406
+PHY-3002 : Step(273): len = 667541, overlap = 102.062
+PHY-3001 : Final: Len = 667541, Over = 102.062
+PHY-3001 : End incremental placement; 5.433542s wall, 5.859375s user + 0.234375s system = 6.093750s CPU (112.2%)
+
+OPT-1001 : Total overflow 425.44 peak overflow 3.97
+OPT-1001 : End high-fanout net optimization; 8.881425s wall, 10.125000s user + 0.250000s system = 10.375000s CPU (116.8%)
+
+OPT-1001 : Current memory(MB): used = 715, reserve = 710, peak = 732.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16841/20603.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 764712, over cnt = 3164(8%), over = 10252, worst = 23
+PHY-1002 : len = 818192, over cnt = 2145(6%), over = 5172, worst = 23
+PHY-1002 : len = 859872, over cnt = 893(2%), over = 1893, worst = 17
+PHY-1002 : len = 878248, over cnt = 405(1%), over = 771, worst = 14
+PHY-1002 : len = 894816, over cnt = 3(0%), over = 4, worst = 2
+PHY-1001 : End global iterations; 1.682860s wall, 2.562500s user + 0.000000s system = 2.562500s CPU (152.3%)
+
+PHY-1001 : Congestion index: top1 = 60.02, top5 = 52.14, top10 = 48.54, top15 = 46.16.
+OPT-1001 : End congestion update; 1.968267s wall, 2.843750s user + 0.000000s system = 2.843750s CPU (144.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20425 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.010570s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (83.5%)
+
+OPT-0007 : Start: WNS -1168 TNS -1628 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 84 cells processed and 6884 slack improved
+OPT-0007 : Iter 2: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 17 cells processed and 1458 slack improved
+OPT-0007 : Iter 3: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 11 cells processed and 450 slack improved
+OPT-1001 : End global optimization; 3.018634s wall, 3.687500s user + 0.031250s system = 3.718750s CPU (123.2%)
+
+OPT-1001 : Current memory(MB): used = 692, reserve = 689, peak = 732.
+OPT-1001 : End physical optimization; 14.161182s wall, 16.125000s user + 0.312500s system = 16.437500s CPU (116.1%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7585 LUT to BLE ...
+SYN-4008 : Packed 7585 LUT and 3081 SEQ to BLE.
+SYN-4003 : Packing 6136 remaining SEQ's ...
+SYN-4005 : Packed 3937 SEQ with LUT/SLICE
+SYN-4006 : 847 single LUT's are left
+SYN-4006 : 2199 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9784/13515 primitive instances ...
+PHY-3001 : End packing; 1.824465s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (100.2%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6848 instances
+RUN-1001 : 3350 mslices, 3350 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17653 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9990 nets have 2 pins
+RUN-1001 : 5824 nets have [3 - 5] pins
+RUN-1001 : 1143 nets have [6 - 10] pins
+RUN-1001 : 319 nets have [11 - 20] pins
+RUN-1001 : 344 nets have [21 - 99] pins
+RUN-1001 : 13 nets have 100+ pins
+PHY-3001 : design contains 6846 instances, 6700 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3573 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 677688, Over = 278.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7360/17653.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 835424, over cnt = 2031(5%), over = 3263, worst = 9
+PHY-1002 : len = 840664, over cnt = 1494(4%), over = 2226, worst = 9
+PHY-1002 : len = 859256, over cnt = 503(1%), over = 693, worst = 9
+PHY-1002 : len = 866664, over cnt = 153(0%), over = 197, worst = 4
+PHY-1002 : len = 870312, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.709808s wall, 2.421875s user + 0.015625s system = 2.437500s CPU (142.6%)
+
+PHY-1001 : Congestion index: top1 = 58.71, top5 = 52.05, top10 = 47.94, top15 = 45.36.
+PHY-3001 : End congestion estimation; 2.120855s wall, 2.828125s user + 0.015625s system = 2.843750s CPU (134.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74266, tnet num: 17475, tinst num: 6846, tnode num: 96696, tedge num: 124693.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.689614s wall, 1.625000s user + 0.046875s system = 1.671875s CPU (99.0%)
+
+RUN-1004 : used memory is 609 MB, reserved memory is 611 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17475 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.624319s wall, 2.515625s user + 0.093750s system = 2.609375s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.92706e-05
+PHY-3002 : Step(274): len = 663813, overlap = 278
+PHY-3002 : Step(275): len = 656989, overlap = 274
+PHY-3002 : Step(276): len = 652804, overlap = 269.75
+PHY-3002 : Step(277): len = 650188, overlap = 275
+PHY-3002 : Step(278): len = 647911, overlap = 272.75
+PHY-3002 : Step(279): len = 646645, overlap = 274.25
+PHY-3002 : Step(280): len = 643841, overlap = 276
+PHY-3002 : Step(281): len = 641700, overlap = 274
+PHY-3002 : Step(282): len = 639307, overlap = 273.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.85411e-05
+PHY-3002 : Step(283): len = 641598, overlap = 270.75
+PHY-3002 : Step(284): len = 648034, overlap = 260
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000197082
+PHY-3002 : Step(285): len = 654845, overlap = 252.5
+PHY-3002 : Step(286): len = 668916, overlap = 232.25
+PHY-3002 : Step(287): len = 669197, overlap = 223.25
+PHY-3002 : Step(288): len = 669384, overlap = 220.25
+PHY-3002 : Step(289): len = 669586, overlap = 220.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.391056s wall, 0.453125s user + 0.453125s system = 0.906250s CPU (231.7%)
+
+PHY-3001 : Trial Legalized: Len = 760274
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 797/17653.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 886056, over cnt = 2845(8%), over = 4808, worst = 8
+PHY-1002 : len = 902912, over cnt = 1840(5%), over = 2764, worst = 8
+PHY-1002 : len = 926256, over cnt = 694(1%), over = 1052, worst = 7
+PHY-1002 : len = 936600, over cnt = 286(0%), over = 438, worst = 5
+PHY-1002 : len = 943968, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.626371s wall, 3.781250s user + 0.031250s system = 3.812500s CPU (145.2%)
+
+PHY-1001 : Congestion index: top1 = 57.35, top5 = 52.16, top10 = 49.28, top15 = 47.23.
+PHY-3001 : End congestion estimation; 3.112389s wall, 4.265625s user + 0.031250s system = 4.296875s CPU (138.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17475 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.901773s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (100.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000160075
+PHY-3002 : Step(290): len = 731170, overlap = 46.75
+PHY-3002 : Step(291): len = 715477, overlap = 73.5
+PHY-3002 : Step(292): len = 701504, overlap = 99.25
+PHY-3002 : Step(293): len = 692938, overlap = 120.5
+PHY-3002 : Step(294): len = 686075, overlap = 149
+PHY-3002 : Step(295): len = 683281, overlap = 155.5
+PHY-3002 : Step(296): len = 681605, overlap = 159.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000320151
+PHY-3002 : Step(297): len = 686514, overlap = 158.5
+PHY-3002 : Step(298): len = 693478, overlap = 154.75
+PHY-3002 : Step(299): len = 697623, overlap = 148
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000640302
+PHY-3002 : Step(300): len = 703226, overlap = 144.5
+PHY-3002 : Step(301): len = 715989, overlap = 143.75
+PHY-3002 : Step(302): len = 720218, overlap = 142.75
+PHY-3002 : Step(303): len = 720731, overlap = 142.75
+PHY-3002 : Step(304): len = 721887, overlap = 142.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.035319s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (88.5%)
+
+PHY-3001 : Legalized: Len = 748503, Over = 0
+PHY-3001 : Spreading special nets. 468 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.111957s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (97.7%)
+
+PHY-3001 : 689 instances has been re-located, deltaX = 254, deltaY = 381, maxDist = 3.
+PHY-3001 : Final: Len = 758271, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74266, tnet num: 17475, tinst num: 6849, tnode num: 96696, tedge num: 124693.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.947399s wall, 1.921875s user + 0.031250s system = 1.953125s CPU (100.3%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 607 MB, peak memory is 732 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3196/17653.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 894616, over cnt = 2612(7%), over = 4292, worst = 7
+PHY-1002 : len = 908408, over cnt = 1661(4%), over = 2484, worst = 6
+PHY-1002 : len = 921576, over cnt = 864(2%), over = 1331, worst = 6
+PHY-1002 : len = 934896, over cnt = 292(0%), over = 473, worst = 6
+PHY-1002 : len = 943744, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.274770s wall, 3.296875s user + 0.015625s system = 3.312500s CPU (145.6%)
+
+PHY-1001 : Congestion index: top1 = 56.94, top5 = 51.26, top10 = 48.22, top15 = 46.18.
+PHY-1001 : End incremental global routing; 2.684245s wall, 3.687500s user + 0.015625s system = 3.703125s CPU (138.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17475 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.922980s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (99.9%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6756 has valid locations, 22 needs to be replaced
+PHY-3001 : design contains 6866 instances, 6717 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3655 pins
+PHY-3001 : Found 503 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 761110
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16070/17671.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 946400, over cnt = 77(0%), over = 95, worst = 4
+PHY-1002 : len = 946672, over cnt = 26(0%), over = 26, worst = 1
+PHY-1002 : len = 946864, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 947048, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.709493s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (110.1%)
+
+PHY-1001 : Congestion index: top1 = 56.94, top5 = 51.28, top10 = 48.25, top15 = 46.22.
+PHY-3001 : End congestion estimation; 1.068241s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (106.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74418, tnet num: 17493, tinst num: 6866, tnode num: 96890, tedge num: 124901.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.049304s wall, 2.046875s user + 0.000000s system = 2.046875s CPU (99.9%)
+
+RUN-1004 : used memory is 662 MB, reserved memory is 667 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.041031s wall, 3.031250s user + 0.000000s system = 3.031250s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(305): len = 760722, overlap = 0
+PHY-3002 : Step(306): len = 760048, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16058/17671.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 945440, over cnt = 65(0%), over = 74, worst = 3
+PHY-1002 : len = 945488, over cnt = 20(0%), over = 21, worst = 2
+PHY-1002 : len = 945616, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 945728, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.668414s wall, 0.687500s user + 0.015625s system = 0.703125s CPU (105.2%)
+
+PHY-1001 : Congestion index: top1 = 56.94, top5 = 51.34, top10 = 48.26, top15 = 46.20.
+PHY-3001 : End congestion estimation; 1.030549s wall, 1.062500s user + 0.015625s system = 1.078125s CPU (104.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.961666s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (100.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00185655
+PHY-3002 : Step(307): len = 760048, overlap = 0.5
+PHY-3002 : Step(308): len = 760036, overlap = 0
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.006684s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 760167, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063475s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.5%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 3, deltaY = 8, maxDist = 2.
+PHY-3001 : Final: Len = 760311, Over = 0
+PHY-3001 : End incremental placement; 6.612675s wall, 6.718750s user + 0.093750s system = 6.812500s CPU (103.0%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.743521s wall, 11.828125s user + 0.125000s system = 11.953125s CPU (111.3%)
+
+OPT-1001 : Current memory(MB): used = 738, reserve = 741, peak = 743.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16031/17671.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 945776, over cnt = 55(0%), over = 69, worst = 5
+PHY-1002 : len = 945848, over cnt = 31(0%), over = 33, worst = 2
+PHY-1002 : len = 946080, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 946216, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 946336, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.809620s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (98.4%)
+
+PHY-1001 : Congestion index: top1 = 56.72, top5 = 51.26, top10 = 48.21, top15 = 46.17.
+OPT-1001 : End congestion update; 1.147853s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.759187s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (98.8%)
+
+OPT-0007 : Start: WNS -1233 TNS -1997 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6778 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6866 instances, 6717 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3655 pins
+PHY-3001 : Found 503 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 764107, Over = 0
+PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.069177s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (90.3%)
+
+PHY-3001 : 27 instances has been re-located, deltaX = 24, deltaY = 14, maxDist = 3.
+PHY-3001 : Final: Len = 764645, Over = 0
+PHY-3001 : End incremental legalization; 0.422744s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (122.0%)
+
+OPT-0007 : Iter 1: improved WNS -1033 TNS -1568 NUM_FEPS 2 with 42 cells processed and 10270 slack improved
+OPT-0007 : Iter 2: improved WNS -1033 TNS -1568 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.517649s wall, 2.625000s user + 0.000000s system = 2.625000s CPU (104.3%)
+
+OPT-1001 : Current memory(MB): used = 737, reserve = 740, peak = 743.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.816496s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.5%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15862/17671.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 950288, over cnt = 138(0%), over = 158, worst = 3
+PHY-1002 : len = 950288, over cnt = 79(0%), over = 86, worst = 3
+PHY-1002 : len = 951080, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 951240, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 951256, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.985940s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (103.0%)
+
+PHY-1001 : Congestion index: top1 = 56.62, top5 = 51.31, top10 = 48.20, top15 = 46.17.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.750633s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.9%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -1133 TNS -1668 NUM_FEPS 2
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 56.172414
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -1133ps with logic level 2
+RUN-1001 : #2 path slack -1047ps with logic level 2
+RUN-1001 : 0 HFN exist on timing critical paths out of 17671 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 17671 nets
+OPT-1001 : End physical optimization; 18.606258s wall, 19.781250s user + 0.171875s system = 19.953125s CPU (107.2%)
+
+RUN-1003 : finish command "place" in 64.210228s wall, 93.156250s user + 6.140625s system = 99.296875s CPU (154.6%)
+
+RUN-1004 : used memory is 576 MB, reserved memory is 567 MB, peak memory is 743 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.735382s wall, 2.984375s user + 0.031250s system = 3.015625s CPU (173.8%)
+
+RUN-1004 : used memory is 577 MB, reserved memory is 568 MB, peak memory is 743 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6868 instances
+RUN-1001 : 3353 mslices, 3364 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17671 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9991 nets have 2 pins
+RUN-1001 : 5821 nets have [3 - 5] pins
+RUN-1001 : 1147 nets have [6 - 10] pins
+RUN-1001 : 323 nets have [11 - 20] pins
+RUN-1001 : 361 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74418, tnet num: 17493, tinst num: 6866, tnode num: 96890, tedge num: 124901.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.666902s wall, 1.625000s user + 0.031250s system = 1.656250s CPU (99.4%)
+
+RUN-1004 : used memory is 605 MB, reserved memory is 619 MB, peak memory is 743 MB
+PHY-1001 : 3353 mslices, 3364 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 880208, over cnt = 2800(7%), over = 4534, worst = 8
+PHY-1002 : len = 896544, over cnt = 1776(5%), over = 2560, worst = 8
+PHY-1002 : len = 912936, over cnt = 925(2%), over = 1298, worst = 6
+PHY-1002 : len = 933744, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 933792, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.383032s wall, 4.328125s user + 0.031250s system = 4.359375s CPU (128.9%)
+
+PHY-1001 : Congestion index: top1 = 56.23, top5 = 50.92, top10 = 47.76, top15 = 45.65.
+PHY-1001 : End global routing; 3.743055s wall, 4.687500s user + 0.046875s system = 4.734375s CPU (126.5%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 710, reserve = 714, peak = 743.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 986, reserve = 990, peak = 986.
+PHY-1001 : End build detailed router design. 4.285160s wall, 4.250000s user + 0.046875s system = 4.296875s CPU (100.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267216, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.669922s wall, 5.656250s user + 0.015625s system = 5.671875s CPU (100.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267272, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.651399s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (98.3%)
+
+PHY-1001 : Current memory(MB): used = 1021, reserve = 1027, peak = 1021.
+PHY-1001 : End phase 1; 6.335940s wall, 6.312500s user + 0.015625s system = 6.328125s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.37964e+06, over cnt = 1971(0%), over = 1977, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1041, reserve = 1046, peak = 1041.
+PHY-1001 : End initial routed; 31.267498s wall, 65.906250s user + 0.265625s system = 66.171875s CPU (211.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 15/16594(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -2.183 | -4.924 | 5
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.415966s wall, 3.421875s user + 0.000000s system = 3.421875s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1044, reserve = 1046, peak = 1045.
+PHY-1001 : End phase 2; 34.683525s wall, 69.328125s user + 0.265625s system = 69.593750s CPU (200.7%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 7 pins with SWNS -2.059ns STNS -4.082ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.169985s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (91.9%)
+
+PHY-1022 : len = 2.37967e+06, over cnt = 1980(0%), over = 1986, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.454651s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (99.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.34211e+06, over cnt = 870(0%), over = 871, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.998422s wall, 3.109375s user + 0.000000s system = 3.109375s CPU (155.6%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.33666e+06, over cnt = 161(0%), over = 161, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.137973s wall, 1.500000s user + 0.000000s system = 1.500000s CPU (131.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.3379e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.473188s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (105.7%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.207091s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (105.6%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.203889s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.6%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.235846s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (106.0%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.336177s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (102.3%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.171852s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.165922s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (103.6%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.178607s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (96.2%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.214834s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.259477s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (96.3%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.33796e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.174955s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (107.2%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.33796e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.188837s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.33794e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 15; 0.177585s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (96.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16594(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -2.059 | -4.082 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.393742s wall, 3.406250s user + 0.000000s system = 3.406250s CPU (100.4%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 627 feed throughs used by 436 nets
+PHY-1001 : End commit to database; 2.750311s wall, 2.734375s user + 0.015625s system = 2.750000s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1153, reserve = 1159, peak = 1153.
+PHY-1001 : End phase 3; 13.147565s wall, 14.640625s user + 0.015625s system = 14.656250s CPU (111.5%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.059ns STNS -4.082ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.143056s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (109.2%)
+
+PHY-1022 : len = 2.33794e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.407062s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.8%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-2.059ns, -4.082ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16594(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -2.059 | -4.082 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.434702s wall, 3.406250s user + 0.015625s system = 3.421875s CPU (99.6%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 627 feed throughs used by 436 nets
+PHY-1001 : End commit to database; 2.820905s wall, 2.828125s user + 0.000000s system = 2.828125s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1161, reserve = 1167, peak = 1161.
+PHY-1001 : End phase 4; 6.687954s wall, 6.656250s user + 0.015625s system = 6.671875s CPU (99.8%)
+
+PHY-1003 : Routed, final wirelength = 2.33794e+06
+PHY-1001 : Current memory(MB): used = 1163, reserve = 1170, peak = 1163.
+PHY-1001 : End export database. 0.064184s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.4%)
+
+PHY-1001 : End detail routing; 65.614555s wall, 101.640625s user + 0.359375s system = 102.000000s CPU (155.5%)
+
+RUN-1003 : finish command "route" in 72.153959s wall, 109.062500s user + 0.468750s system = 109.531250s CPU (151.8%)
+
+RUN-1004 : used memory is 1088 MB, reserved memory is 1104 MB, peak memory is 1163 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10345 out of 19600 52.78%
+#reg 9356 out of 19600 47.73%
+#le 12483
+ #lut only 3127 out of 12483 25.05%
+ #reg only 2138 out of 12483 17.13%
+ #lut® 7218 out of 12483 57.82%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1785
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1421
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1348
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 951
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 144
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg40_syn_225.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg50_syn_208.f1 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P140 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P17 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P25 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P16 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P118 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P104 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P83 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P32 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12483 |9318 |1027 |9390 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |558 |470 |23 |457 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |103 |85 |4 |91 |4 |0 |
+| U_crc16_24b |crc16_24b |34 |34 |0 |21 |0 |0 |
+| U_ecc_gen |ecc_gen |9 |9 |0 |8 |0 |0 |
+| exdev_ctl_a |exdev_ctl |785 |405 |96 |577 |0 |0 |
+| u_ADconfig |AD_config |191 |139 |25 |145 |0 |0 |
+| u_gen_sp |gen_sp |276 |185 |71 |114 |0 |0 |
+| exdev_ctl_b |exdev_ctl |761 |400 |96 |555 |0 |0 |
+| u_ADconfig |AD_config |186 |137 |25 |123 |0 |0 |
+| u_gen_sp |gen_sp |259 |173 |71 |116 |0 |0 |
+| sampling_fe_a |sampling_fe |2929 |2427 |306 |1994 |25 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |187 |138 |17 |141 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort |2708 |2271 |289 |1819 |25 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2358 |1986 |253 |1518 |22 |0 |
+| channelPart |channel_part_8478 |154 |151 |3 |138 |0 |0 |
+| fifo_adc |fifo_adc |61 |52 |9 |42 |0 |0 |
+| ram_switch |ram_switch |1853 |1549 |197 |1126 |0 |0 |
+| adc_addr_gen |adc_addr_gen |250 |223 |27 |124 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |8 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |27 |24 |3 |16 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |21 |18 |3 |9 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |29 |26 |3 |14 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |27 |24 |3 |12 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |30 |27 |3 |13 |0 |0 |
+| insert |insert |962 |685 |170 |654 |0 |0 |
+| ram_switch_state |ram_switch_state |641 |641 |0 |348 |0 |0 |
+| read_ram_i |read_ram |263 |208 |44 |185 |0 |0 |
+| read_ram_addr |read_ram_addr |210 |170 |40 |146 |0 |0 |
+| read_ram_data |read_ram_data |51 |36 |4 |37 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |316 |259 |36 |267 |3 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3306 |2572 |349 |2092 |25 |1 |
+| u0_soft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |185 |101 |17 |148 |0 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_sort |sort_rev |3087 |2458 |332 |1910 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2665 |2161 |290 |1546 |22 |1 |
+| channelPart |channel_part_8478 |232 |228 |3 |136 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |44 |0 |1 |
+| ram_switch |ram_switch |1981 |1613 |197 |1120 |0 |0 |
+| adc_addr_gen |adc_addr_gen |228 |201 |27 |105 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |4 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |28 |25 |3 |14 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |21 |18 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |21 |18 |3 |8 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |6 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |27 |24 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 |
+| insert |insert |1007 |668 |170 |696 |0 |0 |
+| ram_switch_state |ram_switch_state |746 |744 |0 |319 |0 |0 |
+| read_ram_i |read_ram_rev |359 |248 |81 |213 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |286 |202 |73 |160 |0 |0 |
+| read_ram_data |read_ram_data_rev |73 |46 |8 |53 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9929
+ #2 2 3890
+ #3 3 1404
+ #4 4 524
+ #5 5-10 1204
+ #6 11-50 601
+ #7 51-100 23
+ #8 >500 1
+ Average 2.92
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.120173s wall, 3.656250s user + 0.000000s system = 3.656250s CPU (172.5%)
+
+RUN-1004 : used memory is 1089 MB, reserved memory is 1105 MB, peak memory is 1163 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74418, tnet num: 17493, tinst num: 6866, tnode num: 96890, tedge num: 124901.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.658851s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (99.8%)
+
+RUN-1004 : used memory is 1093 MB, reserved memory is 1110 MB, peak memory is 1163 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.573032s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (98.3%)
+
+RUN-1004 : used memory is 1099 MB, reserved memory is 1115 MB, peak memory is 1163 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6866
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17671, pip num: 175043
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 627
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3247 valid insts, and 483910 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 10.817826s wall, 66.953125s user + 0.343750s system = 67.296875s CPU (622.1%)
+
+RUN-1004 : used memory is 1263 MB, reserved memory is 1267 MB, peak memory is 1378 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240123_173806.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240124_150658.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240124_150658.log
new file mode 100644
index 0000000..1dca66d
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240124_150658.log
@@ -0,0 +1,1888 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Wed Jan 24 15:06:58 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(102)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.362391s wall, 2.218750s user + 0.109375s system = 2.328125s CPU (98.5%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 315 MB, peak memory is 341 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2946 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17751 instances
+RUN-0007 : 7488 luts, 9040 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20329 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13320 nets have 2 pins
+RUN-1001 : 5543 nets have [3 - 5] pins
+RUN-1001 : 1047 nets have [6 - 10] pins
+RUN-1001 : 168 nets have [11 - 20] pins
+RUN-1001 : 177 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 789
+RUN-1001 : No | No | Yes | 1968
+RUN-1001 : No | Yes | No | 3474
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 56
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 141
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17749 instances, 7488 luts, 9040 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 5913 pins
+PHY-0007 : Cell area utilization is 49%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85053, tnet num: 20151, tinst num: 17749, tnode num: 115138, tedge num: 136535.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.255843s wall, 1.187500s user + 0.062500s system = 1.250000s CPU (99.5%)
+
+RUN-1004 : used memory is 530 MB, reserved memory is 514 MB, peak memory is 530 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20151 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 4 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.147551s wall, 2.078125s user + 0.062500s system = 2.140625s CPU (99.7%)
+
+PHY-3001 : Found 1221 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 3.87272e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17749.
+PHY-3001 : Level 1 #clusters 1994.
+PHY-3001 : End clustering; 0.157564s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (119.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 49%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.30601e+06, overlap = 474.562
+PHY-3002 : Step(2): len = 1.18493e+06, overlap = 506.281
+PHY-3002 : Step(3): len = 888608, overlap = 546.469
+PHY-3002 : Step(4): len = 760675, overlap = 630.156
+PHY-3002 : Step(5): len = 597521, overlap = 780.781
+PHY-3002 : Step(6): len = 542110, overlap = 875.5
+PHY-3002 : Step(7): len = 477561, overlap = 954.188
+PHY-3002 : Step(8): len = 423131, overlap = 994
+PHY-3002 : Step(9): len = 382447, overlap = 1043.81
+PHY-3002 : Step(10): len = 347359, overlap = 1076.69
+PHY-3002 : Step(11): len = 310049, overlap = 1145.16
+PHY-3002 : Step(12): len = 282647, overlap = 1159.47
+PHY-3002 : Step(13): len = 258010, overlap = 1250.56
+PHY-3002 : Step(14): len = 235004, overlap = 1332.06
+PHY-3002 : Step(15): len = 212533, overlap = 1393.38
+PHY-3002 : Step(16): len = 191032, overlap = 1431.53
+PHY-3002 : Step(17): len = 176467, overlap = 1474.12
+PHY-3002 : Step(18): len = 161078, overlap = 1493.84
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.32138e-07
+PHY-3002 : Step(19): len = 161497, overlap = 1471
+PHY-3002 : Step(20): len = 191425, overlap = 1320.41
+PHY-3002 : Step(21): len = 194383, overlap = 1278.19
+PHY-3002 : Step(22): len = 197916, overlap = 1245.69
+PHY-3002 : Step(23): len = 191835, overlap = 1229.03
+PHY-3002 : Step(24): len = 187214, overlap = 1208.31
+PHY-3002 : Step(25): len = 183936, overlap = 1195.72
+PHY-3002 : Step(26): len = 182483, overlap = 1194.12
+PHY-3002 : Step(27): len = 181134, overlap = 1192.22
+PHY-3002 : Step(28): len = 180886, overlap = 1189.34
+PHY-3002 : Step(29): len = 179762, overlap = 1188.03
+PHY-3002 : Step(30): len = 178349, overlap = 1177.09
+PHY-3002 : Step(31): len = 177243, overlap = 1168.34
+PHY-3002 : Step(32): len = 176445, overlap = 1172.78
+PHY-3002 : Step(33): len = 174887, overlap = 1164.47
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.66428e-06
+PHY-3002 : Step(34): len = 178044, overlap = 1161.06
+PHY-3002 : Step(35): len = 190742, overlap = 1105.47
+PHY-3002 : Step(36): len = 195116, overlap = 1081.25
+PHY-3002 : Step(37): len = 199702, overlap = 1079.12
+PHY-3002 : Step(38): len = 201879, overlap = 1081.72
+PHY-3002 : Step(39): len = 203026, overlap = 1072.66
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.32855e-06
+PHY-3002 : Step(40): len = 208643, overlap = 1038.78
+PHY-3002 : Step(41): len = 222726, overlap = 1013.44
+PHY-3002 : Step(42): len = 229484, overlap = 963.5
+PHY-3002 : Step(43): len = 235024, overlap = 933.188
+PHY-3002 : Step(44): len = 236984, overlap = 913.344
+PHY-3002 : Step(45): len = 237318, overlap = 903.75
+PHY-3002 : Step(46): len = 235368, overlap = 904.75
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 6.65711e-06
+PHY-3002 : Step(47): len = 248210, overlap = 851.719
+PHY-3002 : Step(48): len = 278918, overlap = 737.625
+PHY-3002 : Step(49): len = 294865, overlap = 687.688
+PHY-3002 : Step(50): len = 301984, overlap = 639.062
+PHY-3002 : Step(51): len = 302296, overlap = 618.125
+PHY-3002 : Step(52): len = 298996, overlap = 601.25
+PHY-3002 : Step(53): len = 295627, overlap = 576.25
+PHY-3002 : Step(54): len = 293903, overlap = 572
+PHY-3002 : Step(55): len = 293415, overlap = 574.125
+PHY-3002 : Step(56): len = 294138, overlap = 580.719
+PHY-3002 : Step(57): len = 293661, overlap = 600.375
+PHY-3002 : Step(58): len = 293536, overlap = 604.656
+PHY-3002 : Step(59): len = 292948, overlap = 602.594
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.33142e-05
+PHY-3002 : Step(60): len = 308507, overlap = 550.5
+PHY-3002 : Step(61): len = 324193, overlap = 495.312
+PHY-3002 : Step(62): len = 327686, overlap = 449.531
+PHY-3002 : Step(63): len = 330410, overlap = 425.75
+PHY-3002 : Step(64): len = 330241, overlap = 422.875
+PHY-3002 : Step(65): len = 331715, overlap = 413.938
+PHY-3002 : Step(66): len = 331402, overlap = 424.812
+PHY-3002 : Step(67): len = 332689, overlap = 410.812
+PHY-3002 : Step(68): len = 333251, overlap = 424.719
+PHY-3002 : Step(69): len = 334428, overlap = 416
+PHY-3002 : Step(70): len = 333987, overlap = 411.344
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 2.66284e-05
+PHY-3002 : Step(71): len = 350858, overlap = 395.031
+PHY-3002 : Step(72): len = 366710, overlap = 356.281
+PHY-3002 : Step(73): len = 372324, overlap = 330.531
+PHY-3002 : Step(74): len = 373258, overlap = 322.625
+PHY-3002 : Step(75): len = 374614, overlap = 329.219
+PHY-3002 : Step(76): len = 376600, overlap = 324.75
+PHY-3002 : Step(77): len = 375732, overlap = 315.25
+PHY-3002 : Step(78): len = 375685, overlap = 313.156
+PHY-3002 : Step(79): len = 375713, overlap = 330.125
+PHY-3002 : Step(80): len = 377146, overlap = 328.531
+PHY-3002 : Step(81): len = 377875, overlap = 321.656
+PHY-3002 : Step(82): len = 378086, overlap = 327.344
+PHY-3002 : Step(83): len = 377607, overlap = 329.281
+PHY-3002 : Step(84): len = 378911, overlap = 329.75
+PHY-3002 : Step(85): len = 379833, overlap = 331.062
+PHY-3002 : Step(86): len = 379099, overlap = 325.656
+PHY-3002 : Step(87): len = 377846, overlap = 336
+PHY-3002 : Step(88): len = 379514, overlap = 345.781
+PHY-3002 : Step(89): len = 379723, overlap = 340.781
+PHY-3002 : Step(90): len = 378264, overlap = 328.031
+PHY-3002 : Step(91): len = 376984, overlap = 312.312
+PHY-3002 : Step(92): len = 377082, overlap = 303.562
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 5.32569e-05
+PHY-3002 : Step(93): len = 392649, overlap = 267.156
+PHY-3002 : Step(94): len = 401156, overlap = 257.219
+PHY-3002 : Step(95): len = 399349, overlap = 253.625
+PHY-3002 : Step(96): len = 400584, overlap = 252.25
+PHY-3002 : Step(97): len = 405095, overlap = 243.656
+PHY-3002 : Step(98): len = 407456, overlap = 248.375
+PHY-3002 : Step(99): len = 405200, overlap = 249.156
+PHY-3002 : Step(100): len = 405964, overlap = 241.562
+PHY-3002 : Step(101): len = 408588, overlap = 239.031
+PHY-3002 : Step(102): len = 410648, overlap = 236.75
+PHY-3002 : Step(103): len = 408651, overlap = 253.25
+PHY-3002 : Step(104): len = 409698, overlap = 239.938
+PHY-3002 : Step(105): len = 410964, overlap = 225.375
+PHY-3002 : Step(106): len = 411994, overlap = 224.438
+PHY-3002 : Step(107): len = 410657, overlap = 240.094
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000100885
+PHY-3002 : Step(108): len = 424786, overlap = 192.031
+PHY-3002 : Step(109): len = 433350, overlap = 178.344
+PHY-3002 : Step(110): len = 431515, overlap = 194.531
+PHY-3002 : Step(111): len = 431726, overlap = 195.469
+PHY-3002 : Step(112): len = 433899, overlap = 186.469
+PHY-3002 : Step(113): len = 436013, overlap = 183.812
+PHY-3002 : Step(114): len = 434689, overlap = 184.969
+PHY-3002 : Step(115): len = 435618, overlap = 188.438
+PHY-3002 : Step(116): len = 438352, overlap = 179.25
+PHY-3002 : Step(117): len = 440041, overlap = 177.219
+PHY-3002 : Step(118): len = 437621, overlap = 182.281
+PHY-3002 : Step(119): len = 437311, overlap = 186.656
+PHY-3002 : Step(120): len = 438832, overlap = 188.656
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.00020177
+PHY-3002 : Step(121): len = 452573, overlap = 166.75
+PHY-3002 : Step(122): len = 463883, overlap = 160.531
+PHY-3002 : Step(123): len = 463057, overlap = 164.375
+PHY-3002 : Step(124): len = 463732, overlap = 162.938
+PHY-3002 : Step(125): len = 467568, overlap = 155.625
+PHY-3002 : Step(126): len = 469787, overlap = 147.625
+PHY-3002 : Step(127): len = 467186, overlap = 154.875
+PHY-3002 : Step(128): len = 467498, overlap = 160.344
+PHY-3002 : Step(129): len = 471916, overlap = 159.938
+PHY-3002 : Step(130): len = 476564, overlap = 158.031
+PHY-3002 : Step(131): len = 475316, overlap = 157.656
+PHY-3002 : Step(132): len = 476957, overlap = 151.562
+PHY-3002 : Step(133): len = 480076, overlap = 137.531
+PHY-3002 : Step(134): len = 481577, overlap = 143.375
+PHY-3002 : Step(135): len = 478954, overlap = 144.094
+PHY-3002 : Step(136): len = 478190, overlap = 151.031
+PHY-3002 : Step(137): len = 479214, overlap = 143.906
+PHY-3002 : Step(138): len = 479721, overlap = 136.656
+PHY-3002 : Step(139): len = 477756, overlap = 143.375
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000386982
+PHY-3002 : Step(140): len = 485476, overlap = 141.969
+PHY-3002 : Step(141): len = 490130, overlap = 140.094
+PHY-3002 : Step(142): len = 490142, overlap = 138.562
+PHY-3002 : Step(143): len = 490546, overlap = 138.25
+PHY-3002 : Step(144): len = 493148, overlap = 136.219
+PHY-3002 : Step(145): len = 494805, overlap = 136.406
+PHY-3002 : Step(146): len = 493651, overlap = 134.281
+PHY-3002 : Step(147): len = 494099, overlap = 131.25
+PHY-3002 : Step(148): len = 496842, overlap = 135.188
+PHY-3002 : Step(149): len = 497787, overlap = 131.844
+PHY-3002 : Step(150): len = 496249, overlap = 128.438
+PHY-3002 : Step(151): len = 495742, overlap = 126.25
+PHY-3002 : Step(152): len = 497768, overlap = 128.281
+PHY-3002 : Step(153): len = 500219, overlap = 121.375
+PHY-3002 : Step(154): len = 498341, overlap = 121.656
+PHY-3002 : Step(155): len = 497917, overlap = 120.594
+PHY-3002 : Step(156): len = 498871, overlap = 124.438
+PHY-3002 : Step(157): len = 499321, overlap = 122.438
+PHY-3002 : Step(158): len = 497960, overlap = 120
+PHY-3002 : Step(159): len = 497620, overlap = 119.312
+PHY-3002 : Step(160): len = 498664, overlap = 111.344
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000742668
+PHY-3002 : Step(161): len = 503009, overlap = 114.906
+PHY-3002 : Step(162): len = 509106, overlap = 109.906
+PHY-3002 : Step(163): len = 511173, overlap = 108.875
+PHY-3002 : Step(164): len = 513152, overlap = 111.062
+PHY-3002 : Step(165): len = 515282, overlap = 108.969
+PHY-3002 : Step(166): len = 516304, overlap = 108.844
+PHY-3002 : Step(167): len = 515433, overlap = 105.344
+PHY-3002 : Step(168): len = 515361, overlap = 107.125
+PHY-3002 : Step(169): len = 515851, overlap = 108.031
+PHY-3002 : Step(170): len = 516005, overlap = 107.719
+PHY-3002 : Step(171): len = 516141, overlap = 106.219
+PHY-3002 : Step(172): len = 516523, overlap = 106.594
+PHY-3002 : Step(173): len = 517028, overlap = 106.844
+PHY-3002 : Step(174): len = 517144, overlap = 108.719
+PHY-3002 : Step(175): len = 516992, overlap = 101.969
+PHY-3002 : Step(176): len = 517020, overlap = 102.719
+PHY-3002 : Step(177): len = 517600, overlap = 106.25
+PHY-3002 : Step(178): len = 517953, overlap = 106.625
+PHY-3002 : Step(179): len = 518160, overlap = 104.312
+PHY-3002 : Step(180): len = 518291, overlap = 101.75
+PHY-3002 : Step(181): len = 519237, overlap = 104.812
+PHY-3002 : Step(182): len = 520219, overlap = 108.5
+PHY-3002 : Step(183): len = 520115, overlap = 106.375
+PHY-3002 : Step(184): len = 520095, overlap = 106.312
+PHY-3002 : Step(185): len = 519921, overlap = 106.875
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00124578
+PHY-3002 : Step(186): len = 522739, overlap = 106.906
+PHY-3002 : Step(187): len = 526133, overlap = 105.469
+PHY-3002 : Step(188): len = 526360, overlap = 103.844
+PHY-3002 : Step(189): len = 526641, overlap = 106.594
+PHY-3002 : Step(190): len = 527781, overlap = 107.656
+PHY-3002 : Step(191): len = 528332, overlap = 107.344
+PHY-3002 : Step(192): len = 527947, overlap = 107.625
+PHY-3002 : Step(193): len = 527903, overlap = 106.562
+PHY-3002 : Step(194): len = 529107, overlap = 108.312
+PHY-3002 : Step(195): len = 529741, overlap = 106.438
+PHY-3002 : Step(196): len = 529501, overlap = 106.219
+PHY-3002 : Step(197): len = 529490, overlap = 106.719
+PHY-3002 : Step(198): len = 530139, overlap = 106
+PHY-3002 : Step(199): len = 530782, overlap = 104.594
+PHY-3002 : Step(200): len = 530670, overlap = 105.5
+PHY-3002 : Step(201): len = 530708, overlap = 105.656
+PHY-3002 : Step(202): len = 531472, overlap = 104.75
+PHY-3002 : Step(203): len = 532282, overlap = 105.062
+PHY-3002 : Step(204): len = 532287, overlap = 104.875
+PHY-3002 : Step(205): len = 532448, overlap = 105.25
+PHY-3002 : Step(206): len = 532959, overlap = 100.25
+PHY-3002 : Step(207): len = 533182, overlap = 100.594
+PHY-3002 : Step(208): len = 533715, overlap = 98.4062
+PHY-3002 : Step(209): len = 534982, overlap = 102.031
+PHY-3002 : Step(210): len = 536265, overlap = 99.8125
+PHY-3002 : Step(211): len = 536721, overlap = 97.6875
+PHY-3002 : Step(212): len = 536982, overlap = 100.156
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00203865
+PHY-3002 : Step(213): len = 538210, overlap = 98.1875
+PHY-3002 : Step(214): len = 538767, overlap = 100.219
+PHY-3002 : Step(215): len = 539065, overlap = 100.781
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.015752s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (99.2%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20329.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 703024, over cnt = 1596(4%), over = 7137, worst = 30
+PHY-1001 : End global iterations; 0.813791s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (136.3%)
+
+PHY-1001 : Congestion index: top1 = 77.74, top5 = 59.26, top10 = 50.61, top15 = 45.51.
+PHY-3001 : End congestion estimation; 1.105577s wall, 1.359375s user + 0.046875s system = 1.406250s CPU (127.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20151 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.957268s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000123338
+PHY-3002 : Step(216): len = 636013, overlap = 55.25
+PHY-3002 : Step(217): len = 643950, overlap = 56.0312
+PHY-3002 : Step(218): len = 640757, overlap = 58.4062
+PHY-3002 : Step(219): len = 641452, overlap = 57.875
+PHY-3002 : Step(220): len = 641226, overlap = 54.8125
+PHY-3002 : Step(221): len = 640747, overlap = 47.6562
+PHY-3002 : Step(222): len = 638327, overlap = 45.625
+PHY-3002 : Step(223): len = 638249, overlap = 39.3438
+PHY-3002 : Step(224): len = 638212, overlap = 36.0312
+PHY-3002 : Step(225): len = 635699, overlap = 34.4062
+PHY-3002 : Step(226): len = 634217, overlap = 33
+PHY-3002 : Step(227): len = 631546, overlap = 32.1562
+PHY-3002 : Step(228): len = 630418, overlap = 34.9688
+PHY-3002 : Step(229): len = 628930, overlap = 33.3438
+PHY-3002 : Step(230): len = 627735, overlap = 31.4688
+PHY-3002 : Step(231): len = 627632, overlap = 30.0625
+PHY-3002 : Step(232): len = 626140, overlap = 33.4688
+PHY-3002 : Step(233): len = 624809, overlap = 29.5938
+PHY-3002 : Step(234): len = 623738, overlap = 30.0625
+PHY-3002 : Step(235): len = 622396, overlap = 28.3438
+PHY-3002 : Step(236): len = 622091, overlap = 27.7812
+PHY-3002 : Step(237): len = 620449, overlap = 25.5938
+PHY-3002 : Step(238): len = 619583, overlap = 26.5
+PHY-3002 : Step(239): len = 618849, overlap = 23.9375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000246677
+PHY-3002 : Step(240): len = 620967, overlap = 23.0625
+PHY-3002 : Step(241): len = 622322, overlap = 23.4375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 87/20329.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 714912, over cnt = 2587(7%), over = 10815, worst = 40
+PHY-1001 : End global iterations; 2.005318s wall, 2.578125s user + 0.000000s system = 2.578125s CPU (128.6%)
+
+PHY-1001 : Congestion index: top1 = 78.66, top5 = 62.56, top10 = 54.88, top15 = 50.20.
+PHY-3001 : End congestion estimation; 2.308876s wall, 2.890625s user + 0.000000s system = 2.890625s CPU (125.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20151 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.394335s wall, 1.390625s user + 0.000000s system = 1.390625s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.60391e-05
+PHY-3002 : Step(242): len = 620665, overlap = 248.531
+PHY-3002 : Step(243): len = 624625, overlap = 204.375
+PHY-3002 : Step(244): len = 622386, overlap = 179.219
+PHY-3002 : Step(245): len = 620594, overlap = 166.312
+PHY-3002 : Step(246): len = 621554, overlap = 154.219
+PHY-3002 : Step(247): len = 617100, overlap = 146.406
+PHY-3002 : Step(248): len = 614371, overlap = 144.625
+PHY-3002 : Step(249): len = 611794, overlap = 143.844
+PHY-3002 : Step(250): len = 608880, overlap = 141.625
+PHY-3002 : Step(251): len = 606596, overlap = 140.75
+PHY-3002 : Step(252): len = 604151, overlap = 142.594
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000192078
+PHY-3002 : Step(253): len = 604228, overlap = 141.25
+PHY-3002 : Step(254): len = 605307, overlap = 139.594
+PHY-3002 : Step(255): len = 608528, overlap = 132.844
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000384156
+PHY-3002 : Step(256): len = 614231, overlap = 120.531
+PHY-3002 : Step(257): len = 620121, overlap = 111.188
+PHY-3002 : Step(258): len = 625256, overlap = 105.062
+PHY-3002 : Step(259): len = 625448, overlap = 101.094
+PHY-3002 : Step(260): len = 626224, overlap = 106.938
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000768313
+PHY-3002 : Step(261): len = 629764, overlap = 100.938
+PHY-3002 : Step(262): len = 637326, overlap = 99
+PHY-3002 : Step(263): len = 643260, overlap = 99.4062
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85053, tnet num: 20151, tinst num: 17749, tnode num: 115138, tedge num: 136535.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.592820s wall, 1.562500s user + 0.031250s system = 1.593750s CPU (100.1%)
+
+RUN-1004 : used memory is 573 MB, reserved memory is 562 MB, peak memory is 711 MB
+OPT-1001 : Total overflow 419.75 peak overflow 3.97
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1271/20329.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 748544, over cnt = 3189(9%), over = 11299, worst = 23
+PHY-1001 : End global iterations; 1.266747s wall, 2.000000s user + 0.015625s system = 2.015625s CPU (159.1%)
+
+PHY-1001 : Congestion index: top1 = 72.18, top5 = 58.80, top10 = 52.44, top15 = 48.48.
+PHY-1001 : End incremental global routing; 1.640026s wall, 2.359375s user + 0.031250s system = 2.390625s CPU (145.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20151 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 4 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.034315s wall, 1.000000s user + 0.031250s system = 1.031250s CPU (99.7%)
+
+OPT-1001 : 49 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17615 has valid locations, 323 needs to be replaced
+PHY-3001 : design contains 18023 instances, 7585 luts, 9217 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 6038 pins
+PHY-3001 : Found 1233 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 667488
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16819/20603.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 762024, over cnt = 3226(9%), over = 11355, worst = 23
+PHY-1001 : End global iterations; 0.289769s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (113.2%)
+
+PHY-1001 : Congestion index: top1 = 72.05, top5 = 59.12, top10 = 52.76, top15 = 48.95.
+PHY-3001 : End congestion estimation; 0.580857s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (107.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86155, tnet num: 20425, tinst num: 18023, tnode num: 116775, tedge num: 138191.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.738367s wall, 1.718750s user + 0.015625s system = 1.734375s CPU (99.8%)
+
+RUN-1004 : used memory is 617 MB, reserved memory is 612 MB, peak memory is 713 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20425 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 4 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.382636s wall, 3.312500s user + 0.046875s system = 3.359375s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(264): len = 666471, overlap = 0
+PHY-3002 : Step(265): len = 666093, overlap = 0
+PHY-3002 : Step(266): len = 665930, overlap = 0
+PHY-3002 : Step(267): len = 665817, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16917/20603.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 760216, over cnt = 3236(9%), over = 11405, worst = 23
+PHY-1001 : End global iterations; 0.253804s wall, 0.296875s user + 0.031250s system = 0.328125s CPU (129.3%)
+
+PHY-1001 : Congestion index: top1 = 73.12, top5 = 59.60, top10 = 53.11, top15 = 49.15.
+PHY-3001 : End congestion estimation; 0.569303s wall, 0.609375s user + 0.031250s system = 0.640625s CPU (112.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20425 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.108708s wall, 1.093750s user + 0.015625s system = 1.109375s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00045159
+PHY-3002 : Step(268): len = 665744, overlap = 102.062
+PHY-3002 : Step(269): len = 665776, overlap = 102.156
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00090318
+PHY-3002 : Step(270): len = 666141, overlap = 102.375
+PHY-3002 : Step(271): len = 666604, overlap = 102.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00176571
+PHY-3002 : Step(272): len = 666761, overlap = 102.406
+PHY-3002 : Step(273): len = 667541, overlap = 102.062
+PHY-3001 : Final: Len = 667541, Over = 102.062
+PHY-3001 : End incremental placement; 6.596522s wall, 6.890625s user + 0.250000s system = 7.140625s CPU (108.2%)
+
+OPT-1001 : Total overflow 425.44 peak overflow 3.97
+OPT-1001 : End high-fanout net optimization; 10.000656s wall, 11.093750s user + 0.312500s system = 11.406250s CPU (114.1%)
+
+OPT-1001 : Current memory(MB): used = 715, reserve = 710, peak = 733.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16841/20603.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 764712, over cnt = 3164(8%), over = 10252, worst = 23
+PHY-1002 : len = 818192, over cnt = 2145(6%), over = 5172, worst = 23
+PHY-1002 : len = 859872, over cnt = 893(2%), over = 1893, worst = 17
+PHY-1002 : len = 878248, over cnt = 405(1%), over = 771, worst = 14
+PHY-1002 : len = 894816, over cnt = 3(0%), over = 4, worst = 2
+PHY-1001 : End global iterations; 2.056008s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (156.6%)
+
+PHY-1001 : Congestion index: top1 = 60.02, top5 = 52.14, top10 = 48.54, top15 = 46.16.
+OPT-1001 : End congestion update; 2.379295s wall, 3.515625s user + 0.015625s system = 3.531250s CPU (148.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20425 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.961399s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (100.8%)
+
+OPT-0007 : Start: WNS -1168 TNS -1628 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 84 cells processed and 6884 slack improved
+OPT-0007 : Iter 2: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 17 cells processed and 1458 slack improved
+OPT-0007 : Iter 3: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 11 cells processed and 450 slack improved
+OPT-1001 : End global optimization; 3.388393s wall, 4.531250s user + 0.015625s system = 4.546875s CPU (134.2%)
+
+OPT-1001 : Current memory(MB): used = 693, reserve = 693, peak = 733.
+OPT-1001 : End physical optimization; 15.720060s wall, 18.000000s user + 0.375000s system = 18.375000s CPU (116.9%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7585 LUT to BLE ...
+SYN-4008 : Packed 7585 LUT and 3081 SEQ to BLE.
+SYN-4003 : Packing 6136 remaining SEQ's ...
+SYN-4005 : Packed 3937 SEQ with LUT/SLICE
+SYN-4006 : 847 single LUT's are left
+SYN-4006 : 2199 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9784/13515 primitive instances ...
+PHY-3001 : End packing; 1.920284s wall, 1.906250s user + 0.015625s system = 1.921875s CPU (100.1%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6848 instances
+RUN-1001 : 3350 mslices, 3350 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17653 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9990 nets have 2 pins
+RUN-1001 : 5824 nets have [3 - 5] pins
+RUN-1001 : 1143 nets have [6 - 10] pins
+RUN-1001 : 319 nets have [11 - 20] pins
+RUN-1001 : 344 nets have [21 - 99] pins
+RUN-1001 : 13 nets have 100+ pins
+PHY-3001 : design contains 6846 instances, 6700 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3573 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 677688, Over = 278.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7360/17653.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 835424, over cnt = 2031(5%), over = 3263, worst = 9
+PHY-1002 : len = 840664, over cnt = 1494(4%), over = 2226, worst = 9
+PHY-1002 : len = 859256, over cnt = 503(1%), over = 693, worst = 9
+PHY-1002 : len = 866664, over cnt = 153(0%), over = 197, worst = 4
+PHY-1002 : len = 870312, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.982489s wall, 2.781250s user + 0.000000s system = 2.781250s CPU (140.3%)
+
+PHY-1001 : Congestion index: top1 = 58.71, top5 = 52.05, top10 = 47.94, top15 = 45.36.
+PHY-3001 : End congestion estimation; 2.435529s wall, 3.234375s user + 0.000000s system = 3.234375s CPU (132.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74266, tnet num: 17475, tinst num: 6846, tnode num: 96696, tedge num: 124693.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.794518s wall, 1.750000s user + 0.046875s system = 1.796875s CPU (100.1%)
+
+RUN-1004 : used memory is 610 MB, reserved memory is 606 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17475 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 4 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.778515s wall, 2.734375s user + 0.046875s system = 2.781250s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.92706e-05
+PHY-3002 : Step(274): len = 663813, overlap = 278
+PHY-3002 : Step(275): len = 656989, overlap = 274
+PHY-3002 : Step(276): len = 652804, overlap = 269.75
+PHY-3002 : Step(277): len = 650188, overlap = 275
+PHY-3002 : Step(278): len = 647911, overlap = 272.75
+PHY-3002 : Step(279): len = 646645, overlap = 274.25
+PHY-3002 : Step(280): len = 643841, overlap = 276
+PHY-3002 : Step(281): len = 641700, overlap = 274
+PHY-3002 : Step(282): len = 639307, overlap = 273.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.85411e-05
+PHY-3002 : Step(283): len = 641598, overlap = 270.75
+PHY-3002 : Step(284): len = 648034, overlap = 260
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000197082
+PHY-3002 : Step(285): len = 654845, overlap = 252.5
+PHY-3002 : Step(286): len = 668916, overlap = 232.25
+PHY-3002 : Step(287): len = 669197, overlap = 223.25
+PHY-3002 : Step(288): len = 669384, overlap = 220.25
+PHY-3002 : Step(289): len = 669586, overlap = 220.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.412675s wall, 0.437500s user + 0.625000s system = 1.062500s CPU (257.5%)
+
+PHY-3001 : Trial Legalized: Len = 760274
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 797/17653.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 886056, over cnt = 2845(8%), over = 4808, worst = 8
+PHY-1002 : len = 902912, over cnt = 1840(5%), over = 2764, worst = 8
+PHY-1002 : len = 926256, over cnt = 694(1%), over = 1052, worst = 7
+PHY-1002 : len = 936600, over cnt = 286(0%), over = 438, worst = 5
+PHY-1002 : len = 943968, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.867619s wall, 4.140625s user + 0.015625s system = 4.156250s CPU (144.9%)
+
+PHY-1001 : Congestion index: top1 = 57.35, top5 = 52.16, top10 = 49.28, top15 = 47.23.
+PHY-3001 : End congestion estimation; 3.396937s wall, 4.640625s user + 0.015625s system = 4.656250s CPU (137.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17475 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.033449s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000160075
+PHY-3002 : Step(290): len = 731170, overlap = 46.75
+PHY-3002 : Step(291): len = 715477, overlap = 73.5
+PHY-3002 : Step(292): len = 701504, overlap = 99.25
+PHY-3002 : Step(293): len = 692938, overlap = 120.5
+PHY-3002 : Step(294): len = 686075, overlap = 149
+PHY-3002 : Step(295): len = 683281, overlap = 155.5
+PHY-3002 : Step(296): len = 681605, overlap = 159.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000320151
+PHY-3002 : Step(297): len = 686514, overlap = 158.5
+PHY-3002 : Step(298): len = 693478, overlap = 154.75
+PHY-3002 : Step(299): len = 697623, overlap = 148
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000640302
+PHY-3002 : Step(300): len = 703226, overlap = 144.5
+PHY-3002 : Step(301): len = 715989, overlap = 143.75
+PHY-3002 : Step(302): len = 720218, overlap = 142.75
+PHY-3002 : Step(303): len = 720731, overlap = 142.75
+PHY-3002 : Step(304): len = 721887, overlap = 142.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.040004s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (117.2%)
+
+PHY-3001 : Legalized: Len = 748503, Over = 0
+PHY-3001 : Spreading special nets. 468 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.118098s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (105.8%)
+
+PHY-3001 : 689 instances has been re-located, deltaX = 254, deltaY = 381, maxDist = 3.
+PHY-3001 : Final: Len = 758271, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74266, tnet num: 17475, tinst num: 6849, tnode num: 96696, tedge num: 124693.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.071645s wall, 2.062500s user + 0.000000s system = 2.062500s CPU (99.6%)
+
+RUN-1004 : used memory is 637 MB, reserved memory is 654 MB, peak memory is 733 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3196/17653.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 894616, over cnt = 2612(7%), over = 4292, worst = 7
+PHY-1002 : len = 908408, over cnt = 1661(4%), over = 2484, worst = 6
+PHY-1002 : len = 921576, over cnt = 864(2%), over = 1331, worst = 6
+PHY-1002 : len = 934896, over cnt = 292(0%), over = 473, worst = 6
+PHY-1002 : len = 943744, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.455006s wall, 3.500000s user + 0.062500s system = 3.562500s CPU (145.1%)
+
+PHY-1001 : Congestion index: top1 = 56.94, top5 = 51.26, top10 = 48.22, top15 = 46.18.
+PHY-1001 : End incremental global routing; 2.885652s wall, 3.937500s user + 0.062500s system = 4.000000s CPU (138.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17475 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 4 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.998416s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (100.2%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6756 has valid locations, 22 needs to be replaced
+PHY-3001 : design contains 6866 instances, 6717 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3655 pins
+PHY-3001 : Found 503 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 761110
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16070/17671.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 946400, over cnt = 77(0%), over = 95, worst = 4
+PHY-1002 : len = 946672, over cnt = 26(0%), over = 26, worst = 1
+PHY-1002 : len = 946864, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 947048, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.695802s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (103.3%)
+
+PHY-1001 : Congestion index: top1 = 56.94, top5 = 51.28, top10 = 48.25, top15 = 46.22.
+PHY-3001 : End congestion estimation; 1.063508s wall, 1.078125s user + 0.015625s system = 1.093750s CPU (102.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74418, tnet num: 17493, tinst num: 6866, tnode num: 96890, tedge num: 124901.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.124806s wall, 2.062500s user + 0.000000s system = 2.062500s CPU (97.1%)
+
+RUN-1004 : used memory is 661 MB, reserved memory is 672 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 4 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.137490s wall, 3.078125s user + 0.000000s system = 3.078125s CPU (98.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(305): len = 760722, overlap = 0
+PHY-3002 : Step(306): len = 760048, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16058/17671.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 945440, over cnt = 65(0%), over = 74, worst = 3
+PHY-1002 : len = 945488, over cnt = 20(0%), over = 21, worst = 2
+PHY-1002 : len = 945616, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 945728, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.682888s wall, 0.718750s user + 0.031250s system = 0.750000s CPU (109.8%)
+
+PHY-1001 : Congestion index: top1 = 56.94, top5 = 51.34, top10 = 48.26, top15 = 46.20.
+PHY-3001 : End congestion estimation; 1.050729s wall, 1.109375s user + 0.031250s system = 1.140625s CPU (108.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.979180s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (98.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00185655
+PHY-3002 : Step(307): len = 760048, overlap = 0.5
+PHY-3002 : Step(308): len = 760036, overlap = 0
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005745s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 760167, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.070202s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (111.3%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 3, deltaY = 8, maxDist = 2.
+PHY-3001 : Final: Len = 760311, Over = 0
+PHY-3001 : End incremental placement; 6.815259s wall, 6.906250s user + 0.125000s system = 7.031250s CPU (103.2%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 11.265727s wall, 12.390625s user + 0.187500s system = 12.578125s CPU (111.6%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 740, peak = 742.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16031/17671.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 945776, over cnt = 55(0%), over = 69, worst = 5
+PHY-1002 : len = 945848, over cnt = 31(0%), over = 33, worst = 2
+PHY-1002 : len = 946080, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 946216, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 946336, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.881829s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (104.5%)
+
+PHY-1001 : Congestion index: top1 = 56.72, top5 = 51.26, top10 = 48.21, top15 = 46.17.
+OPT-1001 : End congestion update; 1.247651s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (103.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.814823s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (97.8%)
+
+OPT-0007 : Start: WNS -1233 TNS -1997 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6778 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6866 instances, 6717 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3655 pins
+PHY-3001 : Found 503 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 764107, Over = 0
+PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.076604s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (102.0%)
+
+PHY-3001 : 27 instances has been re-located, deltaX = 24, deltaY = 14, maxDist = 3.
+PHY-3001 : Final: Len = 764645, Over = 0
+PHY-3001 : End incremental legalization; 0.473207s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (102.4%)
+
+OPT-0007 : Iter 1: improved WNS -1033 TNS -1568 NUM_FEPS 2 with 42 cells processed and 10270 slack improved
+OPT-0007 : Iter 2: improved WNS -1033 TNS -1568 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.736178s wall, 2.765625s user + 0.000000s system = 2.765625s CPU (101.1%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 740, peak = 742.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.824679s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (100.4%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15862/17671.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 950288, over cnt = 138(0%), over = 158, worst = 3
+PHY-1002 : len = 950288, over cnt = 79(0%), over = 86, worst = 3
+PHY-1002 : len = 951080, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 951240, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 951256, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.001041s wall, 1.031250s user + 0.031250s system = 1.062500s CPU (106.1%)
+
+PHY-1001 : Congestion index: top1 = 56.62, top5 = 51.31, top10 = 48.20, top15 = 46.17.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.891334s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (99.9%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -1133 TNS -1668 NUM_FEPS 2
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 56.172414
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -1133ps with logic level 2
+RUN-1001 : #2 path slack -1047ps with logic level 2
+RUN-1001 : 0 HFN exist on timing critical paths out of 17671 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 17671 nets
+OPT-1001 : End physical optimization; 19.598356s wall, 20.718750s user + 0.250000s system = 20.968750s CPU (107.0%)
+
+RUN-1003 : finish command "place" in 69.392099s wall, 100.046875s user + 7.000000s system = 107.046875s CPU (154.3%)
+
+RUN-1004 : used memory is 646 MB, reserved memory is 659 MB, peak memory is 742 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.777703s wall, 3.062500s user + 0.015625s system = 3.078125s CPU (173.2%)
+
+RUN-1004 : used memory is 646 MB, reserved memory is 659 MB, peak memory is 742 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6868 instances
+RUN-1001 : 3353 mslices, 3364 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17671 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9991 nets have 2 pins
+RUN-1001 : 5821 nets have [3 - 5] pins
+RUN-1001 : 1147 nets have [6 - 10] pins
+RUN-1001 : 323 nets have [11 - 20] pins
+RUN-1001 : 361 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74418, tnet num: 17493, tinst num: 6866, tnode num: 96890, tedge num: 124901.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.771858s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (97.9%)
+
+RUN-1004 : used memory is 626 MB, reserved memory is 632 MB, peak memory is 742 MB
+PHY-1001 : 3353 mslices, 3364 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 4 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 880208, over cnt = 2800(7%), over = 4534, worst = 8
+PHY-1002 : len = 896544, over cnt = 1776(5%), over = 2560, worst = 8
+PHY-1002 : len = 912936, over cnt = 925(2%), over = 1298, worst = 6
+PHY-1002 : len = 933744, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 933792, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.622952s wall, 4.828125s user + 0.015625s system = 4.843750s CPU (133.7%)
+
+PHY-1001 : Congestion index: top1 = 56.23, top5 = 50.92, top10 = 47.76, top15 = 45.65.
+PHY-1001 : End global routing; 4.014911s wall, 5.218750s user + 0.015625s system = 5.234375s CPU (130.4%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 717, reserve = 722, peak = 742.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 991, reserve = 994, peak = 991.
+PHY-1001 : End build detailed router design. 4.554361s wall, 4.484375s user + 0.031250s system = 4.515625s CPU (99.1%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267216, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 6.775794s wall, 6.750000s user + 0.000000s system = 6.750000s CPU (99.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267272, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.630337s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (99.2%)
+
+PHY-1001 : Current memory(MB): used = 1026, reserve = 1030, peak = 1026.
+PHY-1001 : End phase 1; 7.420333s wall, 7.390625s user + 0.000000s system = 7.390625s CPU (99.6%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.37964e+06, over cnt = 1971(0%), over = 1977, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1042, reserve = 1044, peak = 1042.
+PHY-1001 : End initial routed; 37.043917s wall, 76.859375s user + 0.328125s system = 77.187500s CPU (208.4%)
+
+PHY-1001 : Update timing.....
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+PHY-1001 : 15/16594(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -2.183 | -4.924 | 5
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.720732s wall, 3.718750s user + 0.015625s system = 3.734375s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1051, reserve = 1054, peak = 1051.
+PHY-1001 : End phase 2; 40.764718s wall, 80.578125s user + 0.343750s system = 80.921875s CPU (198.5%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 7 pins with SWNS -2.059ns STNS -4.082ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.186124s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (92.3%)
+
+PHY-1022 : len = 2.37967e+06, over cnt = 1980(0%), over = 1986, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.509399s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (98.2%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.34211e+06, over cnt = 870(0%), over = 871, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.419541s wall, 3.640625s user + 0.000000s system = 3.640625s CPU (150.5%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.33666e+06, over cnt = 161(0%), over = 161, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.365958s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (125.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.3379e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.592767s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (110.7%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.221656s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (105.7%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.221049s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.0%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.259453s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (102.4%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.317609s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (103.3%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.200046s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.192279s wall, 0.218750s user + 0.031250s system = 0.250000s CPU (130.0%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.203108s wall, 0.234375s user + 0.015625s system = 0.250000s CPU (123.1%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.244604s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (102.2%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.320011s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (102.5%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.33796e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.216028s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (94.0%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.33796e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.202730s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (92.5%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.33794e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 15; 0.219983s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.4%)
+
+PHY-1001 : Update timing.....
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+PHY-1001 : 4/16594(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -2.059 | -4.082 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.695814s wall, 3.671875s user + 0.000000s system = 3.671875s CPU (99.4%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 627 feed throughs used by 436 nets
+PHY-1001 : End commit to database; 2.867116s wall, 2.843750s user + 0.000000s system = 2.843750s CPU (99.2%)
+
+PHY-1001 : Current memory(MB): used = 1157, reserve = 1164, peak = 1157.
+PHY-1001 : End phase 3; 14.730725s wall, 16.390625s user + 0.046875s system = 16.437500s CPU (111.6%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.059ns STNS -4.082ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.156939s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.6%)
+
+PHY-1022 : len = 2.33794e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.450946s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.5%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-2.059ns, -4.082ns, 3}
+PHY-1001 : Update timing.....
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+PHY-1001 : 4/16594(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -2.059 | -4.082 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.728404s wall, 3.703125s user + 0.015625s system = 3.718750s CPU (99.7%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 627 feed throughs used by 436 nets
+PHY-1001 : End commit to database; 2.961929s wall, 2.937500s user + 0.000000s system = 2.937500s CPU (99.2%)
+
+PHY-1001 : Current memory(MB): used = 1166, reserve = 1173, peak = 1166.
+PHY-1001 : End phase 4; 7.173864s wall, 7.125000s user + 0.015625s system = 7.140625s CPU (99.5%)
+
+PHY-1003 : Routed, final wirelength = 2.33794e+06
+PHY-1001 : Current memory(MB): used = 1168, reserve = 1175, peak = 1168.
+PHY-1001 : End export database. 0.074445s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (104.9%)
+
+PHY-1001 : End detail routing; 75.173417s wall, 116.453125s user + 0.437500s system = 116.890625s CPU (155.5%)
+
+RUN-1003 : finish command "route" in 82.200830s wall, 124.609375s user + 0.484375s system = 125.093750s CPU (152.2%)
+
+RUN-1004 : used memory is 1094 MB, reserved memory is 1103 MB, peak memory is 1168 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10345 out of 19600 52.78%
+#reg 9356 out of 19600 47.73%
+#le 12483
+ #lut only 3127 out of 12483 25.05%
+ #reg only 2138 out of 12483 17.13%
+ #lut® 7218 out of 12483 57.82%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1785
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1421
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1348
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 951
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 144
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg40_syn_225.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg50_syn_208.f1 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P140 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P17 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P25 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P16 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P118 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P104 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P83 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P32 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12483 |9318 |1027 |9390 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |558 |470 |23 |457 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |103 |85 |4 |91 |4 |0 |
+| U_crc16_24b |crc16_24b |34 |34 |0 |21 |0 |0 |
+| U_ecc_gen |ecc_gen |9 |9 |0 |8 |0 |0 |
+| exdev_ctl_a |exdev_ctl |785 |405 |96 |577 |0 |0 |
+| u_ADconfig |AD_config |191 |139 |25 |145 |0 |0 |
+| u_gen_sp |gen_sp |276 |185 |71 |114 |0 |0 |
+| exdev_ctl_b |exdev_ctl |761 |400 |96 |555 |0 |0 |
+| u_ADconfig |AD_config |186 |137 |25 |123 |0 |0 |
+| u_gen_sp |gen_sp |259 |173 |71 |116 |0 |0 |
+| sampling_fe_a |sampling_fe |2929 |2427 |306 |1994 |25 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |187 |138 |17 |141 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort |2708 |2271 |289 |1819 |25 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2358 |1986 |253 |1518 |22 |0 |
+| channelPart |channel_part_8478 |154 |151 |3 |138 |0 |0 |
+| fifo_adc |fifo_adc |61 |52 |9 |42 |0 |0 |
+| ram_switch |ram_switch |1853 |1549 |197 |1126 |0 |0 |
+| adc_addr_gen |adc_addr_gen |250 |223 |27 |124 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |8 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |27 |24 |3 |16 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |21 |18 |3 |9 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |29 |26 |3 |14 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |27 |24 |3 |12 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |30 |27 |3 |13 |0 |0 |
+| insert |insert |962 |685 |170 |654 |0 |0 |
+| ram_switch_state |ram_switch_state |641 |641 |0 |348 |0 |0 |
+| read_ram_i |read_ram |263 |208 |44 |185 |0 |0 |
+| read_ram_addr |read_ram_addr |210 |170 |40 |146 |0 |0 |
+| read_ram_data |read_ram_data |51 |36 |4 |37 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |316 |259 |36 |267 |3 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3306 |2572 |349 |2092 |25 |1 |
+| u0_soft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |185 |101 |17 |148 |0 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_sort |sort_rev |3087 |2458 |332 |1910 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2665 |2161 |290 |1546 |22 |1 |
+| channelPart |channel_part_8478 |232 |228 |3 |136 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |44 |0 |1 |
+| ram_switch |ram_switch |1981 |1613 |197 |1120 |0 |0 |
+| adc_addr_gen |adc_addr_gen |228 |201 |27 |105 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |4 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |28 |25 |3 |14 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |21 |18 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |21 |18 |3 |8 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |6 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |27 |24 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 |
+| insert |insert |1007 |668 |170 |696 |0 |0 |
+| ram_switch_state |ram_switch_state |746 |744 |0 |319 |0 |0 |
+| read_ram_i |read_ram_rev |359 |248 |81 |213 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |286 |202 |73 |160 |0 |0 |
+| read_ram_data |read_ram_data_rev |73 |46 |8 |53 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9929
+ #2 2 3890
+ #3 3 1404
+ #4 4 524
+ #5 5-10 1204
+ #6 11-50 601
+ #7 51-100 23
+ #8 >500 1
+ Average 2.92
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.188239s wall, 3.796875s user + 0.015625s system = 3.812500s CPU (174.2%)
+
+RUN-1004 : used memory is 1096 MB, reserved memory is 1104 MB, peak memory is 1168 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74418, tnet num: 17493, tinst num: 6866, tnode num: 96890, tedge num: 124901.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.780463s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (99.2%)
+
+RUN-1004 : used memory is 1100 MB, reserved memory is 1108 MB, peak memory is 1168 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 4 constraints in total.
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.728211s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (99.5%)
+
+RUN-1004 : used memory is 1102 MB, reserved memory is 1111 MB, peak memory is 1168 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6866
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17671, pip num: 175043
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 627
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3247 valid insts, and 483906 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 10.616648s wall, 62.578125s user + 0.265625s system = 62.843750s CPU (591.9%)
+
+RUN-1004 : used memory is 1266 MB, reserved memory is 1268 MB, peak memory is 1381 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240124_150658.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240125_160129.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240125_160129.log
new file mode 100644
index 0000000..4e23363
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240125_160129.log
@@ -0,0 +1,2137 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Jan 25 16:01:29 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.125701s wall, 2.031250s user + 0.093750s system = 2.125000s CPU (100.0%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 315 MB, peak memory is 341 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2945 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17775 instances
+RUN-0007 : 7512 luts, 9040 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20353 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13332 nets have 2 pins
+RUN-1001 : 5562 nets have [3 - 5] pins
+RUN-1001 : 1037 nets have [6 - 10] pins
+RUN-1001 : 172 nets have [11 - 20] pins
+RUN-1001 : 176 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 789
+RUN-1001 : No | No | Yes | 1968
+RUN-1001 : No | Yes | No | 3474
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 56
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 141
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17773 instances, 7512 luts, 9040 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 5912 pins
+PHY-0007 : Cell area utilization is 49%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85138, tnet num: 20175, tinst num: 17773, tnode num: 115214, tedge num: 136657.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.140641s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (100.0%)
+
+RUN-1004 : used memory is 530 MB, reserved memory is 514 MB, peak memory is 530 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20175 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.923289s wall, 1.906250s user + 0.015625s system = 1.921875s CPU (99.9%)
+
+PHY-3001 : Found 1221 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 3.89596e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17773.
+PHY-3001 : Level 1 #clusters 2040.
+PHY-3001 : End clustering; 0.130991s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (131.2%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 49%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.29757e+06, overlap = 462.656
+PHY-3002 : Step(2): len = 1.1629e+06, overlap = 479.438
+PHY-3002 : Step(3): len = 877919, overlap = 603.688
+PHY-3002 : Step(4): len = 773088, overlap = 624.219
+PHY-3002 : Step(5): len = 617637, overlap = 730.594
+PHY-3002 : Step(6): len = 538411, overlap = 804.375
+PHY-3002 : Step(7): len = 468960, overlap = 891.531
+PHY-3002 : Step(8): len = 424872, overlap = 971.75
+PHY-3002 : Step(9): len = 378631, overlap = 1037.12
+PHY-3002 : Step(10): len = 342449, overlap = 1120.22
+PHY-3002 : Step(11): len = 311259, overlap = 1160
+PHY-3002 : Step(12): len = 290794, overlap = 1184.34
+PHY-3002 : Step(13): len = 260766, overlap = 1259.06
+PHY-3002 : Step(14): len = 244497, overlap = 1335.81
+PHY-3002 : Step(15): len = 222920, overlap = 1324.88
+PHY-3002 : Step(16): len = 205645, overlap = 1356.78
+PHY-3002 : Step(17): len = 186751, overlap = 1417.72
+PHY-3002 : Step(18): len = 175204, overlap = 1435.75
+PHY-3002 : Step(19): len = 158208, overlap = 1442.38
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.8099e-07
+PHY-3002 : Step(20): len = 156663, overlap = 1402.94
+PHY-3002 : Step(21): len = 186690, overlap = 1305.41
+PHY-3002 : Step(22): len = 190772, overlap = 1238.53
+PHY-3002 : Step(23): len = 193578, overlap = 1174.28
+PHY-3002 : Step(24): len = 194097, overlap = 1145.38
+PHY-3002 : Step(25): len = 191056, overlap = 1144.28
+PHY-3002 : Step(26): len = 186137, overlap = 1131.47
+PHY-3002 : Step(27): len = 182203, overlap = 1127.28
+PHY-3002 : Step(28): len = 177149, overlap = 1132.38
+PHY-3002 : Step(29): len = 173968, overlap = 1134.75
+PHY-3002 : Step(30): len = 171438, overlap = 1122.5
+PHY-3002 : Step(31): len = 170745, overlap = 1137.44
+PHY-3002 : Step(32): len = 169880, overlap = 1155.31
+PHY-3002 : Step(33): len = 168072, overlap = 1159.62
+PHY-3002 : Step(34): len = 167510, overlap = 1179.16
+PHY-3002 : Step(35): len = 166098, overlap = 1179.12
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.96198e-06
+PHY-3002 : Step(36): len = 168935, overlap = 1178.62
+PHY-3002 : Step(37): len = 181195, overlap = 1159.62
+PHY-3002 : Step(38): len = 186322, overlap = 1129.03
+PHY-3002 : Step(39): len = 190015, overlap = 1121.06
+PHY-3002 : Step(40): len = 191488, overlap = 1092.59
+PHY-3002 : Step(41): len = 193055, overlap = 1089.22
+PHY-3002 : Step(42): len = 192200, overlap = 1079.25
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.92396e-06
+PHY-3002 : Step(43): len = 197331, overlap = 1040.91
+PHY-3002 : Step(44): len = 213722, overlap = 967.469
+PHY-3002 : Step(45): len = 223009, overlap = 895.438
+PHY-3002 : Step(46): len = 229131, overlap = 855.469
+PHY-3002 : Step(47): len = 231083, overlap = 842.312
+PHY-3002 : Step(48): len = 233377, overlap = 856.969
+PHY-3002 : Step(49): len = 233744, overlap = 857.875
+PHY-3002 : Step(50): len = 235587, overlap = 867.031
+PHY-3002 : Step(51): len = 235354, overlap = 861.438
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.84792e-06
+PHY-3002 : Step(52): len = 246896, overlap = 834.469
+PHY-3002 : Step(53): len = 268089, overlap = 739.219
+PHY-3002 : Step(54): len = 279391, overlap = 659.062
+PHY-3002 : Step(55): len = 287928, overlap = 594.281
+PHY-3002 : Step(56): len = 288906, overlap = 585.375
+PHY-3002 : Step(57): len = 288771, overlap = 593.406
+PHY-3002 : Step(58): len = 286923, overlap = 585.344
+PHY-3002 : Step(59): len = 287061, overlap = 573.062
+PHY-3002 : Step(60): len = 285808, overlap = 580.281
+PHY-3002 : Step(61): len = 284942, overlap = 575.844
+PHY-3002 : Step(62): len = 283975, overlap = 577.094
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.56958e-05
+PHY-3002 : Step(63): len = 301612, overlap = 554.906
+PHY-3002 : Step(64): len = 316624, overlap = 504.219
+PHY-3002 : Step(65): len = 322629, overlap = 480.094
+PHY-3002 : Step(66): len = 324137, overlap = 469.531
+PHY-3002 : Step(67): len = 323361, overlap = 472.406
+PHY-3002 : Step(68): len = 325058, overlap = 450.469
+PHY-3002 : Step(69): len = 325597, overlap = 430.094
+PHY-3002 : Step(70): len = 327829, overlap = 418.938
+PHY-3002 : Step(71): len = 329741, overlap = 414.156
+PHY-3002 : Step(72): len = 331913, overlap = 401.656
+PHY-3002 : Step(73): len = 332237, overlap = 400.969
+PHY-3002 : Step(74): len = 333391, overlap = 391.031
+PHY-3002 : Step(75): len = 333103, overlap = 391
+PHY-3002 : Step(76): len = 333776, overlap = 394.125
+PHY-3002 : Step(77): len = 332190, overlap = 405.5
+PHY-3002 : Step(78): len = 332437, overlap = 407.719
+PHY-3002 : Step(79): len = 331329, overlap = 407.906
+PHY-3002 : Step(80): len = 332142, overlap = 411.781
+PHY-3002 : Step(81): len = 331701, overlap = 413.281
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.13917e-05
+PHY-3002 : Step(82): len = 351585, overlap = 386.875
+PHY-3002 : Step(83): len = 367888, overlap = 351.5
+PHY-3002 : Step(84): len = 371263, overlap = 341.5
+PHY-3002 : Step(85): len = 371893, overlap = 341.469
+PHY-3002 : Step(86): len = 371268, overlap = 331.375
+PHY-3002 : Step(87): len = 373947, overlap = 316.781
+PHY-3002 : Step(88): len = 372578, overlap = 331.281
+PHY-3002 : Step(89): len = 372262, overlap = 311
+PHY-3002 : Step(90): len = 370875, overlap = 305.688
+PHY-3002 : Step(91): len = 369481, overlap = 316.344
+PHY-3002 : Step(92): len = 368228, overlap = 325.875
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.27833e-05
+PHY-3002 : Step(93): len = 386162, overlap = 324.625
+PHY-3002 : Step(94): len = 398071, overlap = 314.969
+PHY-3002 : Step(95): len = 397724, overlap = 315.312
+PHY-3002 : Step(96): len = 398588, overlap = 306.125
+PHY-3002 : Step(97): len = 400836, overlap = 299
+PHY-3002 : Step(98): len = 404172, overlap = 294.875
+PHY-3002 : Step(99): len = 400926, overlap = 303.688
+PHY-3002 : Step(100): len = 401232, overlap = 311.594
+PHY-3002 : Step(101): len = 402184, overlap = 306.562
+PHY-3002 : Step(102): len = 403572, overlap = 301.562
+PHY-3002 : Step(103): len = 401082, overlap = 294.625
+PHY-3002 : Step(104): len = 401332, overlap = 293.188
+PHY-3002 : Step(105): len = 402786, overlap = 289.438
+PHY-3002 : Step(106): len = 404474, overlap = 282.25
+PHY-3002 : Step(107): len = 401570, overlap = 282.156
+PHY-3002 : Step(108): len = 400928, overlap = 281.875
+PHY-3002 : Step(109): len = 401320, overlap = 280.031
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000125567
+PHY-3002 : Step(110): len = 415734, overlap = 278.844
+PHY-3002 : Step(111): len = 424875, overlap = 277.594
+PHY-3002 : Step(112): len = 423431, overlap = 274.656
+PHY-3002 : Step(113): len = 423706, overlap = 272.375
+PHY-3002 : Step(114): len = 426866, overlap = 268
+PHY-3002 : Step(115): len = 429973, overlap = 257.938
+PHY-3002 : Step(116): len = 428844, overlap = 265.594
+PHY-3002 : Step(117): len = 431188, overlap = 269
+PHY-3002 : Step(118): len = 433840, overlap = 260.062
+PHY-3002 : Step(119): len = 435929, overlap = 259
+PHY-3002 : Step(120): len = 432763, overlap = 265.5
+PHY-3002 : Step(121): len = 432653, overlap = 262.219
+PHY-3002 : Step(122): len = 435177, overlap = 260.031
+PHY-3002 : Step(123): len = 436603, overlap = 259.219
+PHY-3002 : Step(124): len = 433791, overlap = 267.469
+PHY-3002 : Step(125): len = 433574, overlap = 260.344
+PHY-3002 : Step(126): len = 435343, overlap = 253.344
+PHY-3002 : Step(127): len = 436562, overlap = 245.688
+PHY-3002 : Step(128): len = 434797, overlap = 246.062
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000236903
+PHY-3002 : Step(129): len = 444282, overlap = 238.844
+PHY-3002 : Step(130): len = 451012, overlap = 228.938
+PHY-3002 : Step(131): len = 450372, overlap = 225.688
+PHY-3002 : Step(132): len = 451431, overlap = 225.531
+PHY-3002 : Step(133): len = 455272, overlap = 223.906
+PHY-3002 : Step(134): len = 458279, overlap = 213.156
+PHY-3002 : Step(135): len = 456500, overlap = 219.812
+PHY-3002 : Step(136): len = 456383, overlap = 215.5
+PHY-3002 : Step(137): len = 459537, overlap = 209.531
+PHY-3002 : Step(138): len = 462095, overlap = 204.5
+PHY-3002 : Step(139): len = 459085, overlap = 201.312
+PHY-3002 : Step(140): len = 458873, overlap = 196
+PHY-3002 : Step(141): len = 461435, overlap = 190.344
+PHY-3002 : Step(142): len = 462591, overlap = 189.406
+PHY-3002 : Step(143): len = 461447, overlap = 189.25
+PHY-3002 : Step(144): len = 461471, overlap = 187.688
+PHY-3002 : Step(145): len = 462359, overlap = 189.625
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000452482
+PHY-3002 : Step(146): len = 470617, overlap = 184.094
+PHY-3002 : Step(147): len = 477917, overlap = 173.219
+PHY-3002 : Step(148): len = 478610, overlap = 176.656
+PHY-3002 : Step(149): len = 480161, overlap = 164.375
+PHY-3002 : Step(150): len = 484571, overlap = 155.562
+PHY-3002 : Step(151): len = 488258, overlap = 153.25
+PHY-3002 : Step(152): len = 486499, overlap = 147.875
+PHY-3002 : Step(153): len = 487343, overlap = 145.531
+PHY-3002 : Step(154): len = 491700, overlap = 147.812
+PHY-3002 : Step(155): len = 494491, overlap = 145.688
+PHY-3002 : Step(156): len = 491951, overlap = 144.531
+PHY-3002 : Step(157): len = 491821, overlap = 150.344
+PHY-3002 : Step(158): len = 493596, overlap = 140.969
+PHY-3002 : Step(159): len = 494833, overlap = 127.844
+PHY-3002 : Step(160): len = 493597, overlap = 136.469
+PHY-3002 : Step(161): len = 493390, overlap = 137.125
+PHY-3002 : Step(162): len = 494495, overlap = 144.438
+PHY-3002 : Step(163): len = 495586, overlap = 144.812
+PHY-3002 : Step(164): len = 494259, overlap = 146.812
+PHY-3002 : Step(165): len = 494157, overlap = 146.781
+PHY-3002 : Step(166): len = 494939, overlap = 149.312
+PHY-3002 : Step(167): len = 495234, overlap = 150.75
+PHY-3002 : Step(168): len = 494605, overlap = 148.469
+PHY-3002 : Step(169): len = 494596, overlap = 150.625
+PHY-3002 : Step(170): len = 495427, overlap = 150.719
+PHY-3002 : Step(171): len = 495907, overlap = 150.562
+PHY-3002 : Step(172): len = 495995, overlap = 153.688
+PHY-3002 : Step(173): len = 496634, overlap = 147.406
+PHY-3002 : Step(174): len = 497727, overlap = 148.812
+PHY-3002 : Step(175): len = 498234, overlap = 148.906
+PHY-3002 : Step(176): len = 497088, overlap = 151.688
+PHY-3002 : Step(177): len = 496812, overlap = 142.656
+PHY-3002 : Step(178): len = 497044, overlap = 144.5
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000886506
+PHY-3002 : Step(179): len = 501976, overlap = 136.312
+PHY-3002 : Step(180): len = 506417, overlap = 132.906
+PHY-3002 : Step(181): len = 506643, overlap = 133.438
+PHY-3002 : Step(182): len = 507287, overlap = 135.5
+PHY-3002 : Step(183): len = 509665, overlap = 133.625
+PHY-3002 : Step(184): len = 510585, overlap = 132.625
+PHY-3002 : Step(185): len = 509590, overlap = 137.625
+PHY-3002 : Step(186): len = 509229, overlap = 137.688
+PHY-3002 : Step(187): len = 510837, overlap = 136.719
+PHY-3002 : Step(188): len = 511943, overlap = 132.969
+PHY-3002 : Step(189): len = 511142, overlap = 135.562
+PHY-3002 : Step(190): len = 510980, overlap = 135.062
+PHY-3002 : Step(191): len = 512087, overlap = 128.594
+PHY-3002 : Step(192): len = 512355, overlap = 125.688
+PHY-3002 : Step(193): len = 511831, overlap = 125.938
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00147078
+PHY-3002 : Step(194): len = 514237, overlap = 123.344
+PHY-3002 : Step(195): len = 517269, overlap = 125.594
+PHY-3002 : Step(196): len = 517984, overlap = 126.438
+PHY-3002 : Step(197): len = 519003, overlap = 119.812
+PHY-3002 : Step(198): len = 521306, overlap = 119.031
+PHY-3002 : Step(199): len = 522408, overlap = 118.156
+PHY-3002 : Step(200): len = 521643, overlap = 118.219
+PHY-3002 : Step(201): len = 521643, overlap = 118.219
+PHY-3002 : Step(202): len = 521990, overlap = 116.656
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00246286
+PHY-3002 : Step(203): len = 524384, overlap = 108.938
+PHY-3002 : Step(204): len = 530370, overlap = 105.438
+PHY-3002 : Step(205): len = 530913, overlap = 105.375
+PHY-3002 : Step(206): len = 531118, overlap = 104.156
+PHY-3002 : Step(207): len = 531394, overlap = 105.781
+PHY-3002 : Step(208): len = 531956, overlap = 104.406
+PHY-3002 : Step(209): len = 533544, overlap = 98.4688
+PHY-3002 : Step(210): len = 536114, overlap = 99.1562
+PHY-3002 : Step(211): len = 537107, overlap = 96.75
+PHY-3002 : Step(212): len = 537530, overlap = 96.4062
+PHY-3002 : Step(213): len = 537758, overlap = 95.2188
+PHY-3002 : Step(214): len = 537806, overlap = 93.3438
+PHY-3002 : Step(215): len = 537817, overlap = 93.1562
+PHY-3002 : Step(216): len = 537829, overlap = 93.1562
+PHY-3002 : Step(217): len = 537748, overlap = 91.9062
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.014266s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (109.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20353.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 700672, over cnt = 1609(4%), over = 7201, worst = 42
+PHY-1001 : End global iterations; 0.720828s wall, 0.921875s user + 0.031250s system = 0.953125s CPU (132.2%)
+
+PHY-1001 : Congestion index: top1 = 73.84, top5 = 59.34, top10 = 51.29, top15 = 46.17.
+PHY-3001 : End congestion estimation; 0.938893s wall, 1.125000s user + 0.046875s system = 1.171875s CPU (124.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20175 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.848947s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (101.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000135377
+PHY-3002 : Step(218): len = 630948, overlap = 46
+PHY-3002 : Step(219): len = 635028, overlap = 49
+PHY-3002 : Step(220): len = 631250, overlap = 51.0625
+PHY-3002 : Step(221): len = 626604, overlap = 53.0312
+PHY-3002 : Step(222): len = 623408, overlap = 51.6875
+PHY-3002 : Step(223): len = 623545, overlap = 49.0312
+PHY-3002 : Step(224): len = 621522, overlap = 43.5
+PHY-3002 : Step(225): len = 621229, overlap = 35.125
+PHY-3002 : Step(226): len = 616062, overlap = 32.5
+PHY-3002 : Step(227): len = 614580, overlap = 33.0625
+PHY-3002 : Step(228): len = 610792, overlap = 33.4688
+PHY-3002 : Step(229): len = 610321, overlap = 32.5938
+PHY-3002 : Step(230): len = 608441, overlap = 29.5625
+PHY-3002 : Step(231): len = 607054, overlap = 26.2188
+PHY-3002 : Step(232): len = 605476, overlap = 28.9062
+PHY-3002 : Step(233): len = 606073, overlap = 31.3438
+PHY-3002 : Step(234): len = 603996, overlap = 30.3438
+PHY-3002 : Step(235): len = 603258, overlap = 29.5312
+PHY-3002 : Step(236): len = 601756, overlap = 24.4688
+PHY-3002 : Step(237): len = 602156, overlap = 23.2812
+PHY-3002 : Step(238): len = 600075, overlap = 24.2188
+PHY-3002 : Step(239): len = 599165, overlap = 24.5625
+PHY-3002 : Step(240): len = 598241, overlap = 25.8438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000270753
+PHY-3002 : Step(241): len = 601678, overlap = 21.9062
+PHY-3002 : Step(242): len = 604997, overlap = 20.1875
+PHY-3002 : Step(243): len = 611069, overlap = 20.6562
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000541506
+PHY-3002 : Step(244): len = 617901, overlap = 19.5
+PHY-3002 : Step(245): len = 632241, overlap = 18.9688
+PHY-3002 : Step(246): len = 641823, overlap = 17.0938
+PHY-3002 : Step(247): len = 641020, overlap = 17.1562
+PHY-3002 : Step(248): len = 639625, overlap = 18.8438
+PHY-3002 : Step(249): len = 639937, overlap = 20.9062
+PHY-3002 : Step(250): len = 639997, overlap = 23.5625
+PHY-3002 : Step(251): len = 641594, overlap = 22.8438
+PHY-3002 : Step(252): len = 642912, overlap = 24.5312
+PHY-3002 : Step(253): len = 642882, overlap = 25.5938
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00108301
+PHY-3002 : Step(254): len = 646252, overlap = 26.5938
+PHY-3002 : Step(255): len = 655391, overlap = 24.0625
+PHY-3002 : Step(256): len = 667010, overlap = 23.6562
+PHY-3002 : Step(257): len = 669904, overlap = 28.7812
+PHY-3002 : Step(258): len = 671784, overlap = 31.9688
+PHY-3002 : Step(259): len = 671015, overlap = 33.1562
+PHY-3002 : Step(260): len = 670204, overlap = 33.6562
+PHY-3002 : Step(261): len = 667843, overlap = 36.25
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00177864
+PHY-3002 : Step(262): len = 671303, overlap = 36.0938
+PHY-3002 : Step(263): len = 678221, overlap = 38.875
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 60/20353.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 763952, over cnt = 2693(7%), over = 13615, worst = 42
+PHY-1001 : End global iterations; 1.492361s wall, 2.125000s user + 0.062500s system = 2.187500s CPU (146.6%)
+
+PHY-1001 : Congestion index: top1 = 98.94, top5 = 76.35, top10 = 66.08, top15 = 59.62.
+PHY-3001 : End congestion estimation; 1.760868s wall, 2.390625s user + 0.062500s system = 2.453125s CPU (139.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20175 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.290801s wall, 1.265625s user + 0.015625s system = 1.281250s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000118726
+PHY-3002 : Step(264): len = 669518, overlap = 269.688
+PHY-3002 : Step(265): len = 664619, overlap = 206.062
+PHY-3002 : Step(266): len = 653150, overlap = 183.188
+PHY-3002 : Step(267): len = 641573, overlap = 168.531
+PHY-3002 : Step(268): len = 633196, overlap = 153.531
+PHY-3002 : Step(269): len = 626548, overlap = 145.188
+PHY-3002 : Step(270): len = 620766, overlap = 136.812
+PHY-3002 : Step(271): len = 615925, overlap = 140.188
+PHY-3002 : Step(272): len = 611682, overlap = 142.344
+PHY-3002 : Step(273): len = 608078, overlap = 134.812
+PHY-3002 : Step(274): len = 604407, overlap = 133.656
+PHY-3002 : Step(275): len = 600785, overlap = 130.938
+PHY-3002 : Step(276): len = 595855, overlap = 133.625
+PHY-3002 : Step(277): len = 592223, overlap = 138.344
+PHY-3002 : Step(278): len = 588694, overlap = 136.969
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000237451
+PHY-3002 : Step(279): len = 589371, overlap = 135.188
+PHY-3002 : Step(280): len = 592314, overlap = 133
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000429447
+PHY-3002 : Step(281): len = 594227, overlap = 125.812
+PHY-3002 : Step(282): len = 602176, overlap = 108.781
+PHY-3002 : Step(283): len = 607678, overlap = 99.6562
+PHY-3002 : Step(284): len = 606782, overlap = 96.75
+PHY-3002 : Step(285): len = 606431, overlap = 90.125
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000794764
+PHY-3002 : Step(286): len = 609761, overlap = 88.5
+PHY-3002 : Step(287): len = 614620, overlap = 81.5625
+PHY-3002 : Step(288): len = 620074, overlap = 76.125
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85138, tnet num: 20175, tinst num: 17773, tnode num: 115214, tedge num: 136657.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.481479s wall, 1.390625s user + 0.078125s system = 1.468750s CPU (99.1%)
+
+RUN-1004 : used memory is 574 MB, reserved memory is 563 MB, peak memory is 711 MB
+OPT-1001 : Total overflow 384.38 peak overflow 4.62
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 413/20353.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 721456, over cnt = 3072(8%), over = 10798, worst = 28
+PHY-1001 : End global iterations; 1.478544s wall, 2.078125s user + 0.015625s system = 2.093750s CPU (141.6%)
+
+PHY-1001 : Congestion index: top1 = 72.07, top5 = 56.62, top10 = 50.94, top15 = 47.39.
+PHY-1001 : End incremental global routing; 1.836822s wall, 2.437500s user + 0.015625s system = 2.453125s CPU (133.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20175 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.921785s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (100.0%)
+
+OPT-1001 : 48 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17640 has valid locations, 324 needs to be replaced
+PHY-3001 : design contains 18049 instances, 7595 luts, 9233 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 6033 pins
+PHY-3001 : Found 1230 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 645008
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16893/20629.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 736584, over cnt = 3129(8%), over = 10834, worst = 28
+PHY-1001 : End global iterations; 0.239303s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (130.6%)
+
+PHY-1001 : Congestion index: top1 = 71.66, top5 = 56.85, top10 = 51.21, top15 = 47.73.
+PHY-3001 : End congestion estimation; 0.502302s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (115.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86241, tnet num: 20451, tinst num: 18049, tnode num: 116901, tedge num: 138311.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.483218s wall, 1.453125s user + 0.031250s system = 1.484375s CPU (100.1%)
+
+RUN-1004 : used memory is 620 MB, reserved memory is 614 MB, peak memory is 716 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20451 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.557506s wall, 2.453125s user + 0.031250s system = 2.484375s CPU (97.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(289): len = 644220, overlap = 0.28125
+PHY-3002 : Step(290): len = 643884, overlap = 0.28125
+PHY-3002 : Step(291): len = 643604, overlap = 0.28125
+PHY-3002 : Step(292): len = 643373, overlap = 0.28125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17008/20629.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 735056, over cnt = 3144(8%), over = 10864, worst = 28
+PHY-1001 : End global iterations; 0.198810s wall, 0.281250s user + 0.031250s system = 0.312500s CPU (157.2%)
+
+PHY-1001 : Congestion index: top1 = 73.25, top5 = 57.36, top10 = 51.51, top15 = 47.89.
+PHY-3001 : End congestion estimation; 0.460963s wall, 0.546875s user + 0.031250s system = 0.578125s CPU (125.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20451 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.934078s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000331278
+PHY-3002 : Step(293): len = 643268, overlap = 78.125
+PHY-3002 : Step(294): len = 643201, overlap = 78.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000662557
+PHY-3002 : Step(295): len = 643388, overlap = 78.125
+PHY-3002 : Step(296): len = 643841, overlap = 79.0312
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00132511
+PHY-3002 : Step(297): len = 644143, overlap = 78.5
+PHY-3002 : Step(298): len = 644374, overlap = 78.5312
+PHY-3001 : Final: Len = 644374, Over = 78.5312
+PHY-3001 : End incremental placement; 5.209263s wall, 5.640625s user + 0.265625s system = 5.906250s CPU (113.4%)
+
+OPT-1001 : Total overflow 393.16 peak overflow 4.62
+OPT-1001 : End high-fanout net optimization; 8.612080s wall, 9.718750s user + 0.296875s system = 10.015625s CPU (116.3%)
+
+OPT-1001 : Current memory(MB): used = 718, reserve = 713, peak = 735.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16915/20629.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 738568, over cnt = 3082(8%), over = 9721, worst = 28
+PHY-1002 : len = 786184, over cnt = 2087(5%), over = 5131, worst = 15
+PHY-1002 : len = 824352, over cnt = 922(2%), over = 2182, worst = 15
+PHY-1002 : len = 852280, over cnt = 264(0%), over = 530, worst = 14
+PHY-1002 : len = 861928, over cnt = 3(0%), over = 3, worst = 1
+PHY-1001 : End global iterations; 1.678530s wall, 2.437500s user + 0.046875s system = 2.484375s CPU (148.0%)
+
+PHY-1001 : Congestion index: top1 = 58.79, top5 = 50.79, top10 = 47.03, top15 = 44.64.
+OPT-1001 : End congestion update; 1.948044s wall, 2.718750s user + 0.046875s system = 2.765625s CPU (142.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20451 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.998850s wall, 0.968750s user + 0.031250s system = 1.000000s CPU (100.1%)
+
+OPT-0007 : Start: WNS -1018 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 62 cells processed and 3408 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 12 cells processed and 1121 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 7 cells processed and 400 slack improved
+OPT-1001 : End global optimization; 2.986793s wall, 3.718750s user + 0.078125s system = 3.796875s CPU (127.1%)
+
+OPT-1001 : Current memory(MB): used = 692, reserve = 689, peak = 735.
+OPT-1001 : End physical optimization; 13.705654s wall, 15.468750s user + 0.453125s system = 15.921875s CPU (116.2%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7595 LUT to BLE ...
+SYN-4008 : Packed 7595 LUT and 3081 SEQ to BLE.
+SYN-4003 : Packing 6152 remaining SEQ's ...
+SYN-4005 : Packed 3984 SEQ with LUT/SLICE
+SYN-4006 : 831 single LUT's are left
+SYN-4006 : 2168 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9763/13494 primitive instances ...
+PHY-3001 : End packing; 1.599109s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (99.7%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6795 instances
+RUN-1001 : 3324 mslices, 3323 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17679 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10042 nets have 2 pins
+RUN-1001 : 5818 nets have [3 - 5] pins
+RUN-1001 : 1124 nets have [6 - 10] pins
+RUN-1001 : 322 nets have [11 - 20] pins
+RUN-1001 : 342 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6793 instances, 6647 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3577 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 653690, Over = 247.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7338/17679.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 809768, over cnt = 2014(5%), over = 3301, worst = 7
+PHY-1002 : len = 817336, over cnt = 1348(3%), over = 2003, worst = 6
+PHY-1002 : len = 829864, over cnt = 696(1%), over = 969, worst = 6
+PHY-1002 : len = 838600, over cnt = 307(0%), over = 405, worst = 6
+PHY-1002 : len = 846448, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.690475s wall, 2.343750s user + 0.015625s system = 2.359375s CPU (139.6%)
+
+PHY-1001 : Congestion index: top1 = 59.72, top5 = 51.25, top10 = 47.19, top15 = 44.64.
+PHY-3001 : End congestion estimation; 2.112802s wall, 2.734375s user + 0.015625s system = 2.750000s CPU (130.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74242, tnet num: 17501, tinst num: 6793, tnode num: 96697, tedge num: 124613.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.641733s wall, 1.578125s user + 0.062500s system = 1.640625s CPU (99.9%)
+
+RUN-1004 : used memory is 613 MB, reserved memory is 619 MB, peak memory is 735 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17501 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.519795s wall, 2.453125s user + 0.062500s system = 2.515625s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.55946e-05
+PHY-3002 : Step(299): len = 642343, overlap = 250
+PHY-3002 : Step(300): len = 636811, overlap = 248.25
+PHY-3002 : Step(301): len = 634048, overlap = 249.5
+PHY-3002 : Step(302): len = 631702, overlap = 251.5
+PHY-3002 : Step(303): len = 629529, overlap = 255.5
+PHY-3002 : Step(304): len = 628030, overlap = 249.5
+PHY-3002 : Step(305): len = 625970, overlap = 248
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.11892e-05
+PHY-3002 : Step(306): len = 629598, overlap = 239.5
+PHY-3002 : Step(307): len = 634077, overlap = 232.25
+PHY-3002 : Step(308): len = 634758, overlap = 228.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000182378
+PHY-3002 : Step(309): len = 647005, overlap = 214.5
+PHY-3002 : Step(310): len = 659949, overlap = 205.25
+PHY-3002 : Step(311): len = 657992, overlap = 203.5
+PHY-3002 : Step(312): len = 656420, overlap = 202.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.395145s wall, 0.343750s user + 0.578125s system = 0.921875s CPU (233.3%)
+
+PHY-3001 : Trial Legalized: Len = 740728
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 892/17679.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 860544, over cnt = 2805(7%), over = 4673, worst = 7
+PHY-1002 : len = 880136, over cnt = 1558(4%), over = 2203, worst = 6
+PHY-1002 : len = 898448, over cnt = 571(1%), over = 768, worst = 6
+PHY-1002 : len = 909120, over cnt = 150(0%), over = 206, worst = 6
+PHY-1002 : len = 912664, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations; 2.512586s wall, 3.625000s user + 0.015625s system = 3.640625s CPU (144.9%)
+
+PHY-1001 : Congestion index: top1 = 57.28, top5 = 51.44, top10 = 48.37, top15 = 46.24.
+PHY-3001 : End congestion estimation; 2.992808s wall, 4.109375s user + 0.015625s system = 4.125000s CPU (137.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17501 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.865999s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (101.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000159859
+PHY-3002 : Step(313): len = 711657, overlap = 44
+PHY-3002 : Step(314): len = 696442, overlap = 67.75
+PHY-3002 : Step(315): len = 683295, overlap = 94.75
+PHY-3002 : Step(316): len = 676340, overlap = 112.25
+PHY-3002 : Step(317): len = 670701, overlap = 128.25
+PHY-3002 : Step(318): len = 667515, overlap = 142.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000319718
+PHY-3002 : Step(319): len = 674272, overlap = 141
+PHY-3002 : Step(320): len = 680380, overlap = 143.25
+PHY-3002 : Step(321): len = 682978, overlap = 141
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000592047
+PHY-3002 : Step(322): len = 689017, overlap = 140
+PHY-3002 : Step(323): len = 702709, overlap = 144.25
+PHY-3002 : Step(324): len = 710832, overlap = 142
+PHY-3002 : Step(325): len = 711581, overlap = 142
+PHY-3002 : Step(326): len = 711658, overlap = 142.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.035407s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (88.3%)
+
+PHY-3001 : Legalized: Len = 737055, Over = 0
+PHY-3001 : Spreading special nets. 461 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.103390s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (105.8%)
+
+PHY-3001 : 663 instances has been re-located, deltaX = 218, deltaY = 381, maxDist = 4.
+PHY-3001 : Final: Len = 747201, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74242, tnet num: 17501, tinst num: 6796, tnode num: 96697, tedge num: 124613.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.885318s wall, 1.859375s user + 0.015625s system = 1.875000s CPU (99.5%)
+
+RUN-1004 : used memory is 626 MB, reserved memory is 647 MB, peak memory is 735 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3223/17679.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 879608, over cnt = 2645(7%), over = 4286, worst = 7
+PHY-1002 : len = 896320, over cnt = 1480(4%), over = 2036, worst = 5
+PHY-1002 : len = 903992, over cnt = 994(2%), over = 1375, worst = 5
+PHY-1002 : len = 921216, over cnt = 259(0%), over = 336, worst = 4
+PHY-1002 : len = 925840, over cnt = 52(0%), over = 60, worst = 4
+PHY-1001 : End global iterations; 2.337459s wall, 3.375000s user + 0.062500s system = 3.437500s CPU (147.1%)
+
+PHY-1001 : Congestion index: top1 = 57.31, top5 = 51.07, top10 = 47.74, top15 = 45.61.
+PHY-1001 : End incremental global routing; 2.728007s wall, 3.750000s user + 0.062500s system = 3.812500s CPU (139.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17501 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.902714s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (100.4%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6703 has valid locations, 25 needs to be replaced
+PHY-3001 : design contains 6816 instances, 6667 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3646 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 750563
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16128/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928816, over cnt = 139(0%), over = 165, worst = 6
+PHY-1002 : len = 928880, over cnt = 79(0%), over = 85, worst = 4
+PHY-1002 : len = 929824, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 929936, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 930000, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.827259s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (105.8%)
+
+PHY-1001 : Congestion index: top1 = 57.35, top5 = 51.02, top10 = 47.73, top15 = 45.62.
+PHY-3001 : End congestion estimation; 1.147801s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (103.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74409, tnet num: 17521, tinst num: 6816, tnode num: 96897, tedge num: 124812.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.867032s wall, 1.859375s user + 0.000000s system = 1.859375s CPU (99.6%)
+
+RUN-1004 : used memory is 657 MB, reserved memory is 665 MB, peak memory is 735 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.757105s wall, 2.734375s user + 0.015625s system = 2.750000s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(327): len = 750183, overlap = 0.25
+PHY-3002 : Step(328): len = 749856, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16132/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928976, over cnt = 37(0%), over = 52, worst = 4
+PHY-1002 : len = 929104, over cnt = 18(0%), over = 23, worst = 3
+PHY-1002 : len = 929352, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 929480, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.609856s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (105.0%)
+
+PHY-1001 : Congestion index: top1 = 57.35, top5 = 51.03, top10 = 47.73, top15 = 45.62.
+PHY-3001 : End congestion estimation; 0.942562s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (102.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.891143s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000333934
+PHY-3002 : Step(329): len = 749842, overlap = 0.5
+PHY-3002 : Step(330): len = 749699, overlap = 0.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.006057s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (258.0%)
+
+PHY-3001 : Legalized: Len = 749683, Over = 0
+PHY-3001 : End spreading; 0.058489s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.9%)
+
+PHY-3001 : Final: Len = 749683, Over = 0
+PHY-3001 : End incremental placement; 6.692545s wall, 6.296875s user + 0.140625s system = 6.437500s CPU (96.2%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.820167s wall, 11.406250s user + 0.218750s system = 11.625000s CPU (107.4%)
+
+OPT-1001 : Current memory(MB): used = 740, reserve = 740, peak = 743.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16123/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 929256, over cnt = 54(0%), over = 70, worst = 5
+PHY-1002 : len = 929416, over cnt = 40(0%), over = 46, worst = 3
+PHY-1002 : len = 929824, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 930032, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 930048, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.791853s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (108.5%)
+
+PHY-1001 : Congestion index: top1 = 57.35, top5 = 51.04, top10 = 47.73, top15 = 45.62.
+OPT-1001 : End congestion update; 1.110805s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (105.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.729037s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.7%)
+
+OPT-0007 : Start: WNS -986 TNS -1650 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6728 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6816 instances, 6667 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3646 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 755367, Over = 0
+PHY-3001 : Spreading special nets. 19 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060791s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.8%)
+
+PHY-3001 : 24 instances has been re-located, deltaX = 15, deltaY = 16, maxDist = 2.
+PHY-3001 : Final: Len = 755869, Over = 0
+PHY-3001 : End incremental legalization; 0.389270s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.3%)
+
+OPT-0007 : Iter 1: improved WNS -890 TNS -1375 NUM_FEPS 2 with 58 cells processed and 13549 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6728 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6816 instances, 6667 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3646 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 759241, Over = 0
+PHY-3001 : Spreading special nets. 17 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062069s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.7%)
+
+PHY-3001 : 24 instances has been re-located, deltaX = 14, deltaY = 20, maxDist = 3.
+PHY-3001 : Final: Len = 759391, Over = 0
+PHY-3001 : End incremental legalization; 0.434159s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.2%)
+
+OPT-0007 : Iter 2: improved WNS -890 TNS -1525 NUM_FEPS 2 with 27 cells processed and 5153 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6728 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6816 instances, 6667 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3646 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 761173, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060238s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.8%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 8, deltaY = 10, maxDist = 2.
+PHY-3001 : Final: Len = 761087, Over = 0
+PHY-3001 : End incremental legalization; 0.429694s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (123.6%)
+
+OPT-0007 : Iter 3: improved WNS -890 TNS -1425 NUM_FEPS 2 with 19 cells processed and 1651 slack improved
+OPT-1001 : End path based optimization; 3.637102s wall, 3.875000s user + 0.031250s system = 3.906250s CPU (107.4%)
+
+OPT-1001 : Current memory(MB): used = 740, reserve = 740, peak = 743.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.726791s wall, 0.718750s user + 0.015625s system = 0.734375s CPU (101.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15728/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 940368, over cnt = 241(0%), over = 309, worst = 7
+PHY-1002 : len = 940664, over cnt = 150(0%), over = 163, worst = 4
+PHY-1002 : len = 941872, over cnt = 44(0%), over = 45, worst = 2
+PHY-1002 : len = 942536, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 942776, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.930813s wall, 1.015625s user + 0.046875s system = 1.062500s CPU (114.1%)
+
+PHY-1001 : Congestion index: top1 = 56.92, top5 = 51.18, top10 = 47.99, top15 = 45.88.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.732554s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.2%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -936 TNS -1571 NUM_FEPS 2
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 56.551724
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -936ps with logic level 2
+RUN-1001 : #2 path slack -890ps with logic level 2
+RUN-1001 : extra opt step will be enabled to improve QoR
+RUN-1001 : 0 HFN exist on timing critical paths out of 17699 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 17699 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6728 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6816 instances, 6667 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3646 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 761087, Over = 0
+PHY-3001 : End spreading; 0.060696s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.0%)
+
+PHY-3001 : Final: Len = 761087, Over = 0
+PHY-3001 : End incremental legalization; 0.389683s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.728650s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (98.6%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16148/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 942776, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.136200s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.2%)
+
+PHY-1001 : Congestion index: top1 = 56.92, top5 = 51.18, top10 = 47.99, top15 = 45.88.
+OPT-1001 : End congestion update; 0.454143s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (99.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.756971s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.1%)
+
+OPT-0007 : Start: WNS -936 TNS -1571 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6728 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6816 instances, 6667 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3646 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 761165, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060224s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.8%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 3, deltaY = 5, maxDist = 3.
+PHY-3001 : Final: Len = 761087, Over = 0
+PHY-3001 : End incremental legalization; 0.389409s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.3%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1471 NUM_FEPS 2 with 4 cells processed and 400 slack improved
+OPT-0007 : Iter 2: improved WNS -936 TNS -1471 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.721775s wall, 1.812500s user + 0.000000s system = 1.812500s CPU (105.3%)
+
+OPT-1001 : Current memory(MB): used = 740, reserve = 740, peak = 743.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16148/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 942776, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.136961s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.7%)
+
+PHY-1001 : Congestion index: top1 = 56.92, top5 = 51.18, top10 = 47.99, top15 = 45.88.
+OPT-1001 : End congestion update; 0.451520s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.722933s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.4%)
+
+OPT-0007 : Start: WNS -936 TNS -1571 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6728 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6816 instances, 6667 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3646 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 761063, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059378s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.3%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 761087, Over = 0
+PHY-3001 : End incremental legalization; 0.392275s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.6%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1571 NUM_FEPS 2 with 1 cells processed and 50 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6728 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6816 instances, 6667 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3646 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 761063, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058972s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.0%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 761087, Over = 0
+PHY-3001 : End incremental legalization; 0.384356s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (101.6%)
+
+OPT-0007 : Iter 2: improved WNS -936 TNS -1571 NUM_FEPS 2 with 1 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS -936 TNS -1571 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 2.233710s wall, 2.234375s user + 0.000000s system = 2.234375s CPU (100.0%)
+
+OPT-1001 : Current memory(MB): used = 741, reserve = 740, peak = 743.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.728501s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (98.7%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 741, reserve = 740, peak = 743.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.726038s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (101.1%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16148/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 942776, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.134349s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.0%)
+
+PHY-1001 : Congestion index: top1 = 56.92, top5 = 51.18, top10 = 47.99, top15 = 45.88.
+RUN-1001 : End congestion update; 0.451734s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.3%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.180728s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.6%)
+
+OPT-1001 : Current memory(MB): used = 741, reserve = 740, peak = 743.
+OPT-1001 : End physical optimization; 26.539723s wall, 27.609375s user + 0.328125s system = 27.937500s CPU (105.3%)
+
+RUN-1003 : finish command "place" in 70.572209s wall, 102.281250s user + 6.546875s system = 108.828125s CPU (154.2%)
+
+RUN-1004 : used memory is 648 MB, reserved memory is 640 MB, peak memory is 743 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.691868s wall, 2.906250s user + 0.015625s system = 2.921875s CPU (172.7%)
+
+RUN-1004 : used memory is 649 MB, reserved memory is 641 MB, peak memory is 743 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6818 instances
+RUN-1001 : 3341 mslices, 3326 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17699 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10038 nets have 2 pins
+RUN-1001 : 5818 nets have [3 - 5] pins
+RUN-1001 : 1128 nets have [6 - 10] pins
+RUN-1001 : 331 nets have [11 - 20] pins
+RUN-1001 : 356 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74409, tnet num: 17521, tinst num: 6816, tnode num: 96897, tedge num: 124812.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.676728s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (99.7%)
+
+RUN-1004 : used memory is 660 MB, reserved memory is 663 MB, peak memory is 743 MB
+PHY-1001 : 3341 mslices, 3326 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 873728, over cnt = 2767(7%), over = 4558, worst = 8
+PHY-1002 : len = 889536, over cnt = 1868(5%), over = 2736, worst = 7
+PHY-1002 : len = 907736, over cnt = 893(2%), over = 1256, worst = 7
+PHY-1002 : len = 928336, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 928576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.098008s wall, 4.281250s user + 0.031250s system = 4.312500s CPU (139.2%)
+
+PHY-1001 : Congestion index: top1 = 56.83, top5 = 51.01, top10 = 47.81, top15 = 45.65.
+PHY-1001 : End global routing; 3.445141s wall, 4.609375s user + 0.031250s system = 4.640625s CPU (134.7%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 716, reserve = 717, peak = 743.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 987, reserve = 989, peak = 987.
+PHY-1001 : End build detailed router design. 4.031442s wall, 3.968750s user + 0.062500s system = 4.031250s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 270120, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.321976s wall, 5.296875s user + 0.015625s system = 5.312500s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 270176, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.433127s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.0%)
+
+PHY-1001 : Current memory(MB): used = 1022, reserve = 1025, peak = 1022.
+PHY-1001 : End phase 1; 5.768124s wall, 5.750000s user + 0.015625s system = 5.765625s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.37919e+06, over cnt = 2012(0%), over = 2019, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1037, reserve = 1038, peak = 1037.
+PHY-1001 : End initial routed; 28.606511s wall, 61.156250s user + 0.437500s system = 61.593750s CPU (215.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16621(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.946 | -3.877 | 4
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.281010s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1047, reserve = 1050, peak = 1047.
+PHY-1001 : End phase 2; 31.887585s wall, 64.437500s user + 0.437500s system = 64.875000s CPU (203.4%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 5 pins with SWNS -1.946ns STNS -3.853ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.148491s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (84.2%)
+
+PHY-1022 : len = 2.37921e+06, over cnt = 2017(0%), over = 2025, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.422743s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (96.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.348e+06, over cnt = 698(0%), over = 699, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.874248s wall, 2.828125s user + 0.000000s system = 2.828125s CPU (150.9%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.34288e+06, over cnt = 160(0%), over = 160, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.998866s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (126.7%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.34361e+06, over cnt = 18(0%), over = 18, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.479068s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (114.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.34393e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.219933s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.5%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.3441e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.267005s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (99.5%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.3441e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.420557s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (96.6%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.3441e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.782351s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.9%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.34411e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.191105s wall, 0.187500s user + 0.031250s system = 0.218750s CPU (114.5%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.3441e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.211676s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (96.0%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.3441e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.233672s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.3441e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.277889s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.3441e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.363287s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.9%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.34412e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.195876s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (103.7%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.34407e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.170183s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16621(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.946 | -3.853 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.282253s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 675 feed throughs used by 490 nets
+PHY-1001 : End commit to database; 2.349148s wall, 2.359375s user + 0.000000s system = 2.359375s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1151, reserve = 1157, peak = 1151.
+PHY-1001 : End phase 3; 13.161149s wall, 14.437500s user + 0.031250s system = 14.468750s CPU (109.9%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.946ns STNS -3.853ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.149208s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (94.2%)
+
+PHY-1022 : len = 2.34407e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.420038s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.4%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.946ns, -3.853ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16621(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.946 | -3.853 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.329739s wall, 3.343750s user + 0.000000s system = 3.343750s CPU (100.4%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 675 feed throughs used by 490 nets
+PHY-1001 : End commit to database; 2.429673s wall, 2.421875s user + 0.000000s system = 2.421875s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1160, reserve = 1167, peak = 1160.
+PHY-1001 : End phase 4; 6.210008s wall, 6.203125s user + 0.000000s system = 6.203125s CPU (99.9%)
+
+PHY-1003 : Routed, final wirelength = 2.34407e+06
+PHY-1001 : Current memory(MB): used = 1162, reserve = 1169, peak = 1162.
+PHY-1001 : End export database. 0.062831s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.5%)
+
+PHY-1001 : End detail routing; 61.529095s wall, 95.265625s user + 0.546875s system = 95.812500s CPU (155.7%)
+
+RUN-1003 : finish command "route" in 67.743883s wall, 102.640625s user + 0.593750s system = 103.234375s CPU (152.4%)
+
+RUN-1004 : used memory is 1089 MB, reserved memory is 1095 MB, peak memory is 1162 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10337 out of 19600 52.74%
+#reg 9372 out of 19600 47.82%
+#le 12446
+ #lut only 3074 out of 12446 24.70%
+ #reg only 2109 out of 12446 16.95%
+ #lut® 7263 out of 12446 58.36%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1812
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1402
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1351
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 949
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 137
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 23
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_a/u_ADconfig/reg1_syn_168.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_319.f0 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P140 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P4 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P138 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P16 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P156 LVCMOS33 8 N/A NONE
+ paper_out OUTPUT P15 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P17 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P107 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12446 |9310 |1027 |9403 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |548 |468 |23 |435 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |102 |86 |4 |90 |4 |0 |
+| U_crc16_24b |crc16_24b |51 |51 |0 |23 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |10 |0 |7 |0 |0 |
+| exdev_ctl_a |exdev_ctl |793 |388 |96 |594 |0 |0 |
+| u_ADconfig |AD_config |197 |128 |25 |148 |0 |0 |
+| u_gen_sp |gen_sp |272 |163 |71 |122 |0 |0 |
+| exdev_ctl_b |exdev_ctl |740 |392 |96 |545 |0 |0 |
+| u_ADconfig |AD_config |169 |117 |25 |119 |0 |0 |
+| u_gen_sp |gen_sp |266 |163 |71 |121 |0 |0 |
+| sampling_fe_a |sampling_fe |2989 |2425 |306 |2064 |25 |0 |
+| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |175 |110 |17 |141 |0 |0 |
+| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_sort |sort |2780 |2308 |289 |1889 |25 |0 |
+| rddpram_ctl |rddpram_ctl |5 |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2390 |2014 |253 |1568 |22 |0 |
+| channelPart |channel_part_8478 |153 |148 |3 |132 |0 |0 |
+| fifo_adc |fifo_adc |57 |48 |9 |38 |0 |0 |
+| ram_switch |ram_switch |1861 |1563 |197 |1164 |0 |0 |
+| adc_addr_gen |adc_addr_gen |245 |217 |27 |125 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |15 |11 |3 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |25 |22 |3 |14 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |25 |22 |3 |15 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |29 |26 |3 |16 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| insert |insert |966 |696 |170 |654 |0 |0 |
+| ram_switch_state |ram_switch_state |650 |650 |0 |385 |0 |0 |
+| read_ram_i |read_ram |273 |215 |44 |193 |0 |0 |
+| read_ram_addr |read_ram_addr |217 |177 |40 |151 |0 |0 |
+| read_ram_data |read_ram_data |53 |36 |4 |39 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |347 |276 |36 |278 |3 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3277 |2562 |349 |2110 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |0 |1 |0 |0 |
+| u_ad_sampling |ad_sampling |183 |92 |17 |148 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort_rev |3063 |2468 |332 |1931 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |5 |5 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2648 |2136 |290 |1572 |22 |1 |
+| channelPart |channel_part_8478 |260 |256 |3 |140 |0 |0 |
+| fifo_adc |fifo_adc |55 |46 |9 |40 |0 |1 |
+| ram_switch |ram_switch |1932 |1552 |197 |1140 |0 |0 |
+| adc_addr_gen |adc_addr_gen |227 |200 |27 |108 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |16 |13 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |21 |18 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |6 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |21 |18 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 |
+| insert |insert |981 |633 |170 |679 |0 |0 |
+| ram_switch_state |ram_switch_state |724 |719 |0 |353 |0 |0 |
+| read_ram_i |read_ram_rev |361 |252 |81 |212 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |284 |199 |73 |159 |0 |0 |
+| read_ram_data |read_ram_data_rev |77 |53 |8 |53 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9976
+ #2 2 3851
+ #3 3 1395
+ #4 4 569
+ #5 5-10 1200
+ #6 11-50 588
+ #7 51-100 24
+ #8 >500 1
+ Average 2.91
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.079398s wall, 3.578125s user + 0.031250s system = 3.609375s CPU (173.6%)
+
+RUN-1004 : used memory is 1090 MB, reserved memory is 1096 MB, peak memory is 1162 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74409, tnet num: 17521, tinst num: 6816, tnode num: 96897, tedge num: 124812.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.617439s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.5%)
+
+RUN-1004 : used memory is 1095 MB, reserved memory is 1101 MB, peak memory is 1162 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.534317s wall, 1.515625s user + 0.015625s system = 1.531250s CPU (99.8%)
+
+RUN-1004 : used memory is 1098 MB, reserved memory is 1103 MB, peak memory is 1162 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6816
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17699, pip num: 175864
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 675
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3254 valid insts, and 485333 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 10.304855s wall, 62.078125s user + 0.250000s system = 62.328125s CPU (604.8%)
+
+RUN-1004 : used memory is 1266 MB, reserved memory is 1269 MB, peak memory is 1381 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240125_160129.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240126_091207.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240126_091207.log
new file mode 100644
index 0000000..0b0bb95
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240126_091207.log
@@ -0,0 +1,2137 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Fri Jan 26 09:12:07 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.120792s wall, 2.062500s user + 0.062500s system = 2.125000s CPU (100.2%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 315 MB, peak memory is 341 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2945 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17775 instances
+RUN-0007 : 7512 luts, 9040 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20353 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13332 nets have 2 pins
+RUN-1001 : 5562 nets have [3 - 5] pins
+RUN-1001 : 1037 nets have [6 - 10] pins
+RUN-1001 : 172 nets have [11 - 20] pins
+RUN-1001 : 176 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 789
+RUN-1001 : No | No | Yes | 1968
+RUN-1001 : No | Yes | No | 3474
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 56
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 141
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17773 instances, 7512 luts, 9040 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 5912 pins
+PHY-0007 : Cell area utilization is 49%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85138, tnet num: 20175, tinst num: 17773, tnode num: 115214, tedge num: 136657.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.134820s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (100.5%)
+
+RUN-1004 : used memory is 530 MB, reserved memory is 514 MB, peak memory is 530 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20175 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.914553s wall, 1.906250s user + 0.015625s system = 1.921875s CPU (100.4%)
+
+PHY-3001 : Found 1221 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 3.89596e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17773.
+PHY-3001 : Level 1 #clusters 2040.
+PHY-3001 : End clustering; 0.129229s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.7%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 49%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.29757e+06, overlap = 462.656
+PHY-3002 : Step(2): len = 1.1629e+06, overlap = 479.438
+PHY-3002 : Step(3): len = 877919, overlap = 603.688
+PHY-3002 : Step(4): len = 773088, overlap = 624.219
+PHY-3002 : Step(5): len = 617637, overlap = 730.594
+PHY-3002 : Step(6): len = 538411, overlap = 804.375
+PHY-3002 : Step(7): len = 468960, overlap = 891.531
+PHY-3002 : Step(8): len = 424872, overlap = 971.75
+PHY-3002 : Step(9): len = 378631, overlap = 1037.12
+PHY-3002 : Step(10): len = 342449, overlap = 1120.22
+PHY-3002 : Step(11): len = 311259, overlap = 1160
+PHY-3002 : Step(12): len = 290794, overlap = 1184.34
+PHY-3002 : Step(13): len = 260766, overlap = 1259.06
+PHY-3002 : Step(14): len = 244497, overlap = 1335.81
+PHY-3002 : Step(15): len = 222920, overlap = 1324.88
+PHY-3002 : Step(16): len = 205645, overlap = 1356.78
+PHY-3002 : Step(17): len = 186751, overlap = 1417.72
+PHY-3002 : Step(18): len = 175204, overlap = 1435.75
+PHY-3002 : Step(19): len = 158208, overlap = 1442.38
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.8099e-07
+PHY-3002 : Step(20): len = 156663, overlap = 1402.94
+PHY-3002 : Step(21): len = 186690, overlap = 1305.41
+PHY-3002 : Step(22): len = 190772, overlap = 1238.53
+PHY-3002 : Step(23): len = 193578, overlap = 1174.28
+PHY-3002 : Step(24): len = 194097, overlap = 1145.38
+PHY-3002 : Step(25): len = 191056, overlap = 1144.28
+PHY-3002 : Step(26): len = 186137, overlap = 1131.47
+PHY-3002 : Step(27): len = 182203, overlap = 1127.28
+PHY-3002 : Step(28): len = 177149, overlap = 1132.38
+PHY-3002 : Step(29): len = 173968, overlap = 1134.75
+PHY-3002 : Step(30): len = 171438, overlap = 1122.5
+PHY-3002 : Step(31): len = 170745, overlap = 1137.44
+PHY-3002 : Step(32): len = 169880, overlap = 1155.31
+PHY-3002 : Step(33): len = 168072, overlap = 1159.62
+PHY-3002 : Step(34): len = 167510, overlap = 1179.16
+PHY-3002 : Step(35): len = 166098, overlap = 1179.12
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.96198e-06
+PHY-3002 : Step(36): len = 168935, overlap = 1178.62
+PHY-3002 : Step(37): len = 181195, overlap = 1159.62
+PHY-3002 : Step(38): len = 186322, overlap = 1129.03
+PHY-3002 : Step(39): len = 190015, overlap = 1121.06
+PHY-3002 : Step(40): len = 191488, overlap = 1092.59
+PHY-3002 : Step(41): len = 193055, overlap = 1089.22
+PHY-3002 : Step(42): len = 192200, overlap = 1079.25
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.92396e-06
+PHY-3002 : Step(43): len = 197331, overlap = 1040.91
+PHY-3002 : Step(44): len = 213722, overlap = 967.469
+PHY-3002 : Step(45): len = 223009, overlap = 895.438
+PHY-3002 : Step(46): len = 229131, overlap = 855.469
+PHY-3002 : Step(47): len = 231083, overlap = 842.312
+PHY-3002 : Step(48): len = 233377, overlap = 856.969
+PHY-3002 : Step(49): len = 233744, overlap = 857.875
+PHY-3002 : Step(50): len = 235587, overlap = 867.031
+PHY-3002 : Step(51): len = 235354, overlap = 861.438
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.84792e-06
+PHY-3002 : Step(52): len = 246896, overlap = 834.469
+PHY-3002 : Step(53): len = 268089, overlap = 739.219
+PHY-3002 : Step(54): len = 279391, overlap = 659.062
+PHY-3002 : Step(55): len = 287928, overlap = 594.281
+PHY-3002 : Step(56): len = 288906, overlap = 585.375
+PHY-3002 : Step(57): len = 288771, overlap = 593.406
+PHY-3002 : Step(58): len = 286923, overlap = 585.344
+PHY-3002 : Step(59): len = 287061, overlap = 573.062
+PHY-3002 : Step(60): len = 285808, overlap = 580.281
+PHY-3002 : Step(61): len = 284942, overlap = 575.844
+PHY-3002 : Step(62): len = 283975, overlap = 577.094
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.56958e-05
+PHY-3002 : Step(63): len = 301612, overlap = 554.906
+PHY-3002 : Step(64): len = 316624, overlap = 504.219
+PHY-3002 : Step(65): len = 322629, overlap = 480.094
+PHY-3002 : Step(66): len = 324137, overlap = 469.531
+PHY-3002 : Step(67): len = 323361, overlap = 472.406
+PHY-3002 : Step(68): len = 325058, overlap = 450.469
+PHY-3002 : Step(69): len = 325597, overlap = 430.094
+PHY-3002 : Step(70): len = 327829, overlap = 418.938
+PHY-3002 : Step(71): len = 329741, overlap = 414.156
+PHY-3002 : Step(72): len = 331913, overlap = 401.656
+PHY-3002 : Step(73): len = 332237, overlap = 400.969
+PHY-3002 : Step(74): len = 333391, overlap = 391.031
+PHY-3002 : Step(75): len = 333103, overlap = 391
+PHY-3002 : Step(76): len = 333776, overlap = 394.125
+PHY-3002 : Step(77): len = 332190, overlap = 405.5
+PHY-3002 : Step(78): len = 332437, overlap = 407.719
+PHY-3002 : Step(79): len = 331329, overlap = 407.906
+PHY-3002 : Step(80): len = 332142, overlap = 411.781
+PHY-3002 : Step(81): len = 331701, overlap = 413.281
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.13917e-05
+PHY-3002 : Step(82): len = 351585, overlap = 386.875
+PHY-3002 : Step(83): len = 367888, overlap = 351.5
+PHY-3002 : Step(84): len = 371263, overlap = 341.5
+PHY-3002 : Step(85): len = 371893, overlap = 341.469
+PHY-3002 : Step(86): len = 371268, overlap = 331.375
+PHY-3002 : Step(87): len = 373947, overlap = 316.781
+PHY-3002 : Step(88): len = 372578, overlap = 331.281
+PHY-3002 : Step(89): len = 372262, overlap = 311
+PHY-3002 : Step(90): len = 370875, overlap = 305.688
+PHY-3002 : Step(91): len = 369481, overlap = 316.344
+PHY-3002 : Step(92): len = 368228, overlap = 325.875
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.27833e-05
+PHY-3002 : Step(93): len = 386162, overlap = 324.625
+PHY-3002 : Step(94): len = 398071, overlap = 314.969
+PHY-3002 : Step(95): len = 397724, overlap = 315.312
+PHY-3002 : Step(96): len = 398588, overlap = 306.125
+PHY-3002 : Step(97): len = 400836, overlap = 299
+PHY-3002 : Step(98): len = 404172, overlap = 294.875
+PHY-3002 : Step(99): len = 400926, overlap = 303.688
+PHY-3002 : Step(100): len = 401232, overlap = 311.594
+PHY-3002 : Step(101): len = 402184, overlap = 306.562
+PHY-3002 : Step(102): len = 403572, overlap = 301.562
+PHY-3002 : Step(103): len = 401082, overlap = 294.625
+PHY-3002 : Step(104): len = 401332, overlap = 293.188
+PHY-3002 : Step(105): len = 402786, overlap = 289.438
+PHY-3002 : Step(106): len = 404474, overlap = 282.25
+PHY-3002 : Step(107): len = 401570, overlap = 282.156
+PHY-3002 : Step(108): len = 400928, overlap = 281.875
+PHY-3002 : Step(109): len = 401320, overlap = 280.031
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000125567
+PHY-3002 : Step(110): len = 415734, overlap = 278.844
+PHY-3002 : Step(111): len = 424875, overlap = 277.594
+PHY-3002 : Step(112): len = 423431, overlap = 274.656
+PHY-3002 : Step(113): len = 423706, overlap = 272.375
+PHY-3002 : Step(114): len = 426866, overlap = 268
+PHY-3002 : Step(115): len = 429973, overlap = 257.938
+PHY-3002 : Step(116): len = 428844, overlap = 265.594
+PHY-3002 : Step(117): len = 431188, overlap = 269
+PHY-3002 : Step(118): len = 433840, overlap = 260.062
+PHY-3002 : Step(119): len = 435929, overlap = 259
+PHY-3002 : Step(120): len = 432763, overlap = 265.5
+PHY-3002 : Step(121): len = 432653, overlap = 262.219
+PHY-3002 : Step(122): len = 435177, overlap = 260.031
+PHY-3002 : Step(123): len = 436603, overlap = 259.219
+PHY-3002 : Step(124): len = 433791, overlap = 267.469
+PHY-3002 : Step(125): len = 433574, overlap = 260.344
+PHY-3002 : Step(126): len = 435343, overlap = 253.344
+PHY-3002 : Step(127): len = 436562, overlap = 245.688
+PHY-3002 : Step(128): len = 434797, overlap = 246.062
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000236903
+PHY-3002 : Step(129): len = 444282, overlap = 238.844
+PHY-3002 : Step(130): len = 451012, overlap = 228.938
+PHY-3002 : Step(131): len = 450372, overlap = 225.688
+PHY-3002 : Step(132): len = 451431, overlap = 225.531
+PHY-3002 : Step(133): len = 455272, overlap = 223.906
+PHY-3002 : Step(134): len = 458279, overlap = 213.156
+PHY-3002 : Step(135): len = 456500, overlap = 219.812
+PHY-3002 : Step(136): len = 456383, overlap = 215.5
+PHY-3002 : Step(137): len = 459537, overlap = 209.531
+PHY-3002 : Step(138): len = 462095, overlap = 204.5
+PHY-3002 : Step(139): len = 459085, overlap = 201.312
+PHY-3002 : Step(140): len = 458873, overlap = 196
+PHY-3002 : Step(141): len = 461435, overlap = 190.344
+PHY-3002 : Step(142): len = 462591, overlap = 189.406
+PHY-3002 : Step(143): len = 461447, overlap = 189.25
+PHY-3002 : Step(144): len = 461471, overlap = 187.688
+PHY-3002 : Step(145): len = 462359, overlap = 189.625
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000452482
+PHY-3002 : Step(146): len = 470617, overlap = 184.094
+PHY-3002 : Step(147): len = 477917, overlap = 173.219
+PHY-3002 : Step(148): len = 478610, overlap = 176.656
+PHY-3002 : Step(149): len = 480161, overlap = 164.375
+PHY-3002 : Step(150): len = 484571, overlap = 155.562
+PHY-3002 : Step(151): len = 488258, overlap = 153.25
+PHY-3002 : Step(152): len = 486499, overlap = 147.875
+PHY-3002 : Step(153): len = 487343, overlap = 145.531
+PHY-3002 : Step(154): len = 491700, overlap = 147.812
+PHY-3002 : Step(155): len = 494491, overlap = 145.688
+PHY-3002 : Step(156): len = 491951, overlap = 144.531
+PHY-3002 : Step(157): len = 491821, overlap = 150.344
+PHY-3002 : Step(158): len = 493596, overlap = 140.969
+PHY-3002 : Step(159): len = 494833, overlap = 127.844
+PHY-3002 : Step(160): len = 493597, overlap = 136.469
+PHY-3002 : Step(161): len = 493390, overlap = 137.125
+PHY-3002 : Step(162): len = 494495, overlap = 144.438
+PHY-3002 : Step(163): len = 495586, overlap = 144.812
+PHY-3002 : Step(164): len = 494259, overlap = 146.812
+PHY-3002 : Step(165): len = 494157, overlap = 146.781
+PHY-3002 : Step(166): len = 494939, overlap = 149.312
+PHY-3002 : Step(167): len = 495234, overlap = 150.75
+PHY-3002 : Step(168): len = 494605, overlap = 148.469
+PHY-3002 : Step(169): len = 494596, overlap = 150.625
+PHY-3002 : Step(170): len = 495427, overlap = 150.719
+PHY-3002 : Step(171): len = 495907, overlap = 150.562
+PHY-3002 : Step(172): len = 495995, overlap = 153.688
+PHY-3002 : Step(173): len = 496634, overlap = 147.406
+PHY-3002 : Step(174): len = 497727, overlap = 148.812
+PHY-3002 : Step(175): len = 498234, overlap = 148.906
+PHY-3002 : Step(176): len = 497088, overlap = 151.688
+PHY-3002 : Step(177): len = 496812, overlap = 142.656
+PHY-3002 : Step(178): len = 497044, overlap = 144.5
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000886506
+PHY-3002 : Step(179): len = 501976, overlap = 136.312
+PHY-3002 : Step(180): len = 506417, overlap = 132.906
+PHY-3002 : Step(181): len = 506643, overlap = 133.438
+PHY-3002 : Step(182): len = 507287, overlap = 135.5
+PHY-3002 : Step(183): len = 509665, overlap = 133.625
+PHY-3002 : Step(184): len = 510585, overlap = 132.625
+PHY-3002 : Step(185): len = 509590, overlap = 137.625
+PHY-3002 : Step(186): len = 509229, overlap = 137.688
+PHY-3002 : Step(187): len = 510837, overlap = 136.719
+PHY-3002 : Step(188): len = 511943, overlap = 132.969
+PHY-3002 : Step(189): len = 511142, overlap = 135.562
+PHY-3002 : Step(190): len = 510980, overlap = 135.062
+PHY-3002 : Step(191): len = 512087, overlap = 128.594
+PHY-3002 : Step(192): len = 512355, overlap = 125.688
+PHY-3002 : Step(193): len = 511831, overlap = 125.938
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00147078
+PHY-3002 : Step(194): len = 514237, overlap = 123.344
+PHY-3002 : Step(195): len = 517269, overlap = 125.594
+PHY-3002 : Step(196): len = 517984, overlap = 126.438
+PHY-3002 : Step(197): len = 519003, overlap = 119.812
+PHY-3002 : Step(198): len = 521306, overlap = 119.031
+PHY-3002 : Step(199): len = 522408, overlap = 118.156
+PHY-3002 : Step(200): len = 521643, overlap = 118.219
+PHY-3002 : Step(201): len = 521643, overlap = 118.219
+PHY-3002 : Step(202): len = 521990, overlap = 116.656
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00246286
+PHY-3002 : Step(203): len = 524384, overlap = 108.938
+PHY-3002 : Step(204): len = 530370, overlap = 105.438
+PHY-3002 : Step(205): len = 530913, overlap = 105.375
+PHY-3002 : Step(206): len = 531118, overlap = 104.156
+PHY-3002 : Step(207): len = 531394, overlap = 105.781
+PHY-3002 : Step(208): len = 531956, overlap = 104.406
+PHY-3002 : Step(209): len = 533544, overlap = 98.4688
+PHY-3002 : Step(210): len = 536114, overlap = 99.1562
+PHY-3002 : Step(211): len = 537107, overlap = 96.75
+PHY-3002 : Step(212): len = 537530, overlap = 96.4062
+PHY-3002 : Step(213): len = 537758, overlap = 95.2188
+PHY-3002 : Step(214): len = 537806, overlap = 93.3438
+PHY-3002 : Step(215): len = 537817, overlap = 93.1562
+PHY-3002 : Step(216): len = 537829, overlap = 93.1562
+PHY-3002 : Step(217): len = 537748, overlap = 91.9062
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.013432s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20353.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 700672, over cnt = 1609(4%), over = 7201, worst = 42
+PHY-1001 : End global iterations; 0.723332s wall, 0.984375s user + 0.031250s system = 1.015625s CPU (140.4%)
+
+PHY-1001 : Congestion index: top1 = 73.84, top5 = 59.34, top10 = 51.29, top15 = 46.17.
+PHY-3001 : End congestion estimation; 0.939563s wall, 1.203125s user + 0.031250s system = 1.234375s CPU (131.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20175 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.854069s wall, 0.812500s user + 0.031250s system = 0.843750s CPU (98.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000135377
+PHY-3002 : Step(218): len = 630948, overlap = 46
+PHY-3002 : Step(219): len = 635028, overlap = 49
+PHY-3002 : Step(220): len = 631250, overlap = 51.0625
+PHY-3002 : Step(221): len = 626604, overlap = 53.0312
+PHY-3002 : Step(222): len = 623408, overlap = 51.6875
+PHY-3002 : Step(223): len = 623545, overlap = 49.0312
+PHY-3002 : Step(224): len = 621522, overlap = 43.5
+PHY-3002 : Step(225): len = 621229, overlap = 35.125
+PHY-3002 : Step(226): len = 616062, overlap = 32.5
+PHY-3002 : Step(227): len = 614580, overlap = 33.0625
+PHY-3002 : Step(228): len = 610792, overlap = 33.4688
+PHY-3002 : Step(229): len = 610321, overlap = 32.5938
+PHY-3002 : Step(230): len = 608441, overlap = 29.5625
+PHY-3002 : Step(231): len = 607054, overlap = 26.2188
+PHY-3002 : Step(232): len = 605476, overlap = 28.9062
+PHY-3002 : Step(233): len = 606073, overlap = 31.3438
+PHY-3002 : Step(234): len = 603996, overlap = 30.3438
+PHY-3002 : Step(235): len = 603258, overlap = 29.5312
+PHY-3002 : Step(236): len = 601756, overlap = 24.4688
+PHY-3002 : Step(237): len = 602156, overlap = 23.2812
+PHY-3002 : Step(238): len = 600075, overlap = 24.2188
+PHY-3002 : Step(239): len = 599165, overlap = 24.5625
+PHY-3002 : Step(240): len = 598241, overlap = 25.8438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000270753
+PHY-3002 : Step(241): len = 601678, overlap = 21.9062
+PHY-3002 : Step(242): len = 604997, overlap = 20.1875
+PHY-3002 : Step(243): len = 611069, overlap = 20.6562
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000541506
+PHY-3002 : Step(244): len = 617901, overlap = 19.5
+PHY-3002 : Step(245): len = 632241, overlap = 18.9688
+PHY-3002 : Step(246): len = 641823, overlap = 17.0938
+PHY-3002 : Step(247): len = 641020, overlap = 17.1562
+PHY-3002 : Step(248): len = 639625, overlap = 18.8438
+PHY-3002 : Step(249): len = 639937, overlap = 20.9062
+PHY-3002 : Step(250): len = 639997, overlap = 23.5625
+PHY-3002 : Step(251): len = 641594, overlap = 22.8438
+PHY-3002 : Step(252): len = 642912, overlap = 24.5312
+PHY-3002 : Step(253): len = 642882, overlap = 25.5938
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00108301
+PHY-3002 : Step(254): len = 646252, overlap = 26.5938
+PHY-3002 : Step(255): len = 655391, overlap = 24.0625
+PHY-3002 : Step(256): len = 667010, overlap = 23.6562
+PHY-3002 : Step(257): len = 669904, overlap = 28.7812
+PHY-3002 : Step(258): len = 671784, overlap = 31.9688
+PHY-3002 : Step(259): len = 671015, overlap = 33.1562
+PHY-3002 : Step(260): len = 670204, overlap = 33.6562
+PHY-3002 : Step(261): len = 667843, overlap = 36.25
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00177864
+PHY-3002 : Step(262): len = 671303, overlap = 36.0938
+PHY-3002 : Step(263): len = 678221, overlap = 38.875
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 60/20353.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 763952, over cnt = 2693(7%), over = 13615, worst = 42
+PHY-1001 : End global iterations; 1.592201s wall, 2.203125s user + 0.000000s system = 2.203125s CPU (138.4%)
+
+PHY-1001 : Congestion index: top1 = 98.94, top5 = 76.35, top10 = 66.08, top15 = 59.62.
+PHY-3001 : End congestion estimation; 1.861326s wall, 2.468750s user + 0.000000s system = 2.468750s CPU (132.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20175 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.911460s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000118726
+PHY-3002 : Step(264): len = 669518, overlap = 269.688
+PHY-3002 : Step(265): len = 664619, overlap = 206.062
+PHY-3002 : Step(266): len = 653150, overlap = 183.188
+PHY-3002 : Step(267): len = 641573, overlap = 168.531
+PHY-3002 : Step(268): len = 633196, overlap = 153.531
+PHY-3002 : Step(269): len = 626548, overlap = 145.188
+PHY-3002 : Step(270): len = 620766, overlap = 136.812
+PHY-3002 : Step(271): len = 615925, overlap = 140.188
+PHY-3002 : Step(272): len = 611682, overlap = 142.344
+PHY-3002 : Step(273): len = 608078, overlap = 134.812
+PHY-3002 : Step(274): len = 604407, overlap = 133.656
+PHY-3002 : Step(275): len = 600785, overlap = 130.938
+PHY-3002 : Step(276): len = 595855, overlap = 133.625
+PHY-3002 : Step(277): len = 592223, overlap = 138.344
+PHY-3002 : Step(278): len = 588694, overlap = 136.969
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000237451
+PHY-3002 : Step(279): len = 589371, overlap = 135.188
+PHY-3002 : Step(280): len = 592314, overlap = 133
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000429447
+PHY-3002 : Step(281): len = 594227, overlap = 125.812
+PHY-3002 : Step(282): len = 602176, overlap = 108.781
+PHY-3002 : Step(283): len = 607678, overlap = 99.6562
+PHY-3002 : Step(284): len = 606782, overlap = 96.75
+PHY-3002 : Step(285): len = 606431, overlap = 90.125
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000794764
+PHY-3002 : Step(286): len = 609761, overlap = 88.5
+PHY-3002 : Step(287): len = 614620, overlap = 81.5625
+PHY-3002 : Step(288): len = 620074, overlap = 76.125
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85138, tnet num: 20175, tinst num: 17773, tnode num: 115214, tedge num: 136657.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.438027s wall, 1.421875s user + 0.031250s system = 1.453125s CPU (101.0%)
+
+RUN-1004 : used memory is 574 MB, reserved memory is 563 MB, peak memory is 711 MB
+OPT-1001 : Total overflow 384.38 peak overflow 4.62
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 413/20353.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 721456, over cnt = 3072(8%), over = 10798, worst = 28
+PHY-1001 : End global iterations; 1.458434s wall, 2.031250s user + 0.000000s system = 2.031250s CPU (139.3%)
+
+PHY-1001 : Congestion index: top1 = 72.07, top5 = 56.62, top10 = 50.94, top15 = 47.39.
+PHY-1001 : End incremental global routing; 1.796102s wall, 2.375000s user + 0.000000s system = 2.375000s CPU (132.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20175 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.908929s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (99.7%)
+
+OPT-1001 : 48 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17640 has valid locations, 324 needs to be replaced
+PHY-3001 : design contains 18049 instances, 7595 luts, 9233 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 6033 pins
+PHY-3001 : Found 1230 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 645008
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16893/20629.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 736584, over cnt = 3129(8%), over = 10834, worst = 28
+PHY-1001 : End global iterations; 0.256273s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (109.7%)
+
+PHY-1001 : Congestion index: top1 = 71.66, top5 = 56.85, top10 = 51.21, top15 = 47.73.
+PHY-3001 : End congestion estimation; 0.533993s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (105.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86241, tnet num: 20451, tinst num: 18049, tnode num: 116901, tedge num: 138311.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.489815s wall, 1.468750s user + 0.015625s system = 1.484375s CPU (99.6%)
+
+RUN-1004 : used memory is 619 MB, reserved memory is 616 MB, peak memory is 715 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20451 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.445456s wall, 2.421875s user + 0.015625s system = 2.437500s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(289): len = 644220, overlap = 0.28125
+PHY-3002 : Step(290): len = 643884, overlap = 0.28125
+PHY-3002 : Step(291): len = 643604, overlap = 0.28125
+PHY-3002 : Step(292): len = 643373, overlap = 0.28125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17008/20629.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 735056, over cnt = 3144(8%), over = 10864, worst = 28
+PHY-1001 : End global iterations; 0.196926s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (111.1%)
+
+PHY-1001 : Congestion index: top1 = 73.25, top5 = 57.36, top10 = 51.51, top15 = 47.89.
+PHY-3001 : End congestion estimation; 0.454776s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (106.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20451 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.926163s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (101.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000331278
+PHY-3002 : Step(293): len = 643268, overlap = 78.125
+PHY-3002 : Step(294): len = 643201, overlap = 78.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000662557
+PHY-3002 : Step(295): len = 643388, overlap = 78.125
+PHY-3002 : Step(296): len = 643841, overlap = 79.0312
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00132511
+PHY-3002 : Step(297): len = 644143, overlap = 78.5
+PHY-3002 : Step(298): len = 644374, overlap = 78.5312
+PHY-3001 : Final: Len = 644374, Over = 78.5312
+PHY-3001 : End incremental placement; 5.105812s wall, 5.359375s user + 0.203125s system = 5.562500s CPU (108.9%)
+
+OPT-1001 : Total overflow 393.16 peak overflow 4.62
+OPT-1001 : End high-fanout net optimization; 8.350872s wall, 9.265625s user + 0.218750s system = 9.484375s CPU (113.6%)
+
+OPT-1001 : Current memory(MB): used = 718, reserve = 712, peak = 734.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16915/20629.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 738568, over cnt = 3082(8%), over = 9721, worst = 28
+PHY-1002 : len = 786184, over cnt = 2087(5%), over = 5131, worst = 15
+PHY-1002 : len = 824352, over cnt = 922(2%), over = 2182, worst = 15
+PHY-1002 : len = 852280, over cnt = 264(0%), over = 530, worst = 14
+PHY-1002 : len = 861928, over cnt = 3(0%), over = 3, worst = 1
+PHY-1001 : End global iterations; 1.636108s wall, 2.406250s user + 0.000000s system = 2.406250s CPU (147.1%)
+
+PHY-1001 : Congestion index: top1 = 58.79, top5 = 50.79, top10 = 47.03, top15 = 44.64.
+OPT-1001 : End congestion update; 1.901596s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (140.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20451 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.798243s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.8%)
+
+OPT-0007 : Start: WNS -1018 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 62 cells processed and 3408 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 12 cells processed and 1121 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 7 cells processed and 400 slack improved
+OPT-1001 : End global optimization; 2.738026s wall, 3.515625s user + 0.000000s system = 3.515625s CPU (128.4%)
+
+OPT-1001 : Current memory(MB): used = 696, reserve = 696, peak = 734.
+OPT-1001 : End physical optimization; 13.143477s wall, 14.796875s user + 0.265625s system = 15.062500s CPU (114.6%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7595 LUT to BLE ...
+SYN-4008 : Packed 7595 LUT and 3081 SEQ to BLE.
+SYN-4003 : Packing 6152 remaining SEQ's ...
+SYN-4005 : Packed 3984 SEQ with LUT/SLICE
+SYN-4006 : 831 single LUT's are left
+SYN-4006 : 2168 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9763/13494 primitive instances ...
+PHY-3001 : End packing; 1.584355s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (99.6%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6795 instances
+RUN-1001 : 3324 mslices, 3323 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17679 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10042 nets have 2 pins
+RUN-1001 : 5818 nets have [3 - 5] pins
+RUN-1001 : 1124 nets have [6 - 10] pins
+RUN-1001 : 322 nets have [11 - 20] pins
+RUN-1001 : 342 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6793 instances, 6647 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3577 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 653690, Over = 247.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7338/17679.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 809768, over cnt = 2014(5%), over = 3301, worst = 7
+PHY-1002 : len = 817336, over cnt = 1348(3%), over = 2003, worst = 6
+PHY-1002 : len = 829864, over cnt = 696(1%), over = 969, worst = 6
+PHY-1002 : len = 838600, over cnt = 307(0%), over = 405, worst = 6
+PHY-1002 : len = 846448, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.642819s wall, 2.343750s user + 0.046875s system = 2.390625s CPU (145.5%)
+
+PHY-1001 : Congestion index: top1 = 59.72, top5 = 51.25, top10 = 47.19, top15 = 44.64.
+PHY-3001 : End congestion estimation; 2.061551s wall, 2.750000s user + 0.046875s system = 2.796875s CPU (135.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74242, tnet num: 17501, tinst num: 6793, tnode num: 96697, tedge num: 124613.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.611888s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (100.8%)
+
+RUN-1004 : used memory is 613 MB, reserved memory is 612 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17501 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.469245s wall, 2.453125s user + 0.015625s system = 2.468750s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.55946e-05
+PHY-3002 : Step(299): len = 642343, overlap = 250
+PHY-3002 : Step(300): len = 636811, overlap = 248.25
+PHY-3002 : Step(301): len = 634048, overlap = 249.5
+PHY-3002 : Step(302): len = 631702, overlap = 251.5
+PHY-3002 : Step(303): len = 629529, overlap = 255.5
+PHY-3002 : Step(304): len = 628030, overlap = 249.5
+PHY-3002 : Step(305): len = 625970, overlap = 248
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.11892e-05
+PHY-3002 : Step(306): len = 629598, overlap = 239.5
+PHY-3002 : Step(307): len = 634077, overlap = 232.25
+PHY-3002 : Step(308): len = 634758, overlap = 228.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000182378
+PHY-3002 : Step(309): len = 647005, overlap = 214.5
+PHY-3002 : Step(310): len = 659949, overlap = 205.25
+PHY-3002 : Step(311): len = 657992, overlap = 203.5
+PHY-3002 : Step(312): len = 656420, overlap = 202.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.393471s wall, 0.343750s user + 0.578125s system = 0.921875s CPU (234.3%)
+
+PHY-3001 : Trial Legalized: Len = 740728
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 892/17679.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 860544, over cnt = 2805(7%), over = 4673, worst = 7
+PHY-1002 : len = 880136, over cnt = 1558(4%), over = 2203, worst = 6
+PHY-1002 : len = 898448, over cnt = 571(1%), over = 768, worst = 6
+PHY-1002 : len = 909120, over cnt = 150(0%), over = 206, worst = 6
+PHY-1002 : len = 912664, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations; 2.461282s wall, 3.687500s user + 0.000000s system = 3.687500s CPU (149.8%)
+
+PHY-1001 : Congestion index: top1 = 57.28, top5 = 51.44, top10 = 48.37, top15 = 46.24.
+PHY-3001 : End congestion estimation; 2.921399s wall, 4.156250s user + 0.000000s system = 4.156250s CPU (142.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17501 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.857652s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000159859
+PHY-3002 : Step(313): len = 711657, overlap = 44
+PHY-3002 : Step(314): len = 696442, overlap = 67.75
+PHY-3002 : Step(315): len = 683295, overlap = 94.75
+PHY-3002 : Step(316): len = 676340, overlap = 112.25
+PHY-3002 : Step(317): len = 670701, overlap = 128.25
+PHY-3002 : Step(318): len = 667515, overlap = 142.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000319718
+PHY-3002 : Step(319): len = 674272, overlap = 141
+PHY-3002 : Step(320): len = 680380, overlap = 143.25
+PHY-3002 : Step(321): len = 682978, overlap = 141
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000592047
+PHY-3002 : Step(322): len = 689017, overlap = 140
+PHY-3002 : Step(323): len = 702709, overlap = 144.25
+PHY-3002 : Step(324): len = 710832, overlap = 142
+PHY-3002 : Step(325): len = 711581, overlap = 142
+PHY-3002 : Step(326): len = 711658, overlap = 142.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.036657s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (85.2%)
+
+PHY-3001 : Legalized: Len = 737055, Over = 0
+PHY-3001 : Spreading special nets. 461 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.106843s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (102.4%)
+
+PHY-3001 : 663 instances has been re-located, deltaX = 218, deltaY = 381, maxDist = 4.
+PHY-3001 : Final: Len = 747201, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74242, tnet num: 17501, tinst num: 6796, tnode num: 96697, tedge num: 124613.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.878562s wall, 1.859375s user + 0.015625s system = 1.875000s CPU (99.8%)
+
+RUN-1004 : used memory is 610 MB, reserved memory is 608 MB, peak memory is 734 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3223/17679.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 879608, over cnt = 2645(7%), over = 4286, worst = 7
+PHY-1002 : len = 896320, over cnt = 1480(4%), over = 2036, worst = 5
+PHY-1002 : len = 903992, over cnt = 994(2%), over = 1375, worst = 5
+PHY-1002 : len = 921216, over cnt = 259(0%), over = 336, worst = 4
+PHY-1002 : len = 925840, over cnt = 52(0%), over = 60, worst = 4
+PHY-1001 : End global iterations; 2.264582s wall, 3.359375s user + 0.046875s system = 3.406250s CPU (150.4%)
+
+PHY-1001 : Congestion index: top1 = 57.31, top5 = 51.07, top10 = 47.74, top15 = 45.61.
+PHY-1001 : End incremental global routing; 2.642742s wall, 3.734375s user + 0.046875s system = 3.781250s CPU (143.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17501 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.063901s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (99.9%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6703 has valid locations, 25 needs to be replaced
+PHY-3001 : design contains 6816 instances, 6667 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3646 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 750563
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16128/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928816, over cnt = 139(0%), over = 165, worst = 6
+PHY-1002 : len = 928880, over cnt = 79(0%), over = 85, worst = 4
+PHY-1002 : len = 929824, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 929936, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 930000, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.794876s wall, 0.843750s user + 0.031250s system = 0.875000s CPU (110.1%)
+
+PHY-1001 : Congestion index: top1 = 57.35, top5 = 51.02, top10 = 47.73, top15 = 45.62.
+PHY-3001 : End congestion estimation; 1.114329s wall, 1.156250s user + 0.031250s system = 1.187500s CPU (106.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74409, tnet num: 17521, tinst num: 6816, tnode num: 96897, tedge num: 124812.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.880791s wall, 1.796875s user + 0.078125s system = 1.875000s CPU (99.7%)
+
+RUN-1004 : used memory is 644 MB, reserved memory is 640 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.867392s wall, 2.781250s user + 0.078125s system = 2.859375s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(327): len = 750183, overlap = 0.25
+PHY-3002 : Step(328): len = 749856, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16132/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928976, over cnt = 37(0%), over = 52, worst = 4
+PHY-1002 : len = 929104, over cnt = 18(0%), over = 23, worst = 3
+PHY-1002 : len = 929352, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 929480, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.612474s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (107.1%)
+
+PHY-1001 : Congestion index: top1 = 57.35, top5 = 51.03, top10 = 47.73, top15 = 45.62.
+PHY-3001 : End congestion estimation; 0.947630s wall, 0.984375s user + 0.015625s system = 1.000000s CPU (105.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.881869s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000333934
+PHY-3002 : Step(329): len = 749842, overlap = 0.5
+PHY-3002 : Step(330): len = 749699, overlap = 0.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.006068s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (257.5%)
+
+PHY-3001 : Legalized: Len = 749683, Over = 0
+PHY-3001 : End spreading; 0.061063s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.4%)
+
+PHY-3001 : Final: Len = 749683, Over = 0
+PHY-3001 : End incremental placement; 6.297919s wall, 6.468750s user + 0.125000s system = 6.593750s CPU (104.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.599955s wall, 11.875000s user + 0.171875s system = 12.046875s CPU (113.7%)
+
+OPT-1001 : Current memory(MB): used = 735, reserve = 737, peak = 740.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16123/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 929256, over cnt = 54(0%), over = 70, worst = 5
+PHY-1002 : len = 929416, over cnt = 40(0%), over = 46, worst = 3
+PHY-1002 : len = 929824, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 930032, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 930048, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.772025s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (103.2%)
+
+PHY-1001 : Congestion index: top1 = 57.35, top5 = 51.04, top10 = 47.73, top15 = 45.62.
+OPT-1001 : End congestion update; 1.087064s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (100.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.715558s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.4%)
+
+OPT-0007 : Start: WNS -986 TNS -1650 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6728 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6816 instances, 6667 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3646 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 755367, Over = 0
+PHY-3001 : Spreading special nets. 19 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060033s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.1%)
+
+PHY-3001 : 24 instances has been re-located, deltaX = 15, deltaY = 16, maxDist = 2.
+PHY-3001 : Final: Len = 755869, Over = 0
+PHY-3001 : End incremental legalization; 0.420601s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.3%)
+
+OPT-0007 : Iter 1: improved WNS -890 TNS -1375 NUM_FEPS 2 with 58 cells processed and 13549 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6728 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6816 instances, 6667 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3646 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 759241, Over = 0
+PHY-3001 : Spreading special nets. 17 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063825s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.9%)
+
+PHY-3001 : 24 instances has been re-located, deltaX = 14, deltaY = 20, maxDist = 3.
+PHY-3001 : Final: Len = 759391, Over = 0
+PHY-3001 : End incremental legalization; 0.416222s wall, 0.437500s user + 0.015625s system = 0.453125s CPU (108.9%)
+
+OPT-0007 : Iter 2: improved WNS -890 TNS -1525 NUM_FEPS 2 with 27 cells processed and 5153 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6728 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6816 instances, 6667 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3646 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 761173, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060374s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (77.6%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 8, deltaY = 10, maxDist = 2.
+PHY-3001 : Final: Len = 761087, Over = 0
+PHY-3001 : End incremental legalization; 0.376717s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (124.4%)
+
+OPT-0007 : Iter 3: improved WNS -890 TNS -1425 NUM_FEPS 2 with 19 cells processed and 1651 slack improved
+OPT-1001 : End path based optimization; 3.491682s wall, 3.609375s user + 0.015625s system = 3.625000s CPU (103.8%)
+
+OPT-1001 : Current memory(MB): used = 735, reserve = 737, peak = 740.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.714539s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.6%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15728/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 940368, over cnt = 241(0%), over = 309, worst = 7
+PHY-1002 : len = 940664, over cnt = 150(0%), over = 163, worst = 4
+PHY-1002 : len = 941872, over cnt = 44(0%), over = 45, worst = 2
+PHY-1002 : len = 942536, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 942776, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.903335s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (105.5%)
+
+PHY-1001 : Congestion index: top1 = 56.92, top5 = 51.18, top10 = 47.99, top15 = 45.88.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.717971s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.1%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -936 TNS -1571 NUM_FEPS 2
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 56.551724
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -936ps with logic level 2
+RUN-1001 : #2 path slack -890ps with logic level 2
+RUN-1001 : extra opt step will be enabled to improve QoR
+RUN-1001 : 0 HFN exist on timing critical paths out of 17699 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 17699 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6728 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6816 instances, 6667 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3646 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 761087, Over = 0
+PHY-3001 : End spreading; 0.060390s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (77.6%)
+
+PHY-3001 : Final: Len = 761087, Over = 0
+PHY-3001 : End incremental legalization; 0.381997s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.717758s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.1%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16148/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 942776, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.139972s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.5%)
+
+PHY-1001 : Congestion index: top1 = 56.92, top5 = 51.18, top10 = 47.99, top15 = 45.88.
+OPT-1001 : End congestion update; 0.481287s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (100.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.728737s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.8%)
+
+OPT-0007 : Start: WNS -936 TNS -1571 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6728 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6816 instances, 6667 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3646 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 761165, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059797s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (78.4%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 3, deltaY = 5, maxDist = 3.
+PHY-3001 : Final: Len = 761087, Over = 0
+PHY-3001 : End incremental legalization; 0.380487s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (127.3%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1471 NUM_FEPS 2 with 4 cells processed and 400 slack improved
+OPT-0007 : Iter 2: improved WNS -936 TNS -1471 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.708227s wall, 1.921875s user + 0.000000s system = 1.921875s CPU (112.5%)
+
+OPT-1001 : Current memory(MB): used = 735, reserve = 737, peak = 740.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16148/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 942776, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.132598s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.3%)
+
+PHY-1001 : Congestion index: top1 = 56.92, top5 = 51.18, top10 = 47.99, top15 = 45.88.
+OPT-1001 : End congestion update; 0.446454s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (101.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.716162s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.4%)
+
+OPT-0007 : Start: WNS -936 TNS -1571 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6728 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6816 instances, 6667 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3646 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 761063, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057953s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.8%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 761087, Over = 0
+PHY-3001 : End incremental legalization; 0.378132s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (103.3%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1571 NUM_FEPS 2 with 1 cells processed and 50 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6728 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6816 instances, 6667 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3646 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 761063, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059362s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.3%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 761087, Over = 0
+PHY-3001 : End incremental legalization; 0.378438s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (103.2%)
+
+OPT-0007 : Iter 2: improved WNS -936 TNS -1571 NUM_FEPS 2 with 1 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS -936 TNS -1571 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 2.202789s wall, 2.203125s user + 0.000000s system = 2.203125s CPU (100.0%)
+
+OPT-1001 : Current memory(MB): used = 735, reserve = 737, peak = 740.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.717719s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.1%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 735, reserve = 737, peak = 740.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.715995s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.4%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16148/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 942776, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.130456s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.8%)
+
+PHY-1001 : Congestion index: top1 = 56.92, top5 = 51.18, top10 = 47.99, top15 = 45.88.
+RUN-1001 : End congestion update; 0.441506s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (102.6%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.160598s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (101.0%)
+
+OPT-1001 : Current memory(MB): used = 735, reserve = 737, peak = 740.
+OPT-1001 : End physical optimization; 26.034630s wall, 27.671875s user + 0.218750s system = 27.890625s CPU (107.1%)
+
+RUN-1003 : finish command "place" in 69.763053s wall, 100.906250s user + 6.593750s system = 107.500000s CPU (154.1%)
+
+RUN-1004 : used memory is 614 MB, reserved memory is 605 MB, peak memory is 740 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.673081s wall, 2.890625s user + 0.031250s system = 2.921875s CPU (174.6%)
+
+RUN-1004 : used memory is 615 MB, reserved memory is 607 MB, peak memory is 740 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6818 instances
+RUN-1001 : 3341 mslices, 3326 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17699 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10038 nets have 2 pins
+RUN-1001 : 5818 nets have [3 - 5] pins
+RUN-1001 : 1128 nets have [6 - 10] pins
+RUN-1001 : 331 nets have [11 - 20] pins
+RUN-1001 : 356 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74409, tnet num: 17521, tinst num: 6816, tnode num: 96897, tedge num: 124812.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.575154s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (100.2%)
+
+RUN-1004 : used memory is 625 MB, reserved memory is 632 MB, peak memory is 740 MB
+PHY-1001 : 3341 mslices, 3326 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[6] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 873728, over cnt = 2767(7%), over = 4558, worst = 8
+PHY-1002 : len = 889536, over cnt = 1868(5%), over = 2736, worst = 7
+PHY-1002 : len = 907736, over cnt = 893(2%), over = 1256, worst = 7
+PHY-1002 : len = 928336, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 928576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.040300s wall, 4.265625s user + 0.078125s system = 4.343750s CPU (142.9%)
+
+PHY-1001 : Congestion index: top1 = 56.83, top5 = 51.01, top10 = 47.81, top15 = 45.65.
+PHY-1001 : End global routing; 3.395332s wall, 4.625000s user + 0.078125s system = 4.703125s CPU (138.5%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 714, reserve = 717, peak = 740.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 989, reserve = 992, peak = 989.
+PHY-1001 : End build detailed router design. 4.013458s wall, 3.984375s user + 0.031250s system = 4.015625s CPU (100.1%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 270120, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.361275s wall, 5.359375s user + 0.000000s system = 5.359375s CPU (100.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 270176, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.437168s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1024, reserve = 1029, peak = 1024.
+PHY-1001 : End phase 1; 5.810535s wall, 5.812500s user + 0.000000s system = 5.812500s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.37919e+06, over cnt = 2012(0%), over = 2019, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1041, reserve = 1044, peak = 1041.
+PHY-1001 : End initial routed; 28.777134s wall, 61.203125s user + 0.171875s system = 61.375000s CPU (213.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16621(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.946 | -3.877 | 4
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.246685s wall, 3.250000s user + 0.000000s system = 3.250000s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1049, reserve = 1053, peak = 1049.
+PHY-1001 : End phase 2; 32.023886s wall, 64.453125s user + 0.171875s system = 64.625000s CPU (201.8%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 5 pins with SWNS -1.946ns STNS -3.853ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.147393s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.4%)
+
+PHY-1022 : len = 2.37921e+06, over cnt = 2017(0%), over = 2025, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.419841s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.348e+06, over cnt = 698(0%), over = 699, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.013846s wall, 3.015625s user + 0.031250s system = 3.046875s CPU (151.3%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.34288e+06, over cnt = 160(0%), over = 160, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.072167s wall, 1.421875s user + 0.000000s system = 1.421875s CPU (132.6%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.34361e+06, over cnt = 18(0%), over = 18, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.504800s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (108.3%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.34393e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.246859s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (101.3%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.3441e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.292363s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (96.2%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.3441e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.494284s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (98.0%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.3441e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.638504s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (100.3%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.34411e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.185719s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (101.0%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.3441e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.208893s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (97.2%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.3441e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.223741s wall, 0.250000s user + 0.015625s system = 0.265625s CPU (118.7%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.3441e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.262041s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (95.4%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.3441e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.446488s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (101.5%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.34412e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.192272s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (97.5%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.34407e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.165976s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (94.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16621(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.946 | -3.853 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.272361s wall, 3.265625s user + 0.015625s system = 3.281250s CPU (100.3%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 675 feed throughs used by 490 nets
+PHY-1001 : End commit to database; 2.324289s wall, 2.281250s user + 0.031250s system = 2.312500s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1158, reserve = 1165, peak = 1158.
+PHY-1001 : End phase 3; 13.388407s wall, 14.750000s user + 0.093750s system = 14.843750s CPU (110.9%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.946ns STNS -3.853ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.139581s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.7%)
+
+PHY-1022 : len = 2.34407e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.391002s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.9%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.946ns, -3.853ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16621(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.946 | -3.853 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.279411s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 675 feed throughs used by 490 nets
+PHY-1001 : End commit to database; 2.416406s wall, 2.421875s user + 0.000000s system = 2.421875s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1167, reserve = 1174, peak = 1167.
+PHY-1001 : End phase 4; 6.114721s wall, 6.109375s user + 0.000000s system = 6.109375s CPU (99.9%)
+
+PHY-1003 : Routed, final wirelength = 2.34407e+06
+PHY-1001 : Current memory(MB): used = 1169, reserve = 1176, peak = 1169.
+PHY-1001 : End export database. 0.061269s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.0%)
+
+PHY-1001 : End detail routing; 61.808362s wall, 95.562500s user + 0.296875s system = 95.859375s CPU (155.1%)
+
+RUN-1003 : finish command "route" in 67.868670s wall, 102.796875s user + 0.421875s system = 103.218750s CPU (152.1%)
+
+RUN-1004 : used memory is 1095 MB, reserved memory is 1101 MB, peak memory is 1169 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10337 out of 19600 52.74%
+#reg 9372 out of 19600 47.82%
+#le 12446
+ #lut only 3074 out of 12446 24.70%
+ #reg only 2109 out of 12446 16.95%
+ #lut® 7263 out of 12446 58.36%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1812
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1402
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1351
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 949
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 137
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 23
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_a/u_ADconfig/reg1_syn_168.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_319.f0 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P140 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P4 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P138 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P16 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P156 LVCMOS33 8 N/A NONE
+ paper_out OUTPUT P15 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P17 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P107 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12446 |9310 |1027 |9403 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |548 |468 |23 |435 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |102 |86 |4 |90 |4 |0 |
+| U_crc16_24b |crc16_24b |51 |51 |0 |23 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |10 |0 |7 |0 |0 |
+| exdev_ctl_a |exdev_ctl |793 |388 |96 |594 |0 |0 |
+| u_ADconfig |AD_config |197 |128 |25 |148 |0 |0 |
+| u_gen_sp |gen_sp |272 |163 |71 |122 |0 |0 |
+| exdev_ctl_b |exdev_ctl |740 |392 |96 |545 |0 |0 |
+| u_ADconfig |AD_config |169 |117 |25 |119 |0 |0 |
+| u_gen_sp |gen_sp |266 |163 |71 |121 |0 |0 |
+| sampling_fe_a |sampling_fe |2989 |2425 |306 |2064 |25 |0 |
+| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |175 |110 |17 |141 |0 |0 |
+| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_sort |sort |2780 |2308 |289 |1889 |25 |0 |
+| rddpram_ctl |rddpram_ctl |5 |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2390 |2014 |253 |1568 |22 |0 |
+| channelPart |channel_part_8478 |153 |148 |3 |132 |0 |0 |
+| fifo_adc |fifo_adc |57 |48 |9 |38 |0 |0 |
+| ram_switch |ram_switch |1861 |1563 |197 |1164 |0 |0 |
+| adc_addr_gen |adc_addr_gen |245 |217 |27 |125 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |15 |11 |3 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |25 |22 |3 |14 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |25 |22 |3 |15 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |29 |26 |3 |16 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| insert |insert |966 |696 |170 |654 |0 |0 |
+| ram_switch_state |ram_switch_state |650 |650 |0 |385 |0 |0 |
+| read_ram_i |read_ram |273 |215 |44 |193 |0 |0 |
+| read_ram_addr |read_ram_addr |217 |177 |40 |151 |0 |0 |
+| read_ram_data |read_ram_data |53 |36 |4 |39 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |347 |276 |36 |278 |3 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3277 |2562 |349 |2110 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |0 |1 |0 |0 |
+| u_ad_sampling |ad_sampling |183 |92 |17 |148 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort_rev |3063 |2468 |332 |1931 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |5 |5 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2648 |2136 |290 |1572 |22 |1 |
+| channelPart |channel_part_8478 |260 |256 |3 |140 |0 |0 |
+| fifo_adc |fifo_adc |55 |46 |9 |40 |0 |1 |
+| ram_switch |ram_switch |1932 |1552 |197 |1140 |0 |0 |
+| adc_addr_gen |adc_addr_gen |227 |200 |27 |108 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |16 |13 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |21 |18 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |6 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |21 |18 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 |
+| insert |insert |981 |633 |170 |679 |0 |0 |
+| ram_switch_state |ram_switch_state |724 |719 |0 |353 |0 |0 |
+| read_ram_i |read_ram_rev |361 |252 |81 |212 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |284 |199 |73 |159 |0 |0 |
+| read_ram_data |read_ram_data_rev |77 |53 |8 |53 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9976
+ #2 2 3851
+ #3 3 1395
+ #4 4 569
+ #5 5-10 1200
+ #6 11-50 588
+ #7 51-100 24
+ #8 >500 1
+ Average 2.91
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.060951s wall, 3.546875s user + 0.000000s system = 3.546875s CPU (172.1%)
+
+RUN-1004 : used memory is 1097 MB, reserved memory is 1103 MB, peak memory is 1169 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74409, tnet num: 17521, tinst num: 6816, tnode num: 96897, tedge num: 124812.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.586381s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (99.5%)
+
+RUN-1004 : used memory is 1101 MB, reserved memory is 1107 MB, peak memory is 1169 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.506654s wall, 1.500000s user + 0.015625s system = 1.515625s CPU (100.6%)
+
+RUN-1004 : used memory is 1103 MB, reserved memory is 1110 MB, peak memory is 1169 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6816
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17699, pip num: 175864
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 675
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3254 valid insts, and 485333 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 10.159850s wall, 68.265625s user + 0.125000s system = 68.390625s CPU (673.1%)
+
+RUN-1004 : used memory is 1262 MB, reserved memory is 1266 MB, peak memory is 1378 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240126_091207.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240202_135725.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240202_135725.log
new file mode 100644
index 0000000..dfcec16
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240202_135725.log
@@ -0,0 +1,1971 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Fri Feb 2 13:57:25 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.511250s wall, 2.281250s user + 0.093750s system = 2.375000s CPU (94.6%)
+
+RUN-1004 : used memory is 336 MB, reserved memory is 315 MB, peak memory is 341 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2945 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17775 instances
+RUN-0007 : 7512 luts, 9040 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20353 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13332 nets have 2 pins
+RUN-1001 : 5562 nets have [3 - 5] pins
+RUN-1001 : 1037 nets have [6 - 10] pins
+RUN-1001 : 172 nets have [11 - 20] pins
+RUN-1001 : 176 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 789
+RUN-1001 : No | No | Yes | 1968
+RUN-1001 : No | Yes | No | 3474
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 56
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 141
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17773 instances, 7512 luts, 9040 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 5912 pins
+PHY-0007 : Cell area utilization is 49%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85138, tnet num: 20175, tinst num: 17773, tnode num: 115214, tedge num: 136657.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.452161s wall, 1.296875s user + 0.062500s system = 1.359375s CPU (93.6%)
+
+RUN-1004 : used memory is 530 MB, reserved memory is 514 MB, peak memory is 530 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20175 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.443298s wall, 2.218750s user + 0.093750s system = 2.312500s CPU (94.6%)
+
+PHY-3001 : Found 1221 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 3.89603e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17773.
+PHY-3001 : Level 1 #clusters 2040.
+PHY-3001 : End clustering; 0.175991s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (133.2%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 49%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.29871e+06, overlap = 464.062
+PHY-3002 : Step(2): len = 1.16387e+06, overlap = 476.438
+PHY-3002 : Step(3): len = 880084, overlap = 600.531
+PHY-3002 : Step(4): len = 775365, overlap = 620.75
+PHY-3002 : Step(5): len = 620451, overlap = 720.125
+PHY-3002 : Step(6): len = 541657, overlap = 806.156
+PHY-3002 : Step(7): len = 471370, overlap = 893.719
+PHY-3002 : Step(8): len = 428267, overlap = 967.562
+PHY-3002 : Step(9): len = 382658, overlap = 1047.03
+PHY-3002 : Step(10): len = 346314, overlap = 1105.34
+PHY-3002 : Step(11): len = 314847, overlap = 1138
+PHY-3002 : Step(12): len = 296195, overlap = 1168.91
+PHY-3002 : Step(13): len = 269976, overlap = 1255.44
+PHY-3002 : Step(14): len = 250682, overlap = 1323.28
+PHY-3002 : Step(15): len = 227268, overlap = 1350.56
+PHY-3002 : Step(16): len = 207644, overlap = 1399.5
+PHY-3002 : Step(17): len = 187402, overlap = 1443.78
+PHY-3002 : Step(18): len = 172916, overlap = 1469.59
+PHY-3002 : Step(19): len = 163771, overlap = 1479.94
+PHY-3002 : Step(20): len = 149199, overlap = 1499.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.36787e-07
+PHY-3002 : Step(21): len = 148876, overlap = 1460.84
+PHY-3002 : Step(22): len = 178617, overlap = 1353.72
+PHY-3002 : Step(23): len = 183402, overlap = 1299.34
+PHY-3002 : Step(24): len = 185604, overlap = 1242.62
+PHY-3002 : Step(25): len = 183574, overlap = 1220.25
+PHY-3002 : Step(26): len = 183668, overlap = 1212.28
+PHY-3002 : Step(27): len = 178408, overlap = 1219.25
+PHY-3002 : Step(28): len = 175686, overlap = 1205.31
+PHY-3002 : Step(29): len = 170762, overlap = 1189.66
+PHY-3002 : Step(30): len = 169959, overlap = 1185.34
+PHY-3002 : Step(31): len = 167983, overlap = 1199.34
+PHY-3002 : Step(32): len = 166890, overlap = 1195.94
+PHY-3002 : Step(33): len = 165147, overlap = 1209.25
+PHY-3002 : Step(34): len = 165835, overlap = 1208.62
+PHY-3002 : Step(35): len = 163212, overlap = 1226.75
+PHY-3002 : Step(36): len = 163151, overlap = 1249.06
+PHY-3002 : Step(37): len = 161100, overlap = 1250.47
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.67357e-06
+PHY-3002 : Step(38): len = 165542, overlap = 1233.28
+PHY-3002 : Step(39): len = 180960, overlap = 1159.53
+PHY-3002 : Step(40): len = 186287, overlap = 1174.84
+PHY-3002 : Step(41): len = 192209, overlap = 1154.72
+PHY-3002 : Step(42): len = 194134, overlap = 1151.78
+PHY-3002 : Step(43): len = 195363, overlap = 1130.5
+PHY-3002 : Step(44): len = 194084, overlap = 1121.81
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.34715e-06
+PHY-3002 : Step(45): len = 198541, overlap = 1095.09
+PHY-3002 : Step(46): len = 211550, overlap = 1051
+PHY-3002 : Step(47): len = 218893, overlap = 997.938
+PHY-3002 : Step(48): len = 224164, overlap = 983.969
+PHY-3002 : Step(49): len = 225597, overlap = 939.5
+PHY-3002 : Step(50): len = 227062, overlap = 919.531
+PHY-3002 : Step(51): len = 227093, overlap = 900.156
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 6.6943e-06
+PHY-3002 : Step(52): len = 238700, overlap = 869.406
+PHY-3002 : Step(53): len = 261961, overlap = 805.656
+PHY-3002 : Step(54): len = 275755, overlap = 777.156
+PHY-3002 : Step(55): len = 287414, overlap = 709.156
+PHY-3002 : Step(56): len = 290258, overlap = 677.75
+PHY-3002 : Step(57): len = 289762, overlap = 650.375
+PHY-3002 : Step(58): len = 288014, overlap = 645.5
+PHY-3002 : Step(59): len = 287278, overlap = 645.969
+PHY-3002 : Step(60): len = 286212, overlap = 643.281
+PHY-3002 : Step(61): len = 284799, overlap = 629.75
+PHY-3002 : Step(62): len = 282920, overlap = 636.844
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.33886e-05
+PHY-3002 : Step(63): len = 300787, overlap = 580.125
+PHY-3002 : Step(64): len = 319319, overlap = 539.188
+PHY-3002 : Step(65): len = 326246, overlap = 516.156
+PHY-3002 : Step(66): len = 328533, overlap = 501.312
+PHY-3002 : Step(67): len = 329323, overlap = 511.344
+PHY-3002 : Step(68): len = 329885, overlap = 544.25
+PHY-3002 : Step(69): len = 329880, overlap = 536.531
+PHY-3002 : Step(70): len = 329596, overlap = 534.625
+PHY-3002 : Step(71): len = 329499, overlap = 534.562
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 2.67772e-05
+PHY-3002 : Step(72): len = 347409, overlap = 509.406
+PHY-3002 : Step(73): len = 366430, overlap = 473.781
+PHY-3002 : Step(74): len = 374422, overlap = 426.875
+PHY-3002 : Step(75): len = 378305, overlap = 443.375
+PHY-3002 : Step(76): len = 378650, overlap = 452.844
+PHY-3002 : Step(77): len = 381816, overlap = 430.062
+PHY-3002 : Step(78): len = 380055, overlap = 383.062
+PHY-3002 : Step(79): len = 379557, overlap = 363.094
+PHY-3002 : Step(80): len = 377323, overlap = 370.031
+PHY-3002 : Step(81): len = 377588, overlap = 368.156
+PHY-3002 : Step(82): len = 378586, overlap = 348.188
+PHY-3002 : Step(83): len = 382453, overlap = 323.125
+PHY-3002 : Step(84): len = 382991, overlap = 319.281
+PHY-3002 : Step(85): len = 383424, overlap = 315.562
+PHY-3002 : Step(86): len = 382365, overlap = 315.781
+PHY-3002 : Step(87): len = 382396, overlap = 313.062
+PHY-3002 : Step(88): len = 380448, overlap = 318.531
+PHY-3002 : Step(89): len = 380260, overlap = 328.875
+PHY-3002 : Step(90): len = 378911, overlap = 320.719
+PHY-3002 : Step(91): len = 377713, overlap = 316.219
+PHY-3002 : Step(92): len = 376585, overlap = 326.594
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 5.35544e-05
+PHY-3002 : Step(93): len = 394299, overlap = 320.844
+PHY-3002 : Step(94): len = 407716, overlap = 310.531
+PHY-3002 : Step(95): len = 409713, overlap = 313.5
+PHY-3002 : Step(96): len = 411470, overlap = 301.906
+PHY-3002 : Step(97): len = 412878, overlap = 277
+PHY-3002 : Step(98): len = 414581, overlap = 269.719
+PHY-3002 : Step(99): len = 411197, overlap = 271.688
+PHY-3002 : Step(100): len = 410554, overlap = 277.531
+PHY-3002 : Step(101): len = 411572, overlap = 271.125
+PHY-3002 : Step(102): len = 412759, overlap = 272.469
+PHY-3002 : Step(103): len = 410166, overlap = 267.844
+PHY-3002 : Step(104): len = 410238, overlap = 257.125
+PHY-3002 : Step(105): len = 411046, overlap = 251.656
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000107109
+PHY-3002 : Step(106): len = 427683, overlap = 255
+PHY-3002 : Step(107): len = 436234, overlap = 240.719
+PHY-3002 : Step(108): len = 434049, overlap = 249.875
+PHY-3002 : Step(109): len = 434457, overlap = 238.688
+PHY-3002 : Step(110): len = 438147, overlap = 244.438
+PHY-3002 : Step(111): len = 442565, overlap = 240.062
+PHY-3002 : Step(112): len = 440949, overlap = 226.844
+PHY-3002 : Step(113): len = 441799, overlap = 235.688
+PHY-3002 : Step(114): len = 444516, overlap = 240.562
+PHY-3002 : Step(115): len = 447000, overlap = 236.344
+PHY-3002 : Step(116): len = 445252, overlap = 238
+PHY-3002 : Step(117): len = 445606, overlap = 226.312
+PHY-3002 : Step(118): len = 446864, overlap = 221.094
+PHY-3002 : Step(119): len = 447129, overlap = 216.969
+PHY-3002 : Step(120): len = 445471, overlap = 216.094
+PHY-3002 : Step(121): len = 446300, overlap = 212.219
+PHY-3002 : Step(122): len = 449269, overlap = 211.188
+PHY-3002 : Step(123): len = 451010, overlap = 214.438
+PHY-3002 : Step(124): len = 448660, overlap = 225.281
+PHY-3002 : Step(125): len = 448157, overlap = 215.531
+PHY-3002 : Step(126): len = 448103, overlap = 214.5
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000207388
+PHY-3002 : Step(127): len = 460501, overlap = 210.719
+PHY-3002 : Step(128): len = 467397, overlap = 207.312
+PHY-3002 : Step(129): len = 466144, overlap = 197.094
+PHY-3002 : Step(130): len = 466829, overlap = 198.219
+PHY-3002 : Step(131): len = 469509, overlap = 200.281
+PHY-3002 : Step(132): len = 471909, overlap = 190.5
+PHY-3002 : Step(133): len = 471107, overlap = 190.875
+PHY-3002 : Step(134): len = 472123, overlap = 188.281
+PHY-3002 : Step(135): len = 475326, overlap = 176.469
+PHY-3002 : Step(136): len = 478259, overlap = 166.656
+PHY-3002 : Step(137): len = 477161, overlap = 168.688
+PHY-3002 : Step(138): len = 477546, overlap = 176.438
+PHY-3002 : Step(139): len = 479313, overlap = 181.531
+PHY-3002 : Step(140): len = 480810, overlap = 180.531
+PHY-3002 : Step(141): len = 479618, overlap = 176.594
+PHY-3002 : Step(142): len = 479404, overlap = 180.812
+PHY-3002 : Step(143): len = 480861, overlap = 180.281
+PHY-3002 : Step(144): len = 481624, overlap = 177.875
+PHY-3002 : Step(145): len = 480465, overlap = 176.562
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000394158
+PHY-3002 : Step(146): len = 488541, overlap = 174.719
+PHY-3002 : Step(147): len = 496095, overlap = 156.625
+PHY-3002 : Step(148): len = 496916, overlap = 144.156
+PHY-3002 : Step(149): len = 498508, overlap = 143.656
+PHY-3002 : Step(150): len = 501606, overlap = 138.156
+PHY-3002 : Step(151): len = 503587, overlap = 132.625
+PHY-3002 : Step(152): len = 502527, overlap = 138.781
+PHY-3002 : Step(153): len = 502190, overlap = 143.094
+PHY-3002 : Step(154): len = 504054, overlap = 141.625
+PHY-3002 : Step(155): len = 505311, overlap = 139.375
+PHY-3002 : Step(156): len = 504647, overlap = 131.688
+PHY-3002 : Step(157): len = 504850, overlap = 131.156
+PHY-3002 : Step(158): len = 505870, overlap = 133.531
+PHY-3002 : Step(159): len = 506243, overlap = 140.406
+PHY-3002 : Step(160): len = 505496, overlap = 135.281
+PHY-3002 : Step(161): len = 505230, overlap = 131.969
+PHY-3002 : Step(162): len = 505915, overlap = 132.375
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000763728
+PHY-3002 : Step(163): len = 510491, overlap = 129.156
+PHY-3002 : Step(164): len = 516288, overlap = 128.75
+PHY-3002 : Step(165): len = 517959, overlap = 118.656
+PHY-3002 : Step(166): len = 519228, overlap = 120.969
+PHY-3002 : Step(167): len = 521036, overlap = 126.219
+PHY-3002 : Step(168): len = 522151, overlap = 128.125
+PHY-3002 : Step(169): len = 521892, overlap = 121.406
+PHY-3002 : Step(170): len = 522325, overlap = 121.219
+PHY-3002 : Step(171): len = 523452, overlap = 118.844
+PHY-3002 : Step(172): len = 524125, overlap = 120.094
+PHY-3002 : Step(173): len = 523822, overlap = 117.844
+PHY-3002 : Step(174): len = 523807, overlap = 116.906
+PHY-3002 : Step(175): len = 524353, overlap = 116.281
+PHY-3002 : Step(176): len = 524768, overlap = 119.812
+PHY-3002 : Step(177): len = 524242, overlap = 117.938
+PHY-3002 : Step(178): len = 524126, overlap = 114.75
+PHY-3002 : Step(179): len = 524607, overlap = 114.375
+PHY-3002 : Step(180): len = 524677, overlap = 114.312
+PHY-3002 : Step(181): len = 524367, overlap = 114.812
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00133242
+PHY-3002 : Step(182): len = 527175, overlap = 116.188
+PHY-3002 : Step(183): len = 531660, overlap = 114.094
+PHY-3002 : Step(184): len = 531886, overlap = 105.781
+PHY-3002 : Step(185): len = 532114, overlap = 106.094
+PHY-3002 : Step(186): len = 533691, overlap = 107.594
+PHY-3002 : Step(187): len = 534332, overlap = 107.406
+PHY-3002 : Step(188): len = 534207, overlap = 104.375
+PHY-3002 : Step(189): len = 534347, overlap = 103.062
+PHY-3002 : Step(190): len = 535187, overlap = 102.906
+PHY-3002 : Step(191): len = 535747, overlap = 97.7812
+PHY-3002 : Step(192): len = 535514, overlap = 100.906
+PHY-3002 : Step(193): len = 535514, overlap = 100.906
+PHY-3002 : Step(194): len = 535751, overlap = 100.469
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00223801
+PHY-3002 : Step(195): len = 538638, overlap = 101.344
+PHY-3002 : Step(196): len = 545753, overlap = 98.6875
+PHY-3002 : Step(197): len = 548324, overlap = 95.25
+PHY-3002 : Step(198): len = 551082, overlap = 100.531
+PHY-3002 : Step(199): len = 553399, overlap = 96.5625
+PHY-3002 : Step(200): len = 554687, overlap = 96.3125
+PHY-3002 : Step(201): len = 553641, overlap = 95.5
+PHY-3002 : Step(202): len = 553120, overlap = 99.3125
+PHY-3002 : Step(203): len = 553093, overlap = 95.9375
+PHY-3002 : Step(204): len = 552991, overlap = 99.625
+PHY-3002 : Step(205): len = 552500, overlap = 100.875
+PHY-3002 : Step(206): len = 552219, overlap = 96.625
+PHY-3002 : Step(207): len = 552110, overlap = 98.6875
+PHY-3002 : Step(208): len = 552044, overlap = 98.6875
+PHY-3002 : Step(209): len = 551937, overlap = 106.188
+PHY-3002 : Step(210): len = 551798, overlap = 106
+PHY-3002 : Step(211): len = 551800, overlap = 105.875
+PHY-3002 : Step(212): len = 551783, overlap = 104.156
+PHY-3002 : Step(213): len = 551762, overlap = 104.594
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.025339s wall, 0.015625s user + 0.031250s system = 0.046875s CPU (185.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20353.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 721168, over cnt = 1582(4%), over = 7083, worst = 51
+PHY-1001 : End global iterations; 0.837872s wall, 1.203125s user + 0.015625s system = 1.218750s CPU (145.5%)
+
+PHY-1001 : Congestion index: top1 = 75.13, top5 = 60.49, top10 = 52.40, top15 = 46.98.
+PHY-3001 : End congestion estimation; 1.285169s wall, 1.609375s user + 0.046875s system = 1.656250s CPU (128.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20175 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.044864s wall, 1.015625s user + 0.031250s system = 1.046875s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000137819
+PHY-3002 : Step(214): len = 646525, overlap = 60.2188
+PHY-3002 : Step(215): len = 651059, overlap = 54.6562
+PHY-3002 : Step(216): len = 646290, overlap = 55.125
+PHY-3002 : Step(217): len = 645768, overlap = 51.8125
+PHY-3002 : Step(218): len = 645043, overlap = 51.8125
+PHY-3002 : Step(219): len = 643036, overlap = 53.7188
+PHY-3002 : Step(220): len = 641194, overlap = 51.2812
+PHY-3002 : Step(221): len = 640221, overlap = 41.5312
+PHY-3002 : Step(222): len = 636862, overlap = 35.4375
+PHY-3002 : Step(223): len = 633882, overlap = 34.0938
+PHY-3002 : Step(224): len = 630391, overlap = 35.75
+PHY-3002 : Step(225): len = 628815, overlap = 35.375
+PHY-3002 : Step(226): len = 626606, overlap = 34.8438
+PHY-3002 : Step(227): len = 626314, overlap = 33.1562
+PHY-3002 : Step(228): len = 624299, overlap = 34.2812
+PHY-3002 : Step(229): len = 623778, overlap = 39.9688
+PHY-3002 : Step(230): len = 622234, overlap = 39.6875
+PHY-3002 : Step(231): len = 619831, overlap = 40.8125
+PHY-3002 : Step(232): len = 618591, overlap = 44.4688
+PHY-3002 : Step(233): len = 617624, overlap = 48.8125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000275638
+PHY-3002 : Step(234): len = 619758, overlap = 45.6562
+PHY-3002 : Step(235): len = 623588, overlap = 41.8438
+PHY-3002 : Step(236): len = 627157, overlap = 40.2812
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000501576
+PHY-3002 : Step(237): len = 632424, overlap = 39.125
+PHY-3002 : Step(238): len = 647965, overlap = 35.9062
+PHY-3002 : Step(239): len = 655163, overlap = 34.1875
+PHY-3002 : Step(240): len = 656944, overlap = 38.375
+PHY-3002 : Step(241): len = 659439, overlap = 37.8125
+PHY-3002 : Step(242): len = 664969, overlap = 38.2812
+PHY-3002 : Step(243): len = 664385, overlap = 38.1562
+PHY-3002 : Step(244): len = 663482, overlap = 41.7812
+PHY-3002 : Step(245): len = 663725, overlap = 40.0625
+PHY-3002 : Step(246): len = 663355, overlap = 40.9688
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00100315
+PHY-3002 : Step(247): len = 666830, overlap = 42.5312
+PHY-3002 : Step(248): len = 674051, overlap = 41.5312
+PHY-3002 : Step(249): len = 680020, overlap = 40.0625
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00169752
+PHY-3002 : Step(250): len = 683908, overlap = 41.0625
+PHY-3002 : Step(251): len = 691546, overlap = 39.9062
+PHY-3002 : Step(252): len = 699202, overlap = 40.9375
+PHY-3002 : Step(253): len = 705199, overlap = 43.5625
+PHY-3002 : Step(254): len = 708649, overlap = 39.9062
+PHY-3002 : Step(255): len = 711006, overlap = 37.2812
+PHY-3002 : Step(256): len = 713128, overlap = 38.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 65/20353.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 803120, over cnt = 2764(7%), over = 13053, worst = 46
+PHY-1001 : End global iterations; 1.945874s wall, 2.406250s user + 0.031250s system = 2.437500s CPU (125.3%)
+
+PHY-1001 : Congestion index: top1 = 90.43, top5 = 73.09, top10 = 63.98, top15 = 58.10.
+PHY-3001 : End congestion estimation; 2.311433s wall, 2.750000s user + 0.031250s system = 2.781250s CPU (120.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20175 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.314688s wall, 1.265625s user + 0.015625s system = 1.281250s CPU (97.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000125838
+PHY-3002 : Step(257): len = 697586, overlap = 254.719
+PHY-3002 : Step(258): len = 687628, overlap = 195.656
+PHY-3002 : Step(259): len = 673643, overlap = 175.062
+PHY-3002 : Step(260): len = 662672, overlap = 158.781
+PHY-3002 : Step(261): len = 653676, overlap = 150.406
+PHY-3002 : Step(262): len = 645379, overlap = 145.156
+PHY-3002 : Step(263): len = 640033, overlap = 131.812
+PHY-3002 : Step(264): len = 634172, overlap = 127.844
+PHY-3002 : Step(265): len = 629646, overlap = 128.438
+PHY-3002 : Step(266): len = 624224, overlap = 130.062
+PHY-3002 : Step(267): len = 621371, overlap = 131.25
+PHY-3002 : Step(268): len = 617086, overlap = 129.344
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000251676
+PHY-3002 : Step(269): len = 617969, overlap = 124.938
+PHY-3002 : Step(270): len = 619355, overlap = 124.625
+PHY-3002 : Step(271): len = 621236, overlap = 118.812
+PHY-3002 : Step(272): len = 623391, overlap = 111.188
+PHY-3002 : Step(273): len = 625661, overlap = 107.938
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000503351
+PHY-3002 : Step(274): len = 627443, overlap = 102
+PHY-3002 : Step(275): len = 628615, overlap = 100.188
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000844815
+PHY-3002 : Step(276): len = 633853, overlap = 91.2188
+PHY-3002 : Step(277): len = 643584, overlap = 87.5938
+PHY-3002 : Step(278): len = 648527, overlap = 81.4375
+PHY-3002 : Step(279): len = 648218, overlap = 76.125
+PHY-3002 : Step(280): len = 648019, overlap = 73.5938
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85138, tnet num: 20175, tinst num: 17773, tnode num: 115214, tedge num: 136657.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.838322s wall, 1.718750s user + 0.062500s system = 1.781250s CPU (96.9%)
+
+RUN-1004 : used memory is 574 MB, reserved memory is 564 MB, peak memory is 711 MB
+OPT-1001 : Total overflow 373.72 peak overflow 6.31
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 508/20353.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 752224, over cnt = 3065(8%), over = 10700, worst = 22
+PHY-1001 : End global iterations; 1.878206s wall, 2.421875s user + 0.000000s system = 2.421875s CPU (128.9%)
+
+PHY-1001 : Congestion index: top1 = 72.35, top5 = 57.68, top10 = 51.37, top15 = 47.60.
+PHY-1001 : End incremental global routing; 2.311767s wall, 2.859375s user + 0.000000s system = 2.859375s CPU (123.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20175 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.319877s wall, 1.296875s user + 0.015625s system = 1.312500s CPU (99.4%)
+
+OPT-1001 : 48 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17640 has valid locations, 322 needs to be replaced
+PHY-3001 : design contains 18047 instances, 7609 luts, 9217 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 6040 pins
+PHY-3001 : Found 1232 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 673563
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16609/20627.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 765640, over cnt = 3112(8%), over = 10742, worst = 22
+PHY-1001 : End global iterations; 0.298895s wall, 0.343750s user + 0.031250s system = 0.375000s CPU (125.5%)
+
+PHY-1001 : Congestion index: top1 = 71.81, top5 = 57.80, top10 = 51.62, top15 = 47.86.
+PHY-3001 : End congestion estimation; 0.645360s wall, 0.671875s user + 0.046875s system = 0.718750s CPU (111.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86229, tnet num: 20449, tinst num: 18047, tnode num: 116848, tedge num: 138291.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.805511s wall, 1.750000s user + 0.046875s system = 1.796875s CPU (99.5%)
+
+RUN-1004 : used memory is 620 MB, reserved memory is 625 MB, peak memory is 715 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20449 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.977857s wall, 2.921875s user + 0.046875s system = 2.968750s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(281): len = 672592, overlap = 0
+PHY-3002 : Step(282): len = 672054, overlap = 0
+PHY-3002 : Step(283): len = 671833, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16726/20627.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 763944, over cnt = 3094(8%), over = 10812, worst = 22
+PHY-1001 : End global iterations; 0.253921s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (123.1%)
+
+PHY-1001 : Congestion index: top1 = 72.89, top5 = 58.38, top10 = 52.15, top15 = 48.28.
+PHY-3001 : End congestion estimation; 0.613767s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (106.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20449 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.377115s wall, 1.312500s user + 0.015625s system = 1.328125s CPU (96.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000378762
+PHY-3002 : Step(284): len = 671669, overlap = 75.5312
+PHY-3002 : Step(285): len = 671888, overlap = 75.7188
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000757525
+PHY-3002 : Step(286): len = 671976, overlap = 75.625
+PHY-3002 : Step(287): len = 672595, overlap = 75.25
+PHY-3001 : Final: Len = 672595, Over = 75.25
+PHY-3001 : End incremental placement; 6.677655s wall, 6.796875s user + 0.281250s system = 7.078125s CPU (106.0%)
+
+OPT-1001 : Total overflow 379.16 peak overflow 6.31
+OPT-1001 : End high-fanout net optimization; 10.996023s wall, 11.703125s user + 0.296875s system = 12.000000s CPU (109.1%)
+
+OPT-1001 : Current memory(MB): used = 716, reserve = 711, peak = 734.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16658/20627.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 767624, over cnt = 3040(8%), over = 9580, worst = 22
+PHY-1002 : len = 810688, over cnt = 2114(6%), over = 5286, worst = 22
+PHY-1002 : len = 860136, over cnt = 799(2%), over = 1587, worst = 22
+PHY-1002 : len = 879960, over cnt = 179(0%), over = 267, worst = 12
+PHY-1002 : len = 884728, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.121508s wall, 2.937500s user + 0.015625s system = 2.953125s CPU (139.2%)
+
+PHY-1001 : Congestion index: top1 = 59.05, top5 = 51.10, top10 = 47.18, top15 = 44.87.
+OPT-1001 : End congestion update; 2.480565s wall, 3.296875s user + 0.015625s system = 3.312500s CPU (133.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20449 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.283681s wall, 1.250000s user + 0.015625s system = 1.265625s CPU (98.6%)
+
+OPT-0007 : Start: WNS -1018 TNS -1478 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 67 cells processed and 4864 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 27 cells processed and 908 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 14 cells processed and 1150 slack improved
+OPT-0007 : Iter 4: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 8 cells processed and 400 slack improved
+OPT-1001 : End global optimization; 3.837006s wall, 4.593750s user + 0.031250s system = 4.625000s CPU (120.5%)
+
+OPT-1001 : Current memory(MB): used = 694, reserve = 694, peak = 734.
+OPT-1001 : End physical optimization; 17.636550s wall, 19.000000s user + 0.390625s system = 19.390625s CPU (109.9%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7609 LUT to BLE ...
+SYN-4008 : Packed 7609 LUT and 3080 SEQ to BLE.
+SYN-4003 : Packing 6137 remaining SEQ's ...
+SYN-4005 : Packed 4155 SEQ with LUT/SLICE
+SYN-4006 : 678 single LUT's are left
+SYN-4006 : 1982 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9591/13322 primitive instances ...
+PHY-3001 : End packing; 2.085532s wall, 2.078125s user + 0.000000s system = 2.078125s CPU (99.6%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6715 instances
+RUN-1001 : 3283 mslices, 3284 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17678 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10014 nets have 2 pins
+RUN-1001 : 5836 nets have [3 - 5] pins
+RUN-1001 : 1121 nets have [6 - 10] pins
+RUN-1001 : 335 nets have [11 - 20] pins
+RUN-1001 : 341 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6713 instances, 6567 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3562 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 686526, Over = 241.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7068/17678.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 837184, over cnt = 1937(5%), over = 3146, worst = 8
+PHY-1002 : len = 844304, over cnt = 1315(3%), over = 1951, worst = 7
+PHY-1002 : len = 856968, over cnt = 609(1%), over = 875, worst = 7
+PHY-1002 : len = 867728, over cnt = 147(0%), over = 209, worst = 5
+PHY-1002 : len = 870192, over cnt = 26(0%), over = 37, worst = 3
+PHY-1001 : End global iterations; 2.059562s wall, 2.875000s user + 0.000000s system = 2.875000s CPU (139.6%)
+
+PHY-1001 : Congestion index: top1 = 57.44, top5 = 50.28, top10 = 46.64, top15 = 44.28.
+PHY-3001 : End congestion estimation; 2.589555s wall, 3.390625s user + 0.000000s system = 3.390625s CPU (130.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74272, tnet num: 17500, tinst num: 6713, tnode num: 96675, tedge num: 124648.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.954220s wall, 1.906250s user + 0.046875s system = 1.953125s CPU (99.9%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 614 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17500 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.061781s wall, 3.000000s user + 0.062500s system = 3.062500s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.05677e-05
+PHY-3002 : Step(288): len = 674842, overlap = 237.5
+PHY-3002 : Step(289): len = 668723, overlap = 234.75
+PHY-3002 : Step(290): len = 664670, overlap = 234.25
+PHY-3002 : Step(291): len = 661959, overlap = 236.5
+PHY-3002 : Step(292): len = 660261, overlap = 245.25
+PHY-3002 : Step(293): len = 658578, overlap = 246
+PHY-3002 : Step(294): len = 656491, overlap = 249
+PHY-3002 : Step(295): len = 653674, overlap = 255.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000101135
+PHY-3002 : Step(296): len = 657554, overlap = 241
+PHY-3002 : Step(297): len = 662159, overlap = 242.75
+PHY-3002 : Step(298): len = 663045, overlap = 239
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000202271
+PHY-3002 : Step(299): len = 674537, overlap = 219.75
+PHY-3002 : Step(300): len = 686952, overlap = 206.25
+PHY-3002 : Step(301): len = 685138, overlap = 209.25
+PHY-3002 : Step(302): len = 682986, overlap = 206.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.666051s wall, 0.484375s user + 0.593750s system = 1.078125s CPU (161.9%)
+
+PHY-3001 : Trial Legalized: Len = 763412
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 819/17678.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 883944, over cnt = 2803(7%), over = 4681, worst = 7
+PHY-1002 : len = 902888, over cnt = 1566(4%), over = 2258, worst = 7
+PHY-1002 : len = 918664, over cnt = 709(2%), over = 994, worst = 6
+PHY-1002 : len = 931248, over cnt = 178(0%), over = 249, worst = 5
+PHY-1002 : len = 935152, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.043492s wall, 4.250000s user + 0.031250s system = 4.281250s CPU (140.7%)
+
+PHY-1001 : Congestion index: top1 = 57.05, top5 = 51.09, top10 = 47.86, top15 = 45.85.
+PHY-3001 : End congestion estimation; 3.644818s wall, 4.843750s user + 0.031250s system = 4.875000s CPU (133.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17500 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.152817s wall, 1.046875s user + 0.046875s system = 1.093750s CPU (94.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000159824
+PHY-3002 : Step(303): len = 735175, overlap = 40.75
+PHY-3002 : Step(304): len = 719362, overlap = 68
+PHY-3002 : Step(305): len = 706347, overlap = 94
+PHY-3002 : Step(306): len = 698743, overlap = 118.25
+PHY-3002 : Step(307): len = 693833, overlap = 131
+PHY-3002 : Step(308): len = 691352, overlap = 137.5
+PHY-3002 : Step(309): len = 689901, overlap = 144
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000319648
+PHY-3002 : Step(310): len = 696642, overlap = 136.25
+PHY-3002 : Step(311): len = 705013, overlap = 135.25
+PHY-3002 : Step(312): len = 708888, overlap = 136.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000639295
+PHY-3002 : Step(313): len = 713358, overlap = 135
+PHY-3002 : Step(314): len = 725618, overlap = 132.25
+PHY-3002 : Step(315): len = 732670, overlap = 131.5
+PHY-3002 : Step(316): len = 733385, overlap = 134.5
+PHY-3002 : Step(317): len = 733737, overlap = 135
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.039898s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (117.5%)
+
+PHY-3001 : Legalized: Len = 760787, Over = 0
+PHY-3001 : Spreading special nets. 446 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.129639s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.4%)
+
+PHY-3001 : 663 instances has been re-located, deltaX = 206, deltaY = 420, maxDist = 4.
+PHY-3001 : Final: Len = 771909, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74272, tnet num: 17500, tinst num: 6716, tnode num: 96675, tedge num: 124648.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.209429s wall, 2.125000s user + 0.062500s system = 2.187500s CPU (99.0%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 607 MB, peak memory is 734 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3030/17678.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 905368, over cnt = 2610(7%), over = 4258, worst = 8
+PHY-1002 : len = 919304, over cnt = 1633(4%), over = 2381, worst = 6
+PHY-1002 : len = 934088, over cnt = 877(2%), over = 1247, worst = 6
+PHY-1002 : len = 944320, over cnt = 402(1%), over = 558, worst = 4
+PHY-1002 : len = 953584, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.904060s wall, 4.015625s user + 0.000000s system = 4.015625s CPU (138.3%)
+
+PHY-1001 : Congestion index: top1 = 57.74, top5 = 51.23, top10 = 47.95, top15 = 45.86.
+PHY-1001 : End incremental global routing; 3.405552s wall, 4.500000s user + 0.015625s system = 4.515625s CPU (132.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17500 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.109744s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.0%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6623 has valid locations, 23 needs to be replaced
+PHY-3001 : design contains 6734 instances, 6585 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3638 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 774193
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16114/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 955976, over cnt = 68(0%), over = 80, worst = 4
+PHY-1002 : len = 956072, over cnt = 23(0%), over = 26, worst = 2
+PHY-1002 : len = 956344, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 956360, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.883399s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (102.6%)
+
+PHY-1001 : Congestion index: top1 = 57.74, top5 = 51.20, top10 = 47.95, top15 = 45.90.
+PHY-3001 : End congestion estimation; 1.330562s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (102.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74438, tnet num: 17521, tinst num: 6734, tnode num: 96886, tedge num: 124853.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.152660s wall, 2.125000s user + 0.031250s system = 2.156250s CPU (100.2%)
+
+RUN-1004 : used memory is 663 MB, reserved memory is 671 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.279935s wall, 3.171875s user + 0.046875s system = 3.218750s CPU (98.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(318): len = 773718, overlap = 0
+PHY-3002 : Step(319): len = 773334, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16099/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 955000, over cnt = 66(0%), over = 93, worst = 7
+PHY-1002 : len = 955176, over cnt = 35(0%), over = 42, worst = 5
+PHY-1002 : len = 955376, over cnt = 20(0%), over = 22, worst = 2
+PHY-1002 : len = 955760, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 955856, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.996715s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (106.6%)
+
+PHY-1001 : Congestion index: top1 = 57.65, top5 = 51.10, top10 = 47.90, top15 = 45.85.
+PHY-3001 : End congestion estimation; 1.419170s wall, 1.468750s user + 0.000000s system = 1.468750s CPU (103.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.055049s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (93.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000252398
+PHY-3002 : Step(320): len = 773340, overlap = 1.75
+PHY-3002 : Step(321): len = 773410, overlap = 2
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.006319s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 773477, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.080245s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (97.4%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 5, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 773595, Over = 0
+PHY-3001 : End incremental placement; 7.774298s wall, 7.656250s user + 0.140625s system = 7.796875s CPU (100.3%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 12.914457s wall, 13.937500s user + 0.171875s system = 14.109375s CPU (109.3%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 739, peak = 741.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16085/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 955784, over cnt = 73(0%), over = 84, worst = 3
+PHY-1002 : len = 956032, over cnt = 21(0%), over = 21, worst = 1
+PHY-1002 : len = 956144, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 956208, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.771488s wall, 0.843750s user + 0.031250s system = 0.875000s CPU (113.4%)
+
+PHY-1001 : Congestion index: top1 = 57.59, top5 = 51.10, top10 = 47.88, top15 = 45.82.
+OPT-1001 : End congestion update; 1.209817s wall, 1.250000s user + 0.031250s system = 1.281250s CPU (105.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.861626s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.7%)
+
+OPT-0007 : Start: WNS -1083 TNS -1797 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6646 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6734 instances, 6585 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3638 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 777862, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.088911s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (87.9%)
+
+PHY-3001 : 17 instances has been re-located, deltaX = 8, deltaY = 12, maxDist = 2.
+PHY-3001 : Final: Len = 777864, Over = 0
+PHY-3001 : End incremental legalization; 0.573289s wall, 0.578125s user + 0.015625s system = 0.593750s CPU (103.6%)
+
+OPT-0007 : Iter 1: improved WNS -983 TNS -1518 NUM_FEPS 2 with 39 cells processed and 9517 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6646 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6734 instances, 6585 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3638 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 781216, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.081209s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (96.2%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 4, deltaY = 9, maxDist = 2.
+PHY-3001 : Final: Len = 781334, Over = 0
+PHY-3001 : End incremental legalization; 0.582251s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (99.3%)
+
+OPT-0007 : Iter 2: improved WNS -983 TNS -1518 NUM_FEPS 2 with 17 cells processed and 5737 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6646 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6734 instances, 6585 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3638 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 781204, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.079911s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (117.3%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 6, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 781356, Over = 0
+PHY-3001 : End incremental legalization; 0.564027s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (99.7%)
+
+OPT-0007 : Iter 3: improved WNS -983 TNS -1518 NUM_FEPS 2 with 6 cells processed and 100 slack improved
+OPT-1001 : End path based optimization; 4.371283s wall, 4.484375s user + 0.046875s system = 4.531250s CPU (103.7%)
+
+OPT-1001 : Current memory(MB): used = 737, reserve = 739, peak = 741.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.905946s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (96.6%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15864/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 963728, over cnt = 175(0%), over = 208, worst = 3
+PHY-1002 : len = 963888, over cnt = 87(0%), over = 99, worst = 3
+PHY-1002 : len = 964448, over cnt = 30(0%), over = 32, worst = 2
+PHY-1002 : len = 964928, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 964992, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.114350s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (102.4%)
+
+PHY-1001 : Congestion index: top1 = 56.23, top5 = 50.83, top10 = 47.77, top15 = 45.75.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.905661s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (98.3%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -1033 TNS -1618 NUM_FEPS 2
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 55.793103
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -1033ps with logic level 2
+RUN-1001 : #2 path slack -947ps with logic level 2
+RUN-1001 : 0 HFN exist on timing critical paths out of 17699 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 17699 nets
+OPT-1001 : End physical optimization; 23.332338s wall, 24.328125s user + 0.312500s system = 24.640625s CPU (105.6%)
+
+RUN-1003 : finish command "place" in 89.213464s wall, 115.500000s user + 7.546875s system = 123.046875s CPU (137.9%)
+
+RUN-1004 : used memory is 644 MB, reserved memory is 655 MB, peak memory is 741 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.832838s wall, 3.218750s user + 0.015625s system = 3.234375s CPU (176.5%)
+
+RUN-1004 : used memory is 645 MB, reserved memory is 656 MB, peak memory is 741 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6736 instances
+RUN-1001 : 3293 mslices, 3292 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17699 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10014 nets have 2 pins
+RUN-1001 : 5834 nets have [3 - 5] pins
+RUN-1001 : 1128 nets have [6 - 10] pins
+RUN-1001 : 341 nets have [11 - 20] pins
+RUN-1001 : 354 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74438, tnet num: 17521, tinst num: 6734, tnode num: 96886, tedge num: 124853.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.892112s wall, 1.890625s user + 0.000000s system = 1.890625s CPU (99.9%)
+
+RUN-1004 : used memory is 627 MB, reserved memory is 618 MB, peak memory is 741 MB
+PHY-1001 : 3293 mslices, 3292 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 897336, over cnt = 2798(7%), over = 4554, worst = 8
+PHY-1002 : len = 913064, over cnt = 1762(5%), over = 2578, worst = 7
+PHY-1002 : len = 930928, over cnt = 723(2%), over = 1104, worst = 6
+PHY-1002 : len = 948256, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 948352, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.861659s wall, 4.937500s user + 0.000000s system = 4.937500s CPU (127.9%)
+
+PHY-1001 : Congestion index: top1 = 57.07, top5 = 50.82, top10 = 47.63, top15 = 45.53.
+PHY-1001 : End global routing; 4.352013s wall, 5.375000s user + 0.000000s system = 5.375000s CPU (123.5%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 706, reserve = 709, peak = 741.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 982, reserve = 986, peak = 982.
+PHY-1001 : End build detailed router design. 4.753823s wall, 4.609375s user + 0.046875s system = 4.656250s CPU (97.9%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 272144, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 8.524998s wall, 8.328125s user + 0.000000s system = 8.328125s CPU (97.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 272200, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.808484s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (100.5%)
+
+PHY-1001 : Current memory(MB): used = 1017, reserve = 1022, peak = 1017.
+PHY-1001 : End phase 1; 9.355751s wall, 9.156250s user + 0.000000s system = 9.156250s CPU (97.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.41642e+06, over cnt = 1987(0%), over = 1991, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1035, reserve = 1039, peak = 1035.
+PHY-1001 : End initial routed; 56.062225s wall, 94.796875s user + 0.328125s system = 95.125000s CPU (169.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 30/16622(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -2.053 | -4.633 | 7
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 4.003597s wall, 3.984375s user + 0.000000s system = 3.984375s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1046, reserve = 1051, peak = 1046.
+PHY-1001 : End phase 2; 60.065890s wall, 98.781250s user + 0.328125s system = 99.109375s CPU (165.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 18 pins with SWNS -2.053ns STNS -3.957ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.294855s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (100.7%)
+
+PHY-1022 : len = 2.41658e+06, over cnt = 2006(0%), over = 2012, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.670108s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (100.3%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.38978e+06, over cnt = 947(0%), over = 950, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.579678s wall, 4.718750s user + 0.031250s system = 4.750000s CPU (184.1%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.3813e+06, over cnt = 216(0%), over = 216, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 2.308151s wall, 3.093750s user + 0.046875s system = 3.140625s CPU (136.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.38042e+06, over cnt = 32(0%), over = 32, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 1.023718s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (114.5%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.38082e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.703095s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (102.2%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.38086e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.373933s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.3%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.38086e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.877522s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.38084e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 1.867158s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (100.4%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.38086e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.245797s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (101.7%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.38086e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.246088s wall, 0.234375s user + 0.031250s system = 0.265625s CPU (107.9%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.38085e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.263165s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (95.0%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.38086e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.364533s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (102.9%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.38086e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.500501s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (99.9%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.38086e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.229357s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (95.4%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.38086e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.213881s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (102.3%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.38086e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.201615s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.38086e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.303395s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (103.0%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.38086e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.546474s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.38086e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 1.132216s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (52.4%)
+
+PHY-1001 : ===== DR Iter 19 =====
+PHY-1022 : len = 2.38086e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.224351s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (97.5%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.38078e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.224458s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (104.4%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.38079e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 21; 0.249375s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (100.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16622(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -2.053 | -3.957 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.961475s wall, 3.937500s user + 0.000000s system = 3.937500s CPU (99.4%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 714 feed throughs used by 507 nets
+PHY-1001 : End commit to database; 2.599328s wall, 2.578125s user + 0.031250s system = 2.609375s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1153, reserve = 1161, peak = 1153.
+PHY-1001 : End phase 3; 22.438647s wall, 24.921875s user + 0.140625s system = 25.062500s CPU (111.7%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -1.903ns STNS -3.807ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.172580s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.6%)
+
+PHY-1022 : len = 2.38076e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.530320s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (100.2%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.903ns, -3.807ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16622(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.903 | -3.807 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.895644s wall, 3.843750s user + 0.000000s system = 3.843750s CPU (98.7%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 716 feed throughs used by 509 nets
+PHY-1001 : End commit to database; 2.629360s wall, 2.625000s user + 0.000000s system = 2.625000s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1162, reserve = 1171, peak = 1162.
+PHY-1001 : End phase 4; 7.092335s wall, 7.031250s user + 0.000000s system = 7.031250s CPU (99.1%)
+
+PHY-1003 : Routed, final wirelength = 2.38076e+06
+PHY-1001 : Current memory(MB): used = 1164, reserve = 1172, peak = 1164.
+PHY-1001 : End export database. 0.078183s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (99.9%)
+
+PHY-1001 : End detail routing; 104.287159s wall, 145.062500s user + 0.531250s system = 145.593750s CPU (139.6%)
+
+RUN-1003 : finish command "route" in 111.934119s wall, 153.656250s user + 0.578125s system = 154.234375s CPU (137.8%)
+
+RUN-1004 : used memory is 1089 MB, reserved memory is 1098 MB, peak memory is 1164 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10357 out of 19600 52.84%
+#reg 9359 out of 19600 47.75%
+#le 12270
+ #lut only 2911 out of 12270 23.72%
+ #reg only 1913 out of 12270 15.59%
+ #lut® 7446 out of 12270 60.68%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1814
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1422
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1338
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 930
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 141
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 68
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 22
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_308.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg45_syn_187.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P140 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P4 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P138 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P16 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P156 LVCMOS33 8 N/A NONE
+ paper_out OUTPUT P15 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P17 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P107 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12270 |9330 |1027 |9390 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |539 |450 |23 |430 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |101 |81 |4 |90 |4 |0 |
+| U_crc16_24b |crc16_24b |39 |39 |0 |19 |0 |0 |
+| U_ecc_gen |ecc_gen |8 |8 |0 |7 |0 |0 |
+| exdev_ctl_a |exdev_ctl |785 |363 |96 |578 |0 |0 |
+| u_ADconfig |AD_config |193 |119 |25 |144 |0 |0 |
+| u_gen_sp |gen_sp |277 |177 |71 |119 |0 |0 |
+| exdev_ctl_b |exdev_ctl |755 |420 |96 |568 |0 |0 |
+| u_ADconfig |AD_config |183 |145 |25 |131 |0 |0 |
+| u_gen_sp |gen_sp |256 |160 |71 |121 |0 |0 |
+| sampling_fe_a |sampling_fe |2940 |2368 |306 |2045 |25 |0 |
+| u0_soft_n |cdc_sync |5 |2 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |174 |119 |17 |133 |0 |0 |
+| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u_sort |sort |2734 |2246 |289 |1880 |25 |0 |
+| rddpram_ctl |rddpram_ctl |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |7 |5 |0 |7 |0 |0 |
+| u0_wrsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2369 |1972 |253 |1571 |22 |0 |
+| channelPart |channel_part_8478 |147 |143 |3 |120 |0 |0 |
+| fifo_adc |fifo_adc |65 |56 |9 |40 |0 |0 |
+| ram_switch |ram_switch |1857 |1527 |197 |1188 |0 |0 |
+| adc_addr_gen |adc_addr_gen |245 |215 |27 |131 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |14 |8 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |29 |26 |3 |16 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |28 |25 |3 |17 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |27 |24 |3 |13 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 |
+| insert |insert |981 |683 |170 |674 |0 |0 |
+| ram_switch_state |ram_switch_state |631 |629 |0 |383 |0 |0 |
+| read_ram_i |read_ram |264 |216 |44 |187 |0 |0 |
+| read_ram_addr |read_ram_addr |213 |173 |40 |150 |0 |0 |
+| read_ram_data |read_ram_data |51 |43 |4 |37 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |323 |242 |36 |267 |3 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3122 |2511 |349 |2099 |25 |1 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |177 |130 |17 |140 |0 |0 |
+| u0_soft_n |cdc_sync |5 |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2915 |2361 |332 |1929 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |5 |3 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2496 |2028 |290 |1568 |22 |1 |
+| channelPart |channel_part_8478 |234 |231 |3 |138 |0 |0 |
+| fifo_adc |fifo_adc |62 |53 |9 |44 |0 |1 |
+| ram_switch |ram_switch |1809 |1451 |197 |1147 |0 |0 |
+| adc_addr_gen |adc_addr_gen |221 |193 |27 |118 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |15 |11 |3 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |27 |24 |3 |17 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |14 |11 |3 |7 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |23 |20 |3 |12 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |25 |22 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| insert |insert |995 |670 |170 |686 |0 |0 |
+| ram_switch_state |ram_switch_state |593 |588 |0 |343 |0 |0 |
+| read_ram_i |read_ram_rev |365 |270 |81 |213 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |286 |204 |73 |160 |0 |0 |
+| read_ram_data |read_ram_data_rev |79 |66 |8 |53 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9952
+ #2 2 3864
+ #3 3 1408
+ #4 4 559
+ #5 5-10 1194
+ #6 11-50 603
+ #7 51-100 23
+ #8 >500 1
+ Average 2.91
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.236276s wall, 3.890625s user + 0.031250s system = 3.921875s CPU (175.4%)
+
+RUN-1004 : used memory is 1090 MB, reserved memory is 1099 MB, peak memory is 1164 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74438, tnet num: 17521, tinst num: 6734, tnode num: 96886, tedge num: 124853.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.812210s wall, 1.796875s user + 0.000000s system = 1.796875s CPU (99.2%)
+
+RUN-1004 : used memory is 1095 MB, reserved memory is 1103 MB, peak memory is 1164 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.827945s wall, 1.781250s user + 0.031250s system = 1.812500s CPU (99.2%)
+
+RUN-1004 : used memory is 1098 MB, reserved memory is 1106 MB, peak memory is 1164 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6734
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17699, pip num: 176676
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 716
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3258 valid insts, and 487697 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 10.730589s wall, 60.453125s user + 0.187500s system = 60.640625s CPU (565.1%)
+
+RUN-1004 : used memory is 1266 MB, reserved memory is 1269 MB, peak memory is 1381 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240202_135725.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240218_154144.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240218_154144.log
new file mode 100644
index 0000000..f9eec1e
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240218_154144.log
@@ -0,0 +1,2028 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sun Feb 18 15:41:44 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.142105s wall, 2.062500s user + 0.078125s system = 2.140625s CPU (99.9%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 315 MB, peak memory is 341 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2945 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17703 instances
+RUN-0007 : 7440 luts, 9040 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20281 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13180 nets have 2 pins
+RUN-1001 : 5799 nets have [3 - 5] pins
+RUN-1001 : 882 nets have [6 - 10] pins
+RUN-1001 : 171 nets have [11 - 20] pins
+RUN-1001 : 175 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 789
+RUN-1001 : No | No | Yes | 1968
+RUN-1001 : No | Yes | No | 3474
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 56
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 141
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17701 instances, 7440 luts, 9040 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 5915 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84691, tnet num: 20103, tinst num: 17701, tnode num: 114767, tedge num: 135907.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.173196s wall, 1.140625s user + 0.031250s system = 1.171875s CPU (99.9%)
+
+RUN-1004 : used memory is 529 MB, reserved memory is 514 MB, peak memory is 529 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20103 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.958599s wall, 1.937500s user + 0.031250s system = 1.968750s CPU (100.5%)
+
+PHY-3001 : Found 1228 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 3.80961e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17701.
+PHY-3001 : Level 1 #clusters 2034.
+PHY-3001 : End clustering; 0.124361s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (138.2%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28216e+06, overlap = 479.625
+PHY-3002 : Step(2): len = 1.16629e+06, overlap = 466.594
+PHY-3002 : Step(3): len = 879184, overlap = 563.188
+PHY-3002 : Step(4): len = 778763, overlap = 603.531
+PHY-3002 : Step(5): len = 610007, overlap = 698.5
+PHY-3002 : Step(6): len = 553353, overlap = 793.531
+PHY-3002 : Step(7): len = 483397, overlap = 865.125
+PHY-3002 : Step(8): len = 428045, overlap = 948.875
+PHY-3002 : Step(9): len = 387650, overlap = 1027.94
+PHY-3002 : Step(10): len = 347429, overlap = 1091.44
+PHY-3002 : Step(11): len = 320060, overlap = 1115.94
+PHY-3002 : Step(12): len = 291839, overlap = 1155.03
+PHY-3002 : Step(13): len = 261286, overlap = 1162.31
+PHY-3002 : Step(14): len = 241329, overlap = 1257.91
+PHY-3002 : Step(15): len = 218162, overlap = 1327.19
+PHY-3002 : Step(16): len = 201977, overlap = 1380.91
+PHY-3002 : Step(17): len = 188610, overlap = 1409.34
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.17875e-06
+PHY-3002 : Step(18): len = 192522, overlap = 1393.97
+PHY-3002 : Step(19): len = 219286, overlap = 1267.19
+PHY-3002 : Step(20): len = 216608, overlap = 1219.03
+PHY-3002 : Step(21): len = 221491, overlap = 1189.69
+PHY-3002 : Step(22): len = 217335, overlap = 1176.91
+PHY-3002 : Step(23): len = 213907, overlap = 1169
+PHY-3002 : Step(24): len = 207477, overlap = 1155.03
+PHY-3002 : Step(25): len = 204839, overlap = 1121.84
+PHY-3002 : Step(26): len = 201758, overlap = 1095.22
+PHY-3002 : Step(27): len = 199103, overlap = 1074.72
+PHY-3002 : Step(28): len = 195864, overlap = 1068.25
+PHY-3002 : Step(29): len = 194181, overlap = 1056.53
+PHY-3002 : Step(30): len = 190914, overlap = 1055.34
+PHY-3002 : Step(31): len = 190364, overlap = 1063.09
+PHY-3002 : Step(32): len = 189352, overlap = 1080.78
+PHY-3002 : Step(33): len = 188271, overlap = 1086.03
+PHY-3002 : Step(34): len = 187676, overlap = 1096.19
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.35749e-06
+PHY-3002 : Step(35): len = 191338, overlap = 1089.16
+PHY-3002 : Step(36): len = 206908, overlap = 1048.03
+PHY-3002 : Step(37): len = 212447, overlap = 1036.25
+PHY-3002 : Step(38): len = 216650, overlap = 1013.75
+PHY-3002 : Step(39): len = 217121, overlap = 1007.72
+PHY-3002 : Step(40): len = 218523, overlap = 984.438
+PHY-3002 : Step(41): len = 218264, overlap = 975.406
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.71498e-06
+PHY-3002 : Step(42): len = 226950, overlap = 968.812
+PHY-3002 : Step(43): len = 245710, overlap = 872.906
+PHY-3002 : Step(44): len = 257664, overlap = 797.438
+PHY-3002 : Step(45): len = 266586, overlap = 762.031
+PHY-3002 : Step(46): len = 271617, overlap = 731.906
+PHY-3002 : Step(47): len = 274607, overlap = 691.5
+PHY-3002 : Step(48): len = 276377, overlap = 653.438
+PHY-3002 : Step(49): len = 276817, overlap = 646.938
+PHY-3002 : Step(50): len = 276581, overlap = 660.125
+PHY-3002 : Step(51): len = 276637, overlap = 682.438
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.42996e-06
+PHY-3002 : Step(52): len = 292794, overlap = 631.031
+PHY-3002 : Step(53): len = 315192, overlap = 541.281
+PHY-3002 : Step(54): len = 325580, overlap = 488.906
+PHY-3002 : Step(55): len = 330349, overlap = 470.656
+PHY-3002 : Step(56): len = 330984, overlap = 479.5
+PHY-3002 : Step(57): len = 329740, overlap = 469.5
+PHY-3002 : Step(58): len = 328432, overlap = 476.188
+PHY-3002 : Step(59): len = 329101, overlap = 476
+PHY-3002 : Step(60): len = 327860, overlap = 473.656
+PHY-3002 : Step(61): len = 327626, overlap = 460.375
+PHY-3002 : Step(62): len = 326421, overlap = 465.219
+PHY-3002 : Step(63): len = 326449, overlap = 460.844
+PHY-3002 : Step(64): len = 325947, overlap = 463.781
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.88599e-05
+PHY-3002 : Step(65): len = 345594, overlap = 405.844
+PHY-3002 : Step(66): len = 358504, overlap = 380.375
+PHY-3002 : Step(67): len = 361349, overlap = 342.25
+PHY-3002 : Step(68): len = 363338, overlap = 326.031
+PHY-3002 : Step(69): len = 363377, overlap = 309.844
+PHY-3002 : Step(70): len = 364627, overlap = 326.219
+PHY-3002 : Step(71): len = 365087, overlap = 328.219
+PHY-3002 : Step(72): len = 365792, overlap = 333.594
+PHY-3002 : Step(73): len = 364897, overlap = 330.188
+PHY-3002 : Step(74): len = 365206, overlap = 329.875
+PHY-3002 : Step(75): len = 363871, overlap = 332.094
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.77199e-05
+PHY-3002 : Step(76): len = 383140, overlap = 311.875
+PHY-3002 : Step(77): len = 395177, overlap = 289.969
+PHY-3002 : Step(78): len = 395172, overlap = 281.938
+PHY-3002 : Step(79): len = 396342, overlap = 263.188
+PHY-3002 : Step(80): len = 399773, overlap = 272.594
+PHY-3002 : Step(81): len = 403999, overlap = 252.812
+PHY-3002 : Step(82): len = 402545, overlap = 237.156
+PHY-3002 : Step(83): len = 402877, overlap = 213.281
+PHY-3002 : Step(84): len = 404121, overlap = 220.188
+PHY-3002 : Step(85): len = 405404, overlap = 208.75
+PHY-3002 : Step(86): len = 404198, overlap = 210.375
+PHY-3002 : Step(87): len = 404719, overlap = 206.062
+PHY-3002 : Step(88): len = 405666, overlap = 203.531
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.54397e-05
+PHY-3002 : Step(89): len = 422768, overlap = 199
+PHY-3002 : Step(90): len = 433682, overlap = 201.625
+PHY-3002 : Step(91): len = 431641, overlap = 196.031
+PHY-3002 : Step(92): len = 430725, overlap = 188.062
+PHY-3002 : Step(93): len = 432978, overlap = 187.25
+PHY-3002 : Step(94): len = 435457, overlap = 191.875
+PHY-3002 : Step(95): len = 433279, overlap = 195.875
+PHY-3002 : Step(96): len = 435016, overlap = 188.656
+PHY-3002 : Step(97): len = 438049, overlap = 188.688
+PHY-3002 : Step(98): len = 438940, overlap = 184.656
+PHY-3002 : Step(99): len = 437194, overlap = 189.844
+PHY-3002 : Step(100): len = 437650, overlap = 189.219
+PHY-3002 : Step(101): len = 438669, overlap = 183.594
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000150879
+PHY-3002 : Step(102): len = 451568, overlap = 191.656
+PHY-3002 : Step(103): len = 458537, overlap = 182.375
+PHY-3002 : Step(104): len = 458416, overlap = 164.906
+PHY-3002 : Step(105): len = 459084, overlap = 159.875
+PHY-3002 : Step(106): len = 460562, overlap = 160.438
+PHY-3002 : Step(107): len = 461926, overlap = 168.562
+PHY-3002 : Step(108): len = 460202, overlap = 162.594
+PHY-3002 : Step(109): len = 461085, overlap = 163.625
+PHY-3002 : Step(110): len = 463855, overlap = 157.969
+PHY-3002 : Step(111): len = 466293, overlap = 153.281
+PHY-3002 : Step(112): len = 465161, overlap = 163.906
+PHY-3002 : Step(113): len = 465966, overlap = 159.062
+PHY-3002 : Step(114): len = 468286, overlap = 147.875
+PHY-3002 : Step(115): len = 469272, overlap = 143.812
+PHY-3002 : Step(116): len = 467852, overlap = 146.781
+PHY-3002 : Step(117): len = 468130, overlap = 146.781
+PHY-3002 : Step(118): len = 470349, overlap = 145.562
+PHY-3002 : Step(119): len = 471970, overlap = 149.188
+PHY-3002 : Step(120): len = 470240, overlap = 150.781
+PHY-3002 : Step(121): len = 470218, overlap = 152.906
+PHY-3002 : Step(122): len = 471502, overlap = 158.875
+PHY-3002 : Step(123): len = 472437, overlap = 157
+PHY-3002 : Step(124): len = 471668, overlap = 161.594
+PHY-3002 : Step(125): len = 471740, overlap = 160.219
+PHY-3002 : Step(126): len = 472430, overlap = 161.719
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000301759
+PHY-3002 : Step(127): len = 481561, overlap = 157.75
+PHY-3002 : Step(128): len = 491291, overlap = 148.5
+PHY-3002 : Step(129): len = 495046, overlap = 138.031
+PHY-3002 : Step(130): len = 496710, overlap = 134.188
+PHY-3002 : Step(131): len = 498607, overlap = 129.844
+PHY-3002 : Step(132): len = 499874, overlap = 130.438
+PHY-3002 : Step(133): len = 498023, overlap = 130.094
+PHY-3002 : Step(134): len = 497863, overlap = 133
+PHY-3002 : Step(135): len = 499555, overlap = 133
+PHY-3002 : Step(136): len = 500548, overlap = 124.969
+PHY-3002 : Step(137): len = 499129, overlap = 125.719
+PHY-3002 : Step(138): len = 498751, overlap = 127
+PHY-3002 : Step(139): len = 499579, overlap = 130.312
+PHY-3002 : Step(140): len = 500234, overlap = 129.875
+PHY-3002 : Step(141): len = 499512, overlap = 130.406
+PHY-3002 : Step(142): len = 499876, overlap = 132.219
+PHY-3002 : Step(143): len = 501054, overlap = 132.281
+PHY-3002 : Step(144): len = 501728, overlap = 135.094
+PHY-3002 : Step(145): len = 500931, overlap = 129.344
+PHY-3002 : Step(146): len = 500875, overlap = 130.469
+PHY-3002 : Step(147): len = 501276, overlap = 127.719
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000595753
+PHY-3002 : Step(148): len = 508170, overlap = 120.156
+PHY-3002 : Step(149): len = 513247, overlap = 115.562
+PHY-3002 : Step(150): len = 513677, overlap = 112.656
+PHY-3002 : Step(151): len = 514601, overlap = 115.906
+PHY-3002 : Step(152): len = 515876, overlap = 109.062
+PHY-3002 : Step(153): len = 517064, overlap = 110.969
+PHY-3002 : Step(154): len = 517158, overlap = 109.438
+PHY-3002 : Step(155): len = 517550, overlap = 115.094
+PHY-3002 : Step(156): len = 518867, overlap = 109.156
+PHY-3002 : Step(157): len = 519944, overlap = 101.531
+PHY-3002 : Step(158): len = 519809, overlap = 102.156
+PHY-3002 : Step(159): len = 519917, overlap = 104.344
+PHY-3002 : Step(160): len = 519662, overlap = 104.531
+PHY-3002 : Step(161): len = 519991, overlap = 106
+PHY-3002 : Step(162): len = 520598, overlap = 107.938
+PHY-3002 : Step(163): len = 521229, overlap = 101.469
+PHY-3002 : Step(164): len = 520862, overlap = 102.031
+PHY-3002 : Step(165): len = 520876, overlap = 102.094
+PHY-3002 : Step(166): len = 520991, overlap = 99.8438
+PHY-3002 : Step(167): len = 521046, overlap = 102.344
+PHY-3002 : Step(168): len = 520694, overlap = 104.531
+PHY-3002 : Step(169): len = 521123, overlap = 105.562
+PHY-3002 : Step(170): len = 521670, overlap = 103.312
+PHY-3002 : Step(171): len = 521936, overlap = 103.594
+PHY-3002 : Step(172): len = 521952, overlap = 101.719
+PHY-3002 : Step(173): len = 522327, overlap = 104.531
+PHY-3002 : Step(174): len = 522609, overlap = 104.156
+PHY-3002 : Step(175): len = 522585, overlap = 104.156
+PHY-3002 : Step(176): len = 521950, overlap = 103.969
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00101933
+PHY-3002 : Step(177): len = 524620, overlap = 106.344
+PHY-3002 : Step(178): len = 527198, overlap = 104.719
+PHY-3002 : Step(179): len = 528003, overlap = 102.719
+PHY-3002 : Step(180): len = 528529, overlap = 101.5
+PHY-3002 : Step(181): len = 529519, overlap = 101.969
+PHY-3002 : Step(182): len = 529809, overlap = 102
+PHY-3002 : Step(183): len = 529605, overlap = 102.531
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.022690s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (68.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20281.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 683856, over cnt = 1540(4%), over = 6849, worst = 32
+PHY-1001 : End global iterations; 0.735224s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (123.3%)
+
+PHY-1001 : Congestion index: top1 = 72.93, top5 = 56.93, top10 = 49.43, top15 = 44.73.
+PHY-3001 : End congestion estimation; 0.992063s wall, 1.125000s user + 0.031250s system = 1.156250s CPU (116.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20103 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.829601s wall, 0.796875s user + 0.031250s system = 0.828125s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000117893
+PHY-3002 : Step(184): len = 619912, overlap = 37.3125
+PHY-3002 : Step(185): len = 625258, overlap = 40.3438
+PHY-3002 : Step(186): len = 619999, overlap = 41.1875
+PHY-3002 : Step(187): len = 618039, overlap = 46.5
+PHY-3002 : Step(188): len = 619855, overlap = 48.0625
+PHY-3002 : Step(189): len = 617680, overlap = 44.5625
+PHY-3002 : Step(190): len = 615660, overlap = 44.2812
+PHY-3002 : Step(191): len = 615121, overlap = 38.375
+PHY-3002 : Step(192): len = 613095, overlap = 32.5625
+PHY-3002 : Step(193): len = 612369, overlap = 32.7812
+PHY-3002 : Step(194): len = 609716, overlap = 31.7812
+PHY-3002 : Step(195): len = 608656, overlap = 30.7188
+PHY-3002 : Step(196): len = 606789, overlap = 31.4062
+PHY-3002 : Step(197): len = 606288, overlap = 31.5938
+PHY-3002 : Step(198): len = 604330, overlap = 28.7188
+PHY-3002 : Step(199): len = 603101, overlap = 25.875
+PHY-3002 : Step(200): len = 601975, overlap = 24.9062
+PHY-3002 : Step(201): len = 601508, overlap = 23.7188
+PHY-3002 : Step(202): len = 601148, overlap = 23.3125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000235786
+PHY-3002 : Step(203): len = 602900, overlap = 22.1875
+PHY-3002 : Step(204): len = 605450, overlap = 21.625
+PHY-3002 : Step(205): len = 610775, overlap = 20.875
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000463887
+PHY-3002 : Step(206): len = 619828, overlap = 19.5625
+PHY-3002 : Step(207): len = 630216, overlap = 18.0312
+PHY-3002 : Step(208): len = 635697, overlap = 17.0938
+PHY-3002 : Step(209): len = 638971, overlap = 16.0625
+PHY-3002 : Step(210): len = 643006, overlap = 15.0312
+PHY-3002 : Step(211): len = 644334, overlap = 13.4062
+PHY-3002 : Step(212): len = 646449, overlap = 14
+PHY-3002 : Step(213): len = 648472, overlap = 12.4375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 73/20281.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 735472, over cnt = 2714(7%), over = 12154, worst = 36
+PHY-1001 : End global iterations; 1.620831s wall, 2.218750s user + 0.031250s system = 2.250000s CPU (138.8%)
+
+PHY-1001 : Congestion index: top1 = 80.47, top5 = 65.06, top10 = 57.39, top15 = 52.62.
+PHY-3001 : End congestion estimation; 1.889132s wall, 2.468750s user + 0.046875s system = 2.515625s CPU (133.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20103 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.914317s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000126876
+PHY-3002 : Step(214): len = 641840, overlap = 242.125
+PHY-3002 : Step(215): len = 643778, overlap = 194.875
+PHY-3002 : Step(216): len = 636240, overlap = 186.906
+PHY-3002 : Step(217): len = 631784, overlap = 173.156
+PHY-3002 : Step(218): len = 627649, overlap = 166.156
+PHY-3002 : Step(219): len = 625175, overlap = 157.625
+PHY-3002 : Step(220): len = 620478, overlap = 156.344
+PHY-3002 : Step(221): len = 617497, overlap = 143.594
+PHY-3002 : Step(222): len = 614855, overlap = 138.469
+PHY-3002 : Step(223): len = 610915, overlap = 137.188
+PHY-3002 : Step(224): len = 608956, overlap = 135.125
+PHY-3002 : Step(225): len = 606719, overlap = 138.219
+PHY-3002 : Step(226): len = 603712, overlap = 136.312
+PHY-3002 : Step(227): len = 602610, overlap = 126.375
+PHY-3002 : Step(228): len = 599637, overlap = 126.562
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000253752
+PHY-3002 : Step(229): len = 601163, overlap = 119.375
+PHY-3002 : Step(230): len = 602373, overlap = 117.344
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84691, tnet num: 20103, tinst num: 17701, tnode num: 114767, tedge num: 135907.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.420815s wall, 1.359375s user + 0.062500s system = 1.421875s CPU (100.1%)
+
+RUN-1004 : used memory is 575 MB, reserved memory is 564 MB, peak memory is 709 MB
+OPT-1001 : Total overflow 449.03 peak overflow 8.34
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 857/20281.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 699552, over cnt = 2835(8%), over = 10043, worst = 25
+PHY-1001 : End global iterations; 1.257309s wall, 1.765625s user + 0.015625s system = 1.781250s CPU (141.7%)
+
+PHY-1001 : Congestion index: top1 = 66.31, top5 = 55.55, top10 = 50.15, top15 = 46.60.
+PHY-1001 : End incremental global routing; 1.584568s wall, 2.078125s user + 0.015625s system = 2.093750s CPU (132.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20103 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.016175s wall, 0.984375s user + 0.031250s system = 1.015625s CPU (99.9%)
+
+OPT-1001 : 49 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17567 has valid locations, 322 needs to be replaced
+PHY-3001 : design contains 17974 instances, 7534 luts, 9219 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 6039 pins
+PHY-3001 : Found 1242 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 625679
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16052/20554.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 714888, over cnt = 2876(8%), over = 10033, worst = 26
+PHY-1001 : End global iterations; 0.238854s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (150.5%)
+
+PHY-1001 : Congestion index: top1 = 66.66, top5 = 55.46, top10 = 50.11, top15 = 46.70.
+PHY-3001 : End congestion estimation; 0.481612s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (123.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85780, tnet num: 20376, tinst num: 17974, tnode num: 116409, tedge num: 137539.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.417373s wall, 1.375000s user + 0.046875s system = 1.421875s CPU (100.3%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 624 MB, peak memory is 712 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20376 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.342310s wall, 2.296875s user + 0.046875s system = 2.343750s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(231): len = 624841, overlap = 1.84375
+PHY-3002 : Step(232): len = 624485, overlap = 1.875
+PHY-3002 : Step(233): len = 624208, overlap = 1.9375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16167/20554.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 712584, over cnt = 2884(8%), over = 10123, worst = 26
+PHY-1001 : End global iterations; 0.195509s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (119.9%)
+
+PHY-1001 : Congestion index: top1 = 67.16, top5 = 55.92, top10 = 50.46, top15 = 46.96.
+PHY-3001 : End congestion estimation; 0.447302s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (111.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20376 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.899527s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (99.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000234242
+PHY-3002 : Step(234): len = 624067, overlap = 118.844
+PHY-3002 : Step(235): len = 624142, overlap = 118.875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000468484
+PHY-3002 : Step(236): len = 624150, overlap = 119.438
+PHY-3002 : Step(237): len = 624515, overlap = 119.781
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000936969
+PHY-3002 : Step(238): len = 624747, overlap = 119.469
+PHY-3002 : Step(239): len = 625394, overlap = 119.125
+PHY-3001 : Final: Len = 625394, Over = 119.125
+PHY-3001 : End incremental placement; 4.868718s wall, 5.000000s user + 0.281250s system = 5.281250s CPU (108.5%)
+
+OPT-1001 : Total overflow 455.03 peak overflow 8.34
+OPT-1001 : End high-fanout net optimization; 8.026133s wall, 8.718750s user + 0.328125s system = 9.046875s CPU (112.7%)
+
+OPT-1001 : Current memory(MB): used = 715, reserve = 710, peak = 732.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16083/20554.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 715384, over cnt = 2806(7%), over = 9025, worst = 25
+PHY-1002 : len = 749816, over cnt = 2175(6%), over = 5692, worst = 18
+PHY-1002 : len = 797800, over cnt = 922(2%), over = 2171, worst = 15
+PHY-1002 : len = 829904, over cnt = 103(0%), over = 176, worst = 10
+PHY-1002 : len = 833304, over cnt = 8(0%), over = 8, worst = 1
+PHY-1001 : End global iterations; 1.711902s wall, 2.296875s user + 0.015625s system = 2.312500s CPU (135.1%)
+
+PHY-1001 : Congestion index: top1 = 56.66, top5 = 49.86, top10 = 46.49, top15 = 44.26.
+OPT-1001 : End congestion update; 1.962362s wall, 2.546875s user + 0.015625s system = 2.562500s CPU (130.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20376 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.772777s wall, 0.734375s user + 0.015625s system = 0.750000s CPU (97.1%)
+
+OPT-0007 : Start: WNS -1068 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 69 cells processed and 4172 slack improved
+OPT-0007 : Iter 2: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 37 cells processed and 2642 slack improved
+OPT-0007 : Iter 3: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 18 cells processed and 1540 slack improved
+OPT-0007 : Iter 4: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 8 cells processed and 700 slack improved
+OPT-1001 : End global optimization; 2.774158s wall, 3.328125s user + 0.031250s system = 3.359375s CPU (121.1%)
+
+OPT-1001 : Current memory(MB): used = 693, reserve = 690, peak = 732.
+OPT-1001 : End physical optimization; 12.926119s wall, 14.109375s user + 0.437500s system = 14.546875s CPU (112.5%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7534 LUT to BLE ...
+SYN-4008 : Packed 7534 LUT and 3081 SEQ to BLE.
+SYN-4003 : Packing 6138 remaining SEQ's ...
+SYN-4005 : Packed 3728 SEQ with LUT/SLICE
+SYN-4006 : 1033 single LUT's are left
+SYN-4006 : 2410 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9944/13675 primitive instances ...
+PHY-3001 : End packing; 1.592357s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (100.1%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6908 instances
+RUN-1001 : 3380 mslices, 3380 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17605 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9882 nets have 2 pins
+RUN-1001 : 6039 nets have [3 - 5] pins
+RUN-1001 : 996 nets have [6 - 10] pins
+RUN-1001 : 319 nets have [11 - 20] pins
+RUN-1001 : 336 nets have [21 - 99] pins
+RUN-1001 : 13 nets have 100+ pins
+PHY-3001 : design contains 6906 instances, 6760 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3598 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 639903, Over = 311.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7236/17605.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 789120, over cnt = 1925(5%), over = 3253, worst = 8
+PHY-1002 : len = 798072, over cnt = 1216(3%), over = 1800, worst = 7
+PHY-1002 : len = 811296, over cnt = 503(1%), over = 716, worst = 6
+PHY-1002 : len = 820752, over cnt = 125(0%), over = 177, worst = 6
+PHY-1002 : len = 824224, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.588180s wall, 2.187500s user + 0.062500s system = 2.250000s CPU (141.7%)
+
+PHY-1001 : Congestion index: top1 = 57.07, top5 = 50.13, top10 = 46.41, top15 = 44.00.
+PHY-3001 : End congestion estimation; 1.964790s wall, 2.562500s user + 0.062500s system = 2.625000s CPU (133.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74010, tnet num: 17427, tinst num: 6906, tnode num: 96499, tedge num: 124264.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.593000s wall, 1.578125s user + 0.015625s system = 1.593750s CPU (100.0%)
+
+RUN-1004 : used memory is 605 MB, reserved memory is 604 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17427 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.436982s wall, 2.421875s user + 0.015625s system = 2.437500s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.06879e-05
+PHY-3002 : Step(240): len = 631140, overlap = 311.75
+PHY-3002 : Step(241): len = 627745, overlap = 297.5
+PHY-3002 : Step(242): len = 626822, overlap = 291.5
+PHY-3002 : Step(243): len = 626753, overlap = 288.75
+PHY-3002 : Step(244): len = 626765, overlap = 289
+PHY-3002 : Step(245): len = 625140, overlap = 294.75
+PHY-3002 : Step(246): len = 623501, overlap = 289.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.13758e-05
+PHY-3002 : Step(247): len = 625054, overlap = 285.75
+PHY-3002 : Step(248): len = 628153, overlap = 280.5
+PHY-3002 : Step(249): len = 629867, overlap = 274.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000162752
+PHY-3002 : Step(250): len = 636527, overlap = 270.25
+PHY-3002 : Step(251): len = 646126, overlap = 260.75
+PHY-3002 : Step(252): len = 647192, overlap = 257
+PHY-3002 : Step(253): len = 648901, overlap = 249.75
+PHY-3002 : Step(254): len = 650656, overlap = 243.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.341697s wall, 0.328125s user + 0.500000s system = 0.828125s CPU (242.4%)
+
+PHY-3001 : Trial Legalized: Len = 743394
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 860/17605.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 863992, over cnt = 2790(7%), over = 4770, worst = 9
+PHY-1002 : len = 879488, over cnt = 1790(5%), over = 2791, worst = 9
+PHY-1002 : len = 898056, over cnt = 932(2%), over = 1462, worst = 9
+PHY-1002 : len = 915752, over cnt = 266(0%), over = 437, worst = 5
+PHY-1002 : len = 922712, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.175131s wall, 3.343750s user + 0.015625s system = 3.359375s CPU (154.4%)
+
+PHY-1001 : Congestion index: top1 = 55.62, top5 = 50.45, top10 = 47.79, top15 = 45.92.
+PHY-3001 : End congestion estimation; 2.629658s wall, 3.796875s user + 0.015625s system = 3.812500s CPU (145.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17427 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.852308s wall, 0.828125s user + 0.031250s system = 0.859375s CPU (100.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000164287
+PHY-3002 : Step(255): len = 712986, overlap = 53.5
+PHY-3002 : Step(256): len = 696944, overlap = 79.75
+PHY-3002 : Step(257): len = 682333, overlap = 116
+PHY-3002 : Step(258): len = 674623, overlap = 137.75
+PHY-3002 : Step(259): len = 668996, overlap = 153.25
+PHY-3002 : Step(260): len = 665196, overlap = 165.5
+PHY-3002 : Step(261): len = 663411, overlap = 179.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000328575
+PHY-3002 : Step(262): len = 669297, overlap = 175.25
+PHY-3002 : Step(263): len = 675703, overlap = 176
+PHY-3002 : Step(264): len = 679816, overlap = 173.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00065715
+PHY-3002 : Step(265): len = 684396, overlap = 170
+PHY-3002 : Step(266): len = 694418, overlap = 160.25
+PHY-3002 : Step(267): len = 698782, overlap = 155
+PHY-3002 : Step(268): len = 701898, overlap = 155.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.034720s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (90.0%)
+
+PHY-3001 : Legalized: Len = 730065, Over = 0
+PHY-3001 : Spreading special nets. 447 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.103485s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (105.7%)
+
+PHY-3001 : 660 instances has been re-located, deltaX = 210, deltaY = 407, maxDist = 2.
+PHY-3001 : Final: Len = 740629, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74010, tnet num: 17427, tinst num: 6909, tnode num: 96499, tedge num: 124264.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.823869s wall, 1.781250s user + 0.046875s system = 1.828125s CPU (100.2%)
+
+RUN-1004 : used memory is 622 MB, reserved memory is 639 MB, peak memory is 732 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3203/17605.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874136, over cnt = 2608(7%), over = 4302, worst = 9
+PHY-1002 : len = 888584, over cnt = 1473(4%), over = 2234, worst = 7
+PHY-1002 : len = 905280, over cnt = 568(1%), over = 888, worst = 7
+PHY-1002 : len = 919032, over cnt = 51(0%), over = 69, worst = 5
+PHY-1002 : len = 920176, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.966731s wall, 2.984375s user + 0.000000s system = 2.984375s CPU (151.7%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.41, top10 = 46.68, top15 = 44.80.
+PHY-1001 : End incremental global routing; 2.337952s wall, 3.359375s user + 0.000000s system = 3.359375s CPU (143.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17427 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.854225s wall, 0.812500s user + 0.031250s system = 0.843750s CPU (98.8%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6816 has valid locations, 26 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 744426
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16034/17630.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 924200, over cnt = 82(0%), over = 95, worst = 3
+PHY-1002 : len = 924280, over cnt = 38(0%), over = 39, worst = 2
+PHY-1002 : len = 924576, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 924704, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 924736, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.761352s wall, 0.843750s user + 0.046875s system = 0.890625s CPU (117.0%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.39, top10 = 46.67, top15 = 44.80.
+PHY-3001 : End congestion estimation; 1.091175s wall, 1.140625s user + 0.062500s system = 1.203125s CPU (110.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74216, tnet num: 17452, tinst num: 6930, tnode num: 96760, tedge num: 124559.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.843879s wall, 1.843750s user + 0.000000s system = 1.843750s CPU (100.0%)
+
+RUN-1004 : used memory is 659 MB, reserved memory is 664 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.715970s wall, 2.703125s user + 0.015625s system = 2.718750s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(269): len = 743276, overlap = 0
+PHY-3002 : Step(270): len = 742723, overlap = 0
+PHY-3002 : Step(271): len = 742706, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16022/17630.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 921320, over cnt = 94(0%), over = 112, worst = 5
+PHY-1002 : len = 921496, over cnt = 44(0%), over = 48, worst = 4
+PHY-1002 : len = 922000, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 922184, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.595777s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (110.2%)
+
+PHY-1001 : Congestion index: top1 = 55.04, top5 = 49.39, top10 = 46.68, top15 = 44.83.
+PHY-3001 : End congestion estimation; 0.898601s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (106.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.840088s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00045968
+PHY-3002 : Step(272): len = 742691, overlap = 1.75
+PHY-3002 : Step(273): len = 742734, overlap = 1.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005581s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (280.0%)
+
+PHY-3001 : Legalized: Len = 742783, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059742s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.6%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 4, deltaY = 0, maxDist = 2.
+PHY-3001 : Final: Len = 742827, Over = 0
+PHY-3001 : End incremental placement; 6.048161s wall, 6.203125s user + 0.171875s system = 6.375000s CPU (105.4%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.724569s wall, 10.859375s user + 0.203125s system = 11.062500s CPU (113.8%)
+
+OPT-1001 : Current memory(MB): used = 742, reserve = 743, peak = 746.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16016/17630.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 922168, over cnt = 57(0%), over = 74, worst = 4
+PHY-1002 : len = 922344, over cnt = 24(0%), over = 27, worst = 2
+PHY-1002 : len = 922616, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 922736, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 922752, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.755695s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (97.2%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.38, top10 = 46.62, top15 = 44.79.
+OPT-1001 : End congestion update; 1.054105s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (99.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.691633s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (99.4%)
+
+OPT-0007 : Start: WNS -1086 TNS -1721 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 746757, Over = 0
+PHY-3001 : Spreading special nets. 28 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059766s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.6%)
+
+PHY-3001 : 35 instances has been re-located, deltaX = 19, deltaY = 20, maxDist = 6.
+PHY-3001 : Final: Len = 747093, Over = 0
+PHY-3001 : End incremental legalization; 0.373001s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.5%)
+
+OPT-0007 : Iter 1: improved WNS -986 TNS -1521 NUM_FEPS 2 with 53 cells processed and 9773 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747839, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057260s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (109.2%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 9, deltaY = 10, maxDist = 5.
+PHY-3001 : Final: Len = 747939, Over = 0
+PHY-3001 : End incremental legalization; 0.377466s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.3%)
+
+OPT-0007 : Iter 2: improved WNS -936 TNS -1471 NUM_FEPS 2 with 20 cells processed and 1573 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 748129, Over = 0
+PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058468s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (80.2%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 12, deltaY = 7, maxDist = 7.
+PHY-3001 : Final: Len = 747949, Over = 0
+PHY-3001 : End incremental legalization; 0.372248s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.7%)
+
+OPT-0007 : Iter 3: improved WNS -936 TNS -1471 NUM_FEPS 2 with 15 cells processed and 349 slack improved
+OPT-1001 : End path based optimization; 3.305753s wall, 3.390625s user + 0.000000s system = 3.390625s CPU (102.6%)
+
+OPT-1001 : Current memory(MB): used = 742, reserve = 743, peak = 746.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.695832s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (101.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15705/17630.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 926848, over cnt = 191(0%), over = 258, worst = 4
+PHY-1002 : len = 927192, over cnt = 104(0%), over = 111, worst = 2
+PHY-1002 : len = 927784, over cnt = 33(0%), over = 34, worst = 2
+PHY-1002 : len = 928328, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 928456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.875775s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (103.5%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.55, top10 = 46.70, top15 = 44.82.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.694579s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (101.2%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -986 TNS -1571 NUM_FEPS 2
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.482759
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -986ps with logic level 2
+RUN-1001 : #2 path slack -940ps with logic level 2
+RUN-1001 : extra opt step will be enabled to improve QoR
+RUN-1001 : 0 HFN exist on timing critical paths out of 17630 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 17630 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747949, Over = 0
+PHY-3001 : End spreading; 0.057870s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (81.0%)
+
+PHY-3001 : Final: Len = 747949, Over = 0
+PHY-3001 : End incremental legalization; 0.378359s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (111.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.696630s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.9%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16057/17630.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.124084s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (100.7%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.55, top10 = 46.70, top15 = 44.82.
+OPT-1001 : End congestion update; 0.423038s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.691596s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (99.4%)
+
+OPT-0007 : Start: WNS -986 TNS -1571 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747889, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059032s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.9%)
+
+PHY-3001 : 3 instances has been re-located, deltaX = 3, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 747949, Over = 0
+PHY-3001 : End incremental legalization; 0.377211s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.4%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1471 NUM_FEPS 2 with 3 cells processed and 150 slack improved
+OPT-0007 : Iter 2: improved WNS -936 TNS -1471 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.602712s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.4%)
+
+OPT-1001 : Current memory(MB): used = 742, reserve = 744, peak = 746.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16057/17630.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.128969s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.9%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.55, top10 = 46.70, top15 = 44.82.
+OPT-1001 : End congestion update; 0.434660s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.709303s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (101.3%)
+
+OPT-0007 : Start: WNS -986 TNS -1571 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747909, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056385s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (110.8%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 2, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 747949, Over = 0
+PHY-3001 : End incremental legalization; 0.374366s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.2%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1471 NUM_FEPS 2 with 2 cells processed and 100 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747909, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057209s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (81.9%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 2, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 747949, Over = 0
+PHY-3001 : End incremental legalization; 0.364922s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.5%)
+
+OPT-0007 : Iter 2: improved WNS -936 TNS -1471 NUM_FEPS 2 with 2 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS -936 TNS -1471 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 2.156671s wall, 2.156250s user + 0.000000s system = 2.156250s CPU (100.0%)
+
+OPT-1001 : Current memory(MB): used = 742, reserve = 744, peak = 746.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.701400s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 742, reserve = 744, peak = 746.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.710653s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (98.9%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16057/17630.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.130421s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.8%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.55, top10 = 46.70, top15 = 44.82.
+RUN-1001 : End congestion update; 0.440946s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.2%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.154790s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (98.8%)
+
+OPT-1001 : Current memory(MB): used = 742, reserve = 744, peak = 746.
+OPT-1001 : End physical optimization; 24.615197s wall, 25.859375s user + 0.250000s system = 26.109375s CPU (106.1%)
+
+RUN-1003 : finish command "place" in 64.828784s wall, 91.515625s user + 5.046875s system = 96.562500s CPU (149.0%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 613 MB, peak memory is 746 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.708077s wall, 2.921875s user + 0.000000s system = 2.921875s CPU (171.1%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 615 MB, peak memory is 746 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6932 instances
+RUN-1001 : 3392 mslices, 3389 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17630 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9886 nets have 2 pins
+RUN-1001 : 6040 nets have [3 - 5] pins
+RUN-1001 : 1001 nets have [6 - 10] pins
+RUN-1001 : 321 nets have [11 - 20] pins
+RUN-1001 : 354 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74216, tnet num: 17452, tinst num: 6930, tnode num: 96760, tedge num: 124559.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.574540s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (100.2%)
+
+RUN-1004 : used memory is 603 MB, reserved memory is 600 MB, peak memory is 746 MB
+PHY-1001 : 3392 mslices, 3389 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 861432, over cnt = 2754(7%), over = 4563, worst = 8
+PHY-1002 : len = 876872, over cnt = 1730(4%), over = 2557, worst = 6
+PHY-1002 : len = 899896, over cnt = 526(1%), over = 774, worst = 6
+PHY-1002 : len = 912264, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 912440, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.877095s wall, 3.843750s user + 0.062500s system = 3.906250s CPU (135.8%)
+
+PHY-1001 : Congestion index: top1 = 54.20, top5 = 49.29, top10 = 46.64, top15 = 44.74.
+PHY-1001 : End global routing; 3.186773s wall, 4.156250s user + 0.062500s system = 4.218750s CPU (132.4%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 712, reserve = 715, peak = 746.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 985, reserve = 990, peak = 985.
+PHY-1001 : End build detailed router design. 3.968041s wall, 3.953125s user + 0.015625s system = 3.968750s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 266520, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.873484s wall, 4.875000s user + 0.000000s system = 4.875000s CPU (100.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 266576, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.406724s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1020, reserve = 1026, peak = 1020.
+PHY-1001 : End phase 1; 5.294590s wall, 5.296875s user + 0.000000s system = 5.296875s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.38544e+06, over cnt = 1940(0%), over = 1945, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1037, reserve = 1041, peak = 1037.
+PHY-1001 : End initial routed; 28.152689s wall, 59.953125s user + 0.312500s system = 60.265625s CPU (214.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 11/16553(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.799 | -4.467 | 4
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.585652s wall, 3.531250s user + 0.000000s system = 3.531250s CPU (98.5%)
+
+PHY-1001 : Current memory(MB): used = 1055, reserve = 1059, peak = 1055.
+PHY-1001 : End phase 2; 31.738410s wall, 63.484375s user + 0.312500s system = 63.796875s CPU (201.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -1.797ns STNS -3.968ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.149728s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (104.4%)
+
+PHY-1022 : len = 2.38541e+06, over cnt = 1942(0%), over = 1947, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.409727s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.2%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.35104e+06, over cnt = 800(0%), over = 801, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.855269s wall, 3.390625s user + 0.015625s system = 3.406250s CPU (183.6%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.34865e+06, over cnt = 253(0%), over = 254, worst = 2, crit = 0
+PHY-1001 : End DR Iter 2; 0.989276s wall, 1.406250s user + 0.000000s system = 1.406250s CPU (142.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.34642e+06, over cnt = 33(0%), over = 33, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.993022s wall, 1.234375s user + 0.015625s system = 1.250000s CPU (125.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.34658e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.354083s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (101.5%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.34667e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.169026s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16553(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.797 | -3.968 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.264518s wall, 3.250000s user + 0.015625s system = 3.265625s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 586 feed throughs used by 421 nets
+PHY-1001 : End commit to database; 2.282707s wall, 2.265625s user + 0.015625s system = 2.281250s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1147, reserve = 1156, peak = 1147.
+PHY-1001 : End phase 3; 10.723600s wall, 12.859375s user + 0.062500s system = 12.921875s CPU (120.5%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.797ns STNS -3.968ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.138577s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.5%)
+
+PHY-1022 : len = 2.34667e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.379205s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.9%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.797ns, -3.968ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16553(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.797 | -3.968 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.262653s wall, 3.265625s user + 0.000000s system = 3.265625s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 586 feed throughs used by 421 nets
+PHY-1001 : End commit to database; 2.347056s wall, 2.343750s user + 0.000000s system = 2.343750s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1157, reserve = 1167, peak = 1157.
+PHY-1001 : End phase 4; 6.016218s wall, 6.015625s user + 0.000000s system = 6.015625s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.34667e+06
+PHY-1001 : Current memory(MB): used = 1161, reserve = 1172, peak = 1161.
+PHY-1001 : End export database. 0.060517s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.3%)
+
+PHY-1001 : End detail routing; 58.195576s wall, 92.062500s user + 0.390625s system = 92.453125s CPU (158.9%)
+
+RUN-1003 : finish command "route" in 64.040255s wall, 98.875000s user + 0.468750s system = 99.343750s CPU (155.1%)
+
+RUN-1004 : used memory is 1034 MB, reserved memory is 1050 MB, peak memory is 1161 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10320 out of 19600 52.65%
+#reg 9363 out of 19600 47.77%
+#le 12661
+ #lut only 3298 out of 12661 26.05%
+ #reg only 2341 out of 12661 18.49%
+ #lut® 7022 out of 12661 55.46%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1795
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1417
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1355
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 967
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 139
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg42_syn_219.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_b/u_ADconfig/reg1_syn_191.f0 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P133 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P4 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P138 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P16 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P152 LVCMOS33 8 N/A NONE
+ paper_out OUTPUT P17 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P15 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P104 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12661 |9293 |1027 |9394 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |545 |451 |23 |442 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |98 |83 |4 |90 |4 |0 |
+| U_crc16_24b |crc16_24b |29 |29 |0 |19 |0 |0 |
+| U_ecc_gen |ecc_gen |14 |14 |0 |10 |0 |0 |
+| exdev_ctl_a |exdev_ctl |767 |373 |96 |581 |0 |0 |
+| u_ADconfig |AD_config |188 |139 |25 |142 |0 |0 |
+| u_gen_sp |gen_sp |263 |160 |71 |123 |0 |0 |
+| exdev_ctl_b |exdev_ctl |752 |423 |96 |556 |0 |0 |
+| u_ADconfig |AD_config |178 |140 |25 |126 |0 |0 |
+| u_gen_sp |gen_sp |262 |168 |71 |118 |0 |0 |
+| sampling_fe_a |sampling_fe |3094 |2433 |306 |2032 |25 |0 |
+| u0_soft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |183 |97 |17 |141 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort |2875 |2311 |289 |1855 |25 |0 |
+| rddpram_ctl |rddpram_ctl |5 |5 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2499 |2063 |253 |1538 |22 |0 |
+| channelPart |channel_part_8478 |133 |130 |3 |122 |0 |0 |
+| fifo_adc |fifo_adc |62 |53 |9 |44 |0 |0 |
+| ram_switch |ram_switch |1994 |1633 |197 |1144 |0 |0 |
+| adc_addr_gen |adc_addr_gen |244 |217 |27 |114 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |8 |5 |3 |4 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |29 |26 |3 |14 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |9 |0 |0 |
+| insert |insert |953 |620 |170 |654 |0 |0 |
+| ram_switch_state |ram_switch_state |797 |796 |0 |376 |0 |0 |
+| read_ram_i |read_ram |265 |209 |44 |186 |0 |0 |
+| read_ram_addr |read_ram_addr |213 |173 |40 |147 |0 |0 |
+| read_ram_data |read_ram_data |51 |35 |4 |38 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |339 |233 |36 |280 |3 |0 |
+| u0_soft_n |cdc_sync |7 |7 |0 |7 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3367 |2648 |349 |2114 |25 |1 |
+| u0_soft_n |cdc_sync |6 |1 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |166 |113 |17 |130 |0 |0 |
+| u0_soft_n |cdc_sync |6 |1 |0 |6 |0 |0 |
+| u_sort |sort_rev |3165 |2522 |332 |1948 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |3 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |7 |2 |0 |7 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2731 |2228 |290 |1587 |22 |1 |
+| channelPart |channel_part_8478 |238 |235 |3 |135 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
+| ram_switch |ram_switch |1983 |1621 |197 |1142 |0 |0 |
+| adc_addr_gen |adc_addr_gen |221 |194 |27 |105 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |30 |27 |3 |18 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |8 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |21 |18 |3 |10 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| insert |insert |974 |641 |170 |669 |0 |0 |
+| ram_switch_state |ram_switch_state |788 |786 |0 |368 |0 |0 |
+| read_ram_i |read_ram_rev |424 |303 |81 |240 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |291 |206 |73 |159 |0 |0 |
+| read_ram_data |read_ram_data_rev |133 |97 |8 |81 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9824
+ #2 2 3937
+ #3 3 1458
+ #4 4 642
+ #5 5-10 1062
+ #6 11-50 587
+ #7 51-100 24
+ #8 >500 1
+ Average 2.91
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.074319s wall, 3.515625s user + 0.031250s system = 3.546875s CPU (171.0%)
+
+RUN-1004 : used memory is 1036 MB, reserved memory is 1052 MB, peak memory is 1161 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74216, tnet num: 17452, tinst num: 6930, tnode num: 96760, tedge num: 124559.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.601093s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (99.5%)
+
+RUN-1004 : used memory is 1040 MB, reserved memory is 1056 MB, peak memory is 1161 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.444477s wall, 1.453125s user + 0.000000s system = 1.453125s CPU (100.6%)
+
+RUN-1004 : used memory is 1086 MB, reserved memory is 1103 MB, peak memory is 1161 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6930
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17630, pip num: 174550
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 586
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3249 valid insts, and 483475 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.597067s wall, 60.812500s user + 0.156250s system = 60.968750s CPU (635.3%)
+
+RUN-1004 : used memory is 1268 MB, reserved memory is 1271 MB, peak memory is 1384 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240218_154144.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240218_160210.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240218_160210.log
new file mode 100644
index 0000000..1535051
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240218_160210.log
@@ -0,0 +1,1921 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sun Feb 18 16:02:11 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.104045s wall, 1.937500s user + 0.171875s system = 2.109375s CPU (100.3%)
+
+RUN-1004 : used memory is 336 MB, reserved memory is 314 MB, peak memory is 340 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2945 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17703 instances
+RUN-0007 : 7440 luts, 9040 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20281 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13180 nets have 2 pins
+RUN-1001 : 5799 nets have [3 - 5] pins
+RUN-1001 : 882 nets have [6 - 10] pins
+RUN-1001 : 171 nets have [11 - 20] pins
+RUN-1001 : 175 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 789
+RUN-1001 : No | No | Yes | 1968
+RUN-1001 : No | Yes | No | 3474
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 56
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 141
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17701 instances, 7440 luts, 9040 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 5915 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84691, tnet num: 20103, tinst num: 17701, tnode num: 114767, tedge num: 135907.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.114186s wall, 1.093750s user + 0.015625s system = 1.109375s CPU (99.6%)
+
+RUN-1004 : used memory is 529 MB, reserved memory is 513 MB, peak memory is 529 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20103 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.876565s wall, 1.843750s user + 0.031250s system = 1.875000s CPU (99.9%)
+
+PHY-3001 : Found 1228 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 3.80944e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17701.
+PHY-3001 : Level 1 #clusters 2034.
+PHY-3001 : End clustering; 0.122700s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (127.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.27994e+06, overlap = 479.281
+PHY-3002 : Step(2): len = 1.16422e+06, overlap = 467.812
+PHY-3002 : Step(3): len = 876023, overlap = 567.969
+PHY-3002 : Step(4): len = 776355, overlap = 600.688
+PHY-3002 : Step(5): len = 607221, overlap = 699.25
+PHY-3002 : Step(6): len = 552728, overlap = 784
+PHY-3002 : Step(7): len = 489411, overlap = 853.375
+PHY-3002 : Step(8): len = 423763, overlap = 956.656
+PHY-3002 : Step(9): len = 381673, overlap = 1051.56
+PHY-3002 : Step(10): len = 341681, overlap = 1091.41
+PHY-3002 : Step(11): len = 315778, overlap = 1122
+PHY-3002 : Step(12): len = 284142, overlap = 1164.06
+PHY-3002 : Step(13): len = 261712, overlap = 1177.75
+PHY-3002 : Step(14): len = 240228, overlap = 1265.06
+PHY-3002 : Step(15): len = 217558, overlap = 1330.25
+PHY-3002 : Step(16): len = 196572, overlap = 1393.09
+PHY-3002 : Step(17): len = 182498, overlap = 1420.12
+PHY-3002 : Step(18): len = 166845, overlap = 1443.06
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.1737e-07
+PHY-3002 : Step(19): len = 166907, overlap = 1417.22
+PHY-3002 : Step(20): len = 187750, overlap = 1322.72
+PHY-3002 : Step(21): len = 187551, overlap = 1275
+PHY-3002 : Step(22): len = 192402, overlap = 1248.44
+PHY-3002 : Step(23): len = 188655, overlap = 1215.47
+PHY-3002 : Step(24): len = 186470, overlap = 1208
+PHY-3002 : Step(25): len = 182288, overlap = 1207.59
+PHY-3002 : Step(26): len = 180842, overlap = 1186.19
+PHY-3002 : Step(27): len = 178240, overlap = 1177.47
+PHY-3002 : Step(28): len = 177863, overlap = 1149.88
+PHY-3002 : Step(29): len = 176080, overlap = 1160.94
+PHY-3002 : Step(30): len = 175217, overlap = 1181.94
+PHY-3002 : Step(31): len = 174554, overlap = 1192.03
+PHY-3002 : Step(32): len = 174910, overlap = 1169.84
+PHY-3002 : Step(33): len = 174332, overlap = 1168.34
+PHY-3002 : Step(34): len = 173633, overlap = 1189.62
+PHY-3002 : Step(35): len = 173157, overlap = 1185.59
+PHY-3002 : Step(36): len = 173581, overlap = 1160.91
+PHY-3002 : Step(37): len = 172088, overlap = 1181.38
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.63474e-06
+PHY-3002 : Step(38): len = 173271, overlap = 1146.19
+PHY-3002 : Step(39): len = 183581, overlap = 1110.34
+PHY-3002 : Step(40): len = 189218, overlap = 1082.31
+PHY-3002 : Step(41): len = 194495, overlap = 1065.38
+PHY-3002 : Step(42): len = 196774, overlap = 1055.34
+PHY-3002 : Step(43): len = 198398, overlap = 1042.88
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.26948e-06
+PHY-3002 : Step(44): len = 205948, overlap = 1009.81
+PHY-3002 : Step(45): len = 220413, overlap = 991.406
+PHY-3002 : Step(46): len = 226424, overlap = 977.062
+PHY-3002 : Step(47): len = 229417, overlap = 947.969
+PHY-3002 : Step(48): len = 231454, overlap = 928.75
+PHY-3002 : Step(49): len = 232562, overlap = 878.875
+PHY-3002 : Step(50): len = 231928, overlap = 866.094
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 6.53896e-06
+PHY-3002 : Step(51): len = 242231, overlap = 846.062
+PHY-3002 : Step(52): len = 268228, overlap = 739.719
+PHY-3002 : Step(53): len = 284448, overlap = 667.875
+PHY-3002 : Step(54): len = 295730, overlap = 611.188
+PHY-3002 : Step(55): len = 299887, overlap = 580.125
+PHY-3002 : Step(56): len = 299038, overlap = 544.969
+PHY-3002 : Step(57): len = 296979, overlap = 519.812
+PHY-3002 : Step(58): len = 293381, overlap = 517.625
+PHY-3002 : Step(59): len = 290591, overlap = 529.562
+PHY-3002 : Step(60): len = 290484, overlap = 517.906
+PHY-3002 : Step(61): len = 290358, overlap = 519.469
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.30779e-05
+PHY-3002 : Step(62): len = 307917, overlap = 502.938
+PHY-3002 : Step(63): len = 324037, overlap = 471.406
+PHY-3002 : Step(64): len = 329409, overlap = 467.594
+PHY-3002 : Step(65): len = 332800, overlap = 471.125
+PHY-3002 : Step(66): len = 332726, overlap = 437.312
+PHY-3002 : Step(67): len = 332012, overlap = 426.969
+PHY-3002 : Step(68): len = 329455, overlap = 439.344
+PHY-3002 : Step(69): len = 329804, overlap = 425.625
+PHY-3002 : Step(70): len = 329590, overlap = 408.031
+PHY-3002 : Step(71): len = 330311, overlap = 390.781
+PHY-3002 : Step(72): len = 329224, overlap = 392.875
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 2.61558e-05
+PHY-3002 : Step(73): len = 348258, overlap = 353.344
+PHY-3002 : Step(74): len = 362781, overlap = 347.969
+PHY-3002 : Step(75): len = 368221, overlap = 362.219
+PHY-3002 : Step(76): len = 369912, overlap = 340.156
+PHY-3002 : Step(77): len = 369224, overlap = 333.844
+PHY-3002 : Step(78): len = 371444, overlap = 324.531
+PHY-3002 : Step(79): len = 368658, overlap = 312.5
+PHY-3002 : Step(80): len = 370461, overlap = 317.469
+PHY-3002 : Step(81): len = 372728, overlap = 306.719
+PHY-3002 : Step(82): len = 375095, overlap = 298.656
+PHY-3002 : Step(83): len = 372910, overlap = 286.812
+PHY-3002 : Step(84): len = 373929, overlap = 279.906
+PHY-3002 : Step(85): len = 375263, overlap = 288.219
+PHY-3002 : Step(86): len = 376310, overlap = 295.938
+PHY-3002 : Step(87): len = 374729, overlap = 302.594
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 5.23117e-05
+PHY-3002 : Step(88): len = 392435, overlap = 283.969
+PHY-3002 : Step(89): len = 403484, overlap = 278.188
+PHY-3002 : Step(90): len = 403547, overlap = 273.656
+PHY-3002 : Step(91): len = 405119, overlap = 278.281
+PHY-3002 : Step(92): len = 406858, overlap = 251.969
+PHY-3002 : Step(93): len = 410467, overlap = 239.062
+PHY-3002 : Step(94): len = 408827, overlap = 244.219
+PHY-3002 : Step(95): len = 410584, overlap = 232.25
+PHY-3002 : Step(96): len = 413595, overlap = 219.531
+PHY-3002 : Step(97): len = 415344, overlap = 218.438
+PHY-3002 : Step(98): len = 412360, overlap = 226
+PHY-3002 : Step(99): len = 412229, overlap = 226.031
+PHY-3002 : Step(100): len = 413258, overlap = 227.312
+PHY-3002 : Step(101): len = 414152, overlap = 228.75
+PHY-3002 : Step(102): len = 411880, overlap = 220.344
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000102888
+PHY-3002 : Step(103): len = 427763, overlap = 214.75
+PHY-3002 : Step(104): len = 436535, overlap = 213.75
+PHY-3002 : Step(105): len = 435187, overlap = 200.25
+PHY-3002 : Step(106): len = 435795, overlap = 203.562
+PHY-3002 : Step(107): len = 438746, overlap = 202.438
+PHY-3002 : Step(108): len = 442493, overlap = 195.781
+PHY-3002 : Step(109): len = 442767, overlap = 200.625
+PHY-3002 : Step(110): len = 446048, overlap = 207.656
+PHY-3002 : Step(111): len = 449114, overlap = 203.719
+PHY-3002 : Step(112): len = 451260, overlap = 191.875
+PHY-3002 : Step(113): len = 450181, overlap = 191.781
+PHY-3002 : Step(114): len = 450170, overlap = 194.5
+PHY-3002 : Step(115): len = 451092, overlap = 193.812
+PHY-3002 : Step(116): len = 452297, overlap = 196.75
+PHY-3002 : Step(117): len = 450509, overlap = 195.656
+PHY-3002 : Step(118): len = 450223, overlap = 192.688
+PHY-3002 : Step(119): len = 451317, overlap = 198.625
+PHY-3002 : Step(120): len = 452236, overlap = 199.281
+PHY-3002 : Step(121): len = 451258, overlap = 185.281
+PHY-3002 : Step(122): len = 451588, overlap = 177.188
+PHY-3002 : Step(123): len = 451945, overlap = 193.219
+PHY-3002 : Step(124): len = 452797, overlap = 204.094
+PHY-3002 : Step(125): len = 451046, overlap = 197.562
+PHY-3002 : Step(126): len = 450846, overlap = 186.531
+PHY-3002 : Step(127): len = 451107, overlap = 190.5
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000205777
+PHY-3002 : Step(128): len = 463555, overlap = 182.906
+PHY-3002 : Step(129): len = 469046, overlap = 175.844
+PHY-3002 : Step(130): len = 466885, overlap = 172.25
+PHY-3002 : Step(131): len = 466629, overlap = 161.75
+PHY-3002 : Step(132): len = 469084, overlap = 167.531
+PHY-3002 : Step(133): len = 470925, overlap = 166.594
+PHY-3002 : Step(134): len = 470871, overlap = 162.219
+PHY-3002 : Step(135): len = 471875, overlap = 162.844
+PHY-3002 : Step(136): len = 474005, overlap = 159.719
+PHY-3002 : Step(137): len = 476185, overlap = 160.031
+PHY-3002 : Step(138): len = 475679, overlap = 157.062
+PHY-3002 : Step(139): len = 475828, overlap = 152.688
+PHY-3002 : Step(140): len = 477035, overlap = 151.812
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000411553
+PHY-3002 : Step(141): len = 484469, overlap = 144.844
+PHY-3002 : Step(142): len = 492915, overlap = 142.75
+PHY-3002 : Step(143): len = 495795, overlap = 132.25
+PHY-3002 : Step(144): len = 498438, overlap = 132.781
+PHY-3002 : Step(145): len = 501835, overlap = 130.156
+PHY-3002 : Step(146): len = 504355, overlap = 128.094
+PHY-3002 : Step(147): len = 503464, overlap = 126.031
+PHY-3002 : Step(148): len = 503878, overlap = 122.188
+PHY-3002 : Step(149): len = 504987, overlap = 123.25
+PHY-3002 : Step(150): len = 505573, overlap = 125.312
+PHY-3002 : Step(151): len = 504398, overlap = 126.031
+PHY-3002 : Step(152): len = 504148, overlap = 128.031
+PHY-3002 : Step(153): len = 504366, overlap = 123.5
+PHY-3002 : Step(154): len = 504701, overlap = 122.969
+PHY-3002 : Step(155): len = 504578, overlap = 121.656
+PHY-3002 : Step(156): len = 504713, overlap = 122.281
+PHY-3002 : Step(157): len = 504983, overlap = 127.969
+PHY-3002 : Step(158): len = 505305, overlap = 124.406
+PHY-3002 : Step(159): len = 505138, overlap = 128.594
+PHY-3002 : Step(160): len = 505117, overlap = 129.281
+PHY-3002 : Step(161): len = 505127, overlap = 126.375
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000798197
+PHY-3002 : Step(162): len = 509710, overlap = 123.531
+PHY-3002 : Step(163): len = 515521, overlap = 125.031
+PHY-3002 : Step(164): len = 516565, overlap = 124.906
+PHY-3002 : Step(165): len = 518181, overlap = 122.812
+PHY-3002 : Step(166): len = 520333, overlap = 128.062
+PHY-3002 : Step(167): len = 521238, overlap = 126.062
+PHY-3002 : Step(168): len = 520103, overlap = 125.031
+PHY-3002 : Step(169): len = 519646, overlap = 118.719
+PHY-3002 : Step(170): len = 520264, overlap = 120.969
+PHY-3002 : Step(171): len = 520399, overlap = 121.188
+PHY-3002 : Step(172): len = 519690, overlap = 122.688
+PHY-3002 : Step(173): len = 519567, overlap = 120.844
+PHY-3002 : Step(174): len = 520317, overlap = 122.156
+PHY-3002 : Step(175): len = 520550, overlap = 122.219
+PHY-3002 : Step(176): len = 520075, overlap = 121.156
+PHY-3002 : Step(177): len = 520188, overlap = 121.156
+PHY-3002 : Step(178): len = 521072, overlap = 121.875
+PHY-3002 : Step(179): len = 521806, overlap = 126.125
+PHY-3002 : Step(180): len = 521718, overlap = 124.531
+PHY-3002 : Step(181): len = 521847, overlap = 123.812
+PHY-3002 : Step(182): len = 522358, overlap = 123.469
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00154509
+PHY-3002 : Step(183): len = 525984, overlap = 125.469
+PHY-3002 : Step(184): len = 531882, overlap = 118.156
+PHY-3002 : Step(185): len = 533454, overlap = 110.375
+PHY-3002 : Step(186): len = 534684, overlap = 104.156
+PHY-3002 : Step(187): len = 536199, overlap = 106.625
+PHY-3002 : Step(188): len = 537341, overlap = 109.219
+PHY-3002 : Step(189): len = 537296, overlap = 108.688
+PHY-3002 : Step(190): len = 537198, overlap = 105.844
+PHY-3002 : Step(191): len = 537525, overlap = 105.969
+PHY-3002 : Step(192): len = 537612, overlap = 107.031
+PHY-3002 : Step(193): len = 536850, overlap = 105.969
+PHY-3002 : Step(194): len = 536635, overlap = 107.594
+PHY-3002 : Step(195): len = 536677, overlap = 107.844
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00251667
+PHY-3002 : Step(196): len = 537805, overlap = 107.875
+PHY-3002 : Step(197): len = 539927, overlap = 105.531
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.012700s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (123.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20281.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 710160, over cnt = 1565(4%), over = 7161, worst = 34
+PHY-1001 : End global iterations; 0.685783s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (134.4%)
+
+PHY-1001 : Congestion index: top1 = 83.92, top5 = 63.52, top10 = 53.57, top15 = 47.45.
+PHY-3001 : End congestion estimation; 0.916196s wall, 1.125000s user + 0.031250s system = 1.156250s CPU (126.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20103 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.833921s wall, 0.781250s user + 0.046875s system = 0.828125s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000143414
+PHY-3002 : Step(198): len = 640825, overlap = 50.4375
+PHY-3002 : Step(199): len = 644017, overlap = 43.25
+PHY-3002 : Step(200): len = 641126, overlap = 45.375
+PHY-3002 : Step(201): len = 641088, overlap = 42.375
+PHY-3002 : Step(202): len = 640491, overlap = 38.2188
+PHY-3002 : Step(203): len = 640070, overlap = 35.375
+PHY-3002 : Step(204): len = 637758, overlap = 31.7812
+PHY-3002 : Step(205): len = 635440, overlap = 30.2812
+PHY-3002 : Step(206): len = 634688, overlap = 27
+PHY-3002 : Step(207): len = 631025, overlap = 27.5312
+PHY-3002 : Step(208): len = 629287, overlap = 27.1562
+PHY-3002 : Step(209): len = 626899, overlap = 24.9688
+PHY-3002 : Step(210): len = 626151, overlap = 22.0625
+PHY-3002 : Step(211): len = 624625, overlap = 22.6875
+PHY-3002 : Step(212): len = 624669, overlap = 20.2188
+PHY-3002 : Step(213): len = 622801, overlap = 20.1562
+PHY-3002 : Step(214): len = 622568, overlap = 19.75
+PHY-3002 : Step(215): len = 621592, overlap = 21.3438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000286827
+PHY-3002 : Step(216): len = 623410, overlap = 22.5312
+PHY-3002 : Step(217): len = 625529, overlap = 22.6562
+PHY-3002 : Step(218): len = 630459, overlap = 22.7812
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000568725
+PHY-3002 : Step(219): len = 637875, overlap = 23.5938
+PHY-3002 : Step(220): len = 648157, overlap = 27.875
+PHY-3002 : Step(221): len = 656122, overlap = 30.5938
+PHY-3002 : Step(222): len = 659615, overlap = 28.0312
+PHY-3002 : Step(223): len = 662661, overlap = 29.5625
+PHY-3002 : Step(224): len = 661763, overlap = 27.1562
+PHY-3002 : Step(225): len = 661618, overlap = 21.8438
+PHY-3002 : Step(226): len = 660920, overlap = 19.9688
+PHY-3002 : Step(227): len = 659582, overlap = 21.0625
+PHY-3002 : Step(228): len = 658214, overlap = 21.6562
+PHY-3002 : Step(229): len = 657539, overlap = 24.2188
+PHY-3002 : Step(230): len = 656347, overlap = 23.6562
+PHY-3002 : Step(231): len = 656092, overlap = 22.4375
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00113745
+PHY-3002 : Step(232): len = 659966, overlap = 22.1562
+PHY-3002 : Step(233): len = 665219, overlap = 21.9375
+PHY-3002 : Step(234): len = 669715, overlap = 21.4688
+PHY-3002 : Step(235): len = 675521, overlap = 22.1875
+PHY-3002 : Step(236): len = 679268, overlap = 22.625
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00212903
+PHY-3002 : Step(237): len = 681979, overlap = 21.4375
+PHY-3002 : Step(238): len = 687483, overlap = 22.375
+PHY-3002 : Step(239): len = 691744, overlap = 22.9375
+PHY-3002 : Step(240): len = 694412, overlap = 22.0312
+PHY-3002 : Step(241): len = 696187, overlap = 20.75
+PHY-3002 : Step(242): len = 697379, overlap = 21.5625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 101/20281.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 782136, over cnt = 2722(7%), over = 12627, worst = 33
+PHY-1001 : End global iterations; 1.521974s wall, 2.125000s user + 0.015625s system = 2.140625s CPU (140.6%)
+
+PHY-1001 : Congestion index: top1 = 90.88, top5 = 71.43, top10 = 62.73, top15 = 57.12.
+PHY-3001 : End congestion estimation; 1.775468s wall, 2.375000s user + 0.015625s system = 2.390625s CPU (134.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20103 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.859977s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000119979
+PHY-3002 : Step(243): len = 686787, overlap = 243.281
+PHY-3002 : Step(244): len = 684687, overlap = 182.75
+PHY-3002 : Step(245): len = 671355, overlap = 172.938
+PHY-3002 : Step(246): len = 664523, overlap = 157.5
+PHY-3002 : Step(247): len = 655621, overlap = 143.438
+PHY-3002 : Step(248): len = 651009, overlap = 137.438
+PHY-3002 : Step(249): len = 644763, overlap = 134.688
+PHY-3002 : Step(250): len = 639685, overlap = 140.562
+PHY-3002 : Step(251): len = 635150, overlap = 136.469
+PHY-3002 : Step(252): len = 631373, overlap = 128.406
+PHY-3002 : Step(253): len = 627792, overlap = 128.219
+PHY-3002 : Step(254): len = 624709, overlap = 126.125
+PHY-3002 : Step(255): len = 620437, overlap = 122.375
+PHY-3002 : Step(256): len = 617963, overlap = 124.812
+PHY-3002 : Step(257): len = 614043, overlap = 125.469
+PHY-3002 : Step(258): len = 610864, overlap = 118.844
+PHY-3002 : Step(259): len = 608433, overlap = 117.719
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000239958
+PHY-3002 : Step(260): len = 610193, overlap = 114.969
+PHY-3002 : Step(261): len = 611601, overlap = 113.5
+PHY-3002 : Step(262): len = 613282, overlap = 112.844
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000459104
+PHY-3002 : Step(263): len = 619575, overlap = 107.219
+PHY-3002 : Step(264): len = 626284, overlap = 98.3125
+PHY-3002 : Step(265): len = 628342, overlap = 92.375
+PHY-3002 : Step(266): len = 627810, overlap = 94.2188
+PHY-3002 : Step(267): len = 628437, overlap = 92.7812
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84691, tnet num: 20103, tinst num: 17701, tnode num: 114767, tedge num: 135907.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.391531s wall, 1.359375s user + 0.031250s system = 1.390625s CPU (99.9%)
+
+RUN-1004 : used memory is 572 MB, reserved memory is 562 MB, peak memory is 708 MB
+OPT-1001 : Total overflow 411.41 peak overflow 5.34
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 584/20281.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 730016, over cnt = 2979(8%), over = 10344, worst = 25
+PHY-1001 : End global iterations; 1.349463s wall, 1.859375s user + 0.000000s system = 1.859375s CPU (137.8%)
+
+PHY-1001 : Congestion index: top1 = 73.08, top5 = 57.58, top10 = 51.03, top15 = 47.40.
+PHY-1001 : End incremental global routing; 1.693298s wall, 2.218750s user + 0.000000s system = 2.218750s CPU (131.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20103 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.903952s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.3%)
+
+OPT-1001 : 49 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17567 has valid locations, 344 needs to be replaced
+PHY-3001 : design contains 17996 instances, 7546 luts, 9229 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 6051 pins
+PHY-3001 : Found 1241 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 651756
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16329/20576.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 744232, over cnt = 3022(8%), over = 10439, worst = 25
+PHY-1001 : End global iterations; 0.223342s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (132.9%)
+
+PHY-1001 : Congestion index: top1 = 72.48, top5 = 57.38, top10 = 51.09, top15 = 47.50.
+PHY-3001 : End congestion estimation; 0.466509s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (117.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85865, tnet num: 20398, tinst num: 17996, tnode num: 116516, tedge num: 137665.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.402749s wall, 1.406250s user + 0.000000s system = 1.406250s CPU (100.2%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 617 MB, peak memory is 713 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20398 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.325108s wall, 2.312500s user + 0.015625s system = 2.328125s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(268): len = 651072, overlap = 0.1875
+PHY-3002 : Step(269): len = 651109, overlap = 0.1875
+PHY-3002 : Step(270): len = 650852, overlap = 0.1875
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16421/20576.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 743024, over cnt = 3028(8%), over = 10478, worst = 27
+PHY-1001 : End global iterations; 0.197367s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (142.5%)
+
+PHY-1001 : Congestion index: top1 = 73.77, top5 = 58.21, top10 = 51.63, top15 = 47.87.
+PHY-3001 : End congestion estimation; 0.443120s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (119.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20398 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.898108s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (99.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000294861
+PHY-3002 : Step(271): len = 650744, overlap = 96.5938
+PHY-3002 : Step(272): len = 651289, overlap = 96.5938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000589723
+PHY-3002 : Step(273): len = 651575, overlap = 95.6875
+PHY-3002 : Step(274): len = 651820, overlap = 95.125
+PHY-3001 : Final: Len = 651820, Over = 95.125
+PHY-3001 : End incremental placement; 4.723453s wall, 5.046875s user + 0.140625s system = 5.187500s CPU (109.8%)
+
+OPT-1001 : Total overflow 418.03 peak overflow 5.34
+OPT-1001 : End high-fanout net optimization; 7.851370s wall, 8.796875s user + 0.140625s system = 8.937500s CPU (113.8%)
+
+OPT-1001 : Current memory(MB): used = 717, reserve = 712, peak = 734.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16387/20576.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 744520, over cnt = 2999(8%), over = 9524, worst = 25
+PHY-1002 : len = 796344, over cnt = 1871(5%), over = 4395, worst = 22
+PHY-1002 : len = 822480, over cnt = 1053(2%), over = 2289, worst = 19
+PHY-1002 : len = 838488, over cnt = 568(1%), over = 1199, worst = 14
+PHY-1002 : len = 860424, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.873506s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (120.9%)
+
+PHY-1001 : Congestion index: top1 = 59.53, top5 = 51.60, top10 = 47.53, top15 = 45.05.
+OPT-1001 : End congestion update; 2.136427s wall, 2.531250s user + 0.000000s system = 2.531250s CPU (118.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20398 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.768376s wall, 0.750000s user + 0.015625s system = 0.765625s CPU (99.6%)
+
+OPT-0007 : Start: WNS -1068 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 72 cells processed and 4814 slack improved
+OPT-0007 : Iter 2: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 23 cells processed and 2150 slack improved
+OPT-0007 : Iter 3: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 9 cells processed and 500 slack improved
+OPT-1001 : End global optimization; 2.941689s wall, 3.312500s user + 0.015625s system = 3.328125s CPU (113.1%)
+
+OPT-1001 : Current memory(MB): used = 694, reserve = 696, peak = 734.
+OPT-1001 : End physical optimization; 12.789716s wall, 14.140625s user + 0.203125s system = 14.343750s CPU (112.2%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7546 LUT to BLE ...
+SYN-4008 : Packed 7546 LUT and 3080 SEQ to BLE.
+SYN-4003 : Packing 6149 remaining SEQ's ...
+SYN-4005 : Packed 4017 SEQ with LUT/SLICE
+SYN-4006 : 747 single LUT's are left
+SYN-4006 : 2132 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9678/13409 primitive instances ...
+PHY-3001 : End packing; 1.610841s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.9%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6782 instances
+RUN-1001 : 3317 mslices, 3317 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17627 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9864 nets have 2 pins
+RUN-1001 : 6072 nets have [3 - 5] pins
+RUN-1001 : 996 nets have [6 - 10] pins
+RUN-1001 : 319 nets have [11 - 20] pins
+RUN-1001 : 343 nets have [21 - 99] pins
+RUN-1001 : 13 nets have 100+ pins
+PHY-3001 : design contains 6780 instances, 6634 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3586 pins
+PHY-3001 : Found 504 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 664826, Over = 259.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7304/17627.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 814768, over cnt = 2049(5%), over = 3432, worst = 9
+PHY-1002 : len = 822792, over cnt = 1442(4%), over = 2149, worst = 9
+PHY-1002 : len = 839168, over cnt = 632(1%), over = 893, worst = 7
+PHY-1002 : len = 851352, over cnt = 123(0%), over = 177, worst = 5
+PHY-1002 : len = 853944, over cnt = 22(0%), over = 41, worst = 5
+PHY-1001 : End global iterations; 1.615049s wall, 2.218750s user + 0.015625s system = 2.234375s CPU (138.3%)
+
+PHY-1001 : Congestion index: top1 = 58.19, top5 = 51.53, top10 = 47.73, top15 = 45.15.
+PHY-3001 : End congestion estimation; 2.009533s wall, 2.625000s user + 0.015625s system = 2.640625s CPU (131.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73971, tnet num: 17449, tinst num: 6780, tnode num: 96357, tedge num: 124162.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.566506s wall, 1.546875s user + 0.015625s system = 1.562500s CPU (99.7%)
+
+RUN-1004 : used memory is 612 MB, reserved memory is 617 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17449 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.405417s wall, 2.375000s user + 0.031250s system = 2.406250s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.39716e-05
+PHY-3002 : Step(275): len = 654775, overlap = 252.5
+PHY-3002 : Step(276): len = 650063, overlap = 255.75
+PHY-3002 : Step(277): len = 646828, overlap = 252
+PHY-3002 : Step(278): len = 645865, overlap = 251.25
+PHY-3002 : Step(279): len = 643893, overlap = 249.25
+PHY-3002 : Step(280): len = 641722, overlap = 254
+PHY-3002 : Step(281): len = 640060, overlap = 254.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.79433e-05
+PHY-3002 : Step(282): len = 642003, overlap = 244.75
+PHY-3002 : Step(283): len = 646070, overlap = 240.25
+PHY-3002 : Step(284): len = 647921, overlap = 235.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000175887
+PHY-3002 : Step(285): len = 654441, overlap = 222.25
+PHY-3002 : Step(286): len = 665663, overlap = 216
+PHY-3002 : Step(287): len = 667548, overlap = 215
+PHY-3002 : Step(288): len = 667840, overlap = 215.5
+PHY-3002 : Step(289): len = 668590, overlap = 217
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000339357
+PHY-3002 : Step(290): len = 674645, overlap = 205
+PHY-3002 : Step(291): len = 682334, overlap = 202
+PHY-3002 : Step(292): len = 690416, overlap = 194.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.356762s wall, 0.390625s user + 0.609375s system = 1.000000s CPU (280.3%)
+
+PHY-3001 : Trial Legalized: Len = 758579
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 817/17627.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 879344, over cnt = 2777(7%), over = 4633, worst = 9
+PHY-1002 : len = 897224, over cnt = 1603(4%), over = 2336, worst = 7
+PHY-1002 : len = 915256, over cnt = 659(1%), over = 935, worst = 6
+PHY-1002 : len = 927328, over cnt = 149(0%), over = 202, worst = 5
+PHY-1002 : len = 930608, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.186365s wall, 3.171875s user + 0.031250s system = 3.203125s CPU (146.5%)
+
+PHY-1001 : Congestion index: top1 = 55.73, top5 = 50.58, top10 = 47.64, top15 = 45.63.
+PHY-3001 : End congestion estimation; 2.635191s wall, 3.609375s user + 0.046875s system = 3.656250s CPU (138.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17449 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.834732s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000174295
+PHY-3002 : Step(293): len = 732193, overlap = 38.75
+PHY-3002 : Step(294): len = 716679, overlap = 64
+PHY-3002 : Step(295): len = 702759, overlap = 95
+PHY-3002 : Step(296): len = 694407, overlap = 113.75
+PHY-3002 : Step(297): len = 687515, overlap = 136
+PHY-3002 : Step(298): len = 685029, overlap = 146
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000348589
+PHY-3002 : Step(299): len = 689970, overlap = 143.25
+PHY-3002 : Step(300): len = 695634, overlap = 143.25
+PHY-3002 : Step(301): len = 698761, overlap = 143.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000697178
+PHY-3002 : Step(302): len = 702155, overlap = 142.75
+PHY-3002 : Step(303): len = 710778, overlap = 143.25
+PHY-3002 : Step(304): len = 717886, overlap = 143.5
+PHY-3002 : Step(305): len = 718470, overlap = 143
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.031257s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (100.0%)
+
+PHY-3001 : Legalized: Len = 745918, Over = 0
+PHY-3001 : Spreading special nets. 471 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.099966s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (93.8%)
+
+PHY-3001 : 697 instances has been re-located, deltaX = 240, deltaY = 391, maxDist = 3.
+PHY-3001 : Final: Len = 756278, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73971, tnet num: 17449, tinst num: 6783, tnode num: 96357, tedge num: 124162.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.797100s wall, 1.796875s user + 0.000000s system = 1.796875s CPU (100.0%)
+
+RUN-1004 : used memory is 628 MB, reserved memory is 643 MB, peak memory is 734 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4449/17627.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 892648, over cnt = 2545(7%), over = 4092, worst = 6
+PHY-1002 : len = 905024, over cnt = 1574(4%), over = 2238, worst = 6
+PHY-1002 : len = 922416, over cnt = 617(1%), over = 846, worst = 6
+PHY-1002 : len = 931008, over cnt = 189(0%), over = 260, worst = 5
+PHY-1002 : len = 935088, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.968136s wall, 2.843750s user + 0.031250s system = 2.875000s CPU (146.1%)
+
+PHY-1001 : Congestion index: top1 = 54.89, top5 = 49.48, top10 = 46.74, top15 = 44.91.
+PHY-1001 : End incremental global routing; 2.340844s wall, 3.218750s user + 0.031250s system = 3.250000s CPU (138.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17449 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.845243s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.8%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6690 has valid locations, 25 needs to be replaced
+PHY-3001 : design contains 6803 instances, 6654 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3672 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 758873
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16086/17652.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 938048, over cnt = 85(0%), over = 93, worst = 5
+PHY-1002 : len = 938336, over cnt = 28(0%), over = 29, worst = 2
+PHY-1002 : len = 938456, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 938640, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 938704, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.761035s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (110.9%)
+
+PHY-1001 : Congestion index: top1 = 54.89, top5 = 49.51, top10 = 46.76, top15 = 44.95.
+PHY-3001 : End congestion estimation; 1.062324s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (107.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74132, tnet num: 17474, tinst num: 6803, tnode num: 96571, tedge num: 124393.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.791346s wall, 1.781250s user + 0.015625s system = 1.796875s CPU (100.3%)
+
+RUN-1004 : used memory is 693 MB, reserved memory is 695 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17474 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.678050s wall, 2.656250s user + 0.015625s system = 2.671875s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(306): len = 758333, overlap = 0
+PHY-3002 : Step(307): len = 758247, overlap = 0
+PHY-3002 : Step(308): len = 758199, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16081/17652.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 936640, over cnt = 58(0%), over = 66, worst = 3
+PHY-1002 : len = 936728, over cnt = 31(0%), over = 31, worst = 1
+PHY-1002 : len = 936992, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 937056, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 937080, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.781980s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (103.9%)
+
+PHY-1001 : Congestion index: top1 = 54.87, top5 = 49.57, top10 = 46.82, top15 = 44.96.
+PHY-3001 : End congestion estimation; 1.101554s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (103.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17474 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.853921s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (98.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000105555
+PHY-3002 : Step(309): len = 758081, overlap = 2
+PHY-3002 : Step(310): len = 758049, overlap = 1.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005695s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (274.4%)
+
+PHY-3001 : Legalized: Len = 758140, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058828s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.2%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 3, deltaY = 9, maxDist = 3.
+PHY-3001 : Final: Len = 758362, Over = 0
+PHY-3001 : End incremental placement; 6.164084s wall, 6.265625s user + 0.078125s system = 6.343750s CPU (102.9%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.920116s wall, 10.890625s user + 0.109375s system = 11.000000s CPU (110.9%)
+
+OPT-1001 : Current memory(MB): used = 743, reserve = 741, peak = 746.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16043/17652.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 937184, over cnt = 48(0%), over = 56, worst = 3
+PHY-1002 : len = 937320, over cnt = 24(0%), over = 24, worst = 1
+PHY-1002 : len = 937384, over cnt = 18(0%), over = 18, worst = 1
+PHY-1002 : len = 937528, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 937680, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.757189s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (107.3%)
+
+PHY-1001 : Congestion index: top1 = 54.87, top5 = 49.53, top10 = 46.73, top15 = 44.92.
+OPT-1001 : End congestion update; 1.060388s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (104.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17474 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.703408s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.0%)
+
+OPT-0007 : Start: WNS -1133 TNS -1847 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6715 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6803 instances, 6654 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3672 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 761860, Over = 0
+PHY-3001 : Spreading special nets. 19 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058442s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.9%)
+
+PHY-3001 : 30 instances has been re-located, deltaX = 21, deltaY = 11, maxDist = 2.
+PHY-3001 : Final: Len = 762604, Over = 0
+PHY-3001 : End incremental legalization; 0.367118s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (97.9%)
+
+OPT-0007 : Iter 1: improved WNS -1033 TNS -1618 NUM_FEPS 2 with 54 cells processed and 11611 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6715 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6803 instances, 6654 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3672 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 765292, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057316s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (109.0%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 14, deltaY = 11, maxDist = 3.
+PHY-3001 : Final: Len = 766014, Over = 0
+PHY-3001 : End incremental legalization; 0.367225s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (110.6%)
+
+OPT-0007 : Iter 2: improved WNS -1033 TNS -1618 NUM_FEPS 2 with 16 cells processed and 2071 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6715 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6803 instances, 6654 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3672 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 766436, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056174s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (83.4%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 7, deltaY = 6, maxDist = 2.
+PHY-3001 : Final: Len = 766602, Over = 0
+PHY-3001 : End incremental legalization; 0.366209s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.1%)
+
+OPT-0007 : Iter 3: improved WNS -1033 TNS -1618 NUM_FEPS 2 with 12 cells processed and 607 slack improved
+OPT-1001 : End path based optimization; 3.276839s wall, 3.468750s user + 0.000000s system = 3.468750s CPU (105.9%)
+
+OPT-1001 : Current memory(MB): used = 743, reserve = 742, peak = 746.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17474 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.697340s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.8%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15780/17652.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 945304, over cnt = 151(0%), over = 185, worst = 4
+PHY-1002 : len = 945440, over cnt = 78(0%), over = 82, worst = 2
+PHY-1002 : len = 945928, over cnt = 19(0%), over = 21, worst = 2
+PHY-1002 : len = 946184, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 946216, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.838479s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (102.5%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.70, top10 = 46.86, top15 = 44.96.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17474 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.700817s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.3%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -1083 TNS -1718 NUM_FEPS 2
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.551724
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -1083ps with logic level 2
+RUN-1001 : #2 path slack -1047ps with logic level 2
+RUN-1001 : 0 HFN exist on timing critical paths out of 17652 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 17652 nets
+OPT-1001 : End physical optimization; 17.893927s wall, 19.062500s user + 0.109375s system = 19.171875s CPU (107.1%)
+
+RUN-1003 : finish command "place" in 58.953695s wall, 89.203125s user + 6.390625s system = 95.593750s CPU (162.2%)
+
+RUN-1004 : used memory is 649 MB, reserved memory is 651 MB, peak memory is 746 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.681705s wall, 2.906250s user + 0.000000s system = 2.906250s CPU (172.8%)
+
+RUN-1004 : used memory is 650 MB, reserved memory is 652 MB, peak memory is 746 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6805 instances
+RUN-1001 : 3329 mslices, 3325 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17652 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9869 nets have 2 pins
+RUN-1001 : 6072 nets have [3 - 5] pins
+RUN-1001 : 1002 nets have [6 - 10] pins
+RUN-1001 : 320 nets have [11 - 20] pins
+RUN-1001 : 361 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74132, tnet num: 17474, tinst num: 6803, tnode num: 96571, tedge num: 124393.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.552303s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (99.7%)
+
+RUN-1004 : used memory is 630 MB, reserved memory is 625 MB, peak memory is 746 MB
+PHY-1001 : 3329 mslices, 3325 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17474 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 877280, over cnt = 2794(7%), over = 4595, worst = 7
+PHY-1002 : len = 896320, over cnt = 1638(4%), over = 2363, worst = 6
+PHY-1002 : len = 914080, over cnt = 688(1%), over = 998, worst = 6
+PHY-1002 : len = 928736, over cnt = 16(0%), over = 16, worst = 1
+PHY-1002 : len = 929328, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.078641s wall, 4.062500s user + 0.031250s system = 4.093750s CPU (133.0%)
+
+PHY-1001 : Congestion index: top1 = 54.03, top5 = 49.02, top10 = 46.40, top15 = 44.60.
+PHY-1001 : End global routing; 3.393305s wall, 4.375000s user + 0.031250s system = 4.406250s CPU (129.9%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 712, reserve = 714, peak = 746.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 985, reserve = 987, peak = 985.
+PHY-1001 : End build detailed router design. 3.918049s wall, 3.875000s user + 0.015625s system = 3.890625s CPU (99.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 273152, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.713023s wall, 4.718750s user + 0.000000s system = 4.718750s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 273208, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.434325s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.7%)
+
+PHY-1001 : Current memory(MB): used = 1021, reserve = 1024, peak = 1021.
+PHY-1001 : End phase 1; 5.160857s wall, 5.171875s user + 0.000000s system = 5.171875s CPU (100.2%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.36741e+06, over cnt = 1803(0%), over = 1814, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1039, reserve = 1042, peak = 1039.
+PHY-1001 : End initial routed; 27.155765s wall, 57.125000s user + 0.281250s system = 57.406250s CPU (211.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16575(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -2.007 | -3.897 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.150028s wall, 3.140625s user + 0.000000s system = 3.140625s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1053, reserve = 1057, peak = 1053.
+PHY-1001 : End phase 2; 30.305855s wall, 60.265625s user + 0.281250s system = 60.546875s CPU (199.8%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -1.898ns STNS -3.801ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.135009s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (92.6%)
+
+PHY-1022 : len = 2.36742e+06, over cnt = 1804(0%), over = 1816, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.386353s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (101.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.33677e+06, over cnt = 630(0%), over = 630, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.647761s wall, 2.562500s user + 0.000000s system = 2.562500s CPU (155.5%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.33187e+06, over cnt = 157(0%), over = 157, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.809625s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (135.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.33359e+06, over cnt = 13(0%), over = 13, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.376735s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (116.1%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.33369e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.216878s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (100.9%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.33374e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.183447s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (102.2%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.33374e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.220665s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.1%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.33374e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.327471s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (95.4%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.33375e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.179208s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (130.8%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.33374e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.180232s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (104.0%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.33375e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.183488s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (93.7%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.3338e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 11; 0.178065s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (105.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16575(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.898 | -3.801 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.141280s wall, 3.140625s user + 0.000000s system = 3.140625s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 580 feed throughs used by 430 nets
+PHY-1001 : End commit to database; 2.220069s wall, 2.203125s user + 0.015625s system = 2.218750s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1154, reserve = 1161, peak = 1154.
+PHY-1001 : End phase 3; 10.644903s wall, 11.890625s user + 0.031250s system = 11.921875s CPU (112.0%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.898ns STNS -3.801ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.131328s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (107.1%)
+
+PHY-1022 : len = 2.3338e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.359884s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.9%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.898ns, -3.801ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16575(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.898 | -3.801 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.205337s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (100.4%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 580 feed throughs used by 430 nets
+PHY-1001 : End commit to database; 2.373614s wall, 2.375000s user + 0.000000s system = 2.375000s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1162, reserve = 1170, peak = 1162.
+PHY-1001 : End phase 4; 5.963537s wall, 5.968750s user + 0.000000s system = 5.968750s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.3338e+06
+PHY-1001 : Current memory(MB): used = 1165, reserve = 1173, peak = 1165.
+PHY-1001 : End export database. 0.060951s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.5%)
+
+PHY-1001 : End detail routing; 56.442690s wall, 87.640625s user + 0.328125s system = 87.968750s CPU (155.9%)
+
+RUN-1003 : finish command "route" in 62.428465s wall, 94.578125s user + 0.375000s system = 94.953125s CPU (152.1%)
+
+RUN-1004 : used memory is 1091 MB, reserved memory is 1104 MB, peak memory is 1165 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10322 out of 19600 52.66%
+#reg 9374 out of 19600 47.83%
+#le 12396
+ #lut only 3022 out of 12396 24.38%
+ #reg only 2074 out of 12396 16.73%
+ #lut® 7300 out of 12396 58.89%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1783
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1429
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1338
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 951
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 139
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 67
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_b/u_ADconfig/reg1_syn_197.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_b/reg1_syn_144.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P133 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P4 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P138 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P16 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P152 LVCMOS33 8 N/A NONE
+ paper_out OUTPUT P17 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P15 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P104 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12396 |9295 |1027 |9405 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |563 |453 |23 |455 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |101 |81 |4 |91 |4 |0 |
+| U_crc16_24b |crc16_24b |35 |35 |0 |22 |0 |0 |
+| U_ecc_gen |ecc_gen |6 |6 |0 |6 |0 |0 |
+| exdev_ctl_a |exdev_ctl |788 |470 |96 |570 |0 |0 |
+| u_ADconfig |AD_config |194 |141 |25 |143 |0 |0 |
+| u_gen_sp |gen_sp |283 |182 |71 |117 |0 |0 |
+| exdev_ctl_b |exdev_ctl |727 |420 |96 |545 |0 |0 |
+| u_ADconfig |AD_config |169 |131 |25 |124 |0 |0 |
+| u_gen_sp |gen_sp |254 |158 |71 |117 |0 |0 |
+| sampling_fe_a |sampling_fe |2923 |2328 |306 |2045 |25 |0 |
+| u0_soft_n |cdc_sync |6 |3 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |193 |136 |17 |147 |0 |0 |
+| u0_soft_n |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u_sort |sort |2694 |2185 |289 |1862 |25 |0 |
+| rddpram_ctl |rddpram_ctl |6 |2 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |2 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2314 |1888 |253 |1540 |22 |0 |
+| channelPart |channel_part_8478 |159 |155 |3 |142 |0 |0 |
+| fifo_adc |fifo_adc |68 |59 |9 |42 |0 |0 |
+| ram_switch |ram_switch |1779 |1437 |197 |1127 |0 |0 |
+| adc_addr_gen |adc_addr_gen |264 |233 |27 |134 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |6 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |28 |25 |3 |17 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |27 |24 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |29 |26 |3 |17 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |27 |24 |3 |12 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |27 |24 |3 |15 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |28 |25 |3 |12 |0 |0 |
+| insert |insert |959 |648 |170 |645 |0 |0 |
+| ram_switch_state |ram_switch_state |556 |556 |0 |348 |0 |0 |
+| read_ram_i |read_ram |274 |214 |44 |196 |0 |0 |
+| read_ram_addr |read_ram_addr |212 |172 |40 |150 |0 |0 |
+| read_ram_data |read_ram_data |58 |40 |4 |42 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |337 |270 |36 |279 |3 |0 |
+| u0_soft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3253 |2563 |349 |2073 |25 |1 |
+| u0_soft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |184 |87 |17 |145 |0 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_sort |sort_rev |3035 |2454 |332 |1894 |25 |1 |
+| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2636 |2187 |290 |1546 |22 |1 |
+| channelPart |channel_part_8478 |248 |240 |3 |140 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |42 |0 |1 |
+| ram_switch |ram_switch |1932 |1612 |197 |1121 |0 |0 |
+| adc_addr_gen |adc_addr_gen |221 |194 |27 |112 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |8 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |19 |16 |3 |10 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |28 |25 |3 |12 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |23 |20 |3 |12 |0 |0 |
+| insert |insert |963 |672 |170 |654 |0 |0 |
+| ram_switch_state |ram_switch_state |748 |746 |0 |355 |0 |0 |
+| read_ram_i |read_ram_rev |363 |258 |81 |208 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |286 |201 |73 |155 |0 |0 |
+| read_ram_data |read_ram_data_rev |77 |57 |8 |53 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9807
+ #2 2 3966
+ #3 3 1455
+ #4 4 648
+ #5 5-10 1064
+ #6 11-50 589
+ #7 51-100 27
+ #8 >500 1
+ Average 2.91
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.069539s wall, 3.515625s user + 0.015625s system = 3.531250s CPU (170.6%)
+
+RUN-1004 : used memory is 1093 MB, reserved memory is 1105 MB, peak memory is 1165 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74132, tnet num: 17474, tinst num: 6803, tnode num: 96571, tedge num: 124393.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.628726s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (99.8%)
+
+RUN-1004 : used memory is 1097 MB, reserved memory is 1108 MB, peak memory is 1165 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17474 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.452718s wall, 1.437500s user + 0.015625s system = 1.453125s CPU (100.0%)
+
+RUN-1004 : used memory is 1102 MB, reserved memory is 1112 MB, peak memory is 1165 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6803
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17652, pip num: 173890
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 580
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3242 valid insts, and 481685 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.513111s wall, 62.593750s user + 0.203125s system = 62.796875s CPU (660.1%)
+
+RUN-1004 : used memory is 1264 MB, reserved memory is 1268 MB, peak memory is 1379 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240218_160210.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240218_161224.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240218_161224.log
new file mode 100644
index 0000000..127d8bf
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240218_161224.log
@@ -0,0 +1,2028 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sun Feb 18 16:12:24 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.252502s wall, 2.234375s user + 0.015625s system = 2.250000s CPU (99.9%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 315 MB, peak memory is 341 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2945 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17703 instances
+RUN-0007 : 7440 luts, 9040 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20281 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13180 nets have 2 pins
+RUN-1001 : 5799 nets have [3 - 5] pins
+RUN-1001 : 882 nets have [6 - 10] pins
+RUN-1001 : 171 nets have [11 - 20] pins
+RUN-1001 : 175 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 789
+RUN-1001 : No | No | Yes | 1968
+RUN-1001 : No | Yes | No | 3474
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 56
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 141
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17701 instances, 7440 luts, 9040 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 5915 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84691, tnet num: 20103, tinst num: 17701, tnode num: 114767, tedge num: 135907.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.209763s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (99.5%)
+
+RUN-1004 : used memory is 529 MB, reserved memory is 514 MB, peak memory is 529 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20103 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.034946s wall, 2.015625s user + 0.015625s system = 2.031250s CPU (99.8%)
+
+PHY-3001 : Found 1228 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 3.80961e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17701.
+PHY-3001 : Level 1 #clusters 2034.
+PHY-3001 : End clustering; 0.139674s wall, 0.125000s user + 0.015625s system = 0.140625s CPU (100.7%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28216e+06, overlap = 479.625
+PHY-3002 : Step(2): len = 1.16629e+06, overlap = 466.594
+PHY-3002 : Step(3): len = 879184, overlap = 563.188
+PHY-3002 : Step(4): len = 778763, overlap = 603.531
+PHY-3002 : Step(5): len = 610007, overlap = 698.5
+PHY-3002 : Step(6): len = 553353, overlap = 793.531
+PHY-3002 : Step(7): len = 483397, overlap = 865.125
+PHY-3002 : Step(8): len = 428045, overlap = 948.875
+PHY-3002 : Step(9): len = 387650, overlap = 1027.94
+PHY-3002 : Step(10): len = 347429, overlap = 1091.44
+PHY-3002 : Step(11): len = 320060, overlap = 1115.94
+PHY-3002 : Step(12): len = 291839, overlap = 1155.03
+PHY-3002 : Step(13): len = 261286, overlap = 1162.31
+PHY-3002 : Step(14): len = 241329, overlap = 1257.91
+PHY-3002 : Step(15): len = 218162, overlap = 1327.19
+PHY-3002 : Step(16): len = 201977, overlap = 1380.91
+PHY-3002 : Step(17): len = 188610, overlap = 1409.34
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.17875e-06
+PHY-3002 : Step(18): len = 192522, overlap = 1393.97
+PHY-3002 : Step(19): len = 219286, overlap = 1267.19
+PHY-3002 : Step(20): len = 216608, overlap = 1219.03
+PHY-3002 : Step(21): len = 221491, overlap = 1189.69
+PHY-3002 : Step(22): len = 217335, overlap = 1176.91
+PHY-3002 : Step(23): len = 213907, overlap = 1169
+PHY-3002 : Step(24): len = 207477, overlap = 1155.03
+PHY-3002 : Step(25): len = 204839, overlap = 1121.84
+PHY-3002 : Step(26): len = 201758, overlap = 1095.22
+PHY-3002 : Step(27): len = 199103, overlap = 1074.72
+PHY-3002 : Step(28): len = 195864, overlap = 1068.25
+PHY-3002 : Step(29): len = 194181, overlap = 1056.53
+PHY-3002 : Step(30): len = 190914, overlap = 1055.34
+PHY-3002 : Step(31): len = 190364, overlap = 1063.09
+PHY-3002 : Step(32): len = 189352, overlap = 1080.78
+PHY-3002 : Step(33): len = 188271, overlap = 1086.03
+PHY-3002 : Step(34): len = 187676, overlap = 1096.19
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.35749e-06
+PHY-3002 : Step(35): len = 191338, overlap = 1089.16
+PHY-3002 : Step(36): len = 206908, overlap = 1048.03
+PHY-3002 : Step(37): len = 212447, overlap = 1036.25
+PHY-3002 : Step(38): len = 216650, overlap = 1013.75
+PHY-3002 : Step(39): len = 217121, overlap = 1007.72
+PHY-3002 : Step(40): len = 218523, overlap = 984.438
+PHY-3002 : Step(41): len = 218264, overlap = 975.406
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.71498e-06
+PHY-3002 : Step(42): len = 226950, overlap = 968.812
+PHY-3002 : Step(43): len = 245710, overlap = 872.906
+PHY-3002 : Step(44): len = 257664, overlap = 797.438
+PHY-3002 : Step(45): len = 266586, overlap = 762.031
+PHY-3002 : Step(46): len = 271617, overlap = 731.906
+PHY-3002 : Step(47): len = 274607, overlap = 691.5
+PHY-3002 : Step(48): len = 276377, overlap = 653.438
+PHY-3002 : Step(49): len = 276817, overlap = 646.938
+PHY-3002 : Step(50): len = 276581, overlap = 660.125
+PHY-3002 : Step(51): len = 276637, overlap = 682.438
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.42996e-06
+PHY-3002 : Step(52): len = 292794, overlap = 631.031
+PHY-3002 : Step(53): len = 315192, overlap = 541.281
+PHY-3002 : Step(54): len = 325580, overlap = 488.906
+PHY-3002 : Step(55): len = 330349, overlap = 470.656
+PHY-3002 : Step(56): len = 330984, overlap = 479.5
+PHY-3002 : Step(57): len = 329740, overlap = 469.5
+PHY-3002 : Step(58): len = 328432, overlap = 476.188
+PHY-3002 : Step(59): len = 329101, overlap = 476
+PHY-3002 : Step(60): len = 327860, overlap = 473.656
+PHY-3002 : Step(61): len = 327626, overlap = 460.375
+PHY-3002 : Step(62): len = 326421, overlap = 465.219
+PHY-3002 : Step(63): len = 326449, overlap = 460.844
+PHY-3002 : Step(64): len = 325947, overlap = 463.781
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.88599e-05
+PHY-3002 : Step(65): len = 345594, overlap = 405.844
+PHY-3002 : Step(66): len = 358504, overlap = 380.375
+PHY-3002 : Step(67): len = 361349, overlap = 342.25
+PHY-3002 : Step(68): len = 363338, overlap = 326.031
+PHY-3002 : Step(69): len = 363377, overlap = 309.844
+PHY-3002 : Step(70): len = 364627, overlap = 326.219
+PHY-3002 : Step(71): len = 365087, overlap = 328.219
+PHY-3002 : Step(72): len = 365792, overlap = 333.594
+PHY-3002 : Step(73): len = 364897, overlap = 330.188
+PHY-3002 : Step(74): len = 365206, overlap = 329.875
+PHY-3002 : Step(75): len = 363871, overlap = 332.094
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.77199e-05
+PHY-3002 : Step(76): len = 383140, overlap = 311.875
+PHY-3002 : Step(77): len = 395177, overlap = 289.969
+PHY-3002 : Step(78): len = 395172, overlap = 281.938
+PHY-3002 : Step(79): len = 396342, overlap = 263.188
+PHY-3002 : Step(80): len = 399773, overlap = 272.594
+PHY-3002 : Step(81): len = 403999, overlap = 252.812
+PHY-3002 : Step(82): len = 402545, overlap = 237.156
+PHY-3002 : Step(83): len = 402877, overlap = 213.281
+PHY-3002 : Step(84): len = 404121, overlap = 220.188
+PHY-3002 : Step(85): len = 405404, overlap = 208.75
+PHY-3002 : Step(86): len = 404198, overlap = 210.375
+PHY-3002 : Step(87): len = 404719, overlap = 206.062
+PHY-3002 : Step(88): len = 405666, overlap = 203.531
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.54397e-05
+PHY-3002 : Step(89): len = 422768, overlap = 199
+PHY-3002 : Step(90): len = 433682, overlap = 201.625
+PHY-3002 : Step(91): len = 431641, overlap = 196.031
+PHY-3002 : Step(92): len = 430725, overlap = 188.062
+PHY-3002 : Step(93): len = 432978, overlap = 187.25
+PHY-3002 : Step(94): len = 435457, overlap = 191.875
+PHY-3002 : Step(95): len = 433279, overlap = 195.875
+PHY-3002 : Step(96): len = 435016, overlap = 188.656
+PHY-3002 : Step(97): len = 438049, overlap = 188.688
+PHY-3002 : Step(98): len = 438940, overlap = 184.656
+PHY-3002 : Step(99): len = 437194, overlap = 189.844
+PHY-3002 : Step(100): len = 437650, overlap = 189.219
+PHY-3002 : Step(101): len = 438669, overlap = 183.594
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000150879
+PHY-3002 : Step(102): len = 451568, overlap = 191.656
+PHY-3002 : Step(103): len = 458537, overlap = 182.375
+PHY-3002 : Step(104): len = 458416, overlap = 164.906
+PHY-3002 : Step(105): len = 459084, overlap = 159.875
+PHY-3002 : Step(106): len = 460562, overlap = 160.438
+PHY-3002 : Step(107): len = 461926, overlap = 168.562
+PHY-3002 : Step(108): len = 460202, overlap = 162.594
+PHY-3002 : Step(109): len = 461085, overlap = 163.625
+PHY-3002 : Step(110): len = 463855, overlap = 157.969
+PHY-3002 : Step(111): len = 466293, overlap = 153.281
+PHY-3002 : Step(112): len = 465161, overlap = 163.906
+PHY-3002 : Step(113): len = 465966, overlap = 159.062
+PHY-3002 : Step(114): len = 468286, overlap = 147.875
+PHY-3002 : Step(115): len = 469272, overlap = 143.812
+PHY-3002 : Step(116): len = 467852, overlap = 146.781
+PHY-3002 : Step(117): len = 468130, overlap = 146.781
+PHY-3002 : Step(118): len = 470349, overlap = 145.562
+PHY-3002 : Step(119): len = 471970, overlap = 149.188
+PHY-3002 : Step(120): len = 470240, overlap = 150.781
+PHY-3002 : Step(121): len = 470218, overlap = 152.906
+PHY-3002 : Step(122): len = 471502, overlap = 158.875
+PHY-3002 : Step(123): len = 472437, overlap = 157
+PHY-3002 : Step(124): len = 471668, overlap = 161.594
+PHY-3002 : Step(125): len = 471740, overlap = 160.219
+PHY-3002 : Step(126): len = 472430, overlap = 161.719
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000301759
+PHY-3002 : Step(127): len = 481561, overlap = 157.75
+PHY-3002 : Step(128): len = 491291, overlap = 148.5
+PHY-3002 : Step(129): len = 495046, overlap = 138.031
+PHY-3002 : Step(130): len = 496710, overlap = 134.188
+PHY-3002 : Step(131): len = 498607, overlap = 129.844
+PHY-3002 : Step(132): len = 499874, overlap = 130.438
+PHY-3002 : Step(133): len = 498023, overlap = 130.094
+PHY-3002 : Step(134): len = 497863, overlap = 133
+PHY-3002 : Step(135): len = 499555, overlap = 133
+PHY-3002 : Step(136): len = 500548, overlap = 124.969
+PHY-3002 : Step(137): len = 499129, overlap = 125.719
+PHY-3002 : Step(138): len = 498751, overlap = 127
+PHY-3002 : Step(139): len = 499579, overlap = 130.312
+PHY-3002 : Step(140): len = 500234, overlap = 129.875
+PHY-3002 : Step(141): len = 499512, overlap = 130.406
+PHY-3002 : Step(142): len = 499876, overlap = 132.219
+PHY-3002 : Step(143): len = 501054, overlap = 132.281
+PHY-3002 : Step(144): len = 501728, overlap = 135.094
+PHY-3002 : Step(145): len = 500931, overlap = 129.344
+PHY-3002 : Step(146): len = 500875, overlap = 130.469
+PHY-3002 : Step(147): len = 501276, overlap = 127.719
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000595753
+PHY-3002 : Step(148): len = 508170, overlap = 120.156
+PHY-3002 : Step(149): len = 513247, overlap = 115.562
+PHY-3002 : Step(150): len = 513677, overlap = 112.656
+PHY-3002 : Step(151): len = 514601, overlap = 115.906
+PHY-3002 : Step(152): len = 515876, overlap = 109.062
+PHY-3002 : Step(153): len = 517064, overlap = 110.969
+PHY-3002 : Step(154): len = 517158, overlap = 109.438
+PHY-3002 : Step(155): len = 517550, overlap = 115.094
+PHY-3002 : Step(156): len = 518867, overlap = 109.156
+PHY-3002 : Step(157): len = 519944, overlap = 101.531
+PHY-3002 : Step(158): len = 519809, overlap = 102.156
+PHY-3002 : Step(159): len = 519917, overlap = 104.344
+PHY-3002 : Step(160): len = 519662, overlap = 104.531
+PHY-3002 : Step(161): len = 519991, overlap = 106
+PHY-3002 : Step(162): len = 520598, overlap = 107.938
+PHY-3002 : Step(163): len = 521229, overlap = 101.469
+PHY-3002 : Step(164): len = 520862, overlap = 102.031
+PHY-3002 : Step(165): len = 520876, overlap = 102.094
+PHY-3002 : Step(166): len = 520991, overlap = 99.8438
+PHY-3002 : Step(167): len = 521046, overlap = 102.344
+PHY-3002 : Step(168): len = 520694, overlap = 104.531
+PHY-3002 : Step(169): len = 521123, overlap = 105.562
+PHY-3002 : Step(170): len = 521670, overlap = 103.312
+PHY-3002 : Step(171): len = 521936, overlap = 103.594
+PHY-3002 : Step(172): len = 521952, overlap = 101.719
+PHY-3002 : Step(173): len = 522327, overlap = 104.531
+PHY-3002 : Step(174): len = 522609, overlap = 104.156
+PHY-3002 : Step(175): len = 522585, overlap = 104.156
+PHY-3002 : Step(176): len = 521950, overlap = 103.969
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00101933
+PHY-3002 : Step(177): len = 524620, overlap = 106.344
+PHY-3002 : Step(178): len = 527198, overlap = 104.719
+PHY-3002 : Step(179): len = 528003, overlap = 102.719
+PHY-3002 : Step(180): len = 528529, overlap = 101.5
+PHY-3002 : Step(181): len = 529519, overlap = 101.969
+PHY-3002 : Step(182): len = 529809, overlap = 102
+PHY-3002 : Step(183): len = 529605, overlap = 102.531
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.019461s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (80.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20281.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 683856, over cnt = 1540(4%), over = 6849, worst = 32
+PHY-1001 : End global iterations; 0.806200s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (133.7%)
+
+PHY-1001 : Congestion index: top1 = 72.93, top5 = 56.93, top10 = 49.43, top15 = 44.73.
+PHY-3001 : End congestion estimation; 1.057142s wall, 1.312500s user + 0.015625s system = 1.328125s CPU (125.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20103 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.906378s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000117893
+PHY-3002 : Step(184): len = 619912, overlap = 37.3125
+PHY-3002 : Step(185): len = 625258, overlap = 40.3438
+PHY-3002 : Step(186): len = 619999, overlap = 41.1875
+PHY-3002 : Step(187): len = 618039, overlap = 46.5
+PHY-3002 : Step(188): len = 619855, overlap = 48.0625
+PHY-3002 : Step(189): len = 617680, overlap = 44.5625
+PHY-3002 : Step(190): len = 615660, overlap = 44.2812
+PHY-3002 : Step(191): len = 615121, overlap = 38.375
+PHY-3002 : Step(192): len = 613095, overlap = 32.5625
+PHY-3002 : Step(193): len = 612369, overlap = 32.7812
+PHY-3002 : Step(194): len = 609716, overlap = 31.7812
+PHY-3002 : Step(195): len = 608656, overlap = 30.7188
+PHY-3002 : Step(196): len = 606789, overlap = 31.4062
+PHY-3002 : Step(197): len = 606288, overlap = 31.5938
+PHY-3002 : Step(198): len = 604330, overlap = 28.7188
+PHY-3002 : Step(199): len = 603101, overlap = 25.875
+PHY-3002 : Step(200): len = 601975, overlap = 24.9062
+PHY-3002 : Step(201): len = 601508, overlap = 23.7188
+PHY-3002 : Step(202): len = 601148, overlap = 23.3125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000235786
+PHY-3002 : Step(203): len = 602900, overlap = 22.1875
+PHY-3002 : Step(204): len = 605450, overlap = 21.625
+PHY-3002 : Step(205): len = 610775, overlap = 20.875
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000463887
+PHY-3002 : Step(206): len = 619828, overlap = 19.5625
+PHY-3002 : Step(207): len = 630216, overlap = 18.0312
+PHY-3002 : Step(208): len = 635697, overlap = 17.0938
+PHY-3002 : Step(209): len = 638971, overlap = 16.0625
+PHY-3002 : Step(210): len = 643006, overlap = 15.0312
+PHY-3002 : Step(211): len = 644334, overlap = 13.4062
+PHY-3002 : Step(212): len = 646449, overlap = 14
+PHY-3002 : Step(213): len = 648472, overlap = 12.4375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 73/20281.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 735472, over cnt = 2714(7%), over = 12154, worst = 36
+PHY-1001 : End global iterations; 1.745193s wall, 2.343750s user + 0.031250s system = 2.375000s CPU (136.1%)
+
+PHY-1001 : Congestion index: top1 = 80.47, top5 = 65.06, top10 = 57.39, top15 = 52.62.
+PHY-3001 : End congestion estimation; 2.034568s wall, 2.640625s user + 0.031250s system = 2.671875s CPU (131.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20103 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.926961s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000126876
+PHY-3002 : Step(214): len = 641840, overlap = 242.125
+PHY-3002 : Step(215): len = 643778, overlap = 194.875
+PHY-3002 : Step(216): len = 636240, overlap = 186.906
+PHY-3002 : Step(217): len = 631784, overlap = 173.156
+PHY-3002 : Step(218): len = 627649, overlap = 166.156
+PHY-3002 : Step(219): len = 625175, overlap = 157.625
+PHY-3002 : Step(220): len = 620478, overlap = 156.344
+PHY-3002 : Step(221): len = 617497, overlap = 143.594
+PHY-3002 : Step(222): len = 614855, overlap = 138.469
+PHY-3002 : Step(223): len = 610915, overlap = 137.188
+PHY-3002 : Step(224): len = 608956, overlap = 135.125
+PHY-3002 : Step(225): len = 606719, overlap = 138.219
+PHY-3002 : Step(226): len = 603712, overlap = 136.312
+PHY-3002 : Step(227): len = 602610, overlap = 126.375
+PHY-3002 : Step(228): len = 599637, overlap = 126.562
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000253752
+PHY-3002 : Step(229): len = 601163, overlap = 119.375
+PHY-3002 : Step(230): len = 602373, overlap = 117.344
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84691, tnet num: 20103, tinst num: 17701, tnode num: 114767, tedge num: 135907.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.566564s wall, 1.484375s user + 0.078125s system = 1.562500s CPU (99.7%)
+
+RUN-1004 : used memory is 574 MB, reserved memory is 563 MB, peak memory is 709 MB
+OPT-1001 : Total overflow 449.03 peak overflow 8.34
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 857/20281.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 699552, over cnt = 2835(8%), over = 10043, worst = 25
+PHY-1001 : End global iterations; 1.393356s wall, 1.921875s user + 0.031250s system = 1.953125s CPU (140.2%)
+
+PHY-1001 : Congestion index: top1 = 66.31, top5 = 55.55, top10 = 50.15, top15 = 46.60.
+PHY-1001 : End incremental global routing; 1.754026s wall, 2.281250s user + 0.031250s system = 2.312500s CPU (131.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20103 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.143365s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (98.4%)
+
+OPT-1001 : 49 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17567 has valid locations, 322 needs to be replaced
+PHY-3001 : design contains 17974 instances, 7534 luts, 9219 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 6039 pins
+PHY-3001 : Found 1242 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 625679
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16052/20554.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 714888, over cnt = 2876(8%), over = 10033, worst = 26
+PHY-1001 : End global iterations; 0.257696s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (121.3%)
+
+PHY-1001 : Congestion index: top1 = 66.66, top5 = 55.46, top10 = 50.11, top15 = 46.70.
+PHY-3001 : End congestion estimation; 0.515356s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (112.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85780, tnet num: 20376, tinst num: 17974, tnode num: 116409, tedge num: 137539.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.515021s wall, 1.468750s user + 0.046875s system = 1.515625s CPU (100.0%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 621 MB, peak memory is 713 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20376 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.511787s wall, 2.468750s user + 0.046875s system = 2.515625s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(231): len = 624841, overlap = 1.84375
+PHY-3002 : Step(232): len = 624485, overlap = 1.875
+PHY-3002 : Step(233): len = 624208, overlap = 1.9375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16167/20554.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 712584, over cnt = 2884(8%), over = 10123, worst = 26
+PHY-1001 : End global iterations; 0.214491s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (109.3%)
+
+PHY-1001 : Congestion index: top1 = 67.16, top5 = 55.92, top10 = 50.46, top15 = 46.96.
+PHY-3001 : End congestion estimation; 0.497612s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (103.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20376 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.982352s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000234242
+PHY-3002 : Step(234): len = 624067, overlap = 118.844
+PHY-3002 : Step(235): len = 624142, overlap = 118.875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000468484
+PHY-3002 : Step(236): len = 624150, overlap = 119.438
+PHY-3002 : Step(237): len = 624515, overlap = 119.781
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000936969
+PHY-3002 : Step(238): len = 624747, overlap = 119.469
+PHY-3002 : Step(239): len = 625394, overlap = 119.125
+PHY-3001 : Final: Len = 625394, Over = 119.125
+PHY-3001 : End incremental placement; 5.297590s wall, 5.406250s user + 0.156250s system = 5.562500s CPU (105.0%)
+
+OPT-1001 : Total overflow 455.03 peak overflow 8.34
+OPT-1001 : End high-fanout net optimization; 8.784785s wall, 9.484375s user + 0.187500s system = 9.671875s CPU (110.1%)
+
+OPT-1001 : Current memory(MB): used = 715, reserve = 710, peak = 733.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16083/20554.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 715384, over cnt = 2806(7%), over = 9025, worst = 25
+PHY-1002 : len = 749816, over cnt = 2175(6%), over = 5692, worst = 18
+PHY-1002 : len = 797800, over cnt = 922(2%), over = 2171, worst = 15
+PHY-1002 : len = 829904, over cnt = 103(0%), over = 176, worst = 10
+PHY-1002 : len = 833304, over cnt = 8(0%), over = 8, worst = 1
+PHY-1001 : End global iterations; 1.858928s wall, 2.453125s user + 0.093750s system = 2.546875s CPU (137.0%)
+
+PHY-1001 : Congestion index: top1 = 56.66, top5 = 49.86, top10 = 46.49, top15 = 44.26.
+OPT-1001 : End congestion update; 2.143489s wall, 2.734375s user + 0.093750s system = 2.828125s CPU (131.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20376 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.845385s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (99.8%)
+
+OPT-0007 : Start: WNS -1068 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 69 cells processed and 4172 slack improved
+OPT-0007 : Iter 2: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 37 cells processed and 2642 slack improved
+OPT-0007 : Iter 3: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 18 cells processed and 1540 slack improved
+OPT-0007 : Iter 4: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 8 cells processed and 700 slack improved
+OPT-1001 : End global optimization; 3.028918s wall, 3.609375s user + 0.109375s system = 3.718750s CPU (122.8%)
+
+OPT-1001 : Current memory(MB): used = 693, reserve = 692, peak = 733.
+OPT-1001 : End physical optimization; 14.149479s wall, 15.406250s user + 0.406250s system = 15.812500s CPU (111.8%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7534 LUT to BLE ...
+SYN-4008 : Packed 7534 LUT and 3081 SEQ to BLE.
+SYN-4003 : Packing 6138 remaining SEQ's ...
+SYN-4005 : Packed 3728 SEQ with LUT/SLICE
+SYN-4006 : 1033 single LUT's are left
+SYN-4006 : 2410 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9944/13675 primitive instances ...
+PHY-3001 : End packing; 1.768773s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (99.8%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6908 instances
+RUN-1001 : 3380 mslices, 3380 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17605 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9882 nets have 2 pins
+RUN-1001 : 6039 nets have [3 - 5] pins
+RUN-1001 : 996 nets have [6 - 10] pins
+RUN-1001 : 319 nets have [11 - 20] pins
+RUN-1001 : 336 nets have [21 - 99] pins
+RUN-1001 : 13 nets have 100+ pins
+PHY-3001 : design contains 6906 instances, 6760 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3598 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 639903, Over = 311.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7236/17605.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 789120, over cnt = 1925(5%), over = 3253, worst = 8
+PHY-1002 : len = 798072, over cnt = 1216(3%), over = 1800, worst = 7
+PHY-1002 : len = 811296, over cnt = 503(1%), over = 716, worst = 6
+PHY-1002 : len = 820752, over cnt = 125(0%), over = 177, worst = 6
+PHY-1002 : len = 824224, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.739831s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (143.7%)
+
+PHY-1001 : Congestion index: top1 = 57.07, top5 = 50.13, top10 = 46.41, top15 = 44.00.
+PHY-3001 : End congestion estimation; 2.153004s wall, 2.921875s user + 0.000000s system = 2.921875s CPU (135.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74010, tnet num: 17427, tinst num: 6906, tnode num: 96499, tedge num: 124264.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.721909s wall, 1.703125s user + 0.015625s system = 1.718750s CPU (99.8%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 612 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17427 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.682779s wall, 2.656250s user + 0.015625s system = 2.671875s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.06879e-05
+PHY-3002 : Step(240): len = 631140, overlap = 311.75
+PHY-3002 : Step(241): len = 627745, overlap = 297.5
+PHY-3002 : Step(242): len = 626822, overlap = 291.5
+PHY-3002 : Step(243): len = 626753, overlap = 288.75
+PHY-3002 : Step(244): len = 626765, overlap = 289
+PHY-3002 : Step(245): len = 625140, overlap = 294.75
+PHY-3002 : Step(246): len = 623501, overlap = 289.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.13758e-05
+PHY-3002 : Step(247): len = 625054, overlap = 285.75
+PHY-3002 : Step(248): len = 628153, overlap = 280.5
+PHY-3002 : Step(249): len = 629867, overlap = 274.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000162752
+PHY-3002 : Step(250): len = 636527, overlap = 270.25
+PHY-3002 : Step(251): len = 646126, overlap = 260.75
+PHY-3002 : Step(252): len = 647192, overlap = 257
+PHY-3002 : Step(253): len = 648901, overlap = 249.75
+PHY-3002 : Step(254): len = 650656, overlap = 243.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.373026s wall, 0.328125s user + 0.546875s system = 0.875000s CPU (234.6%)
+
+PHY-3001 : Trial Legalized: Len = 743394
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 860/17605.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 863992, over cnt = 2790(7%), over = 4770, worst = 9
+PHY-1002 : len = 879488, over cnt = 1790(5%), over = 2791, worst = 9
+PHY-1002 : len = 898056, over cnt = 932(2%), over = 1462, worst = 9
+PHY-1002 : len = 915752, over cnt = 266(0%), over = 437, worst = 5
+PHY-1002 : len = 922712, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.471592s wall, 3.671875s user + 0.015625s system = 3.687500s CPU (149.2%)
+
+PHY-1001 : Congestion index: top1 = 55.62, top5 = 50.45, top10 = 47.79, top15 = 45.92.
+PHY-3001 : End congestion estimation; 2.962224s wall, 4.171875s user + 0.015625s system = 4.187500s CPU (141.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17427 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.933765s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000164287
+PHY-3002 : Step(255): len = 712986, overlap = 53.5
+PHY-3002 : Step(256): len = 696944, overlap = 79.75
+PHY-3002 : Step(257): len = 682333, overlap = 116
+PHY-3002 : Step(258): len = 674623, overlap = 137.75
+PHY-3002 : Step(259): len = 668996, overlap = 153.25
+PHY-3002 : Step(260): len = 665196, overlap = 165.5
+PHY-3002 : Step(261): len = 663411, overlap = 179.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000328575
+PHY-3002 : Step(262): len = 669297, overlap = 175.25
+PHY-3002 : Step(263): len = 675703, overlap = 176
+PHY-3002 : Step(264): len = 679816, overlap = 173.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00065715
+PHY-3002 : Step(265): len = 684396, overlap = 170
+PHY-3002 : Step(266): len = 694418, overlap = 160.25
+PHY-3002 : Step(267): len = 698782, overlap = 155
+PHY-3002 : Step(268): len = 701898, overlap = 155.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.037784s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (82.7%)
+
+PHY-3001 : Legalized: Len = 730065, Over = 0
+PHY-3001 : Spreading special nets. 447 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.109370s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (100.0%)
+
+PHY-3001 : 660 instances has been re-located, deltaX = 210, deltaY = 407, maxDist = 2.
+PHY-3001 : Final: Len = 740629, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74010, tnet num: 17427, tinst num: 6909, tnode num: 96499, tedge num: 124264.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.972104s wall, 1.937500s user + 0.031250s system = 1.968750s CPU (99.8%)
+
+RUN-1004 : used memory is 635 MB, reserved memory is 653 MB, peak memory is 733 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3203/17605.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874136, over cnt = 2608(7%), over = 4302, worst = 9
+PHY-1002 : len = 888584, over cnt = 1473(4%), over = 2234, worst = 7
+PHY-1002 : len = 905280, over cnt = 568(1%), over = 888, worst = 7
+PHY-1002 : len = 919032, over cnt = 51(0%), over = 69, worst = 5
+PHY-1002 : len = 920176, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.311184s wall, 3.625000s user + 0.000000s system = 3.625000s CPU (156.8%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.41, top10 = 46.68, top15 = 44.80.
+PHY-1001 : End incremental global routing; 2.720139s wall, 4.031250s user + 0.000000s system = 4.031250s CPU (148.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17427 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.945794s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.1%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6816 has valid locations, 26 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 744426
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16034/17630.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 924200, over cnt = 82(0%), over = 95, worst = 3
+PHY-1002 : len = 924280, over cnt = 38(0%), over = 39, worst = 2
+PHY-1002 : len = 924576, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 924704, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 924736, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.828284s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (111.3%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.39, top10 = 46.67, top15 = 44.80.
+PHY-3001 : End congestion estimation; 1.163709s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (107.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74216, tnet num: 17452, tinst num: 6930, tnode num: 96760, tedge num: 124559.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.993424s wall, 1.984375s user + 0.015625s system = 2.000000s CPU (100.3%)
+
+RUN-1004 : used memory is 645 MB, reserved memory is 641 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.971579s wall, 2.937500s user + 0.031250s system = 2.968750s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(269): len = 743276, overlap = 0
+PHY-3002 : Step(270): len = 742723, overlap = 0
+PHY-3002 : Step(271): len = 742706, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16022/17630.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 921320, over cnt = 94(0%), over = 112, worst = 5
+PHY-1002 : len = 921496, over cnt = 44(0%), over = 48, worst = 4
+PHY-1002 : len = 922000, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 922184, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.657432s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (104.6%)
+
+PHY-1001 : Congestion index: top1 = 55.04, top5 = 49.39, top10 = 46.68, top15 = 44.83.
+PHY-3001 : End congestion estimation; 1.000205s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (103.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.919630s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00045968
+PHY-3002 : Step(272): len = 742691, overlap = 1.75
+PHY-3002 : Step(273): len = 742734, overlap = 1.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005744s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 742783, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.067353s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (92.8%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 4, deltaY = 0, maxDist = 2.
+PHY-3001 : Final: Len = 742827, Over = 0
+PHY-3001 : End incremental placement; 6.623341s wall, 6.890625s user + 0.093750s system = 6.984375s CPU (105.5%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.816412s wall, 12.390625s user + 0.093750s system = 12.484375s CPU (115.4%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 742, peak = 743.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16016/17630.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 922168, over cnt = 57(0%), over = 74, worst = 4
+PHY-1002 : len = 922344, over cnt = 24(0%), over = 27, worst = 2
+PHY-1002 : len = 922616, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 922736, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 922752, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.912525s wall, 1.000000s user + 0.015625s system = 1.015625s CPU (111.3%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.38, top10 = 46.62, top15 = 44.79.
+OPT-1001 : End congestion update; 1.275360s wall, 1.359375s user + 0.015625s system = 1.375000s CPU (107.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.774240s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (98.9%)
+
+OPT-0007 : Start: WNS -1086 TNS -1721 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 746757, Over = 0
+PHY-3001 : Spreading special nets. 28 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.078671s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (99.3%)
+
+PHY-3001 : 35 instances has been re-located, deltaX = 19, deltaY = 20, maxDist = 6.
+PHY-3001 : Final: Len = 747093, Over = 0
+PHY-3001 : End incremental legalization; 0.451923s wall, 0.437500s user + 0.015625s system = 0.453125s CPU (100.3%)
+
+OPT-0007 : Iter 1: improved WNS -986 TNS -1521 NUM_FEPS 2 with 53 cells processed and 9773 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747839, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.067305s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (92.9%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 9, deltaY = 10, maxDist = 5.
+PHY-3001 : Final: Len = 747939, Over = 0
+PHY-3001 : End incremental legalization; 0.449954s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.7%)
+
+OPT-0007 : Iter 2: improved WNS -936 TNS -1471 NUM_FEPS 2 with 20 cells processed and 1573 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 748129, Over = 0
+PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064779s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.5%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 12, deltaY = 7, maxDist = 7.
+PHY-3001 : Final: Len = 747949, Over = 0
+PHY-3001 : End incremental legalization; 0.418141s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.9%)
+
+OPT-0007 : Iter 3: improved WNS -936 TNS -1471 NUM_FEPS 2 with 15 cells processed and 349 slack improved
+OPT-1001 : End path based optimization; 3.906012s wall, 3.953125s user + 0.046875s system = 4.000000s CPU (102.4%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 742, peak = 743.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.806124s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (96.9%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15705/17630.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 926848, over cnt = 191(0%), over = 258, worst = 4
+PHY-1002 : len = 927192, over cnt = 104(0%), over = 111, worst = 2
+PHY-1002 : len = 927784, over cnt = 33(0%), over = 34, worst = 2
+PHY-1002 : len = 928328, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 928456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.961342s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (102.4%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.55, top10 = 46.70, top15 = 44.82.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.787686s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.2%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -986 TNS -1571 NUM_FEPS 2
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.482759
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -986ps with logic level 2
+RUN-1001 : #2 path slack -940ps with logic level 2
+RUN-1001 : extra opt step will be enabled to improve QoR
+RUN-1001 : 0 HFN exist on timing critical paths out of 17630 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 17630 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747949, Over = 0
+PHY-3001 : End spreading; 0.065259s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.8%)
+
+PHY-3001 : Final: Len = 747949, Over = 0
+PHY-3001 : End incremental legalization; 0.421445s wall, 0.515625s user + 0.031250s system = 0.546875s CPU (129.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.805812s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (100.8%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16057/17630.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.141990s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.0%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.55, top10 = 46.70, top15 = 44.82.
+OPT-1001 : End congestion update; 0.475537s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (98.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.760751s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.6%)
+
+OPT-0007 : Start: WNS -986 TNS -1571 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747889, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.075859s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (103.0%)
+
+PHY-3001 : 3 instances has been re-located, deltaX = 3, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 747949, Over = 0
+PHY-3001 : End incremental legalization; 0.485966s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (135.0%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1471 NUM_FEPS 2 with 3 cells processed and 150 slack improved
+OPT-0007 : Iter 2: improved WNS -936 TNS -1471 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.855841s wall, 2.093750s user + 0.000000s system = 2.093750s CPU (112.8%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 742, peak = 743.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16057/17630.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.169442s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (92.2%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.55, top10 = 46.70, top15 = 44.82.
+OPT-1001 : End congestion update; 0.590557s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (97.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.833191s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (101.3%)
+
+OPT-0007 : Start: WNS -986 TNS -1571 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747909, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066075s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.6%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 2, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 747949, Over = 0
+PHY-3001 : End incremental legalization; 0.428158s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (124.1%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1471 NUM_FEPS 2 with 2 cells processed and 100 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747909, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064488s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.9%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 2, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 747949, Over = 0
+PHY-3001 : End incremental legalization; 0.424749s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (125.1%)
+
+OPT-0007 : Iter 2: improved WNS -936 TNS -1471 NUM_FEPS 2 with 2 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS -936 TNS -1471 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 2.628235s wall, 2.812500s user + 0.000000s system = 2.812500s CPU (107.0%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 742, peak = 743.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.803381s wall, 0.781250s user + 0.015625s system = 0.796875s CPU (99.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 739, reserve = 742, peak = 743.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.128367s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.7%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16057/17630.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.145366s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.7%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.55, top10 = 46.70, top15 = 44.82.
+RUN-1001 : End congestion update; 0.482550s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (97.1%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.614286s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.7%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 742, peak = 743.
+OPT-1001 : End physical optimization; 28.258080s wall, 30.453125s user + 0.250000s system = 30.703125s CPU (108.7%)
+
+RUN-1003 : finish command "place" in 71.802909s wall, 100.937500s user + 5.593750s system = 106.531250s CPU (148.4%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 619 MB, peak memory is 743 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.768222s wall, 3.109375s user + 0.015625s system = 3.125000s CPU (176.7%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 620 MB, peak memory is 743 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6932 instances
+RUN-1001 : 3392 mslices, 3389 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17630 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9886 nets have 2 pins
+RUN-1001 : 6040 nets have [3 - 5] pins
+RUN-1001 : 1001 nets have [6 - 10] pins
+RUN-1001 : 321 nets have [11 - 20] pins
+RUN-1001 : 354 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74216, tnet num: 17452, tinst num: 6930, tnode num: 96760, tedge num: 124559.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.769299s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (99.8%)
+
+RUN-1004 : used memory is 604 MB, reserved memory is 605 MB, peak memory is 743 MB
+PHY-1001 : 3392 mslices, 3389 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 861432, over cnt = 2754(7%), over = 4563, worst = 8
+PHY-1002 : len = 876872, over cnt = 1730(4%), over = 2557, worst = 6
+PHY-1002 : len = 899896, over cnt = 526(1%), over = 774, worst = 6
+PHY-1002 : len = 912264, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 912440, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.203294s wall, 4.343750s user + 0.078125s system = 4.421875s CPU (138.0%)
+
+PHY-1001 : Congestion index: top1 = 54.20, top5 = 49.29, top10 = 46.64, top15 = 44.74.
+PHY-1001 : End global routing; 3.574955s wall, 4.718750s user + 0.078125s system = 4.796875s CPU (134.2%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 710, reserve = 717, peak = 743.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 985, reserve = 991, peak = 985.
+PHY-1001 : End build detailed router design. 4.285590s wall, 4.250000s user + 0.046875s system = 4.296875s CPU (100.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 266520, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.543466s wall, 5.515625s user + 0.000000s system = 5.515625s CPU (99.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 266576, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.456184s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (102.8%)
+
+PHY-1001 : Current memory(MB): used = 1021, reserve = 1028, peak = 1021.
+PHY-1001 : End phase 1; 6.012081s wall, 5.984375s user + 0.000000s system = 5.984375s CPU (99.5%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.38544e+06, over cnt = 1940(0%), over = 1945, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1038, reserve = 1042, peak = 1038.
+PHY-1001 : End initial routed; 31.065055s wall, 66.125000s user + 0.296875s system = 66.421875s CPU (213.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 11/16553(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.799 | -4.467 | 4
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.475285s wall, 3.468750s user + 0.000000s system = 3.468750s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1054, reserve = 1059, peak = 1054.
+PHY-1001 : End phase 2; 34.540448s wall, 69.593750s user + 0.296875s system = 69.890625s CPU (202.3%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -1.797ns STNS -3.968ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.160822s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (106.9%)
+
+PHY-1022 : len = 2.38541e+06, over cnt = 1942(0%), over = 1947, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.456183s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (102.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.35104e+06, over cnt = 800(0%), over = 801, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.258916s wall, 4.187500s user + 0.000000s system = 4.187500s CPU (185.4%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.34865e+06, over cnt = 253(0%), over = 254, worst = 2, crit = 0
+PHY-1001 : End DR Iter 2; 0.761614s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (141.6%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.34642e+06, over cnt = 33(0%), over = 33, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.752782s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (128.7%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.34658e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.332144s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (98.8%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.34667e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.188044s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16553(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.797 | -3.968 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.491980s wall, 3.484375s user + 0.000000s system = 3.484375s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 586 feed throughs used by 421 nets
+PHY-1001 : End commit to database; 2.400501s wall, 2.406250s user + 0.000000s system = 2.406250s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1157, reserve = 1166, peak = 1157.
+PHY-1001 : End phase 3; 11.067591s wall, 13.500000s user + 0.000000s system = 13.500000s CPU (122.0%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.797ns STNS -3.968ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.151432s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (103.2%)
+
+PHY-1022 : len = 2.34667e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.409648s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.2%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.797ns, -3.968ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16553(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.797 | -3.968 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.554722s wall, 3.562500s user + 0.000000s system = 3.562500s CPU (100.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 586 feed throughs used by 421 nets
+PHY-1001 : End commit to database; 2.510793s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (99.6%)
+
+PHY-1001 : Current memory(MB): used = 1166, reserve = 1175, peak = 1166.
+PHY-1001 : End phase 4; 6.505379s wall, 6.500000s user + 0.000000s system = 6.500000s CPU (99.9%)
+
+PHY-1003 : Routed, final wirelength = 2.34667e+06
+PHY-1001 : Current memory(MB): used = 1169, reserve = 1177, peak = 1169.
+PHY-1001 : End export database. 0.065920s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.8%)
+
+PHY-1001 : End detail routing; 62.899885s wall, 100.312500s user + 0.343750s system = 100.656250s CPU (160.0%)
+
+RUN-1003 : finish command "route" in 69.437223s wall, 107.968750s user + 0.453125s system = 108.421875s CPU (156.1%)
+
+RUN-1004 : used memory is 1090 MB, reserved memory is 1098 MB, peak memory is 1169 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10320 out of 19600 52.65%
+#reg 9363 out of 19600 47.77%
+#le 12661
+ #lut only 3298 out of 12661 26.05%
+ #reg only 2341 out of 12661 18.49%
+ #lut® 7022 out of 12661 55.46%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1795
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1417
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1355
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 967
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 139
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg42_syn_219.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_b/u_ADconfig/reg1_syn_191.f0 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P133 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P4 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P138 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P16 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P152 LVCMOS33 8 N/A NONE
+ paper_out OUTPUT P17 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P15 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P104 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12661 |9293 |1027 |9394 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |545 |451 |23 |442 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |98 |83 |4 |90 |4 |0 |
+| U_crc16_24b |crc16_24b |29 |29 |0 |19 |0 |0 |
+| U_ecc_gen |ecc_gen |14 |14 |0 |10 |0 |0 |
+| exdev_ctl_a |exdev_ctl |767 |373 |96 |581 |0 |0 |
+| u_ADconfig |AD_config |188 |139 |25 |142 |0 |0 |
+| u_gen_sp |gen_sp |263 |160 |71 |123 |0 |0 |
+| exdev_ctl_b |exdev_ctl |752 |423 |96 |556 |0 |0 |
+| u_ADconfig |AD_config |178 |140 |25 |126 |0 |0 |
+| u_gen_sp |gen_sp |262 |168 |71 |118 |0 |0 |
+| sampling_fe_a |sampling_fe |3094 |2433 |306 |2032 |25 |0 |
+| u0_soft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |183 |97 |17 |141 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort |2875 |2311 |289 |1855 |25 |0 |
+| rddpram_ctl |rddpram_ctl |5 |5 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2499 |2063 |253 |1538 |22 |0 |
+| channelPart |channel_part_8478 |133 |130 |3 |122 |0 |0 |
+| fifo_adc |fifo_adc |62 |53 |9 |44 |0 |0 |
+| ram_switch |ram_switch |1994 |1633 |197 |1144 |0 |0 |
+| adc_addr_gen |adc_addr_gen |244 |217 |27 |114 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |8 |5 |3 |4 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |29 |26 |3 |14 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |9 |0 |0 |
+| insert |insert |953 |620 |170 |654 |0 |0 |
+| ram_switch_state |ram_switch_state |797 |796 |0 |376 |0 |0 |
+| read_ram_i |read_ram |265 |209 |44 |186 |0 |0 |
+| read_ram_addr |read_ram_addr |213 |173 |40 |147 |0 |0 |
+| read_ram_data |read_ram_data |51 |35 |4 |38 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |339 |233 |36 |280 |3 |0 |
+| u0_soft_n |cdc_sync |7 |7 |0 |7 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3367 |2648 |349 |2114 |25 |1 |
+| u0_soft_n |cdc_sync |6 |1 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |166 |113 |17 |130 |0 |0 |
+| u0_soft_n |cdc_sync |6 |1 |0 |6 |0 |0 |
+| u_sort |sort_rev |3165 |2522 |332 |1948 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |3 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |7 |2 |0 |7 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2731 |2228 |290 |1587 |22 |1 |
+| channelPart |channel_part_8478 |238 |235 |3 |135 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
+| ram_switch |ram_switch |1983 |1621 |197 |1142 |0 |0 |
+| adc_addr_gen |adc_addr_gen |221 |194 |27 |105 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |30 |27 |3 |18 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |8 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |21 |18 |3 |10 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| insert |insert |974 |641 |170 |669 |0 |0 |
+| ram_switch_state |ram_switch_state |788 |786 |0 |368 |0 |0 |
+| read_ram_i |read_ram_rev |424 |303 |81 |240 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |291 |206 |73 |159 |0 |0 |
+| read_ram_data |read_ram_data_rev |133 |97 |8 |81 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9824
+ #2 2 3937
+ #3 3 1458
+ #4 4 642
+ #5 5-10 1062
+ #6 11-50 587
+ #7 51-100 24
+ #8 >500 1
+ Average 2.91
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.179280s wall, 3.765625s user + 0.015625s system = 3.781250s CPU (173.5%)
+
+RUN-1004 : used memory is 1091 MB, reserved memory is 1099 MB, peak memory is 1169 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74216, tnet num: 17452, tinst num: 6930, tnode num: 96760, tedge num: 124559.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.739411s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (100.6%)
+
+RUN-1004 : used memory is 1096 MB, reserved memory is 1104 MB, peak memory is 1169 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.583424s wall, 1.562500s user + 0.015625s system = 1.578125s CPU (99.7%)
+
+RUN-1004 : used memory is 1099 MB, reserved memory is 1106 MB, peak memory is 1169 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6930
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17630, pip num: 174550
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 586
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3249 valid insts, and 483475 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.850289s wall, 64.062500s user + 0.187500s system = 64.250000s CPU (652.3%)
+
+RUN-1004 : used memory is 1267 MB, reserved memory is 1270 MB, peak memory is 1383 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240218_161224.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240123_172602.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240123_172602.log
new file mode 100644
index 0000000..fb54eee
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240123_172602.log
@@ -0,0 +1,444 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Tue Jan 23 17:26:03 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1698)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1699)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1700)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1701)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1703)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1704)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1698)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1699)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1700)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1701)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1703)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1704)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(677)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1009)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1698)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1699)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1700)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1701)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1703)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1704)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(192)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(36)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(194)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(38)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-8007 ERROR: external reference 'debug' remains unresolved in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
+HDL-1007 : module 'huagao_mipi_top' remains a black box due to errors in its contents in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240123_172602.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240123_172649.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240123_172649.log
new file mode 100644
index 0000000..479d273
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240123_172649.log
@@ -0,0 +1,444 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Tue Jan 23 17:26:49 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1698)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1699)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1700)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1701)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1703)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1704)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1698)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1699)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1700)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1701)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1703)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1704)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(677)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1009)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1698)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1699)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1700)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1701)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1703)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1704)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(192)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(36)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(194)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(38)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-8007 ERROR: external reference 'debug' remains unresolved in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
+HDL-1007 : module 'huagao_mipi_top' remains a black box due to errors in its contents in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240123_172649.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240123_172801.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240123_172801.log
new file mode 100644
index 0000000..4af59be
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240123_172801.log
@@ -0,0 +1,441 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Tue Jan 23 17:28:01 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1699)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1700)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1701)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1703)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1704)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1699)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1700)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1701)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1703)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1704)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(677)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1009)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1699)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1700)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1701)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1703)
+HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1704)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(192)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(36)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(194)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(38)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-8007 ERROR: external reference 'debug' remains unresolved in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
+HDL-1007 : module 'huagao_mipi_top' remains a black box due to errors in its contents in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240123_172801.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240123_172844.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240123_172844.log
new file mode 100644
index 0000000..0926bf3
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240123_172844.log
@@ -0,0 +1,1880 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Tue Jan 23 17:28:44 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(677)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1009)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(192)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(36)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(194)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(38)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.106914s wall, 1.062500s user + 0.046875s system = 1.109375s CPU (100.2%)
+
+RUN-1004 : used memory is 192 MB, reserved memory is 169 MB, peak memory is 232 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 20 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_out has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53810/19108 useful/useless nets, 20665/1812 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42353/8970 useful/useless nets, 10953/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(283) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40025/364 useful/useless nets, 37222/552 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3817 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6180 instances.
+SYN-1015 : Optimize round 1, 29670 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25763/1547 useful/useless nets, 23052/7489 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 117 instances.
+SYN-1015 : Optimize round 2, 9332 better
+SYN-1032 : 25515/80 useful/useless nets, 22836/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25416/99 useful/useless nets, 22750/7 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25138/20 useful/useless nets, 22488/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 19.597321s wall, 17.390625s user + 2.093750s system = 19.484375s CPU (99.4%)
+
+RUN-1004 : used memory is 330 MB, reserved memory is 303 MB, peak memory is 348 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 13930
+ #and 2463
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 204
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 615
+ #FADD 0
+ #DFF 9090
+ #LATCH 6
+#MACRO_ADD 496
+#MACRO_EQ 225
+#MACRO_MULT 4
+#MACRO_MUX 4819
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4834 |9096 |798 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1838 |1894 |269 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |10 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1794 |1712 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1539 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |112 |164 |32 |
+| read_ram_addr |read_ram_addr |64 |127 |22 |
+| read_ram_data |read_ram_data |46 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1799 |1958 |267 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1757 |1776 |257 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1503 |1405 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |82 |178 |32 |
+| read_ram_addr |read_ram_addr_rev |50 |136 |22 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.068084s wall, 1.718750s user + 0.031250s system = 1.750000s CPU (163.8%)
+
+RUN-1004 : used memory is 339 MB, reserved memory is 313 MB, peak memory is 398 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | low | medium | *
+RUN-1001 : opt_timing | high | auto | *
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25172/24 useful/useless nets, 22537/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25490/670 useful/useless nets, 22871/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 313 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28922/338 useful/useless nets, 26304/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 497 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12104 instances.
+SYN-1032 : 36464/295 useful/useless nets, 33740/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121622, tnet num: 36466, tinst num: 33740, tnode num: 155584, tedge num: 179067.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 1.402041s wall, 1.406250s user + 0.000000s system = 1.406250s CPU (100.3%)
+
+RUN-1004 : used memory is 517 MB, reserved memory is 495 MB, peak memory is 517 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36466 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7517 (3.86), #lev = 10 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7464 (3.96), #lev = 7 (3.07)
+SYN-3001 : Logic optimization runtime opt = 1.32 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 18898 instances into 7492 LUTs, name keeping = 56%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 10067
+ #lut4 5290
+ #lut5 2222
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2555
+
+Utilization Statistics
+#lut 10067 out of 19600 51.36%
+#reg 9170 out of 19600 46.79%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 20
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |7512 |2555 |9203 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |335 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |283 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |98 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |127 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |279 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |91 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |130 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2109 |738 |1894 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |2039 |691 |1712 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |1909 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |147 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
+| ram_switch |ram_switch |1482 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1088 |0 |216 |0 |0 |
+| read_ram_i |read_ram |193 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |162 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |30 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |123 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2301 |751 |1958 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2231 |704 |1776 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2106 |628 |1405 |22 |1 |
+| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1477 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1083 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |394 |171 |178 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |175 |145 |136 |0 |0 |
+| read_ram_data |read_ram_data_rev |219 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9170 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 67.005920s wall, 66.656250s user + 0.125000s system = 66.781250s CPU (99.7%)
+
+RUN-1004 : used memory is 396 MB, reserved memory is 389 MB, peak memory is 699 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.598255s wall, 2.750000s user + 0.031250s system = 2.781250s CPU (174.0%)
+
+RUN-1004 : used memory is 403 MB, reserved memory is 386 MB, peak memory is 699 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240123_172844.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240123_173633.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240123_173633.log
new file mode 100644
index 0000000..eb4d26c
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240123_173633.log
@@ -0,0 +1,1877 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Tue Jan 23 17:36:33 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(192)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(36)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(194)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(38)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.217825s wall, 1.203125s user + 0.015625s system = 1.218750s CPU (100.1%)
+
+RUN-1004 : used memory is 193 MB, reserved memory is 173 MB, peak memory is 233 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 20 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_out has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53811/19108 useful/useless nets, 20667/1811 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42352/8970 useful/useless nets, 10953/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(283) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40025/363 useful/useless nets, 37222/552 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3817 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6180 instances.
+SYN-1015 : Optimize round 1, 29670 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25763/1547 useful/useless nets, 23052/7489 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 117 instances.
+SYN-1015 : Optimize round 2, 9332 better
+SYN-1032 : 25515/80 useful/useless nets, 22836/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25416/99 useful/useless nets, 22750/7 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25138/20 useful/useless nets, 22488/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 19.688294s wall, 17.546875s user + 2.109375s system = 19.656250s CPU (99.8%)
+
+RUN-1004 : used memory is 330 MB, reserved memory is 303 MB, peak memory is 348 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 13930
+ #and 2463
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 204
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 615
+ #FADD 0
+ #DFF 9090
+ #LATCH 6
+#MACRO_ADD 496
+#MACRO_EQ 225
+#MACRO_MULT 4
+#MACRO_MUX 4819
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4834 |9096 |798 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1837 |1894 |269 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |10 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1793 |1712 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1538 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |112 |164 |32 |
+| read_ram_addr |read_ram_addr |64 |127 |22 |
+| read_ram_data |read_ram_data |46 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1799 |1958 |267 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1757 |1776 |257 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1503 |1405 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |82 |178 |32 |
+| read_ram_addr |read_ram_addr_rev |50 |136 |22 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.128275s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (156.5%)
+
+RUN-1004 : used memory is 325 MB, reserved memory is 298 MB, peak memory is 399 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | low | medium | *
+RUN-1001 : opt_timing | high | auto | *
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25172/24 useful/useless nets, 22537/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25490/670 useful/useless nets, 22871/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 313 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28922/338 useful/useless nets, 26304/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 497 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12104 instances.
+SYN-1032 : 36464/295 useful/useless nets, 33740/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121626, tnet num: 36466, tinst num: 33740, tnode num: 155591, tedge num: 179075.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 1.336917s wall, 1.281250s user + 0.031250s system = 1.312500s CPU (98.2%)
+
+RUN-1004 : used memory is 516 MB, reserved memory is 495 MB, peak memory is 516 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36466 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7522 (3.86), #lev = 9 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7440 (3.97), #lev = 7 (3.07)
+SYN-3001 : Logic optimization runtime opt = 1.34 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 18898 instances into 7468 LUTs, name keeping = 56%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 10043
+ #lut4 5250
+ #lut5 2238
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2555
+
+Utilization Statistics
+#lut 10043 out of 19600 51.24%
+#reg 9170 out of 19600 46.79%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |7488 |2555 |9204 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |339 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |287 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |100 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |129 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |275 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |91 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |126 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2108 |738 |1894 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |2038 |691 |1712 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |1909 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |147 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
+| ram_switch |ram_switch |1483 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1089 |0 |216 |0 |0 |
+| read_ram_i |read_ram |192 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |161 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |30 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |122 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2299 |751 |1958 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2229 |704 |1776 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2104 |628 |1405 |22 |1 |
+| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1478 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1084 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |391 |171 |178 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |177 |145 |136 |0 |0 |
+| read_ram_data |read_ram_data_rev |214 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9170 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 66.771529s wall, 66.015625s user + 0.453125s system = 66.468750s CPU (99.5%)
+
+RUN-1004 : used memory is 393 MB, reserved memory is 378 MB, peak memory is 700 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.675305s wall, 2.937500s user + 0.000000s system = 2.937500s CPU (175.3%)
+
+RUN-1004 : used memory is 403 MB, reserved memory is 384 MB, peak memory is 700 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240123_173633.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240124_150444.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240124_150444.log
new file mode 100644
index 0000000..33a95b9
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240124_150444.log
@@ -0,0 +1,1536 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Wed Jan 24 15:04:44 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(102)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="105.000",CLKC0_DIV=7,CLKC1_DIV=2,CLKC2_DIV=5,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=6,CLKC2_CPHASE=4,GMC_GAIN=6,GMC_TEST=15,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=2,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(192)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(36)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(194)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(38)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.068474s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (99.4%)
+
+RUN-1004 : used memory is 192 MB, reserved memory is 171 MB, peak memory is 233 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 20 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_out has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53811/19108 useful/useless nets, 20667/1811 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42352/8970 useful/useless nets, 10953/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(283) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40025/363 useful/useless nets, 37222/552 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3817 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6180 instances.
+SYN-1015 : Optimize round 1, 29670 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25763/1547 useful/useless nets, 23052/7489 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 117 instances.
+SYN-1015 : Optimize round 2, 9332 better
+SYN-1032 : 25515/80 useful/useless nets, 22836/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25416/99 useful/useless nets, 22750/7 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25138/20 useful/useless nets, 22488/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 19.047521s wall, 16.671875s user + 2.359375s system = 19.031250s CPU (99.9%)
+
+RUN-1004 : used memory is 331 MB, reserved memory is 303 MB, peak memory is 349 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 13930
+ #and 2463
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 204
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 615
+ #FADD 0
+ #DFF 9090
+ #LATCH 6
+#MACRO_ADD 496
+#MACRO_EQ 225
+#MACRO_MULT 4
+#MACRO_MUX 4819
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4834 |9096 |798 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1837 |1894 |269 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |10 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1793 |1712 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1538 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |112 |164 |32 |
+| read_ram_addr |read_ram_addr |64 |127 |22 |
+| read_ram_data |read_ram_data |46 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1799 |1958 |267 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1757 |1776 |257 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1503 |1405 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |82 |178 |32 |
+| read_ram_addr |read_ram_addr_rev |50 |136 |22 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.043906s wall, 1.687500s user + 0.015625s system = 1.703125s CPU (163.1%)
+
+RUN-1004 : used memory is 345 MB, reserved memory is 318 MB, peak memory is 399 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets O_clk_lp_n"
+RUN-1002 : start command "get_regs ubus_lpclk_d0[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets O_clk_lp_p"
+USR-8132 ERROR: No net match the pattern: O_clk_lp_p.
+USR-8159 ERROR: ../../hg_anlogic.sdc Line: 24, set_false_path -from [get_nets {O_clk_lp_p}] -to [get_regs {ubus_lpclk_d0[*]}] fails.
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240124_150444.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240124_150530.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240124_150530.log
new file mode 100644
index 0000000..4f7dccb
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240124_150530.log
@@ -0,0 +1,1871 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Wed Jan 24 15:05:30 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(102)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="105.000",CLKC0_DIV=7,CLKC1_DIV=2,CLKC2_DIV=5,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=6,CLKC2_CPHASE=4,GMC_GAIN=6,GMC_TEST=15,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=2,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(192)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(36)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(194)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(38)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.060625s wall, 1.031250s user + 0.015625s system = 1.046875s CPU (98.7%)
+
+RUN-1004 : used memory is 193 MB, reserved memory is 170 MB, peak memory is 233 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 20 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_out has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53811/19108 useful/useless nets, 20667/1811 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42352/8970 useful/useless nets, 10953/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(283) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40025/363 useful/useless nets, 37222/552 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3817 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6180 instances.
+SYN-1015 : Optimize round 1, 29670 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25763/1547 useful/useless nets, 23052/7489 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 117 instances.
+SYN-1015 : Optimize round 2, 9332 better
+SYN-1032 : 25515/80 useful/useless nets, 22836/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25416/99 useful/useless nets, 22750/7 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25138/20 useful/useless nets, 22488/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 18.456459s wall, 16.453125s user + 1.968750s system = 18.421875s CPU (99.8%)
+
+RUN-1004 : used memory is 332 MB, reserved memory is 304 MB, peak memory is 351 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 13930
+ #and 2463
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 204
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 615
+ #FADD 0
+ #DFF 9090
+ #LATCH 6
+#MACRO_ADD 496
+#MACRO_EQ 225
+#MACRO_MULT 4
+#MACRO_MUX 4819
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4834 |9096 |798 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1837 |1894 |269 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |10 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1793 |1712 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1538 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |112 |164 |32 |
+| read_ram_addr |read_ram_addr |64 |127 |22 |
+| read_ram_data |read_ram_data |46 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1799 |1958 |267 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1757 |1776 |257 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1503 |1405 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |82 |178 |32 |
+| read_ram_addr |read_ram_addr_rev |50 |136 |22 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.043849s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (166.2%)
+
+RUN-1004 : used memory is 326 MB, reserved memory is 298 MB, peak memory is 400 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | low | medium | *
+RUN-1001 : opt_timing | high | auto | *
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25172/24 useful/useless nets, 22537/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25490/670 useful/useless nets, 22871/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 313 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28922/338 useful/useless nets, 26304/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 497 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12104 instances.
+SYN-1032 : 36464/295 useful/useless nets, 33740/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121626, tnet num: 36466, tinst num: 33740, tnode num: 155591, tedge num: 179075.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 1.284878s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (99.7%)
+
+RUN-1004 : used memory is 516 MB, reserved memory is 494 MB, peak memory is 516 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36466 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 4 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7522 (3.86), #lev = 9 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7440 (3.97), #lev = 7 (3.07)
+SYN-3001 : Logic optimization runtime opt = 1.31 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 18898 instances into 7468 LUTs, name keeping = 56%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 10043
+ #lut4 5250
+ #lut5 2238
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2555
+
+Utilization Statistics
+#lut 10043 out of 19600 51.24%
+#reg 9170 out of 19600 46.79%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |7488 |2555 |9204 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |339 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |287 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |100 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |129 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |275 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |91 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |126 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2108 |738 |1894 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |2038 |691 |1712 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |1909 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |147 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
+| ram_switch |ram_switch |1483 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1089 |0 |216 |0 |0 |
+| read_ram_i |read_ram |192 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |161 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |30 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |122 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2299 |751 |1958 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2229 |704 |1776 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2104 |628 |1405 |22 |1 |
+| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1478 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1084 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |391 |171 |178 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |177 |145 |136 |0 |0 |
+| read_ram_data |read_ram_data_rev |214 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9170 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 64.248064s wall, 63.375000s user + 0.406250s system = 63.781250s CPU (99.3%)
+
+RUN-1004 : used memory is 394 MB, reserved memory is 385 MB, peak memory is 699 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.697501s wall, 2.828125s user + 0.062500s system = 2.890625s CPU (170.3%)
+
+RUN-1004 : used memory is 404 MB, reserved memory is 386 MB, peak memory is 699 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240124_150530.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240125_160003.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240125_160003.log
new file mode 100644
index 0000000..f05705c
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240125_160003.log
@@ -0,0 +1,1877 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Jan 25 16:00:03 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(192)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(36)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(194)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(38)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.065707s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (101.2%)
+
+RUN-1004 : used memory is 193 MB, reserved memory is 170 MB, peak memory is 233 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 20 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_out has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53810/19109 useful/useless nets, 20666/1812 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42352/8970 useful/useless nets, 10953/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(283) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40025/363 useful/useless nets, 37222/552 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3817 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6180 instances.
+SYN-1015 : Optimize round 1, 29670 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25763/1547 useful/useless nets, 23052/7489 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 117 instances.
+SYN-1015 : Optimize round 2, 9332 better
+SYN-1032 : 25515/80 useful/useless nets, 22836/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25416/99 useful/useless nets, 22750/7 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25138/20 useful/useless nets, 22488/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 19.440043s wall, 16.718750s user + 1.937500s system = 18.656250s CPU (96.0%)
+
+RUN-1004 : used memory is 331 MB, reserved memory is 303 MB, peak memory is 349 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 13930
+ #and 2463
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 204
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 615
+ #FADD 0
+ #DFF 9090
+ #LATCH 6
+#MACRO_ADD 496
+#MACRO_EQ 225
+#MACRO_MULT 4
+#MACRO_MUX 4819
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4834 |9096 |798 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1838 |1894 |269 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |10 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1794 |1712 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1539 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |112 |164 |32 |
+| read_ram_addr |read_ram_addr |64 |127 |22 |
+| read_ram_data |read_ram_data |46 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1799 |1958 |267 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1757 |1776 |257 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1503 |1405 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |82 |178 |32 |
+| read_ram_addr |read_ram_addr_rev |50 |136 |22 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.045803s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (165.8%)
+
+RUN-1004 : used memory is 340 MB, reserved memory is 313 MB, peak memory is 399 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | low | medium | *
+RUN-1001 : opt_timing | high | auto | *
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25172/24 useful/useless nets, 22537/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25490/670 useful/useless nets, 22871/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 313 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28922/338 useful/useless nets, 26304/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 497 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12104 instances.
+SYN-1032 : 36464/295 useful/useless nets, 33740/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121620, tnet num: 36466, tinst num: 33740, tnode num: 155576, tedge num: 179063.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 1.377452s wall, 1.234375s user + 0.046875s system = 1.281250s CPU (93.0%)
+
+RUN-1004 : used memory is 517 MB, reserved memory is 495 MB, peak memory is 517 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36466 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7517 (3.86), #lev = 10 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7464 (3.96), #lev = 7 (3.07)
+SYN-3001 : Logic optimization runtime opt = 1.26 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 18898 instances into 7492 LUTs, name keeping = 56%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 10067
+ #lut4 5290
+ #lut5 2222
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2555
+
+Utilization Statistics
+#lut 10067 out of 19600 51.36%
+#reg 9170 out of 19600 46.79%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |7512 |2555 |9201 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |335 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |283 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |98 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |127 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |279 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |91 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |130 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2109 |738 |1894 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |2039 |691 |1712 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |1909 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |147 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
+| ram_switch |ram_switch |1482 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1088 |0 |216 |0 |0 |
+| read_ram_i |read_ram |193 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |162 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |30 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |123 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2301 |751 |1958 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2231 |704 |1776 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2106 |628 |1405 |22 |1 |
+| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1477 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1083 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |394 |171 |178 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |175 |145 |136 |0 |0 |
+| read_ram_data |read_ram_data_rev |219 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9170 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 60.538581s wall, 59.984375s user + 0.406250s system = 60.390625s CPU (99.8%)
+
+RUN-1004 : used memory is 395 MB, reserved memory is 384 MB, peak memory is 699 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.561119s wall, 2.718750s user + 0.000000s system = 2.718750s CPU (174.2%)
+
+RUN-1004 : used memory is 404 MB, reserved memory is 389 MB, peak memory is 699 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240125_160003.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240126_091044.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240126_091044.log
new file mode 100644
index 0000000..d536dc6
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240126_091044.log
@@ -0,0 +1,1877 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Fri Jan 26 09:10:45 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(192)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(36)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(194)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(38)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.046007s wall, 1.000000s user + 0.046875s system = 1.046875s CPU (100.1%)
+
+RUN-1004 : used memory is 193 MB, reserved memory is 167 MB, peak memory is 233 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 20 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_out has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53810/19109 useful/useless nets, 20666/1812 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42352/8970 useful/useless nets, 10953/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(283) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40025/363 useful/useless nets, 37222/552 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3817 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6180 instances.
+SYN-1015 : Optimize round 1, 29670 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25763/1547 useful/useless nets, 23052/7489 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 117 instances.
+SYN-1015 : Optimize round 2, 9332 better
+SYN-1032 : 25515/80 useful/useless nets, 22836/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25416/99 useful/useless nets, 22750/7 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25138/20 useful/useless nets, 22488/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 18.694240s wall, 16.625000s user + 1.984375s system = 18.609375s CPU (99.5%)
+
+RUN-1004 : used memory is 331 MB, reserved memory is 303 MB, peak memory is 349 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 13930
+ #and 2463
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 204
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 615
+ #FADD 0
+ #DFF 9090
+ #LATCH 6
+#MACRO_ADD 496
+#MACRO_EQ 225
+#MACRO_MULT 4
+#MACRO_MUX 4819
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4834 |9096 |798 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1838 |1894 |269 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |10 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1794 |1712 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1539 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |112 |164 |32 |
+| read_ram_addr |read_ram_addr |64 |127 |22 |
+| read_ram_data |read_ram_data |46 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1799 |1958 |267 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1757 |1776 |257 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1503 |1405 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |82 |178 |32 |
+| read_ram_addr |read_ram_addr_rev |50 |136 |22 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.106401s wall, 1.718750s user + 0.015625s system = 1.734375s CPU (156.8%)
+
+RUN-1004 : used memory is 340 MB, reserved memory is 313 MB, peak memory is 399 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | low | medium | *
+RUN-1001 : opt_timing | high | auto | *
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25172/24 useful/useless nets, 22537/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25490/670 useful/useless nets, 22871/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 313 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28922/338 useful/useless nets, 26304/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 497 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12104 instances.
+SYN-1032 : 36464/295 useful/useless nets, 33740/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121620, tnet num: 36466, tinst num: 33740, tnode num: 155576, tedge num: 179063.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 1.281505s wall, 1.250000s user + 0.031250s system = 1.281250s CPU (100.0%)
+
+RUN-1004 : used memory is 517 MB, reserved memory is 495 MB, peak memory is 517 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36466 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7517 (3.86), #lev = 10 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7464 (3.96), #lev = 7 (3.07)
+SYN-3001 : Logic optimization runtime opt = 1.26 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 18898 instances into 7492 LUTs, name keeping = 56%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 10067
+ #lut4 5290
+ #lut5 2222
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2555
+
+Utilization Statistics
+#lut 10067 out of 19600 51.36%
+#reg 9170 out of 19600 46.79%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |7512 |2555 |9201 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |335 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |283 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |98 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |127 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |279 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |91 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |130 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2109 |738 |1894 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |2039 |691 |1712 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |1909 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |147 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
+| ram_switch |ram_switch |1482 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1088 |0 |216 |0 |0 |
+| read_ram_i |read_ram |193 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |162 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |30 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |123 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2301 |751 |1958 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2231 |704 |1776 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2106 |628 |1405 |22 |1 |
+| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1477 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1083 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |394 |171 |178 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |175 |145 |136 |0 |0 |
+| read_ram_data |read_ram_data_rev |219 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9170 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 57.472794s wall, 56.906250s user + 0.390625s system = 57.296875s CPU (99.7%)
+
+RUN-1004 : used memory is 397 MB, reserved memory is 389 MB, peak memory is 700 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.544803s wall, 2.671875s user + 0.015625s system = 2.687500s CPU (174.0%)
+
+RUN-1004 : used memory is 403 MB, reserved memory is 387 MB, peak memory is 700 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240126_091044.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240202_135501.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240202_135501.log
new file mode 100644
index 0000000..02b0770
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240202_135501.log
@@ -0,0 +1,1877 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Fri Feb 2 13:55:02 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(192)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(36)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(194)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(38)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.375814s wall, 1.250000s user + 0.046875s system = 1.296875s CPU (94.3%)
+
+RUN-1004 : used memory is 193 MB, reserved memory is 173 MB, peak memory is 233 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 20 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_out has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53810/19109 useful/useless nets, 20666/1812 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42352/8970 useful/useless nets, 10953/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(283) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40025/363 useful/useless nets, 37222/552 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3817 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6180 instances.
+SYN-1015 : Optimize round 1, 29670 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25763/1547 useful/useless nets, 23052/7489 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 117 instances.
+SYN-1015 : Optimize round 2, 9332 better
+SYN-1032 : 25515/80 useful/useless nets, 22836/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25416/99 useful/useless nets, 22750/7 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25138/20 useful/useless nets, 22488/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 24.857364s wall, 21.687500s user + 2.453125s system = 24.140625s CPU (97.1%)
+
+RUN-1004 : used memory is 329 MB, reserved memory is 301 MB, peak memory is 348 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 13930
+ #and 2463
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 204
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 615
+ #FADD 0
+ #DFF 9090
+ #LATCH 6
+#MACRO_ADD 496
+#MACRO_EQ 225
+#MACRO_MULT 4
+#MACRO_MUX 4819
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4834 |9096 |798 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1838 |1894 |269 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |10 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1794 |1712 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1539 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |112 |164 |32 |
+| read_ram_addr |read_ram_addr |64 |127 |22 |
+| read_ram_data |read_ram_data |46 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1799 |1958 |267 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1757 |1776 |257 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1503 |1405 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |82 |178 |32 |
+| read_ram_addr |read_ram_addr_rev |50 |136 |22 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.145535s wall, 1.843750s user + 0.046875s system = 1.890625s CPU (165.0%)
+
+RUN-1004 : used memory is 341 MB, reserved memory is 314 MB, peak memory is 398 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | low | medium | *
+RUN-1001 : opt_timing | high | auto | *
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25172/24 useful/useless nets, 22537/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25490/670 useful/useless nets, 22871/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 313 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28922/338 useful/useless nets, 26304/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 497 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12104 instances.
+SYN-1032 : 36464/295 useful/useless nets, 33740/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121620, tnet num: 36466, tinst num: 33740, tnode num: 155576, tedge num: 179063.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 2.063518s wall, 1.812500s user + 0.046875s system = 1.859375s CPU (90.1%)
+
+RUN-1004 : used memory is 515 MB, reserved memory is 493 MB, peak memory is 515 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36466 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7517 (3.86), #lev = 10 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7464 (3.96), #lev = 7 (3.07)
+SYN-3001 : Logic optimization runtime opt = 1.66 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 18898 instances into 7492 LUTs, name keeping = 56%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 10067
+ #lut4 5290
+ #lut5 2222
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2555
+
+Utilization Statistics
+#lut 10067 out of 19600 51.36%
+#reg 9170 out of 19600 46.79%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |7512 |2555 |9201 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |335 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |283 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |98 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |127 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |279 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |91 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |130 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2109 |738 |1894 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |2039 |691 |1712 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |1909 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |147 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
+| ram_switch |ram_switch |1482 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1088 |0 |216 |0 |0 |
+| read_ram_i |read_ram |193 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |162 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |30 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |123 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2301 |751 |1958 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2231 |704 |1776 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2106 |628 |1405 |22 |1 |
+| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1477 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1083 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |394 |171 |178 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |175 |145 |136 |0 |0 |
+| read_ram_data |read_ram_data_rev |219 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9170 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 110.725697s wall, 106.796875s user + 0.562500s system = 107.359375s CPU (97.0%)
+
+RUN-1004 : used memory is 393 MB, reserved memory is 376 MB, peak memory is 698 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.743743s wall, 2.968750s user + 0.046875s system = 3.015625s CPU (172.9%)
+
+RUN-1004 : used memory is 428 MB, reserved memory is 412 MB, peak memory is 698 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240202_135501.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240218_154027.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240218_154027.log
new file mode 100644
index 0000000..971aa7a
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240218_154027.log
@@ -0,0 +1,1877 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sun Feb 18 15:40:27 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(192)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(36)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(194)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(38)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.017572s wall, 0.984375s user + 0.031250s system = 1.015625s CPU (99.8%)
+
+RUN-1004 : used memory is 192 MB, reserved memory is 173 MB, peak memory is 233 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 20 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_out has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53810/19109 useful/useless nets, 20666/1812 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42352/8970 useful/useless nets, 10953/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(283) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40025/363 useful/useless nets, 37222/552 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3817 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6180 instances.
+SYN-1015 : Optimize round 1, 29670 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25763/1547 useful/useless nets, 23052/7489 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 117 instances.
+SYN-1015 : Optimize round 2, 9332 better
+SYN-1032 : 25515/80 useful/useless nets, 22836/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25416/99 useful/useless nets, 22750/7 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25138/20 useful/useless nets, 22488/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 18.042521s wall, 16.328125s user + 1.703125s system = 18.031250s CPU (99.9%)
+
+RUN-1004 : used memory is 330 MB, reserved memory is 303 MB, peak memory is 348 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 13930
+ #and 2463
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 204
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 615
+ #FADD 0
+ #DFF 9090
+ #LATCH 6
+#MACRO_ADD 496
+#MACRO_EQ 225
+#MACRO_MULT 4
+#MACRO_MUX 4819
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4834 |9096 |798 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1838 |1894 |269 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |10 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1794 |1712 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1539 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |112 |164 |32 |
+| read_ram_addr |read_ram_addr |64 |127 |22 |
+| read_ram_data |read_ram_data |46 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1799 |1958 |267 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1757 |1776 |257 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1503 |1405 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |82 |178 |32 |
+| read_ram_addr |read_ram_addr_rev |50 |136 |22 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.043431s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (163.2%)
+
+RUN-1004 : used memory is 325 MB, reserved memory is 299 MB, peak memory is 398 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | low | medium | *
+RUN-1001 : opt_timing | high | auto | *
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25172/24 useful/useless nets, 22537/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25490/670 useful/useless nets, 22871/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 313 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28922/338 useful/useless nets, 26304/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 497 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12104 instances.
+SYN-1032 : 36464/295 useful/useless nets, 33740/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121620, tnet num: 36466, tinst num: 33740, tnode num: 155576, tedge num: 179063.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 1.241003s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (99.5%)
+
+RUN-1004 : used memory is 517 MB, reserved memory is 495 MB, peak memory is 517 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36466 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7519 (3.86), #lev = 10 (3.15)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7392 (3.95), #lev = 8 (3.06)
+SYN-3001 : Logic optimization runtime opt = 1.25 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 18898 instances into 7420 LUTs, name keeping = 59%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 9995
+ #lut4 5129
+ #lut5 2311
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2555
+
+Utilization Statistics
+#lut 9995 out of 19600 50.99%
+#reg 9170 out of 19600 46.79%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |7440 |2555 |9201 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |339 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |282 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |99 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |125 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |279 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |91 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |130 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2067 |738 |1894 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |1997 |691 |1712 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |1868 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |147 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
+| ram_switch |ram_switch |1448 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1054 |0 |216 |0 |0 |
+| read_ram_i |read_ram |186 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |158 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |27 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |122 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2261 |751 |1958 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2191 |704 |1776 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2066 |628 |1405 |22 |1 |
+| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1441 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1047 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |390 |171 |178 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |176 |145 |136 |0 |0 |
+| read_ram_data |read_ram_data_rev |214 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9170 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 53.737459s wall, 53.406250s user + 0.312500s system = 53.718750s CPU (100.0%)
+
+RUN-1004 : used memory is 395 MB, reserved memory is 387 MB, peak memory is 700 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.554947s wall, 2.687500s user + 0.000000s system = 2.687500s CPU (172.8%)
+
+RUN-1004 : used memory is 403 MB, reserved memory is 384 MB, peak memory is 700 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240218_154027.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240218_160047.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240218_160047.log
new file mode 100644
index 0000000..c2cbba6
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240218_160047.log
@@ -0,0 +1,1877 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sun Feb 18 16:00:47 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(192)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(36)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(194)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(38)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.067577s wall, 1.062500s user + 0.015625s system = 1.078125s CPU (101.0%)
+
+RUN-1004 : used memory is 193 MB, reserved memory is 170 MB, peak memory is 233 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 20 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_out has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53810/19109 useful/useless nets, 20666/1812 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42352/8970 useful/useless nets, 10953/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(283) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40025/363 useful/useless nets, 37222/552 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3817 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6180 instances.
+SYN-1015 : Optimize round 1, 29670 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25763/1547 useful/useless nets, 23052/7489 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 117 instances.
+SYN-1015 : Optimize round 2, 9332 better
+SYN-1032 : 25515/80 useful/useless nets, 22836/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25416/99 useful/useless nets, 22750/7 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25138/20 useful/useless nets, 22488/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 18.340360s wall, 16.937500s user + 1.406250s system = 18.343750s CPU (100.0%)
+
+RUN-1004 : used memory is 330 MB, reserved memory is 302 MB, peak memory is 350 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 13930
+ #and 2463
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 204
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 615
+ #FADD 0
+ #DFF 9090
+ #LATCH 6
+#MACRO_ADD 496
+#MACRO_EQ 225
+#MACRO_MULT 4
+#MACRO_MUX 4819
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4834 |9096 |798 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1838 |1894 |269 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |10 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1794 |1712 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1539 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |112 |164 |32 |
+| read_ram_addr |read_ram_addr |64 |127 |22 |
+| read_ram_data |read_ram_data |46 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1799 |1958 |267 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1757 |1776 |257 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1503 |1405 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |82 |178 |32 |
+| read_ram_addr |read_ram_addr_rev |50 |136 |22 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.050758s wall, 1.687500s user + 0.015625s system = 1.703125s CPU (162.1%)
+
+RUN-1004 : used memory is 325 MB, reserved memory is 300 MB, peak memory is 399 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | low | medium | *
+RUN-1001 : opt_timing | high | auto | *
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25172/24 useful/useless nets, 22537/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25490/670 useful/useless nets, 22871/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 313 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28922/338 useful/useless nets, 26304/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 497 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12104 instances.
+SYN-1032 : 36464/295 useful/useless nets, 33740/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121620, tnet num: 36466, tinst num: 33740, tnode num: 155576, tedge num: 179063.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 1.262405s wall, 1.250000s user + 0.015625s system = 1.265625s CPU (100.3%)
+
+RUN-1004 : used memory is 517 MB, reserved memory is 494 MB, peak memory is 517 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36466 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7519 (3.86), #lev = 10 (3.15)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7392 (3.95), #lev = 8 (3.06)
+SYN-3001 : Logic optimization runtime opt = 1.28 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 18898 instances into 7420 LUTs, name keeping = 59%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 9995
+ #lut4 5129
+ #lut5 2311
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2555
+
+Utilization Statistics
+#lut 9995 out of 19600 50.99%
+#reg 9170 out of 19600 46.79%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |7440 |2555 |9201 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |339 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |282 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |99 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |125 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |279 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |91 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |130 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2067 |738 |1894 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |1997 |691 |1712 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |1868 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |147 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
+| ram_switch |ram_switch |1448 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1054 |0 |216 |0 |0 |
+| read_ram_i |read_ram |186 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |158 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |27 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |122 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2261 |751 |1958 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2191 |704 |1776 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2066 |628 |1405 |22 |1 |
+| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1441 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1047 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |390 |171 |178 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |176 |145 |136 |0 |0 |
+| read_ram_data |read_ram_data_rev |214 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9170 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 59.524799s wall, 58.781250s user + 0.281250s system = 59.062500s CPU (99.2%)
+
+RUN-1004 : used memory is 397 MB, reserved memory is 386 MB, peak memory is 700 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.554293s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (171.9%)
+
+RUN-1004 : used memory is 404 MB, reserved memory is 390 MB, peak memory is 700 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240218_160047.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240218_161055.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240218_161055.log
new file mode 100644
index 0000000..ae5250f
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240218_161055.log
@@ -0,0 +1,1877 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sun Feb 18 16:10:55 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(192)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(36)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(194)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(38)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.135611s wall, 1.109375s user + 0.015625s system = 1.125000s CPU (99.1%)
+
+RUN-1004 : used memory is 193 MB, reserved memory is 171 MB, peak memory is 233 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 20 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_out has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53810/19109 useful/useless nets, 20666/1812 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42352/8970 useful/useless nets, 10953/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(283) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40025/363 useful/useless nets, 37222/552 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3817 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6180 instances.
+SYN-1015 : Optimize round 1, 29670 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25763/1547 useful/useless nets, 23052/7489 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 117 instances.
+SYN-1015 : Optimize round 2, 9332 better
+SYN-1032 : 25515/80 useful/useless nets, 22836/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25416/99 useful/useless nets, 22750/7 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25138/20 useful/useless nets, 22488/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 19.412269s wall, 17.515625s user + 1.875000s system = 19.390625s CPU (99.9%)
+
+RUN-1004 : used memory is 330 MB, reserved memory is 302 MB, peak memory is 350 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 13930
+ #and 2463
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 204
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 615
+ #FADD 0
+ #DFF 9090
+ #LATCH 6
+#MACRO_ADD 496
+#MACRO_EQ 225
+#MACRO_MULT 4
+#MACRO_MUX 4819
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4834 |9096 |798 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1838 |1894 |269 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |10 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1794 |1712 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1539 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |112 |164 |32 |
+| read_ram_addr |read_ram_addr |64 |127 |22 |
+| read_ram_data |read_ram_data |46 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1799 |1958 |267 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1757 |1776 |257 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1503 |1405 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |82 |178 |32 |
+| read_ram_addr |read_ram_addr_rev |50 |136 |22 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.150280s wall, 1.781250s user + 0.015625s system = 1.796875s CPU (156.2%)
+
+RUN-1004 : used memory is 339 MB, reserved memory is 312 MB, peak memory is 399 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | low | medium | *
+RUN-1001 : opt_timing | high | auto | *
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25172/24 useful/useless nets, 22537/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25490/670 useful/useless nets, 22871/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 313 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28922/338 useful/useless nets, 26304/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 497 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12104 instances.
+SYN-1032 : 36464/295 useful/useless nets, 33740/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121620, tnet num: 36466, tinst num: 33740, tnode num: 155576, tedge num: 179063.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 1.483913s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (99.0%)
+
+RUN-1004 : used memory is 518 MB, reserved memory is 495 MB, peak memory is 518 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36466 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7519 (3.86), #lev = 10 (3.15)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7392 (3.95), #lev = 8 (3.06)
+SYN-3001 : Logic optimization runtime opt = 1.35 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 18898 instances into 7420 LUTs, name keeping = 59%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 9995
+ #lut4 5129
+ #lut5 2311
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2555
+
+Utilization Statistics
+#lut 9995 out of 19600 50.99%
+#reg 9170 out of 19600 46.79%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |7440 |2555 |9201 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |339 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |282 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |99 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |125 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |279 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |91 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |130 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2067 |738 |1894 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |1997 |691 |1712 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |1868 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |147 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
+| ram_switch |ram_switch |1448 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1054 |0 |216 |0 |0 |
+| read_ram_i |read_ram |186 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |158 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |27 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |122 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2261 |751 |1958 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2191 |704 |1776 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2066 |628 |1405 |22 |1 |
+| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1441 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1047 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |390 |171 |178 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |176 |145 |136 |0 |0 |
+| read_ram_data |read_ram_data_rev |214 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9170 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 63.896196s wall, 63.531250s user + 0.296875s system = 63.828125s CPU (99.9%)
+
+RUN-1004 : used memory is 395 MB, reserved memory is 386 MB, peak memory is 698 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.634628s wall, 2.843750s user + 0.031250s system = 2.875000s CPU (175.9%)
+
+RUN-1004 : used memory is 401 MB, reserved memory is 385 MB, peak memory is 698 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240218_161055.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/.bitgen.begin.f b/src/prj/td_project/hg_anlogic_Runs/phy_1/.bitgen.begin.f
index ab86eff..e65be6c 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/.bitgen.begin.f
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/.bitgen.begin.f
@@ -1,5 +1,5 @@
-
+
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_place.begin.f b/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_place.begin.f
index ab86eff..e65be6c 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_place.begin.f
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_place.begin.f
@@ -1,5 +1,5 @@
-
+
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_route.begin.f b/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_route.begin.f
index ab86eff..e65be6c 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_route.begin.f
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_route.begin.f
@@ -1,5 +1,5 @@
-
+
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bin b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bin
deleted file mode 100644
index ca3531f..0000000
Binary files a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bin and /dev/null differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit
index 36f8ce5..f579b29 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit and b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.prj b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.prj
index 6f6b8a7..203766c 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.prj
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.prj
@@ -1,5 +1,5 @@
-
+
UTF-8
5.6.71036
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.rbf b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.rbf
index f7ea0ca..9be9f4e 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.rbf and b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.rbf differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_20240218_a002_1615_soft_reset.bin b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_20240218_a002_1615_soft_reset.bin
new file mode 100644
index 0000000..907f1f9
Binary files /dev/null and b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_20240218_a002_1615_soft_reset.bin differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.area b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.area
index 1a69cff..532e8aa 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.area
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.area
@@ -8,12 +8,12 @@ IO Statistics
#inout 0
Utilization Statistics
-#lut 10345 out of 19600 52.78%
-#reg 9356 out of 19600 47.73%
-#le 12483
- #lut only 3127 out of 12483 25.05%
- #reg only 2138 out of 12483 17.13%
- #lut® 7218 out of 12483 57.82%
+#lut 10320 out of 19600 52.65%
+#reg 9363 out of 19600 47.77%
+#le 12661
+ #lut only 3298 out of 12661 26.05%
+ #reg only 2341 out of 12661 18.49%
+ #lut® 7022 out of 12661 55.46%
#dsp 3 out of 29 10.34%
#bram 54 out of 64 84.38%
#bram9k 50
@@ -21,24 +21,24 @@ Utilization Statistics
#bram32k 4 out of 16 25.00%
#pad 75 out of 130 57.69%
#ireg 13
- #oreg 21
+ #oreg 18
#treg 0
#pll 3 out of 4 75.00%
#gclk 6 out of 16 37.50%
Clock Resource Statistics
Index ClockNet Type DriverType Driver Fanout
-#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1785
-#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1421
-#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1348
-#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 951
-#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 144
-#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
-#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
-#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1795
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1417
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1355
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 967
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 139
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24
#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
-#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg40_syn_225.f1 3
-#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg50_syn_208.f1 2
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg42_syn_219.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_b/u_ADconfig/reg1_syn_191.f0 2
#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
@@ -48,36 +48,36 @@ Index ClockNet Type
Detailed IO Report
Name Direction Location IOStandard DriveStrength PullType PackReg
- a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
- a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
- a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
- b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
- b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
- b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ a_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
- onoff_in INPUT P140 LVCMOS33 N/A N/A NONE
- paper_in INPUT P17 LVCMOS25 N/A N/A NONE
+ onoff_in INPUT P133 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P4 LVCMOS25 N/A N/A NONE
rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
@@ -99,126 +99,128 @@ Detailed IO Report
O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
- a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
- a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
- a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
- a_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ a_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
- b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
- b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
- b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
- b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ b_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
- debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
- debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
- debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
- fan_pwm OUTPUT P25 LVCMOS25 8 N/A NONE
+ fan_pwm OUTPUT P138 LVCMOS33 8 N/A NONE
frame_indicator OUTPUT P16 LVCMOS25 8 N/A OREG
- onoff_out OUTPUT P118 LVCMOS25 8 N/A NONE
- paper_out OUTPUT P104 LVCMOS25 8 N/A NONE
- scan_out OUTPUT P83 LVCMOS25 8 N/A NONE
- sys_initial_done OUTPUT P32 LVCMOS25 8 N/A NONE
+ onoff_out OUTPUT P152 LVCMOS33 8 N/A NONE
+ paper_out OUTPUT P17 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P15 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P104 LVCMOS25 8 N/A NONE
txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
Report Hierarchy Area:
+---------------------------------------------------------------------------------------------------------+
|Instance |Module |le |lut |ripple |seq |bram |dsp |
+---------------------------------------------------------------------------------------------------------+
-|top |huagao_mipi_top |12483 |9318 |1027 |9390 |58 |3 |
-| U_rgb_to_csi_pakage |rgb_to_csi_pakage |558 |470 |23 |457 |4 |1 |
-| U_fifo_w32_d8192 |fifo_w32_d8192 |103 |85 |4 |91 |4 |0 |
-| U_crc16_24b |crc16_24b |34 |34 |0 |21 |0 |0 |
-| U_ecc_gen |ecc_gen |9 |9 |0 |8 |0 |0 |
-| exdev_ctl_a |exdev_ctl |785 |405 |96 |577 |0 |0 |
-| u_ADconfig |AD_config |191 |139 |25 |145 |0 |0 |
-| u_gen_sp |gen_sp |276 |185 |71 |114 |0 |0 |
-| exdev_ctl_b |exdev_ctl |761 |400 |96 |555 |0 |0 |
-| u_ADconfig |AD_config |186 |137 |25 |123 |0 |0 |
-| u_gen_sp |gen_sp |259 |173 |71 |116 |0 |0 |
-| sampling_fe_a |sampling_fe |2929 |2427 |306 |1994 |25 |0 |
-| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
-| u_ad_sampling |ad_sampling |187 |138 |17 |141 |0 |0 |
+|top |huagao_mipi_top |12661 |9293 |1027 |9394 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |545 |451 |23 |442 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |98 |83 |4 |90 |4 |0 |
+| U_crc16_24b |crc16_24b |29 |29 |0 |19 |0 |0 |
+| U_ecc_gen |ecc_gen |14 |14 |0 |10 |0 |0 |
+| exdev_ctl_a |exdev_ctl |767 |373 |96 |581 |0 |0 |
+| u_ADconfig |AD_config |188 |139 |25 |142 |0 |0 |
+| u_gen_sp |gen_sp |263 |160 |71 |123 |0 |0 |
+| exdev_ctl_b |exdev_ctl |752 |423 |96 |556 |0 |0 |
+| u_ADconfig |AD_config |178 |140 |25 |126 |0 |0 |
+| u_gen_sp |gen_sp |262 |168 |71 |118 |0 |0 |
+| sampling_fe_a |sampling_fe |3094 |2433 |306 |2032 |25 |0 |
+| u0_soft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |183 |97 |17 |141 |0 |0 |
| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
-| u_sort |sort |2708 |2271 |289 |1819 |25 |0 |
-| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
-| u0_wrsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
-| u_data_prebuffer |data_prebuffer |2358 |1986 |253 |1518 |22 |0 |
-| channelPart |channel_part_8478 |154 |151 |3 |138 |0 |0 |
-| fifo_adc |fifo_adc |61 |52 |9 |42 |0 |0 |
-| ram_switch |ram_switch |1853 |1549 |197 |1126 |0 |0 |
-| adc_addr_gen |adc_addr_gen |250 |223 |27 |124 |0 |0 |
-| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |8 |0 |0 |
-| [1]$ch_addr_gen |ch_addr_gen |27 |24 |3 |16 |0 |0 |
-| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
-| [3]$ch_addr_gen |ch_addr_gen |21 |18 |3 |9 |0 |0 |
-| [4]$ch_addr_gen |ch_addr_gen |29 |26 |3 |14 |0 |0 |
-| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
-| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
-| [7]$ch_addr_gen |ch_addr_gen |27 |24 |3 |12 |0 |0 |
-| [8]$ch_addr_gen |ch_addr_gen |30 |27 |3 |13 |0 |0 |
-| insert |insert |962 |685 |170 |654 |0 |0 |
-| ram_switch_state |ram_switch_state |641 |641 |0 |348 |0 |0 |
-| read_ram_i |read_ram |263 |208 |44 |185 |0 |0 |
-| read_ram_addr |read_ram_addr |210 |170 |40 |146 |0 |0 |
-| read_ram_data |read_ram_data |51 |36 |4 |37 |0 |0 |
-| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
-| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u_transfer_300_to_200 |transfer_300_to_200 |316 |259 |36 |267 |3 |0 |
-| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
-| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
-| sampling_fe_b |sampling_fe_rev |3306 |2572 |349 |2092 |25 |1 |
-| u0_soft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
-| u_ad_sampling |ad_sampling |185 |101 |17 |148 |0 |0 |
-| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
-| u_sort |sort_rev |3087 |2458 |332 |1910 |25 |1 |
-| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
-| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
-| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
-| u0_wrsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
-| u_data_prebuffer_rev |data_prebuffer_rev |2665 |2161 |290 |1546 |22 |1 |
-| channelPart |channel_part_8478 |232 |228 |3 |136 |0 |0 |
-| fifo_adc |fifo_adc |60 |51 |9 |44 |0 |1 |
-| ram_switch |ram_switch |1981 |1613 |197 |1120 |0 |0 |
-| adc_addr_gen |adc_addr_gen |228 |201 |27 |105 |0 |0 |
-| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |4 |0 |0 |
-| [1]$ch_addr_gen |ch_addr_gen |28 |25 |3 |14 |0 |0 |
-| [2]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
-| [3]$ch_addr_gen |ch_addr_gen |21 |18 |3 |12 |0 |0 |
-| [4]$ch_addr_gen |ch_addr_gen |21 |18 |3 |8 |0 |0 |
-| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |6 |0 |0 |
-| [6]$ch_addr_gen |ch_addr_gen |27 |24 |3 |12 |0 |0 |
+| u_sort |sort |2875 |2311 |289 |1855 |25 |0 |
+| rddpram_ctl |rddpram_ctl |5 |5 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2499 |2063 |253 |1538 |22 |0 |
+| channelPart |channel_part_8478 |133 |130 |3 |122 |0 |0 |
+| fifo_adc |fifo_adc |62 |53 |9 |44 |0 |0 |
+| ram_switch |ram_switch |1994 |1633 |197 |1144 |0 |0 |
+| adc_addr_gen |adc_addr_gen |244 |217 |27 |114 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |8 |5 |3 |4 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |29 |26 |3 |14 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
-| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 |
-| insert |insert |1007 |668 |170 |696 |0 |0 |
-| ram_switch_state |ram_switch_state |746 |744 |0 |319 |0 |0 |
-| read_ram_i |read_ram_rev |359 |248 |81 |213 |0 |0 |
-| read_ram_addr |read_ram_addr_rev |286 |202 |73 |160 |0 |0 |
-| read_ram_data |read_ram_data_rev |73 |46 |8 |53 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |9 |0 |0 |
+| insert |insert |953 |620 |170 |654 |0 |0 |
+| ram_switch_state |ram_switch_state |797 |796 |0 |376 |0 |0 |
+| read_ram_i |read_ram |265 |209 |44 |186 |0 |0 |
+| read_ram_addr |read_ram_addr |213 |173 |40 |147 |0 |0 |
+| read_ram_data |read_ram_data |51 |35 |4 |38 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |339 |233 |36 |280 |3 |0 |
+| u0_soft_n |cdc_sync |7 |7 |0 |7 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3367 |2648 |349 |2114 |25 |1 |
+| u0_soft_n |cdc_sync |6 |1 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |166 |113 |17 |130 |0 |0 |
+| u0_soft_n |cdc_sync |6 |1 |0 |6 |0 |0 |
+| u_sort |sort_rev |3165 |2522 |332 |1948 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |3 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |7 |2 |0 |7 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2731 |2228 |290 |1587 |22 |1 |
+| channelPart |channel_part_8478 |238 |235 |3 |135 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
+| ram_switch |ram_switch |1983 |1621 |197 |1142 |0 |0 |
+| adc_addr_gen |adc_addr_gen |221 |194 |27 |105 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |30 |27 |3 |18 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |8 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |21 |18 |3 |10 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| insert |insert |974 |641 |170 |669 |0 |0 |
+| ram_switch_state |ram_switch_state |788 |786 |0 |368 |0 |0 |
+| read_ram_i |read_ram_rev |424 |303 |81 |240 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |291 |206 |73 |159 |0 |0 |
+| read_ram_data |read_ram_data_rev |133 |97 |8 |81 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
@@ -241,65 +243,66 @@ Report Hierarchy Area:
| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u_transfer_300_to_200 |transfer_300_to_200 |315 |215 |42 |278 |3 |0 |
-| u0_soft_n |cdc_sync |5 |1 |0 |5 |0 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |327 |215 |42 |273 |3 |0 |
+| u0_soft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
-| scan_start_diff |scan_start_diff |23 |22 |0 |15 |0 |0 |
-| u0_test_en |cdc_sync |3 |3 |0 |3 |0 |0 |
-| u1_test_en |cdc_sync |2 |1 |0 |2 |0 |0 |
-| u2_test_en |cdc_sync |4 |4 |0 |4 |0 |0 |
-| u_a_pclk |cdc_sync |4 |4 |0 |4 |0 |0 |
-| u_a_sp_sampling |cdc_sync |2 |2 |0 |2 |0 |0 |
-| u_a_sp_sampling_cam |cdc_sync |8 |4 |0 |8 |0 |0 |
-| u_a_sp_sampling_last |cdc_sync |2 |0 |0 |2 |0 |0 |
-| u_b_pclk |cdc_sync |3 |2 |0 |3 |0 |0 |
-| u_b_sp_sampling |cdc_sync |5 |3 |0 |5 |0 |0 |
-| u_b_sp_sampling_cam |cdc_sync |7 |4 |0 |7 |0 |0 |
+| scan_start_diff |scan_start_diff |23 |23 |0 |15 |0 |0 |
+| u0_test_en |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u1_test_en |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u2_test_en |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_a_pclk |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_a_sp_sampling |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_a_sp_sampling_cam |cdc_sync |5 |1 |0 |5 |0 |0 |
+| u_a_sp_sampling_last |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_b_pclk |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u_b_sp_sampling |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u_b_sp_sampling_cam |cdc_sync |6 |4 |0 |6 |0 |0 |
| u_b_sp_sampling_last |cdc_sync |2 |2 |0 |2 |0 |0 |
-| u_bus_top |ubus_top |1329 |1076 |22 |1238 |0 |0 |
-| u_local_bus_slve_cis |local_bus_slve_cis |826 |729 |22 |735 |0 |0 |
-| u_uart_2dsp |uart_2dsp |110 |98 |12 |63 |0 |0 |
-| u_dpi_mode |cdc_sync |11 |11 |0 |11 |0 |0 |
-| u_lv_en_flag |cdc_sync |3 |3 |0 |3 |0 |0 |
-| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |277 |240 |20 |222 |4 |0 |
-| u_hs_tx_wrapper |hs_tx_wrapper |241 |204 |20 |194 |4 |0 |
-| [0]$u_data_lane_wrapper |data_lane_wrapper |115 |86 |15 |87 |1 |0 |
-| u_data_hs_generate |data_hs_generate |112 |83 |15 |84 |1 |0 |
-| u_dphy_tx_fifo |dphy_tx_fifo |2 |2 |0 |0 |1 |0 |
-| u_d1024_w8_fifo |d1024_w8_fifo |2 |2 |0 |0 |1 |0 |
-| u_data_lp_generate |data_lp_generate |3 |3 |0 |3 |0 |0 |
-| [1]$u_data_lane_wrapper |data_lane_wrapper |30 |29 |0 |29 |1 |0 |
-| u_data_hs_generate |data_hs_generate |30 |29 |0 |29 |1 |0 |
+| u_bus_top |ubus_top |1297 |1117 |22 |1208 |0 |0 |
+| u_local_bus_slve_cis |local_bus_slve_cis |800 |724 |22 |711 |0 |0 |
+| u_uart_2dsp |uart_2dsp |98 |86 |12 |61 |0 |0 |
+| u_dpi_mode |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_eot |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_lv_en_flag |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |275 |237 |20 |213 |4 |0 |
+| u_hs_tx_wrapper |hs_tx_wrapper |227 |189 |20 |185 |4 |0 |
+| [0]$u_data_lane_wrapper |data_lane_wrapper |112 |89 |15 |86 |1 |0 |
+| u_data_hs_generate |data_hs_generate |107 |84 |15 |81 |1 |0 |
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
-| [2]$u_data_lane_wrapper |data_lane_wrapper |28 |26 |0 |28 |1 |0 |
-| u_data_hs_generate |data_hs_generate |28 |26 |0 |28 |1 |0 |
+| u_data_lp_generate |data_lp_generate |5 |5 |0 |5 |0 |0 |
+| [1]$u_data_lane_wrapper |data_lane_wrapper |27 |17 |0 |27 |1 |0 |
+| u_data_hs_generate |data_hs_generate |27 |17 |0 |27 |1 |0 |
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
-| [3]$u_data_lane_wrapper |data_lane_wrapper |25 |25 |0 |25 |1 |0 |
-| u_data_hs_generate |data_hs_generate |25 |25 |0 |25 |1 |0 |
+| [2]$u_data_lane_wrapper |data_lane_wrapper |22 |22 |0 |22 |1 |0 |
+| u_data_hs_generate |data_hs_generate |22 |22 |0 |22 |1 |0 |
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
-| u_hs_tx_controler |hs_tx_controler |35 |30 |5 |17 |0 |0 |
-| u_clk_lane_wrapper |clk_lane_wrapper |7 |7 |0 |7 |0 |0 |
+| [3]$u_data_lane_wrapper |data_lane_wrapper |24 |24 |0 |24 |1 |0 |
+| u_data_hs_generate |data_hs_generate |24 |24 |0 |24 |1 |0 |
+| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
+| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
+| u_hs_tx_controler |hs_tx_controler |34 |29 |5 |18 |0 |0 |
+| u_clk_lane_wrapper |clk_lane_wrapper |8 |8 |0 |8 |0 |0 |
| u_clk_lp_generate |clk_lp_generate |4 |4 |0 |4 |0 |0 |
-| u_clk_hs_generate |clk_hs_generate |3 |3 |0 |3 |0 |0 |
-| u_mipi_eot_min |cdc_sync |69 |68 |0 |69 |0 |0 |
-| u_mipi_sot_min |cdc_sync |60 |56 |0 |60 |0 |0 |
-| u_pic_cnt |cdc_sync |116 |46 |0 |116 |0 |0 |
-| u_pixel_cdc |pixel_cdc |712 |534 |0 |712 |0 |1 |
-| u_clk_cis_frame_num |cdc_sync |74 |60 |0 |74 |0 |0 |
-| u_clk_cis_pixel_y |cdc_sync |75 |54 |0 |75 |0 |0 |
-| u_clk_mipi_pixel_y |cdc_sync |74 |68 |0 |74 |0 |0 |
-| u_clka_cis_total_num |cdc_sync |106 |52 |0 |106 |0 |0 |
-| u_clka_mipi_total_num |cdc_sync |97 |72 |0 |97 |0 |0 |
-| u_clkb_cis_total_num |cdc_sync |106 |70 |0 |106 |0 |0 |
-| u_clkb_mipi_total_num |cdc_sync |108 |95 |0 |108 |0 |0 |
+| u_clk_hs_generate |clk_hs_generate |4 |4 |0 |4 |0 |0 |
+| u_mipi_eot_min |cdc_sync |58 |58 |0 |58 |0 |0 |
+| u_mipi_sot_min |cdc_sync |66 |65 |0 |66 |0 |0 |
+| u_pic_cnt |cdc_sync |117 |40 |0 |117 |0 |0 |
+| u_pixel_cdc |pixel_cdc |688 |412 |0 |688 |0 |1 |
+| u_clk_cis_frame_num |cdc_sync |75 |65 |0 |75 |0 |0 |
+| u_clk_cis_pixel_y |cdc_sync |74 |47 |0 |74 |0 |0 |
+| u_clk_mipi_pixel_y |cdc_sync |67 |45 |0 |67 |0 |0 |
+| u_clka_cis_total_num |cdc_sync |108 |33 |0 |108 |0 |0 |
+| u_clka_mipi_total_num |cdc_sync |108 |58 |0 |108 |0 |0 |
+| u_clkb_cis_total_num |cdc_sync |104 |65 |0 |104 |0 |0 |
+| u_clkb_mipi_total_num |cdc_sync |89 |58 |0 |89 |0 |0 |
| u_pll |pll |0 |0 |0 |0 |0 |0 |
| u_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |0 |
-| u_softrst_done |cdc_sync |3 |3 |0 |3 |0 |0 |
-| ua_lvds_rx |lvds_rx |290 |205 |19 |207 |0 |0 |
-| ub_lvds_rx |lvds_rx |288 |194 |19 |209 |0 |0 |
+| u_softrst_done |cdc_sync |2 |0 |0 |2 |0 |0 |
+| ua_lvds_rx |lvds_rx |286 |192 |19 |206 |0 |0 |
+| ub_lvds_rx |lvds_rx |287 |185 |19 |207 |0 |0 |
| uu_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |0 |
+---------------------------------------------------------------------------------------------------------+
@@ -307,12 +310,12 @@ Report Hierarchy Area:
DataNet Average Fanout:
Index Fanout Nets
- #1 1 9929
- #2 2 3890
- #3 3 1404
- #4 4 524
- #5 5-10 1204
- #6 11-50 601
- #7 51-100 23
+ #1 1 9824
+ #2 2 3937
+ #3 3 1458
+ #4 4 642
+ #5 5-10 1062
+ #6 11-50 587
+ #7 51-100 24
#8 >500 1
- Average 2.92
+ Average 2.91
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.timing b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.timing
index 6398f8e..66632a8 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.timing
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.timing
@@ -1,7 +1,7 @@
=========================================================================================================
Auto created by Tang Dynasty v5.6.71036
Copyright (c) 2012-2023 Anlogic Inc.
-Tue Jan 23 14:19:31 2024
+Sun Feb 18 16:14:56 2024
=========================================================================================================
@@ -25,186 +25,20 @@ Minimum period is 0ns
Timing constraint: clock: a_pclk
Clock = a_pclk, period 20.833ns, rising at 0ns, falling at 10.417ns
-6214 endpoints analyzed totally, and 104856 paths analyzed
+6230 endpoints analyzed totally, and 105934 paths analyzed
0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 12.785ns
----------------------------------------------------------------------------------------------------------
-
-Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 (659 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check): 8.048 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1] (rising edge triggered by clock a_pclk)
- Clock group: a_lvds_clk_p
- Process: Slow
- Data Path Delay: 12.605ns (logic 6.927ns, net 5.678ns, 54% logic)
- Logic Levels: 7 ( LUT5=4 ADDER=2 MULT18=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 2.276
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[0] clk2q 0.146 r 2.422
- U_rgb_to_csi_pakage/mult0_syn_4.a[9] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net (fanout = 4) 1.989 r 4.411 ../../../../hg_mp/fe/prebuffer.v(105)
- U_rgb_to_csi_pakage/mult0_syn_4.p[19] cell (MULT18) 3.563 r 7.974
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 1.109 r 9.083
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 9.789
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 9.789
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 9.862
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 9.862
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 9.935
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 9.935
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.290
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg3_syn_51_syn_2.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.759 r 11.049
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg3_syn_51_syn_2.f[0] cell (LUT5) 0.424 r 11.473
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_17.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.561 r 12.034 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_17.f[0] cell (LUT5) 0.424 r 12.458
- u_bus_top/reg0_syn_192.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.503 r 12.961 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_bus_top/reg0_syn_192.f[0] cell (LUT5) 0.431 r 13.392
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 0.757 r 14.149 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.732 14.881
- Arrival time 14.881 (7 lvl)
-
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 20.833 22.878
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 22.762
- clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.167 22.929
- Required time 22.929
----------------------------------------------------------------------------------------------------------
- Slack 8.048ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check): 8.048 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[0] (rising edge triggered by clock a_pclk)
- Clock group: a_lvds_clk_p
- Process: Slow
- Data Path Delay: 12.605ns (logic 6.927ns, net 5.678ns, 54% logic)
- Logic Levels: 7 ( LUT5=4 ADDER=2 MULT18=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 2.276
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[0] clk2q 0.146 r 2.422
- U_rgb_to_csi_pakage/mult0_syn_4.a[9] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net (fanout = 4) 1.989 r 4.411 ../../../../hg_mp/fe/prebuffer.v(105)
- U_rgb_to_csi_pakage/mult0_syn_4.p[19] cell (MULT18) 3.563 r 7.974
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 1.109 r 9.083
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 9.789
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 9.789
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 9.862
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 9.862
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 9.935
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 9.935
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.290
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg3_syn_51_syn_2.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.759 r 11.049
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg3_syn_51_syn_2.f[0] cell (LUT5) 0.424 r 11.473
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_17.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.561 r 12.034 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_17.f[0] cell (LUT5) 0.424 r 12.458
- u_bus_top/reg0_syn_192.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.503 r 12.961 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_bus_top/reg0_syn_192.f[0] cell (LUT5) 0.431 r 13.392
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 0.757 r 14.149 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.732 14.881
- Arrival time 14.881 (7 lvl)
-
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 20.833 22.878
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 22.762
- clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.167 22.929
- Required time 22.929
----------------------------------------------------------------------------------------------------------
- Slack 8.048ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check): 8.053 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1] (rising edge triggered by clock a_pclk)
- Clock group: a_lvds_clk_p
- Process: Slow
- Data Path Delay: 12.600ns (logic 6.921ns, net 5.679ns, 54% logic)
- Logic Levels: 7 ( LUT5=4 ADDER=2 MULT18=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 2.276
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[0] clk2q 0.146 r 2.422
- U_rgb_to_csi_pakage/mult0_syn_4.a[9] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net (fanout = 4) 1.989 r 4.411 ../../../../hg_mp/fe/prebuffer.v(105)
- U_rgb_to_csi_pakage/mult0_syn_4.p[18] cell (MULT18) 3.563 r 7.974
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.110 r 9.084
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 9.711
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 9.711
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 9.784
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 9.784
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 9.857
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 9.857
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 9.930
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 9.930
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.285
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg3_syn_51_syn_2.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.759 r 11.044
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg3_syn_51_syn_2.f[0] cell (LUT5) 0.424 r 11.468
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_17.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.561 r 12.029 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_17.f[0] cell (LUT5) 0.424 r 12.453
- u_bus_top/reg0_syn_192.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.503 r 12.956 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_bus_top/reg0_syn_192.f[0] cell (LUT5) 0.431 r 13.387
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 0.757 r 14.144 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.732 14.876
- Arrival time 14.876 (7 lvl)
-
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 20.833 22.878
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 22.762
- clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.167 22.929
- Required time 22.929
----------------------------------------------------------------------------------------------------------
- Slack 8.053ns
-
+Minimum period is 13.964ns
---------------------------------------------------------------------------------------------------------
Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 (691 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 8.116 ns
+ Slack (setup check): 6.869 ns
Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (rising edge triggered by clock a_pclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 12.537ns (logic 6.927ns, net 5.610ns, 55% logic)
- Logic Levels: 7 ( LUT5=4 ADDER=2 MULT18=1 )
+ Data Path Delay: 13.712ns (logic 6.927ns, net 6.785ns, 50% logic)
+ Logic Levels: 7 ( LUT5=3 ADDER=2 LUT2=1 MULT18=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -216,25 +50,25 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 (
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[0] clk2q 0.146 r 2.422
- U_rgb_to_csi_pakage/mult0_syn_4.a[9] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net (fanout = 4) 1.989 r 4.411 ../../../../hg_mp/fe/prebuffer.v(105)
- U_rgb_to_csi_pakage/mult0_syn_4.p[19] cell (MULT18) 3.563 r 7.974
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 1.109 r 9.083
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 9.789
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 9.789
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 9.862
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 9.862
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 9.935
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 9.935
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.290
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg3_syn_51_syn_2.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.759 r 11.049
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg3_syn_51_syn_2.f[0] cell (LUT5) 0.424 r 11.473
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_17.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.561 r 12.034 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_17.f[0] cell (LUT5) 0.424 r 12.458
- u_bus_top/reg0_syn_192.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.503 r 12.961 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_bus_top/reg0_syn_192.f[0] cell (LUT5) 0.431 r 13.392
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 0.689 r 14.081 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 14.813
- Arrival time 14.813 (7 lvl)
+ U_rgb_to_csi_pakage/mult0_syn_4.a[12] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net (fanout = 4) 1.971 r 4.393 ../../../../hg_mp/fe/prebuffer.v(105)
+ U_rgb_to_csi_pakage/mult0_syn_4.p[19] cell (MULT18) 3.563 r 7.956
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 1.345 r 9.301
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 10.007
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 10.007
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 10.080
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 10.080
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 10.153
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 10.153
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.508
+ u_pixel_cdc/reg6_syn_65.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.794 r 11.302
+ u_pixel_cdc/reg6_syn_65.f[0] cell (LUT5) 0.424 r 11.726
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.738 r 12.464 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.f[1] cell (LUT2) 0.424 r 12.888
+ u_pixel_cdc/reg6_syn_67.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.468 r 13.356 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pixel_cdc/reg6_syn_67.f[0] cell (LUT5) 0.431 r 13.787
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 1.469 r 15.256 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 15.988
+ Arrival time 15.988 (7 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
@@ -245,20 +79,20 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 (
---------------------------------------------------------------------------------------------------------
cell setup -0.116 22.762
clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.167 22.929
- Required time 22.929
+ clock recovergence pessimism 0.095 22.857
+ Required time 22.857
---------------------------------------------------------------------------------------------------------
- Slack 8.116ns
+ Slack 6.869ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 8.116 ns
+ Slack (setup check): 6.869 ns
Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[0] (rising edge triggered by clock a_pclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 12.537ns (logic 6.927ns, net 5.610ns, 55% logic)
- Logic Levels: 7 ( LUT5=4 ADDER=2 MULT18=1 )
+ Data Path Delay: 13.712ns (logic 6.927ns, net 6.785ns, 50% logic)
+ Logic Levels: 7 ( LUT5=3 ADDER=2 LUT2=1 MULT18=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -270,25 +104,25 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 (
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[0] clk2q 0.146 r 2.422
- U_rgb_to_csi_pakage/mult0_syn_4.a[9] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net (fanout = 4) 1.989 r 4.411 ../../../../hg_mp/fe/prebuffer.v(105)
- U_rgb_to_csi_pakage/mult0_syn_4.p[19] cell (MULT18) 3.563 r 7.974
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 1.109 r 9.083
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 9.789
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 9.789
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 9.862
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 9.862
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 9.935
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 9.935
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.290
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg3_syn_51_syn_2.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.759 r 11.049
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg3_syn_51_syn_2.f[0] cell (LUT5) 0.424 r 11.473
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_17.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.561 r 12.034 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_17.f[0] cell (LUT5) 0.424 r 12.458
- u_bus_top/reg0_syn_192.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.503 r 12.961 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_bus_top/reg0_syn_192.f[0] cell (LUT5) 0.431 r 13.392
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 0.689 r 14.081 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 14.813
- Arrival time 14.813 (7 lvl)
+ U_rgb_to_csi_pakage/mult0_syn_4.a[12] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net (fanout = 4) 1.971 r 4.393 ../../../../hg_mp/fe/prebuffer.v(105)
+ U_rgb_to_csi_pakage/mult0_syn_4.p[19] cell (MULT18) 3.563 r 7.956
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 1.345 r 9.301
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 10.007
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 10.007
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 10.080
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 10.080
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 10.153
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 10.153
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.508
+ u_pixel_cdc/reg6_syn_65.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.794 r 11.302
+ u_pixel_cdc/reg6_syn_65.f[0] cell (LUT5) 0.424 r 11.726
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.738 r 12.464 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.f[1] cell (LUT2) 0.424 r 12.888
+ u_pixel_cdc/reg6_syn_67.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.468 r 13.356 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pixel_cdc/reg6_syn_67.f[0] cell (LUT5) 0.431 r 13.787
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 1.469 r 15.256 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 15.988
+ Arrival time 15.988 (7 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
@@ -299,20 +133,20 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 (
---------------------------------------------------------------------------------------------------------
cell setup -0.116 22.762
clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.167 22.929
- Required time 22.929
+ clock recovergence pessimism 0.095 22.857
+ Required time 22.857
---------------------------------------------------------------------------------------------------------
- Slack 8.116ns
+ Slack 6.869ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 8.121 ns
+ Slack (setup check): 6.875 ns
Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (rising edge triggered by clock a_pclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 12.532ns (logic 6.921ns, net 5.611ns, 55% logic)
- Logic Levels: 7 ( LUT5=4 ADDER=2 MULT18=1 )
+ Data Path Delay: 13.706ns (logic 6.921ns, net 6.785ns, 50% logic)
+ Logic Levels: 7 ( LUT5=3 ADDER=2 LUT2=1 MULT18=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -324,27 +158,27 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 (
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[0] clk2q 0.146 r 2.422
- U_rgb_to_csi_pakage/mult0_syn_4.a[9] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net (fanout = 4) 1.989 r 4.411 ../../../../hg_mp/fe/prebuffer.v(105)
- U_rgb_to_csi_pakage/mult0_syn_4.p[18] cell (MULT18) 3.563 r 7.974
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.110 r 9.084
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 9.711
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 9.711
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 9.784
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 9.784
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 9.857
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 9.857
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 9.930
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 9.930
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.285
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg3_syn_51_syn_2.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.759 r 11.044
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg3_syn_51_syn_2.f[0] cell (LUT5) 0.424 r 11.468
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_17.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.561 r 12.029 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_17.f[0] cell (LUT5) 0.424 r 12.453
- u_bus_top/reg0_syn_192.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.503 r 12.956 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_bus_top/reg0_syn_192.f[0] cell (LUT5) 0.431 r 13.387
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 0.689 r 14.076 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 14.808
- Arrival time 14.808 (7 lvl)
+ U_rgb_to_csi_pakage/mult0_syn_4.a[12] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net (fanout = 4) 1.971 r 4.393 ../../../../hg_mp/fe/prebuffer.v(105)
+ U_rgb_to_csi_pakage/mult0_syn_4.p[18] cell (MULT18) 3.563 r 7.956
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.345 r 9.301
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 9.928
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 9.928
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 10.001
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 10.001
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 10.074
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 10.074
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 10.147
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 10.147
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.502
+ u_pixel_cdc/reg6_syn_65.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.794 r 11.296
+ u_pixel_cdc/reg6_syn_65.f[0] cell (LUT5) 0.424 r 11.720
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.738 r 12.458 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.f[1] cell (LUT2) 0.424 r 12.882
+ u_pixel_cdc/reg6_syn_67.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.468 r 13.350 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pixel_cdc/reg6_syn_67.f[0] cell (LUT5) 0.431 r 13.781
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 1.469 r 15.250 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 15.982
+ Arrival time 15.982 (7 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
@@ -355,22 +189,22 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 (
---------------------------------------------------------------------------------------------------------
cell setup -0.116 22.762
clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.167 22.929
- Required time 22.929
+ clock recovergence pessimism 0.095 22.857
+ Required time 22.857
---------------------------------------------------------------------------------------------------------
- Slack 8.121ns
+ Slack 6.875ns
---------------------------------------------------------------------------------------------------------
-Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216 (20 paths)
+Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 (659 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 12.412 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.clk (rising edge triggered by clock a_pclk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216.mi[0] (rising edge triggered by clock a_pclk)
+ Slack (setup check): 7.164 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1] (rising edge triggered by clock a_pclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 8.241ns (logic 1.600ns, net 6.641ns, 19% logic)
- Logic Levels: 4 ( LUT5=2 LUT2=2 )
+ Data Path Delay: 13.417ns (logic 6.927ns, net 6.490ns, 51% logic)
+ Logic Levels: 7 ( LUT5=3 ADDER=2 LUT2=1 MULT18=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -378,45 +212,53 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.q[0] clk2q 0.146 r 2.422
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg0_syn_26_syn_2.c[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[1]) net (fanout = 92) 1.440 r 3.862 ../../../../hg_mp/fe/ram_switch.v(33)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg0_syn_26_syn_2.f[0] cell (LUT2) 0.251 r 4.113
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/adc_addr_gen/reg1_syn_22.b[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_15) net (fanout = 49) 1.890 r 6.003 ../../../../hg_mp/fe/ram_switch_state.v(64)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/adc_addr_gen/reg1_syn_22.f[1] cell (LUT5) 0.431 r 6.434
- reg42_syn_184.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert_en_n) net (fanout = 16) 0.820 r 7.254
- reg42_syn_184.f[0] cell (LUT5) 0.424 r 7.678
- sampling_fe_a/u_sort/u_data_prebuffer/channelPart/reg1_syn_62.d[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_11) net (fanout = 1) 0.456 r 8.134 ../../../../hg_mp/fe/ram_switch_state.v(64)
- sampling_fe_a/u_sort/u_data_prebuffer/channelPart/reg1_syn_62.f[0] cell (LUT2) 0.205 r 8.339
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216.mi[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_13) net (fanout = 9) 2.035 r 10.374 ../../../../hg_mp/fe/ram_switch_state.v(64)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216 path2reg0 0.143 10.517
- Arrival time 10.517 (4 lvl)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[0] clk2q 0.146 r 2.422
+ U_rgb_to_csi_pakage/mult0_syn_4.a[12] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net (fanout = 4) 1.971 r 4.393 ../../../../hg_mp/fe/prebuffer.v(105)
+ U_rgb_to_csi_pakage/mult0_syn_4.p[19] cell (MULT18) 3.563 r 7.956
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 1.345 r 9.301
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 10.007
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 10.007
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 10.080
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 10.080
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 10.153
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 10.153
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.508
+ u_pixel_cdc/reg6_syn_65.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.794 r 11.302
+ u_pixel_cdc/reg6_syn_65.f[0] cell (LUT5) 0.424 r 11.726
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.738 r 12.464 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.f[1] cell (LUT2) 0.424 r 12.888
+ u_pixel_cdc/reg6_syn_67.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.468 r 13.356 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pixel_cdc/reg6_syn_67.f[0] cell (LUT5) 0.431 r 13.787
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 1.174 r 14.961 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.732 15.693
+ Arrival time 15.693 (7 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 20.833 22.878
---------------------------------------------------------------------------------------------------------
cell setup -0.116 22.762
clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.167 22.929
- Required time 22.929
+ clock recovergence pessimism 0.095 22.857
+ Required time 22.857
---------------------------------------------------------------------------------------------------------
- Slack 12.412ns
+ Slack 7.164ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 12.431 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.clk (rising edge triggered by clock a_pclk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216.mi[0] (rising edge triggered by clock a_pclk)
+ Slack (setup check): 7.164 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[0] (rising edge triggered by clock a_pclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 8.222ns (logic 1.554ns, net 6.668ns, 18% logic)
- Logic Levels: 4 ( LUT5=2 LUT2=2 )
+ Data Path Delay: 13.417ns (logic 6.927ns, net 6.490ns, 51% logic)
+ Logic Levels: 7 ( LUT5=3 ADDER=2 LUT2=1 MULT18=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -424,45 +266,53 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.q[1] clk2q 0.146 r 2.422
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg0_syn_26_syn_2.d[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[0]) net (fanout = 88) 1.467 r 3.889 ../../../../hg_mp/fe/ram_switch.v(33)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg0_syn_26_syn_2.f[0] cell (LUT2) 0.205 r 4.094
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/adc_addr_gen/reg1_syn_22.b[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_15) net (fanout = 49) 1.890 r 5.984 ../../../../hg_mp/fe/ram_switch_state.v(64)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/adc_addr_gen/reg1_syn_22.f[1] cell (LUT5) 0.431 r 6.415
- reg42_syn_184.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert_en_n) net (fanout = 16) 0.820 r 7.235
- reg42_syn_184.f[0] cell (LUT5) 0.424 r 7.659
- sampling_fe_a/u_sort/u_data_prebuffer/channelPart/reg1_syn_62.d[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_11) net (fanout = 1) 0.456 r 8.115 ../../../../hg_mp/fe/ram_switch_state.v(64)
- sampling_fe_a/u_sort/u_data_prebuffer/channelPart/reg1_syn_62.f[0] cell (LUT2) 0.205 r 8.320
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216.mi[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_13) net (fanout = 9) 2.035 r 10.355 ../../../../hg_mp/fe/ram_switch_state.v(64)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216 path2reg0 0.143 10.498
- Arrival time 10.498 (4 lvl)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[0] clk2q 0.146 r 2.422
+ U_rgb_to_csi_pakage/mult0_syn_4.a[12] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net (fanout = 4) 1.971 r 4.393 ../../../../hg_mp/fe/prebuffer.v(105)
+ U_rgb_to_csi_pakage/mult0_syn_4.p[19] cell (MULT18) 3.563 r 7.956
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 1.345 r 9.301
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 10.007
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 10.007
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 10.080
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 10.080
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 10.153
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 10.153
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.508
+ u_pixel_cdc/reg6_syn_65.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.794 r 11.302
+ u_pixel_cdc/reg6_syn_65.f[0] cell (LUT5) 0.424 r 11.726
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.738 r 12.464 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.f[1] cell (LUT2) 0.424 r 12.888
+ u_pixel_cdc/reg6_syn_67.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.468 r 13.356 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pixel_cdc/reg6_syn_67.f[0] cell (LUT5) 0.431 r 13.787
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 1.174 r 14.961 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.732 15.693
+ Arrival time 15.693 (7 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 20.833 22.878
---------------------------------------------------------------------------------------------------------
cell setup -0.116 22.762
clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.167 22.929
- Required time 22.929
+ clock recovergence pessimism 0.095 22.857
+ Required time 22.857
---------------------------------------------------------------------------------------------------------
- Slack 12.431ns
+ Slack 7.164ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 13.227 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/channelPart/reg0_syn_60.clk (rising edge triggered by clock a_pclk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216.mi[0] (rising edge triggered by clock a_pclk)
+ Slack (setup check): 7.170 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1] (rising edge triggered by clock a_pclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 7.426ns (logic 2.197ns, net 5.229ns, 29% logic)
- Logic Levels: 5 ( LUT5=4 LUT2=1 )
+ Data Path Delay: 13.411ns (logic 6.921ns, net 6.490ns, 51% logic)
+ Logic Levels: 7 ( LUT5=3 ADDER=2 LUT2=1 MULT18=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -470,88 +320,220 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/channelPart/reg0_syn_60.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/channelPart/reg0_syn_60.q[1] clk2q 0.146 r 2.422
- reg42_syn_187.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/channelPart/WR_addr[4]) net (fanout = 4) 0.775 r 3.197 ../../../../hg_mp/fe/channel_part_8478.v(30)
- reg42_syn_187.f[0] cell (LUT5) 0.431 r 3.628
- reg42_syn_187.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_20) net (fanout = 1) 0.158 r 3.786 ../../../../hg_mp/fe/ram_switch_state.v(64)
- reg42_syn_187.f[1] cell (LUT5) 0.424 r 4.210
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/adc_addr_gen/reg1_syn_22.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_22) net (fanout = 3) 0.985 r 5.195 ../../../../hg_mp/fe/ram_switch_state.v(64)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/adc_addr_gen/reg1_syn_22.f[1] cell (LUT5) 0.424 r 5.619
- reg42_syn_184.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert_en_n) net (fanout = 16) 0.820 r 6.439
- reg42_syn_184.f[0] cell (LUT5) 0.424 r 6.863
- sampling_fe_a/u_sort/u_data_prebuffer/channelPart/reg1_syn_62.d[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_11) net (fanout = 1) 0.456 r 7.319 ../../../../hg_mp/fe/ram_switch_state.v(64)
- sampling_fe_a/u_sort/u_data_prebuffer/channelPart/reg1_syn_62.f[0] cell (LUT2) 0.205 r 7.524
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216.mi[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_13) net (fanout = 9) 2.035 r 9.559 ../../../../hg_mp/fe/ram_switch_state.v(64)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216 path2reg0 0.143 9.702
- Arrival time 9.702 (5 lvl)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[0] clk2q 0.146 r 2.422
+ U_rgb_to_csi_pakage/mult0_syn_4.a[12] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net (fanout = 4) 1.971 r 4.393 ../../../../hg_mp/fe/prebuffer.v(105)
+ U_rgb_to_csi_pakage/mult0_syn_4.p[18] cell (MULT18) 3.563 r 7.956
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.345 r 9.301
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 9.928
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 9.928
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 10.001
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 10.001
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 10.074
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 10.074
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 10.147
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 10.147
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.502
+ u_pixel_cdc/reg6_syn_65.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.794 r 11.296
+ u_pixel_cdc/reg6_syn_65.f[0] cell (LUT5) 0.424 r 11.720
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.738 r 12.458 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.f[1] cell (LUT2) 0.424 r 12.882
+ u_pixel_cdc/reg6_syn_67.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.468 r 13.350 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pixel_cdc/reg6_syn_67.f[0] cell (LUT5) 0.431 r 13.781
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 1.174 r 14.955 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.732 15.687
+ Arrival time 15.687 (7 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 20.833 22.878
---------------------------------------------------------------------------------------------------------
cell setup -0.116 22.762
clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.167 22.929
- Required time 22.929
+ clock recovergence pessimism 0.095 22.857
+ Required time 22.857
---------------------------------------------------------------------------------------------------------
- Slack 13.227ns
+ Slack 7.170ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point exdev_ctl_a/u_gen_sp/reg0_syn_81 (217 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check): 12.294 ns
+ Start Point: exdev_ctl_a/u_gen_sp/reg9_syn_103.clk (rising edge triggered by clock a_pclk)
+ End Point: exdev_ctl_a/u_gen_sp/reg0_syn_81.sr (rising edge triggered by clock a_pclk)
+ Clock group: a_lvds_clk_p
+ Process: Slow
+ Data Path Delay: 8.216ns (logic 3.713ns, net 4.503ns, 45% logic)
+ Logic Levels: 7 ( LUT5=5 ADDER=2 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ exdev_ctl_a/u_gen_sp/reg9_syn_103.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 2.276
+---------------------------------------------------------------------------------------------------------
+ exdev_ctl_a/u_gen_sp/reg9_syn_103.q[0] clk2q 0.146 r 2.422
+ exdev_ctl_a/u_gen_sp/sub1_syn_103.a[0] (exdev_ctl_a/u_gen_sp/sp_t_d1[3]) net (fanout = 1) 0.803 r 3.225 ../../../../hg_mp/fe/gen_sp.v(87)
+ exdev_ctl_a/u_gen_sp/sub1_syn_103.fco cell (ADDER) 0.947 r 4.172
+ exdev_ctl_a/u_gen_sp/sub1_syn_104.fci (exdev_ctl_a/u_gen_sp/sub1_syn_91) net (fanout = 1) 0.000 f 4.172 ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_a/u_gen_sp/sub1_syn_104.fco cell (ADDER) 0.132 r 4.304
+ exdev_ctl_a/u_gen_sp/sub1_syn_105.fci (exdev_ctl_a/u_gen_sp/sub1_syn_95) net (fanout = 1) 0.000 f 4.304 ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_a/u_gen_sp/sub1_syn_105.fx[0] cell (ADDER) 0.387 r 4.691
+ exdev_ctl_a/reg8_syn_103.a[1] (exdev_ctl_a/u_gen_sp/cnt_one_line_b5[12]) net (fanout = 1) 0.591 r 5.282
+ exdev_ctl_a/reg8_syn_103.f[1] cell (LUT5) 0.424 r 5.706
+ exdev_ctl_b/reg6_syn_103.a[1] (exdev_ctl_a/u_gen_sp/mux31_syn_140) net (fanout = 1) 0.738 r 6.444 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_b/reg6_syn_103.f[1] cell (LUT5) 0.424 r 6.868
+ u_bus_top/reg5_syn_196.a[0] (exdev_ctl_a/u_gen_sp/mux31_syn_142) net (fanout = 1) 0.307 r 7.175 ../../../../hg_mp/fe/gen_sp.v(137)
+ u_bus_top/reg5_syn_196.f[0] cell (LUT5) 0.424 r 7.599
+ exdev_ctl_a/reg8_syn_103.a[0] (exdev_ctl_a/u_gen_sp/mux31_syn_150) net (fanout = 1) 0.456 r 8.055 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_a/reg8_syn_103.f[0] cell (LUT5) 0.424 r 8.479
+ exdev_ctl_a/reg8_syn_109.d[1] (exdev_ctl_a/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.612 r 9.091
+ exdev_ctl_a/reg8_syn_109.f[1] cell (LUT5) 0.262 r 9.353
+ exdev_ctl_a/u_gen_sp/reg0_syn_81.sr (exdev_ctl_a/u_gen_sp/mux31_syn_19) net (fanout = 8) 0.996 r 10.349 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_a/u_gen_sp/reg0_syn_81 path2reg 0.143 10.492
+ Arrival time 10.492 (7 lvl)
+
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ exdev_ctl_a/u_gen_sp/reg0_syn_81.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 20.833 22.878
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.187 22.691
+ clock uncertainty -0.000 22.691
+ clock recovergence pessimism 0.095 22.786
+ Required time 22.786
+---------------------------------------------------------------------------------------------------------
+ Slack 12.294ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check): 12.405 ns
+ Start Point: exdev_ctl_a/u_gen_sp/reg9_syn_100.clk (rising edge triggered by clock a_pclk)
+ End Point: exdev_ctl_a/u_gen_sp/reg0_syn_81.sr (rising edge triggered by clock a_pclk)
+ Clock group: a_lvds_clk_p
+ Process: Slow
+ Data Path Delay: 8.105ns (logic 3.602ns, net 4.503ns, 44% logic)
+ Logic Levels: 7 ( LUT5=5 ADDER=2 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ exdev_ctl_a/u_gen_sp/reg9_syn_100.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 2.276
+---------------------------------------------------------------------------------------------------------
+ exdev_ctl_a/u_gen_sp/reg9_syn_100.q[0] clk2q 0.146 r 2.422
+ exdev_ctl_a/u_gen_sp/sub1_syn_103.b[0] (exdev_ctl_a/u_gen_sp/sp_t_d1[4]) net (fanout = 1) 0.803 r 3.225 ../../../../hg_mp/fe/gen_sp.v(87)
+ exdev_ctl_a/u_gen_sp/sub1_syn_103.fco cell (ADDER) 0.836 r 4.061
+ exdev_ctl_a/u_gen_sp/sub1_syn_104.fci (exdev_ctl_a/u_gen_sp/sub1_syn_91) net (fanout = 1) 0.000 f 4.061 ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_a/u_gen_sp/sub1_syn_104.fco cell (ADDER) 0.132 r 4.193
+ exdev_ctl_a/u_gen_sp/sub1_syn_105.fci (exdev_ctl_a/u_gen_sp/sub1_syn_95) net (fanout = 1) 0.000 f 4.193 ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_a/u_gen_sp/sub1_syn_105.fx[0] cell (ADDER) 0.387 r 4.580
+ exdev_ctl_a/reg8_syn_103.a[1] (exdev_ctl_a/u_gen_sp/cnt_one_line_b5[12]) net (fanout = 1) 0.591 r 5.171
+ exdev_ctl_a/reg8_syn_103.f[1] cell (LUT5) 0.424 r 5.595
+ exdev_ctl_b/reg6_syn_103.a[1] (exdev_ctl_a/u_gen_sp/mux31_syn_140) net (fanout = 1) 0.738 r 6.333 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_b/reg6_syn_103.f[1] cell (LUT5) 0.424 r 6.757
+ u_bus_top/reg5_syn_196.a[0] (exdev_ctl_a/u_gen_sp/mux31_syn_142) net (fanout = 1) 0.307 r 7.064 ../../../../hg_mp/fe/gen_sp.v(137)
+ u_bus_top/reg5_syn_196.f[0] cell (LUT5) 0.424 r 7.488
+ exdev_ctl_a/reg8_syn_103.a[0] (exdev_ctl_a/u_gen_sp/mux31_syn_150) net (fanout = 1) 0.456 r 7.944 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_a/reg8_syn_103.f[0] cell (LUT5) 0.424 r 8.368
+ exdev_ctl_a/reg8_syn_109.d[1] (exdev_ctl_a/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.612 r 8.980
+ exdev_ctl_a/reg8_syn_109.f[1] cell (LUT5) 0.262 r 9.242
+ exdev_ctl_a/u_gen_sp/reg0_syn_81.sr (exdev_ctl_a/u_gen_sp/mux31_syn_19) net (fanout = 8) 0.996 r 10.238 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_a/u_gen_sp/reg0_syn_81 path2reg 0.143 10.381
+ Arrival time 10.381 (7 lvl)
+
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ exdev_ctl_a/u_gen_sp/reg0_syn_81.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 20.833 22.878
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.187 22.691
+ clock uncertainty -0.000 22.691
+ clock recovergence pessimism 0.095 22.786
+ Required time 22.786
+---------------------------------------------------------------------------------------------------------
+ Slack 12.405ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check): 12.598 ns
+ Start Point: exdev_ctl_a/u_gen_sp/reg9_syn_100.clk (rising edge triggered by clock a_pclk)
+ End Point: exdev_ctl_a/u_gen_sp/reg0_syn_81.sr (rising edge triggered by clock a_pclk)
+ Clock group: a_lvds_clk_p
+ Process: Slow
+ Data Path Delay: 7.912ns (logic 3.581ns, net 4.331ns, 45% logic)
+ Logic Levels: 7 ( LUT5=5 ADDER=2 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ exdev_ctl_a/u_gen_sp/reg9_syn_100.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 2.276
+---------------------------------------------------------------------------------------------------------
+ exdev_ctl_a/u_gen_sp/reg9_syn_100.q[1] clk2q 0.146 r 2.422
+ exdev_ctl_a/u_gen_sp/sub1_syn_104.a[0] (exdev_ctl_a/u_gen_sp/sp_t_d1[7]) net (fanout = 1) 0.631 r 3.053 ../../../../hg_mp/fe/gen_sp.v(87)
+ exdev_ctl_a/u_gen_sp/sub1_syn_104.fco cell (ADDER) 0.947 r 4.000
+ exdev_ctl_a/u_gen_sp/sub1_syn_105.fci (exdev_ctl_a/u_gen_sp/sub1_syn_95) net (fanout = 1) 0.000 f 4.000 ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_a/u_gen_sp/sub1_syn_105.fx[0] cell (ADDER) 0.387 r 4.387
+ exdev_ctl_a/reg8_syn_103.a[1] (exdev_ctl_a/u_gen_sp/cnt_one_line_b5[12]) net (fanout = 1) 0.591 r 4.978
+ exdev_ctl_a/reg8_syn_103.f[1] cell (LUT5) 0.424 r 5.402
+ exdev_ctl_b/reg6_syn_103.a[1] (exdev_ctl_a/u_gen_sp/mux31_syn_140) net (fanout = 1) 0.738 r 6.140 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_b/reg6_syn_103.f[1] cell (LUT5) 0.424 r 6.564
+ u_bus_top/reg5_syn_196.a[0] (exdev_ctl_a/u_gen_sp/mux31_syn_142) net (fanout = 1) 0.307 r 6.871 ../../../../hg_mp/fe/gen_sp.v(137)
+ u_bus_top/reg5_syn_196.f[0] cell (LUT5) 0.424 r 7.295
+ exdev_ctl_a/reg8_syn_103.a[0] (exdev_ctl_a/u_gen_sp/mux31_syn_150) net (fanout = 1) 0.456 r 7.751 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_a/reg8_syn_103.f[0] cell (LUT5) 0.424 r 8.175
+ exdev_ctl_a/reg8_syn_109.d[1] (exdev_ctl_a/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.612 r 8.787
+ exdev_ctl_a/reg8_syn_109.f[1] cell (LUT5) 0.262 r 9.049
+ exdev_ctl_a/u_gen_sp/reg0_syn_81.sr (exdev_ctl_a/u_gen_sp/mux31_syn_19) net (fanout = 8) 0.996 r 10.045 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_a/u_gen_sp/reg0_syn_81 path2reg 0.143 10.188
+ Arrival time 10.188 (7 lvl)
+
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ exdev_ctl_a/u_gen_sp/reg0_syn_81.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 20.833 22.878
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.187 22.691
+ clock uncertainty -0.000 22.691
+ clock recovergence pessimism 0.095 22.786
+ Required time 22.786
+---------------------------------------------------------------------------------------------------------
+ Slack 12.598ns
---------------------------------------------------------------------------------------------------------
Hold checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_290 (1 paths)
+Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1 (10 paths)
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.183 ns
- Start Point: u_bus_top/u_local_bus_slve_cis/reg29_syn_166.clk (rising edge triggered by clock clk_adc)
- End Point: u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_290.mi[0] (rising edge triggered by clock a_pclk)
+ Slack (hold check): 0.114 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_741.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.addra[7] (rising edge triggered by clock a_pclk)
Clock group: a_lvds_clk_p
Process: Fast
- Data Path Delay: 0.436ns (logic 0.204ns, net 0.232ns, 46% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[4] 0.000 0.000
- u_bus_top/u_local_bus_slve_cis/reg29_syn_166.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4)
- launch clock edge 0.000 1.938
----------------------------------------------------------------------------------------------------------
- u_bus_top/u_local_bus_slve_cis/reg29_syn_166.q[0] clk2q 0.109 r 2.047
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_290.mi[0] (u_pixel_cdc/u_clk_cis_frame_num/signal_from[15]) net (fanout = 3) 0.232 r 2.279 ../../../../hg_mp/cdc/cdc_sync.v(9)
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_290 path2reg0 0.095 2.374
- Arrival time 2.374 (0 lvl)
-
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_290.clk (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 0.000 2.130
----------------------------------------------------------------------------------------------------------
- cell hold 0.061 2.191
- clock uncertainty 0.000 2.191
- clock recovergence pessimism 0.000 2.191
- Required time 2.191
----------------------------------------------------------------------------------------------------------
- Slack 0.183ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1 (8 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.186 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_606.clk (rising edge triggered by clock a_pclk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1.dia[2] (rising edge triggered by clock a_pclk)
- Clock group: a_lvds_clk_p
- Process: Fast
- Data Path Delay: 0.431ns (logic 0.109ns, net 0.322ns, 25% logic)
+ Data Path Delay: 0.359ns (logic 0.109ns, net 0.250ns, 30% logic)
Logic Levels: 1 ( EMB=1 )
Point Type Incr Path Info
@@ -560,19 +542,19 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_s
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_606.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_741.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_606.q[1] clk2q 0.109 r 2.047
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1.dia[2] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[2]) net (fanout = 2) 0.322 r 2.369 ../../../../hg_mp/fe/prebuffer.v(325)
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1 path2reg (EMB) 0.000 2.369
- Arrival time 2.369 (1 lvl)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_741.q[0] clk2q 0.109 r 2.047
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.addra[7] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[34]) net (fanout = 2) 0.250 r 2.297 ../../../../hg_mp/fe/prebuffer.v(327)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1 path2reg (EMB) 0.000 2.297
+ Arrival time 2.297 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell hold 0.200 2.330
@@ -580,167 +562,13 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_s
clock recovergence pessimism -0.147 2.183
Required time 2.183
---------------------------------------------------------------------------------------------------------
- Slack 0.186ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check): 0.195 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_606.clk (rising edge triggered by clock a_pclk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1.dia[1] (rising edge triggered by clock a_pclk)
- Clock group: a_lvds_clk_p
- Process: Fast
- Data Path Delay: 0.440ns (logic 0.109ns, net 0.331ns, 24% logic)
- Logic Levels: 1 ( EMB=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_606.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 1.938
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_606.q[0] clk2q 0.109 r 2.047
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1.dia[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[1]) net (fanout = 2) 0.331 r 2.378 ../../../../hg_mp/fe/prebuffer.v(325)
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1 path2reg (EMB) 0.000 2.378
- Arrival time 2.378 (1 lvl)
-
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 0.000 2.130
----------------------------------------------------------------------------------------------------------
- cell hold 0.200 2.330
- clock uncertainty 0.000 2.330
- clock recovergence pessimism -0.147 2.183
- Required time 2.183
----------------------------------------------------------------------------------------------------------
- Slack 0.195ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check): 0.195 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_586.clk (rising edge triggered by clock a_pclk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1.dia[0] (rising edge triggered by clock a_pclk)
- Clock group: a_lvds_clk_p
- Process: Fast
- Data Path Delay: 0.440ns (logic 0.109ns, net 0.331ns, 24% logic)
- Logic Levels: 1 ( EMB=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_586.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 1.938
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_586.q[1] clk2q 0.109 r 2.047
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1.dia[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[0]) net (fanout = 2) 0.331 r 2.378 ../../../../hg_mp/fe/prebuffer.v(325)
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1 path2reg (EMB) 0.000 2.378
- Arrival time 2.378 (1 lvl)
-
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 0.000 2.130
----------------------------------------------------------------------------------------------------------
- cell hold 0.200 2.330
- clock uncertainty 0.000 2.330
- clock recovergence pessimism -0.147 2.183
- Required time 2.183
----------------------------------------------------------------------------------------------------------
- Slack 0.195ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1 (8 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.195 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_618.clk (rising edge triggered by clock a_pclk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1.dia[6] (rising edge triggered by clock a_pclk)
- Clock group: a_lvds_clk_p
- Process: Fast
- Data Path Delay: 0.440ns (logic 0.109ns, net 0.331ns, 24% logic)
- Logic Levels: 1 ( EMB=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_618.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 1.938
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_618.q[0] clk2q 0.109 r 2.047
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1.dia[6] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[30]) net (fanout = 2) 0.331 r 2.378 ../../../../hg_mp/fe/prebuffer.v(325)
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1 path2reg (EMB) 0.000 2.378
- Arrival time 2.378 (1 lvl)
-
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 0.000 2.130
----------------------------------------------------------------------------------------------------------
- cell hold 0.200 2.330
- clock uncertainty 0.000 2.330
- clock recovergence pessimism -0.147 2.183
- Required time 2.183
----------------------------------------------------------------------------------------------------------
- Slack 0.195ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check): 0.205 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_620.clk (rising edge triggered by clock a_pclk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1.dia[4] (rising edge triggered by clock a_pclk)
- Clock group: a_lvds_clk_p
- Process: Fast
- Data Path Delay: 0.450ns (logic 0.109ns, net 0.341ns, 24% logic)
- Logic Levels: 1 ( EMB=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_620.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 1.938
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_620.q[0] clk2q 0.109 r 2.047
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1.dia[4] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[28]) net (fanout = 2) 0.341 r 2.388 ../../../../hg_mp/fe/prebuffer.v(325)
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1 path2reg (EMB) 0.000 2.388
- Arrival time 2.388 (1 lvl)
-
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 0.000 2.130
----------------------------------------------------------------------------------------------------------
- cell hold 0.200 2.330
- clock uncertainty 0.000 2.330
- clock recovergence pessimism -0.147 2.183
- Required time 2.183
----------------------------------------------------------------------------------------------------------
- Slack 0.205ns
+ Slack 0.114ns
---------------------------------------------------------------------------------------------------------
Slack (hold check): 0.234 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_541.clk (rising edge triggered by clock a_pclk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1.dia[7] (rising edge triggered by clock a_pclk)
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_652.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.addra[5] (rising edge triggered by clock a_pclk)
Clock group: a_lvds_clk_p
Process: Fast
Data Path Delay: 0.479ns (logic 0.109ns, net 0.370ns, 22% logic)
@@ -752,19 +580,19 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_s
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_541.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_652.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_541.q[0] clk2q 0.109 r 2.047
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1.dia[7] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[31]) net (fanout = 2) 0.370 r 2.417 ../../../../hg_mp/fe/prebuffer.v(325)
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1 path2reg (EMB) 0.000 2.417
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_652.q[1] clk2q 0.109 r 2.047
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.addra[5] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[32]) net (fanout = 2) 0.370 r 2.417 ../../../../hg_mp/fe/prebuffer.v(327)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1 path2reg (EMB) 0.000 2.417
Arrival time 2.417 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell hold 0.200 2.330
@@ -774,6 +602,120 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_s
---------------------------------------------------------------------------------------------------------
Slack 0.234ns
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check): 0.311 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_648.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.addra[12] (rising edge triggered by clock a_pclk)
+ Clock group: a_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.556ns (logic 0.109ns, net 0.447ns, 19% logic)
+ Logic Levels: 1 ( EMB=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_648.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_648.q[1] clk2q 0.109 r 2.047
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.addra[12] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[39]) net (fanout = 2) 0.447 r 2.494 ../../../../hg_mp/fe/prebuffer.v(327)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1 path2reg (EMB) 0.000 2.494
+ Arrival time 2.494 (1 lvl)
+
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.200 2.330
+ clock uncertainty 0.000 2.330
+ clock recovergence pessimism -0.147 2.183
+ Required time 2.183
+---------------------------------------------------------------------------------------------------------
+ Slack 0.311ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_333 (1 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.183 ns
+ Start Point: u_bus_top/u_local_bus_slve_cis/reg29_syn_227.clk (rising edge triggered by clock clk_adc)
+ End Point: u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_333.mi[0] (rising edge triggered by clock a_pclk)
+ Clock group: a_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.436ns (logic 0.204ns, net 0.232ns, 46% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[4] 0.000 0.000
+ u_bus_top/u_local_bus_slve_cis/reg29_syn_227.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ u_bus_top/u_local_bus_slve_cis/reg29_syn_227.q[0] clk2q 0.109 r 2.047
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_333.mi[0] (u_pixel_cdc/u_clk_cis_frame_num/signal_from[4]) net (fanout = 3) 0.232 r 2.279 ../../../../hg_mp/cdc/cdc_sync.v(9)
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_333 path2reg0 0.095 2.374
+ Arrival time 2.374 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_333.clk (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.061 2.191
+ clock uncertainty 0.000 2.191
+ clock recovergence pessimism 0.000 2.191
+ Required time 2.191
+---------------------------------------------------------------------------------------------------------
+ Slack 0.183ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point exdev_ctl_a/reg6_syn_89 (1 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.183 ns
+ Start Point: u_bus_top/u_local_bus_slve_cis/reg40_syn_204.clk (rising edge triggered by clock clk_adc)
+ End Point: exdev_ctl_a/reg6_syn_89.mi[0] (rising edge triggered by clock a_pclk)
+ Clock group: a_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.436ns (logic 0.204ns, net 0.232ns, 46% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[4] 0.000 0.000
+ u_bus_top/u_local_bus_slve_cis/reg40_syn_204.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ u_bus_top/u_local_bus_slve_cis/reg40_syn_204.q[0] clk2q 0.109 r 2.047
+ exdev_ctl_a/reg6_syn_89.mi[0] (u_bus_top/u_local_bus_slve_cis/reg1[18]) net (fanout = 3) 0.232 r 2.279 ../../../../hg_mp/local_bus/local_bus_slve_cis.v(55)
+ exdev_ctl_a/reg6_syn_89 path2reg0 0.095 2.374
+ Arrival time 2.374 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ exdev_ctl_a/reg6_syn_89.clk (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.061 2.191
+ clock uncertainty 0.000 2.191
+ clock recovergence pessimism 0.000 2.191
+ Required time 2.191
+---------------------------------------------------------------------------------------------------------
+ Slack 0.183ns
+
---------------------------------------------------------------------------------------------------------
@@ -781,406 +723,476 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_s
Timing constraint: clock: a_sclk
Clock = a_sclk, period 5.952ns, rising at 0ns, falling at 2.976ns
-282 endpoints analyzed totally, and 690 paths analyzed
+282 endpoints analyzed totally, and 722 paths analyzed
0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 2.151ns
+Minimum period is 2.239ns
---------------------------------------------------------------------------------------------------------
-Paths for end point ua_lvds_rx/rx_clk_sync_reg_syn_5 (7 paths)
+Paths for end point ua_lvds_rx/reg14_syn_64 (7 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 3.801 ns
- Start Point: ua_lvds_rx/reg7_syn_32.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock a_sclk)
+ Slack (setup check): 3.713 ns
+ Start Point: ua_lvds_rx/reg7_syn_33.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/reg14_syn_64.d[0] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 1.999ns (logic 0.941ns, net 1.058ns, 47% logic)
- Logic Levels: 2 ( LUT5=1 )
+ Data Path Delay: 2.087ns (logic 0.891ns, net 1.196ns, 42% logic)
+ Logic Levels: 2 ( LUT3=1 LUT5=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg7_syn_32.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.410
+ ua_lvds_rx/reg7_syn_33.clk (ua_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg7_syn_32.q[1] clk2q 0.146 r 2.556
- ua_lvds_rx/rx_clk_sync_reg_syn_5.a[0] (ua_lvds_rx/rx_clk_sft[0]) net (fanout = 2) 0.602 r 3.158 encrypted_text(0)
- ua_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.424 r 3.582
- ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ua_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.456 r 4.038 encrypted_text(0)
- ua_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.409
- Arrival time 4.409 (2 lvl)
+ ua_lvds_rx/reg7_syn_33.q[0] clk2q 0.146 r 2.422
+ ua_lvds_rx/reg14_syn_62.b[0] (ua_lvds_rx/rx_clk_sft[1]) net (fanout = 2) 0.602 r 3.024 encrypted_text(0)
+ ua_lvds_rx/reg14_syn_62.f[0] cell (LUT5) 0.431 r 3.455
+ ua_lvds_rx/reg14_syn_64.d[0] (ua_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.594 r 4.049 encrypted_text(0)
+ ua_lvds_rx/reg14_syn_64 path2reg0 (LUT3) 0.314 4.363
+ Arrival time 4.363 (2 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/rx_clk_sync_reg_syn_5.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 8.118
+ ua_lvds_rx/reg14_syn_64.clk (ua_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 7.997
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 8.002
- clock uncertainty -0.000 8.002
- clock recovergence pessimism 0.208 8.210
- Required time 8.210
+ cell setup -0.116 7.881
+ clock uncertainty -0.000 7.881
+ clock recovergence pessimism 0.195 8.076
+ Required time 8.076
---------------------------------------------------------------------------------------------------------
- Slack 3.801ns
+ Slack 3.713ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 3.877 ns
- Start Point: ua_lvds_rx/reg11_syn_17.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock a_sclk)
+ Slack (setup check): 3.811 ns
+ Start Point: ua_lvds_rx/reg7_syn_28.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/reg14_syn_64.d[0] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 1.923ns (logic 0.865ns, net 1.058ns, 44% logic)
- Logic Levels: 2 ( LUT5=1 )
+ Data Path Delay: 2.004ns (logic 0.808ns, net 1.196ns, 40% logic)
+ Logic Levels: 2 ( LUT3=1 LUT5=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg11_syn_17.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.410
+ ua_lvds_rx/reg7_syn_28.clk (ua_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg11_syn_17.q[0] clk2q 0.146 r 2.556
- ua_lvds_rx/rx_clk_sync_reg_syn_5.c[0] (ua_lvds_rx/rx_clk_sft[2]) net (fanout = 2) 0.602 r 3.158 encrypted_text(0)
- ua_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.348 r 3.506
- ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ua_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.456 r 3.962 encrypted_text(0)
- ua_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.333
- Arrival time 4.333 (2 lvl)
+ ua_lvds_rx/reg7_syn_28.q[1] clk2q 0.146 r 2.422
+ ua_lvds_rx/reg14_syn_62.c[0] (ua_lvds_rx/rx_clk_sft[2]) net (fanout = 2) 0.602 r 3.024 encrypted_text(0)
+ ua_lvds_rx/reg14_syn_62.f[0] cell (LUT5) 0.348 r 3.372
+ ua_lvds_rx/reg14_syn_64.d[0] (ua_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.594 r 3.966 encrypted_text(0)
+ ua_lvds_rx/reg14_syn_64 path2reg0 (LUT3) 0.314 4.280
+ Arrival time 4.280 (2 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/rx_clk_sync_reg_syn_5.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 8.118
+ ua_lvds_rx/reg14_syn_64.clk (ua_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 7.997
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 8.002
- clock uncertainty -0.000 8.002
- clock recovergence pessimism 0.208 8.210
- Required time 8.210
+ cell setup -0.116 7.881
+ clock uncertainty -0.000 7.881
+ clock recovergence pessimism 0.210 8.091
+ Required time 8.091
---------------------------------------------------------------------------------------------------------
- Slack 3.877ns
+ Slack 3.811ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.066 ns
- Start Point: ua_lvds_rx/reg7_syn_32.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock a_sclk)
+ Slack (setup check): 3.988 ns
+ Start Point: ua_lvds_rx/reg7_syn_25.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/reg14_syn_64.d[0] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 1.734ns (logic 0.948ns, net 0.786ns, 54% logic)
- Logic Levels: 2 ( LUT5=1 )
+ Data Path Delay: 1.812ns (logic 0.742ns, net 1.070ns, 40% logic)
+ Logic Levels: 2 ( LUT3=1 LUT5=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg7_syn_32.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.410
+ ua_lvds_rx/reg7_syn_25.clk (ua_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg7_syn_32.q[0] clk2q 0.146 r 2.556
- ua_lvds_rx/rx_clk_sync_reg_syn_5.b[0] (ua_lvds_rx/rx_clk_sft[1]) net (fanout = 2) 0.330 r 2.886 encrypted_text(0)
- ua_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.431 r 3.317
- ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ua_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.456 r 3.773 encrypted_text(0)
- ua_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.144
- Arrival time 4.144 (2 lvl)
+ ua_lvds_rx/reg7_syn_25.q[0] clk2q 0.146 r 2.422
+ ua_lvds_rx/reg14_syn_62.e[0] (ua_lvds_rx/rx_clk_sft[4]) net (fanout = 2) 0.476 r 2.898 encrypted_text(0)
+ ua_lvds_rx/reg14_syn_62.f[0] cell (LUT5) 0.282 r 3.180
+ ua_lvds_rx/reg14_syn_64.d[0] (ua_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.594 r 3.774 encrypted_text(0)
+ ua_lvds_rx/reg14_syn_64 path2reg0 (LUT3) 0.314 4.088
+ Arrival time 4.088 (2 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/rx_clk_sync_reg_syn_5.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 8.118
+ ua_lvds_rx/reg14_syn_64.clk (ua_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 7.997
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 8.002
- clock uncertainty -0.000 8.002
- clock recovergence pessimism 0.208 8.210
- Required time 8.210
+ cell setup -0.116 7.881
+ clock uncertainty -0.000 7.881
+ clock recovergence pessimism 0.195 8.076
+ Required time 8.076
---------------------------------------------------------------------------------------------------------
- Slack 4.066ns
+ Slack 3.988ns
---------------------------------------------------------------------------------------------------------
Paths for end point ua_lvds_rx/reg8_syn_155 (9 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.145 ns
- Start Point: ua_lvds_rx/reg8_syn_155.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/reg8_syn_155.a[1] (rising edge triggered by clock a_sclk)
+ Slack (setup check): 4.003 ns
+ Start Point: ua_lvds_rx/reg8_syn_161.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/reg8_syn_155.c[1] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 1.691ns (logic 0.878ns, net 0.813ns, 51% logic)
+ Data Path Delay: 1.797ns (logic 0.701ns, net 1.096ns, 39% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg8_syn_155.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.410
+ ua_lvds_rx/reg8_syn_161.clk (ua_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg8_syn_155.q[0] clk2q 0.146 r 2.556
- ua_lvds_rx/reg8_syn_155.a[1] (ua_lvds_rx/para_data[12]) net (fanout = 3) 0.813 r 3.369 encrypted_text(0)
- ua_lvds_rx/reg8_syn_155 path2reg0 0.732 4.101
- Arrival time 4.101 (1 lvl)
+ ua_lvds_rx/reg8_syn_161.q[0] clk2q 0.146 r 2.422
+ ua_lvds_rx/reg8_syn_155.c[1] (ua_lvds_rx/rx_data[37]) net (fanout = 4) 1.096 r 3.518 encrypted_text(0)
+ ua_lvds_rx/reg8_syn_155 path2reg0 0.555 4.073
+ Arrival time 4.073 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg8_syn_155.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 8.118
+ ua_lvds_rx/reg8_syn_155.clk (ua_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 7.997
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 8.002
- clock uncertainty -0.000 8.002
- clock recovergence pessimism 0.244 8.246
- Required time 8.246
+ cell setup -0.116 7.881
+ clock uncertainty -0.000 7.881
+ clock recovergence pessimism 0.195 8.076
+ Required time 8.076
---------------------------------------------------------------------------------------------------------
- Slack 4.145ns
+ Slack 4.003ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.492 ns
- Start Point: ua_lvds_rx/reg8_syn_155.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/reg8_syn_155.b[1] (rising edge triggered by clock a_sclk)
+ Slack (setup check): 4.003 ns
+ Start Point: ua_lvds_rx/reg8_syn_161.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/reg8_syn_155.c[0] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 1.344ns (logic 0.803ns, net 0.541ns, 59% logic)
+ Data Path Delay: 1.797ns (logic 0.701ns, net 1.096ns, 39% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg8_syn_155.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.410
+ ua_lvds_rx/reg8_syn_161.clk (ua_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg8_syn_155.q[1] clk2q 0.146 r 2.556
- ua_lvds_rx/reg8_syn_155.b[1] (ua_lvds_rx/rx_data[13]) net (fanout = 5) 0.541 r 3.097 encrypted_text(0)
- ua_lvds_rx/reg8_syn_155 path2reg0 0.657 3.754
- Arrival time 3.754 (1 lvl)
+ ua_lvds_rx/reg8_syn_161.q[0] clk2q 0.146 r 2.422
+ ua_lvds_rx/reg8_syn_155.c[0] (ua_lvds_rx/rx_data[37]) net (fanout = 4) 1.096 r 3.518 encrypted_text(0)
+ ua_lvds_rx/reg8_syn_155 path2reg0 0.555 4.073
+ Arrival time 4.073 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg8_syn_155.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 8.118
+ ua_lvds_rx/reg8_syn_155.clk (ua_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 7.997
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 8.002
- clock uncertainty -0.000 8.002
- clock recovergence pessimism 0.244 8.246
- Required time 8.246
+ cell setup -0.116 7.881
+ clock uncertainty -0.000 7.881
+ clock recovergence pessimism 0.195 8.076
+ Required time 8.076
---------------------------------------------------------------------------------------------------------
- Slack 4.492ns
+ Slack 4.003ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.492 ns
- Start Point: ua_lvds_rx/reg8_syn_155.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/reg8_syn_155.b[0] (rising edge triggered by clock a_sclk)
+ Slack (setup check): 4.125 ns
+ Start Point: ua_lvds_rx/reg8_syn_166.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/reg8_syn_155.d[1] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 1.344ns (logic 0.803ns, net 0.541ns, 59% logic)
+ Data Path Delay: 1.647ns (logic 0.655ns, net 0.992ns, 39% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg8_syn_155.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.410
+ ua_lvds_rx/reg8_syn_166.clk (ua_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg8_syn_155.q[1] clk2q 0.146 r 2.556
- ua_lvds_rx/reg8_syn_155.b[0] (ua_lvds_rx/rx_data[13]) net (fanout = 5) 0.541 r 3.097 encrypted_text(0)
- ua_lvds_rx/reg8_syn_155 path2reg0 0.657 3.754
- Arrival time 3.754 (1 lvl)
+ ua_lvds_rx/reg8_syn_166.q[0] clk2q 0.146 r 2.422
+ ua_lvds_rx/reg8_syn_155.d[1] (ua_lvds_rx/sync0) net (fanout = 45) 0.992 r 3.414 encrypted_text(0)
+ ua_lvds_rx/reg8_syn_155 path2reg0 0.509 3.923
+ Arrival time 3.923 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg8_syn_155.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 8.118
+ ua_lvds_rx/reg8_syn_155.clk (ua_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 7.997
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 8.002
- clock uncertainty -0.000 8.002
- clock recovergence pessimism 0.244 8.246
- Required time 8.246
+ cell setup -0.116 7.881
+ clock uncertainty -0.000 7.881
+ clock recovergence pessimism 0.167 8.048
+ Required time 8.048
---------------------------------------------------------------------------------------------------------
- Slack 4.492ns
+ Slack 4.125ns
---------------------------------------------------------------------------------------------------------
-Paths for end point ua_lvds_rx/reg8_syn_151 (9 paths)
+Paths for end point ua_lvds_rx/reg3_syn_198 (5 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.198 ns
- Start Point: ua_lvds_rx/reg8_syn_151.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/reg8_syn_151.a[1] (rising edge triggered by clock a_sclk)
+ Slack (setup check): 4.009 ns
+ Start Point: ua_lvds_rx/reg8_syn_161.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/reg3_syn_198.b[0] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 1.638ns (logic 0.878ns, net 0.760ns, 53% logic)
- Logic Levels: 1
+ Data Path Delay: 1.791ns (logic 0.695ns, net 1.096ns, 38% logic)
+ Logic Levels: 1 ( LUT5=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg8_syn_151.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.410
+ ua_lvds_rx/reg8_syn_161.clk (ua_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg8_syn_151.q[0] clk2q 0.146 r 2.556
- ua_lvds_rx/reg8_syn_151.a[1] (ua_lvds_rx/para_data[22]) net (fanout = 3) 0.760 r 3.316 encrypted_text(0)
- ua_lvds_rx/reg8_syn_151 path2reg0 0.732 4.048
- Arrival time 4.048 (1 lvl)
+ ua_lvds_rx/reg8_syn_161.q[0] clk2q 0.146 r 2.422
+ ua_lvds_rx/reg3_syn_198.b[0] (ua_lvds_rx/rx_data[37]) net (fanout = 4) 1.096 r 3.518 encrypted_text(0)
+ ua_lvds_rx/reg3_syn_198 path2reg0 (LUT5) 0.549 4.067
+ Arrival time 4.067 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg8_syn_151.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 8.118
+ ua_lvds_rx/reg3_syn_198.clk (ua_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 7.997
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 8.002
- clock uncertainty -0.000 8.002
- clock recovergence pessimism 0.244 8.246
- Required time 8.246
+ cell setup -0.116 7.881
+ clock uncertainty -0.000 7.881
+ clock recovergence pessimism 0.195 8.076
+ Required time 8.076
---------------------------------------------------------------------------------------------------------
- Slack 4.198ns
+ Slack 4.009ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.320 ns
- Start Point: add1_syn_65.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/reg8_syn_151.b[1] (rising edge triggered by clock a_sclk)
+ Slack (setup check): 4.454 ns
+ Start Point: ua_lvds_rx/reg8_syn_198.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/reg3_syn_198.c[0] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 1.452ns (logic 0.803ns, net 0.649ns, 55% logic)
- Logic Levels: 1
+ Data Path Delay: 1.361ns (logic 0.612ns, net 0.749ns, 44% logic)
+ Logic Levels: 1 ( LUT5=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- add1_syn_65.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.410
+ ua_lvds_rx/reg8_syn_198.clk (ua_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- add1_syn_65.q[1] clk2q 0.146 r 2.556
- ua_lvds_rx/reg8_syn_151.b[1] (ua_lvds_rx/rx_data[25]) net (fanout = 4) 0.649 r 3.205 encrypted_text(0)
- ua_lvds_rx/reg8_syn_151 path2reg0 0.657 3.862
- Arrival time 3.862 (1 lvl)
+ ua_lvds_rx/reg8_syn_198.q[1] clk2q 0.146 r 2.422
+ ua_lvds_rx/reg3_syn_198.c[0] (ua_lvds_rx/rx_data[38]) net (fanout = 2) 0.749 r 3.171 encrypted_text(0)
+ ua_lvds_rx/reg3_syn_198 path2reg0 (LUT5) 0.466 3.637
+ Arrival time 3.637 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg8_syn_151.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 8.118
+ ua_lvds_rx/reg3_syn_198.clk (ua_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 7.997
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 8.002
- clock uncertainty -0.000 8.002
- clock recovergence pessimism 0.180 8.182
- Required time 8.182
+ cell setup -0.116 7.881
+ clock uncertainty -0.000 7.881
+ clock recovergence pessimism 0.210 8.091
+ Required time 8.091
---------------------------------------------------------------------------------------------------------
- Slack 4.320ns
+ Slack 4.454ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.320 ns
- Start Point: add1_syn_65.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/reg8_syn_151.b[0] (rising edge triggered by clock a_sclk)
+ Slack (setup check): 4.486 ns
+ Start Point: ua_lvds_rx/reg14_syn_62.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/reg3_syn_198.e[0] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Slow
- Data Path Delay: 1.452ns (logic 0.803ns, net 0.649ns, 55% logic)
- Logic Levels: 1
+ Data Path Delay: 1.286ns (logic 0.546ns, net 0.740ns, 42% logic)
+ Logic Levels: 1 ( LUT5=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- add1_syn_65.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.410
+ ua_lvds_rx/reg14_syn_62.clk (ua_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- add1_syn_65.q[1] clk2q 0.146 r 2.556
- ua_lvds_rx/reg8_syn_151.b[0] (ua_lvds_rx/rx_data[25]) net (fanout = 4) 0.649 r 3.205 encrypted_text(0)
- ua_lvds_rx/reg8_syn_151 path2reg0 0.657 3.862
- Arrival time 3.862 (1 lvl)
+ ua_lvds_rx/reg14_syn_62.q[0] clk2q 0.146 r 2.422
+ ua_lvds_rx/reg3_syn_198.e[0] (ua_lvds_rx/sync1) net (fanout = 32) 0.740 r 3.162 encrypted_text(0)
+ ua_lvds_rx/reg3_syn_198 path2reg0 (LUT5) 0.400 3.562
+ Arrival time 3.562 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg8_syn_151.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 8.118
+ ua_lvds_rx/reg3_syn_198.clk (ua_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 7.997
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 8.002
- clock uncertainty -0.000 8.002
- clock recovergence pessimism 0.180 8.182
- Required time 8.182
+ cell setup -0.116 7.881
+ clock uncertainty -0.000 7.881
+ clock recovergence pessimism 0.167 8.048
+ Required time 8.048
---------------------------------------------------------------------------------------------------------
- Slack 4.320ns
+ Slack 4.486ns
---------------------------------------------------------------------------------------------------------
Hold checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point ua_lvds_rx/ramread0_syn_46 (2 paths)
+Paths for end point ua_lvds_rx/ramread0_syn_32 (2 paths)
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.167 ns
- Start Point: ua_lvds_rx/reg3_syn_174.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/ramread0_syn_46.c[1] (rising edge triggered by clock a_sclk)
+ Slack (hold check): 0.092 ns
+ Start Point: ua_lvds_rx/reg3_syn_190.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/ramread0_syn_32.c[1] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Fast
- Data Path Delay: 0.325ns (logic 0.109ns, net 0.216ns, 33% logic)
+ Data Path Delay: 0.220ns (logic 0.109ns, net 0.111ns, 49% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg3_syn_174.clk (ua_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.029
+ ua_lvds_rx/reg3_syn_190.clk (ua_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg3_syn_174.q[1] clk2q 0.109 r 2.138
- ua_lvds_rx/ramread0_syn_46.c[1] (ua_lvds_rx/para_data[10]) net (fanout = 2) 0.216 r 2.354 encrypted_text(0)
- ua_lvds_rx/ramread0_syn_46 path2reg 0.000 2.354
- Arrival time 2.354 (1 lvl)
+ ua_lvds_rx/reg3_syn_190.q[1] clk2q 0.109 r 2.047
+ ua_lvds_rx/ramread0_syn_32.c[1] (ua_lvds_rx/para_data[6]) net (fanout = 2) 0.111 r 2.158 encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_32 path2reg 0.000 2.158
+ Arrival time 2.158 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/ramread0_syn_46.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.230
+ ua_lvds_rx/ramread0_syn_32.clk (ua_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.343
- clock uncertainty 0.000 2.343
- clock recovergence pessimism -0.156 2.187
- Required time 2.187
+ cell hold 0.113 2.243
+ clock uncertainty 0.000 2.243
+ clock recovergence pessimism -0.177 2.066
+ Required time 2.066
---------------------------------------------------------------------------------------------------------
- Slack 0.167ns
+ Slack 0.092ns
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.306 ns
+ Slack (hold check): 0.369 ns
Start Point: ua_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/ramread0_syn_46.c[0] (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/ramread0_syn_32.c[0] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Fast
- Data Path Delay: 0.464ns (logic 0.109ns, net 0.355ns, 23% logic)
+ Data Path Delay: 0.527ns (logic 0.109ns, net 0.418ns, 20% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg16_syn_31.clk (ua_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.029
+ ua_lvds_rx/reg16_syn_31.clk (ua_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg16_syn_31.q[0] clk2q 0.109 r 2.138
- ua_lvds_rx/ramread0_syn_46.c[0] (ua_lvds_rx/wcnt[2]) net (fanout = 9) 0.355 r 2.493 encrypted_text(0)
- ua_lvds_rx/ramread0_syn_46 path2reg 0.000 2.493
- Arrival time 2.493 (1 lvl)
+ ua_lvds_rx/reg16_syn_31.q[0] clk2q 0.109 r 2.047
+ ua_lvds_rx/ramread0_syn_32.c[0] (ua_lvds_rx/wcnt[2]) net (fanout = 9) 0.418 r 2.465 encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_32 path2reg 0.000 2.465
+ Arrival time 2.465 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/ramread0_syn_46.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.230
+ ua_lvds_rx/ramread0_syn_32.clk (ua_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.343
- clock uncertainty 0.000 2.343
- clock recovergence pessimism -0.156 2.187
- Required time 2.187
+ cell hold 0.113 2.243
+ clock uncertainty 0.000 2.243
+ clock recovergence pessimism -0.147 2.096
+ Required time 2.096
---------------------------------------------------------------------------------------------------------
- Slack 0.306ns
+ Slack 0.369ns
---------------------------------------------------------------------------------------------------------
Paths for end point ua_lvds_rx/ramread0_syn_102 (2 paths)
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.183 ns
- Start Point: ua_lvds_rx/reg3_syn_190.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/ramread0_syn_102.c[1] (rising edge triggered by clock a_sclk)
+ Slack (hold check): 0.114 ns
+ Start Point: ua_lvds_rx/reg16_syn_33.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/ramread0_syn_102.b[0] (rising edge triggered by clock a_sclk)
+ Clock group: a_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.242ns (logic 0.109ns, net 0.133ns, 45% logic)
+ Logic Levels: 1
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
+ ua_lvds_rx/reg16_syn_33.clk (ua_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ ua_lvds_rx/reg16_syn_33.q[0] clk2q 0.109 r 2.047
+ ua_lvds_rx/ramread0_syn_102.b[0] (ua_lvds_rx/wcnt[1]) net (fanout = 10) 0.133 r 2.180 encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_102 path2reg 0.000 2.180
+ Arrival time 2.180 (1 lvl)
+
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
+ ua_lvds_rx/ramread0_syn_102.clk (ua_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.113 2.243
+ clock uncertainty 0.000 2.243
+ clock recovergence pessimism -0.177 2.066
+ Required time 2.066
+---------------------------------------------------------------------------------------------------------
+ Slack 0.114ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check): 0.289 ns
+ Start Point: ua_lvds_rx/reg8_syn_147.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/ramread0_syn_102.b[1] (rising edge triggered by clock a_sclk)
+ Clock group: a_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.431ns (logic 0.109ns, net 0.322ns, 25% logic)
+ Logic Levels: 1
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
+ ua_lvds_rx/reg8_syn_147.clk (ua_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ ua_lvds_rx/reg8_syn_147.q[0] clk2q 0.109 r 2.047
+ ua_lvds_rx/ramread0_syn_102.b[1] (ua_lvds_rx/para_data[25]) net (fanout = 3) 0.322 r 2.369 encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_102 path2reg 0.000 2.369
+ Arrival time 2.369 (1 lvl)
+
+ source latency 0.000 0.000
+ u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
+ ua_lvds_rx/ramread0_syn_102.clk (ua_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.113 2.243
+ clock uncertainty 0.000 2.243
+ clock recovergence pessimism -0.163 2.080
+ Required time 2.080
+---------------------------------------------------------------------------------------------------------
+ Slack 0.289ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point ua_lvds_rx/ramread0_syn_116 (2 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.167 ns
+ Start Point: ua_lvds_rx/reg3_syn_198.clk (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/ramread0_syn_116.c[1] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Fast
Data Path Delay: 0.325ns (logic 0.109ns, net 0.216ns, 33% logic)
@@ -1190,129 +1202,59 @@ Paths for end point ua_lvds_rx/ramread0_syn_102 (2 paths)
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg3_syn_190.clk (ua_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.029
+ ua_lvds_rx/reg3_syn_198.clk (ua_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg3_syn_190.q[1] clk2q 0.109 r 2.138
- ua_lvds_rx/ramread0_syn_102.c[1] (ua_lvds_rx/para_data[26]) net (fanout = 2) 0.216 r 2.354 encrypted_text(0)
- ua_lvds_rx/ramread0_syn_102 path2reg 0.000 2.354
- Arrival time 2.354 (1 lvl)
+ ua_lvds_rx/reg3_syn_198.q[1] clk2q 0.109 r 2.047
+ ua_lvds_rx/ramread0_syn_116.c[1] (ua_lvds_rx/para_data[34]) net (fanout = 2) 0.216 r 2.263 encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_116 path2reg 0.000 2.263
+ Arrival time 2.263 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/ramread0_syn_102.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.230
+ ua_lvds_rx/ramread0_syn_116.clk (ua_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.343
- clock uncertainty 0.000 2.343
- clock recovergence pessimism -0.172 2.171
- Required time 2.171
+ cell hold 0.113 2.243
+ clock uncertainty 0.000 2.243
+ clock recovergence pessimism -0.147 2.096
+ Required time 2.096
---------------------------------------------------------------------------------------------------------
- Slack 0.183ns
+ Slack 0.167ns
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.306 ns
+ Slack (hold check): 0.415 ns
Start Point: ua_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/ramread0_syn_102.c[0] (rising edge triggered by clock a_sclk)
+ End Point: ua_lvds_rx/ramread0_syn_116.c[0] (rising edge triggered by clock a_sclk)
Clock group: a_lvds_clk_p
Process: Fast
- Data Path Delay: 0.464ns (logic 0.109ns, net 0.355ns, 23% logic)
+ Data Path Delay: 0.573ns (logic 0.109ns, net 0.464ns, 19% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg16_syn_31.clk (ua_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.029
+ ua_lvds_rx/reg16_syn_31.clk (ua_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg16_syn_31.q[0] clk2q 0.109 r 2.138
- ua_lvds_rx/ramread0_syn_102.c[0] (ua_lvds_rx/wcnt[2]) net (fanout = 9) 0.355 r 2.493 encrypted_text(0)
- ua_lvds_rx/ramread0_syn_102 path2reg 0.000 2.493
- Arrival time 2.493 (1 lvl)
+ ua_lvds_rx/reg16_syn_31.q[0] clk2q 0.109 r 2.047
+ ua_lvds_rx/ramread0_syn_116.c[0] (ua_lvds_rx/wcnt[2]) net (fanout = 9) 0.464 r 2.511 encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_116 path2reg 0.000 2.511
+ Arrival time 2.511 (1 lvl)
source latency 0.000 0.000
u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/ramread0_syn_102.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.230
+ ua_lvds_rx/ramread0_syn_116.clk (ua_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.343
- clock uncertainty 0.000 2.343
- clock recovergence pessimism -0.156 2.187
- Required time 2.187
+ cell hold 0.113 2.243
+ clock uncertainty 0.000 2.243
+ clock recovergence pessimism -0.147 2.096
+ Required time 2.096
---------------------------------------------------------------------------------------------------------
- Slack 0.306ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point ua_lvds_rx/ramread0_syn_18 (2 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.183 ns
- Start Point: ua_lvds_rx/reg3_syn_166.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/ramread0_syn_18.c[1] (rising edge triggered by clock a_sclk)
- Clock group: a_lvds_clk_p
- Process: Fast
- Data Path Delay: 0.325ns (logic 0.109ns, net 0.216ns, 33% logic)
- Logic Levels: 1
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg3_syn_166.clk (ua_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.029
----------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg3_syn_166.q[0] clk2q 0.109 r 2.138
- ua_lvds_rx/ramread0_syn_18.c[1] (ua_lvds_rx/para_data[2]) net (fanout = 2) 0.216 r 2.354 encrypted_text(0)
- ua_lvds_rx/ramread0_syn_18 path2reg 0.000 2.354
- Arrival time 2.354 (1 lvl)
-
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/ramread0_syn_18.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.230
----------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.343
- clock uncertainty 0.000 2.343
- clock recovergence pessimism -0.172 2.171
- Required time 2.171
----------------------------------------------------------------------------------------------------------
- Slack 0.183ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check): 0.306 ns
- Start Point: ua_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock a_sclk)
- End Point: ua_lvds_rx/ramread0_syn_18.c[0] (rising edge triggered by clock a_sclk)
- Clock group: a_lvds_clk_p
- Process: Fast
- Data Path Delay: 0.464ns (logic 0.109ns, net 0.355ns, 23% logic)
- Logic Levels: 1
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/reg16_syn_31.clk (ua_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.029
----------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg16_syn_31.q[0] clk2q 0.109 r 2.138
- ua_lvds_rx/ramread0_syn_18.c[0] (ua_lvds_rx/wcnt[2]) net (fanout = 9) 0.355 r 2.493 encrypted_text(0)
- ua_lvds_rx/ramread0_syn_18 path2reg 0.000 2.493
- Arrival time 2.493 (1 lvl)
-
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ua_lvds_rx/ramread0_syn_18.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.230
----------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.343
- clock uncertainty 0.000 2.343
- clock recovergence pessimism -0.156 2.187
- Required time 2.187
----------------------------------------------------------------------------------------------------------
- Slack 0.306ns
+ Slack 0.415ns
---------------------------------------------------------------------------------------------------------
@@ -1331,19 +1273,215 @@ Minimum period is 0ns
Timing constraint: clock: b_pclk
Clock = b_pclk, period 20.833ns, rising at 0ns, falling at 10.417ns
-5860 endpoints analyzed totally, and 101778 paths analyzed
+5876 endpoints analyzed totally, and 105758 paths analyzed
0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 10.495ns
+Minimum period is 10.242ns
---------------------------------------------------------------------------------------------------------
-Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494 (171 paths)
+Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23 (171 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 10.338 ns
+ Slack (setup check): 10.591 ns
Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494.a[1] (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.a[1] (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 10.452ns (logic 6.638ns, net 3.814ns, 63% logic)
+ Data Path Delay: 10.271ns (logic 6.287ns, net 3.984ns, 61% logic)
+ Logic Levels: 6 ( LUT5=4 ADDER=2 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 2.067
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[1] clk2q 3.433 r 5.500
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 0.882 r 6.382
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 7.088
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.088
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.f[0] cell (ADDER) 0.144 r 7.232
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7]) net (fanout = 1) 1.048 r 8.280
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[1] cell (LUT5) 0.424 r 8.704
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234) net (fanout = 1) 0.738 r 9.442 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[0] cell (LUT5) 0.424 r 9.866
+ sampling_fe_a/reg1_syn_61.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238) net (fanout = 1) 0.755 r 10.621 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/reg1_syn_61.f[0] cell (LUT5) 0.424 r 11.045
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.561 r 11.606 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23 path2reg0 (LUT5) 0.732 12.338
+ Arrival time 12.338 (6 lvl)
+
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 20.833 22.878
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.116 22.762
+ clock uncertainty -0.000 22.762
+ clock recovergence pessimism 0.167 22.929
+ Required time 22.929
+---------------------------------------------------------------------------------------------------------
+ Slack 10.591ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check): 10.591 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.a[0] (rising edge triggered by clock b_pclk)
+ Clock group: b_lvds_clk_p
+ Process: Slow
+ Data Path Delay: 10.271ns (logic 6.287ns, net 3.984ns, 61% logic)
+ Logic Levels: 6 ( LUT5=4 ADDER=2 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 2.067
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[1] clk2q 3.433 r 5.500
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 0.882 r 6.382
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 7.088
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.088
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.f[0] cell (ADDER) 0.144 r 7.232
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7]) net (fanout = 1) 1.048 r 8.280
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[1] cell (LUT5) 0.424 r 8.704
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234) net (fanout = 1) 0.738 r 9.442 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[0] cell (LUT5) 0.424 r 9.866
+ sampling_fe_a/reg1_syn_61.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238) net (fanout = 1) 0.755 r 10.621 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/reg1_syn_61.f[0] cell (LUT5) 0.424 r 11.045
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.561 r 11.606 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23 path2reg0 (LUT5) 0.732 12.338
+ Arrival time 12.338 (6 lvl)
+
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 20.833 22.878
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.116 22.762
+ clock uncertainty -0.000 22.762
+ clock recovergence pessimism 0.167 22.929
+ Required time 22.929
+---------------------------------------------------------------------------------------------------------
+ Slack 10.591ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check): 10.598 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.a[1] (rising edge triggered by clock b_pclk)
+ Clock group: b_lvds_clk_p
+ Process: Slow
+ Data Path Delay: 10.264ns (logic 6.281ns, net 3.983ns, 61% logic)
+ Logic Levels: 6 ( LUT5=4 ADDER=2 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 2.067
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[0] clk2q 3.433 r 5.500
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 0.881 r 6.381
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 7.008
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 7.008
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 7.081
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.081
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.f[0] cell (ADDER) 0.144 r 7.225
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7]) net (fanout = 1) 1.048 r 8.273
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[1] cell (LUT5) 0.424 r 8.697
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234) net (fanout = 1) 0.738 r 9.435 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[0] cell (LUT5) 0.424 r 9.859
+ sampling_fe_a/reg1_syn_61.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238) net (fanout = 1) 0.755 r 10.614 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/reg1_syn_61.f[0] cell (LUT5) 0.424 r 11.038
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.561 r 11.599 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23 path2reg0 (LUT5) 0.732 12.331
+ Arrival time 12.331 (6 lvl)
+
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 20.833 22.878
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.116 22.762
+ clock uncertainty -0.000 22.762
+ clock recovergence pessimism 0.167 22.929
+ Required time 22.929
+---------------------------------------------------------------------------------------------------------
+ Slack 10.598ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514 (70 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check): 10.711 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.a[0] (rising edge triggered by clock b_pclk)
+ Clock group: b_lvds_clk_p
+ Process: Slow
+ Data Path Delay: 10.151ns (logic 6.097ns, net 4.054ns, 60% logic)
+ Logic Levels: 6 ( LUT5=3 ADDER=2 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 2.067
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[1] clk2q 3.433 r 5.500
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 0.882 r 6.382
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 7.088
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.088
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.f[0] cell (ADDER) 0.144 r 7.232
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7]) net (fanout = 1) 1.048 r 8.280
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[1] cell (LUT5) 0.424 r 8.704
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234) net (fanout = 1) 0.738 r 9.442 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[0] cell (LUT5) 0.424 r 9.866
+ sampling_fe_a/reg1_syn_61.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238) net (fanout = 1) 0.755 r 10.621 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/reg1_syn_61.f[0] cell (LUT5) 0.424 r 11.045
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.631 r 11.676 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514 path2reg0 0.542 12.218
+ Arrival time 12.218 (6 lvl)
+
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 20.833 22.878
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.116 22.762
+ clock uncertainty -0.000 22.762
+ clock recovergence pessimism 0.167 22.929
+ Required time 22.929
+---------------------------------------------------------------------------------------------------------
+ Slack 10.711ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check): 10.718 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.a[0] (rising edge triggered by clock b_pclk)
+ Clock group: b_lvds_clk_p
+ Process: Slow
+ Data Path Delay: 10.144ns (logic 6.091ns, net 4.053ns, 60% logic)
Logic Levels: 6 ( LUT5=3 ADDER=2 )
Point Type Incr Path Info
@@ -1356,48 +1494,44 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/
launch clock edge 0.000 2.067
---------------------------------------------------------------------------------------------------------
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[0] clk2q 3.433 r 5.500
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.074 r 6.574
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 7.201
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 7.201
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 7.274
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.274
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 7.347
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 7.347
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 7.420
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 7.420
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.775
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_386.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.889 r 8.664
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_386.f[0] cell (LUT5) 0.424 r 9.088
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.456 r 9.544 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.f[1] cell (LUT5) 0.424 r 9.968
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234) net (fanout = 1) 0.738 r 10.706 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.f[0] cell (LUT5) 0.424 r 11.130
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.657 r 11.787 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494 path2reg0 0.732 12.519
- Arrival time 12.519 (6 lvl)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 0.881 r 6.381
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 7.008
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 7.008
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 7.081
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.081
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.f[0] cell (ADDER) 0.144 r 7.225
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7]) net (fanout = 1) 1.048 r 8.273
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[1] cell (LUT5) 0.424 r 8.697
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234) net (fanout = 1) 0.738 r 9.435 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[0] cell (LUT5) 0.424 r 9.859
+ sampling_fe_a/reg1_syn_61.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238) net (fanout = 1) 0.755 r 10.614 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/reg1_syn_61.f[0] cell (LUT5) 0.424 r 11.038
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.631 r 11.669 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514 path2reg0 0.542 12.211
+ Arrival time 12.211 (6 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 20.833 22.878
---------------------------------------------------------------------------------------------------------
cell setup -0.116 22.762
clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.095 22.857
- Required time 22.857
+ clock recovergence pessimism 0.167 22.929
+ Required time 22.929
---------------------------------------------------------------------------------------------------------
- Slack 10.338ns
+ Slack 10.718ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 10.338 ns
+ Slack (setup check): 10.783 ns
Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494.a[0] (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.a[0] (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 10.452ns (logic 6.638ns, net 3.814ns, 63% logic)
+ Data Path Delay: 10.079ns (logic 6.018ns, net 4.061ns, 59% logic)
Logic Levels: 6 ( LUT5=3 ADDER=2 )
Point Type Incr Path Info
@@ -1409,50 +1543,46 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 2.067
---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[0] clk2q 3.433 r 5.500
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.074 r 6.574
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 7.201
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 7.201
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 7.274
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.274
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 7.347
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 7.347
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 7.420
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 7.420
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.775
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_386.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.889 r 8.664
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_386.f[0] cell (LUT5) 0.424 r 9.088
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.456 r 9.544 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.f[1] cell (LUT5) 0.424 r 9.968
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234) net (fanout = 1) 0.738 r 10.706 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.f[0] cell (LUT5) 0.424 r 11.130
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.657 r 11.787 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494 path2reg0 0.732 12.519
- Arrival time 12.519 (6 lvl)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[2] clk2q 3.433 r 5.500
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[6]) net (fanout = 1) 0.889 r 6.389
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.627 r 7.016
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.016
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.f[0] cell (ADDER) 0.144 r 7.160
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7]) net (fanout = 1) 1.048 r 8.208
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[1] cell (LUT5) 0.424 r 8.632
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234) net (fanout = 1) 0.738 r 9.370 ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.f[0] cell (LUT5) 0.424 r 9.794
+ sampling_fe_a/reg1_syn_61.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238) net (fanout = 1) 0.755 r 10.549 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/reg1_syn_61.f[0] cell (LUT5) 0.424 r 10.973
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.631 r 11.604 ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514 path2reg0 0.542 12.146
+ Arrival time 12.146 (6 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 20.833 22.878
---------------------------------------------------------------------------------------------------------
cell setup -0.116 22.762
clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.095 22.857
- Required time 22.857
+ clock recovergence pessimism 0.167 22.929
+ Required time 22.929
---------------------------------------------------------------------------------------------------------
- Slack 10.338ns
+ Slack 10.783ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 10.434 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494.a[1] (rising edge triggered by clock b_pclk)
+Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_74 (214 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check): 11.561 ns
+ Start Point: exdev_ctl_b/u_gen_sp/reg9_syn_89.clk (rising edge triggered by clock b_pclk)
+ End Point: exdev_ctl_b/u_gen_sp/reg0_syn_74.sr (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 10.356ns (logic 6.419ns, net 3.937ns, 61% logic)
- Logic Levels: 6 ( LUT5=3 ADDER=2 )
+ Data Path Delay: 9.021ns (logic 4.365ns, net 4.656ns, 48% logic)
+ Logic Levels: 8 ( LUT5=5 ADDER=2 LUT4=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -1460,255 +1590,57 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 2.067
----------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[6] clk2q 3.433 r 5.500
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[10]) net (fanout = 1) 1.197 r 6.697
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.627 r 7.324
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 7.324
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.679
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_386.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.889 r 8.568
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_386.f[0] cell (LUT5) 0.424 r 8.992
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.456 r 9.448 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.f[1] cell (LUT5) 0.424 r 9.872
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234) net (fanout = 1) 0.738 r 10.610 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.f[0] cell (LUT5) 0.424 r 11.034
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.657 r 11.691 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494 path2reg0 0.732 12.423
- Arrival time 12.423 (6 lvl)
-
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 20.833 22.878
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 22.762
- clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.095 22.857
- Required time 22.857
----------------------------------------------------------------------------------------------------------
- Slack 10.434ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 (70 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check): 10.717 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (rising edge triggered by clock b_pclk)
- Clock group: b_lvds_clk_p
- Process: Slow
- Data Path Delay: 10.073ns (logic 6.448ns, net 3.625ns, 64% logic)
- Logic Levels: 6 ( LUT5=3 ADDER=2 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 2.067
----------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[0] clk2q 3.433 r 5.500
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.074 r 6.574
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 7.201
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 7.201
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 7.274
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.274
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 7.347
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 7.347
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 7.420
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 7.420
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.775
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_386.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.889 r 8.664
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_386.f[0] cell (LUT5) 0.424 r 9.088
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.456 r 9.544 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.f[1] cell (LUT5) 0.424 r 9.968
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234) net (fanout = 1) 0.738 r 10.706 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.f[0] cell (LUT5) 0.424 r 11.130
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.468 r 11.598 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 path2reg1 0.542 12.140
- Arrival time 12.140 (6 lvl)
-
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 20.833 22.878
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 22.762
- clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.095 22.857
- Required time 22.857
----------------------------------------------------------------------------------------------------------
- Slack 10.717ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check): 10.813 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (rising edge triggered by clock b_pclk)
- Clock group: b_lvds_clk_p
- Process: Slow
- Data Path Delay: 9.977ns (logic 6.229ns, net 3.748ns, 62% logic)
- Logic Levels: 6 ( LUT5=3 ADDER=2 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 2.067
----------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[6] clk2q 3.433 r 5.500
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[10]) net (fanout = 1) 1.197 r 6.697
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.627 r 7.324
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 7.324
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.679
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_386.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.889 r 8.568
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_386.f[0] cell (LUT5) 0.424 r 8.992
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.456 r 9.448 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.f[1] cell (LUT5) 0.424 r 9.872
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234) net (fanout = 1) 0.738 r 10.610 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.f[0] cell (LUT5) 0.424 r 11.034
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.468 r 11.502 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 path2reg1 0.542 12.044
- Arrival time 12.044 (6 lvl)
-
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 20.833 22.878
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 22.762
- clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.095 22.857
- Required time 22.857
----------------------------------------------------------------------------------------------------------
- Slack 10.813ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check): 10.873 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (rising edge triggered by clock b_pclk)
- Clock group: b_lvds_clk_p
- Process: Slow
- Data Path Delay: 9.917ns (logic 6.302ns, net 3.615ns, 63% logic)
- Logic Levels: 6 ( LUT5=3 ADDER=2 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 2.067
----------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[4] clk2q 3.433 r 5.500
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[8]) net (fanout = 1) 1.064 r 6.564
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.627 r 7.191
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 7.191
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 7.264
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 7.264
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.619
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_386.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.889 r 8.508
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_386.f[0] cell (LUT5) 0.424 r 8.932
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.456 r 9.388 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.f[1] cell (LUT5) 0.424 r 9.812
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234) net (fanout = 1) 0.738 r 10.550 ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.f[0] cell (LUT5) 0.424 r 10.974
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 3) 0.468 r 11.442 ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 path2reg1 0.542 11.984
- Arrival time 11.984 (6 lvl)
-
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge 20.833 22.878
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 22.762
- clock uncertainty -0.000 22.762
- clock recovergence pessimism 0.095 22.857
- Required time 22.857
----------------------------------------------------------------------------------------------------------
- Slack 10.873ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_72 (214 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check): 11.454 ns
- Start Point: exdev_ctl_b/u_gen_sp/reg9_syn_93.clk (rising edge triggered by clock b_pclk)
- End Point: exdev_ctl_b/u_gen_sp/reg0_syn_72.sr (rising edge triggered by clock b_pclk)
- Clock group: b_lvds_clk_p
- Process: Slow
- Data Path Delay: 9.056ns (logic 3.997ns, net 5.059ns, 44% logic)
- Logic Levels: 7 ( LUT5=6 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- exdev_ctl_b/u_gen_sp/reg9_syn_93.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ exdev_ctl_b/u_gen_sp/reg9_syn_89.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- exdev_ctl_b/u_gen_sp/reg9_syn_93.q[1] clk2q 0.146 r 2.422
- exdev_ctl_b/u_gen_sp/sub1_syn_102.b[0] (exdev_ctl_b/u_gen_sp/sp_t_d1[0]) net (fanout = 1) 0.473 r 2.895 ../../../../hg_mp/fe/gen_sp.v(87)
- exdev_ctl_b/u_gen_sp/sub1_syn_102.fx[1] cell 1.157 r 4.052
- exdev_ctl_b/u_ADconfig/reg0_syn_140.b[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[2]) net (fanout = 1) 0.737 r 4.789
- exdev_ctl_b/u_ADconfig/reg0_syn_140.f[1] cell (LUT5) 0.431 r 5.220
- exdev_ctl_b/u_ADconfig/reg1_syn_173.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_137) net (fanout = 1) 0.456 r 5.676 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_ADconfig/reg1_syn_173.f[0] cell (LUT5) 0.424 r 6.100
- exdev_ctl_b/u_ADconfig/reg0_syn_140.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_143) net (fanout = 1) 0.757 r 6.857 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_ADconfig/reg0_syn_140.f[0] cell (LUT5) 0.424 r 7.281
- exdev_ctl_b/u_ADconfig/reg1_syn_176.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_145) net (fanout = 1) 0.594 r 7.875 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_ADconfig/reg1_syn_176.f[0] cell (LUT5) 0.424 r 8.299
- exdev_ctl_b/u_gen_sp/reg9_syn_107.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.757 r 9.056
- exdev_ctl_b/u_gen_sp/reg9_syn_107.f[0] cell (LUT5) 0.424 r 9.480
- exdev_ctl_b/u_gen_sp/reg2_syn_21.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2) net (fanout = 1) 0.503 r 9.983
- exdev_ctl_b/u_gen_sp/reg2_syn_21.f[0] cell (LUT5) 0.424 r 10.407
- exdev_ctl_b/u_gen_sp/reg0_syn_72.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net (fanout = 9) 0.782 r 11.189 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_gen_sp/reg0_syn_72 path2reg 0.143 11.332
- Arrival time 11.332 (7 lvl)
+ exdev_ctl_b/u_gen_sp/reg9_syn_89.q[1] clk2q 0.146 r 2.422
+ exdev_ctl_b/u_gen_sp/sub1_syn_102.a[1] (exdev_ctl_b/u_gen_sp/sp_t_d1[1]) net (fanout = 1) 0.602 r 3.024 ../../../../hg_mp/fe/gen_sp.v(87)
+ exdev_ctl_b/u_gen_sp/sub1_syn_102.fco cell (ADDER) 0.881 r 3.905
+ exdev_ctl_b/u_gen_sp/sub1_syn_103.fci (exdev_ctl_b/u_gen_sp/sub1_syn_87) net (fanout = 1) 0.000 f 3.905 ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_103.fco cell (ADDER) 0.132 r 4.037
+ exdev_ctl_b/u_gen_sp/sub1_syn_104.fci (exdev_ctl_b/u_gen_sp/sub1_syn_91) net (fanout = 1) 0.000 f 4.037 ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_104.fco cell (ADDER) 0.132 r 4.169
+ exdev_ctl_b/u_gen_sp/sub1_syn_105.fci (exdev_ctl_b/u_gen_sp/sub1_syn_95) net (fanout = 1) 0.000 f 4.169 ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_105.fx[0] cell (ADDER) 0.387 r 4.556
+ u_a_sp_sampling/reg0_syn_27.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12]) net (fanout = 1) 0.591 r 5.147
+ u_a_sp_sampling/reg0_syn_27.f[0] cell (LUT4) 0.424 r 5.571
+ exdev_ctl_b/u_gen_sp/reg9_syn_103.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_139) net (fanout = 1) 0.594 r 6.165 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_b/u_gen_sp/reg9_syn_103.f[0] cell (LUT5) 0.424 r 6.589
+ sampling_fe_a/u_ad_sampling/sp_1d_reg_syn_8.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_141) net (fanout = 1) 0.456 r 7.045 ../../../../hg_mp/fe/gen_sp.v(137)
+ sampling_fe_a/u_ad_sampling/sp_1d_reg_syn_8.f[0] cell (LUT5) 0.424 r 7.469
+ u_bus_top/u_local_bus_slve_cis/reg53_syn_51.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_149) net (fanout = 1) 0.594 r 8.063 ../../../../hg_mp/fe/gen_sp.v(137)
+ u_bus_top/u_local_bus_slve_cis/reg53_syn_51.f[0] cell (LUT5) 0.424 r 8.487
+ u_bus_top/u_local_bus_slve_cis/reg54_syn_47.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.456 r 8.943
+ u_bus_top/u_local_bus_slve_cis/reg54_syn_47.f[0] cell (LUT5) 0.424 r 9.367
+ u_bus_top/u_local_bus_slve_cis/reg55_syn_42.a[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2) net (fanout = 1) 0.738 r 10.105
+ u_bus_top/u_local_bus_slve_cis/reg55_syn_42.f[1] cell (LUT5) 0.424 r 10.529
+ exdev_ctl_b/u_gen_sp/reg0_syn_74.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net (fanout = 8) 0.625 r 11.154 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_b/u_gen_sp/reg0_syn_74 path2reg 0.143 11.297
+ Arrival time 11.297 (8 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- exdev_ctl_b/u_gen_sp/reg0_syn_72.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ exdev_ctl_b/u_gen_sp/reg0_syn_74.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 20.833 22.878
---------------------------------------------------------------------------------------------------------
cell setup -0.187 22.691
clock uncertainty -0.000 22.691
- clock recovergence pessimism 0.095 22.786
- Required time 22.786
+ clock recovergence pessimism 0.167 22.858
+ Required time 22.858
---------------------------------------------------------------------------------------------------------
- Slack 11.454ns
+ Slack 11.561ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 11.556 ns
- Start Point: exdev_ctl_b/u_gen_sp/reg9_syn_113.clk (rising edge triggered by clock b_pclk)
- End Point: exdev_ctl_b/u_gen_sp/reg0_syn_72.sr (rising edge triggered by clock b_pclk)
+ Slack (setup check): 11.662 ns
+ Start Point: exdev_ctl_b/u_gen_sp/reg8_syn_107.clk (rising edge triggered by clock b_pclk)
+ End Point: exdev_ctl_b/u_gen_sp/reg0_syn_74.sr (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 8.954ns (logic 4.176ns, net 4.778ns, 46% logic)
- Logic Levels: 8 ( LUT5=6 ADDER=2 )
+ Data Path Delay: 8.920ns (logic 4.101ns, net 4.819ns, 45% logic)
+ Logic Levels: 8 ( LUT5=5 ADDER=2 LUT4=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -1716,57 +1648,53 @@ Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_72 (214 paths)
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- exdev_ctl_b/u_gen_sp/reg9_syn_113.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ exdev_ctl_b/u_gen_sp/reg8_syn_107.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- exdev_ctl_b/u_gen_sp/reg9_syn_113.q[0] clk2q 0.146 r 2.422
- exdev_ctl_b/u_gen_sp/sub1_syn_102.a[1] (exdev_ctl_b/u_gen_sp/sp_t_d1[1]) net (fanout = 1) 0.473 r 2.895 ../../../../hg_mp/fe/gen_sp.v(87)
- exdev_ctl_b/u_gen_sp/sub1_syn_102.fco cell (ADDER) 0.881 r 3.776
- exdev_ctl_b/u_gen_sp/sub1_syn_103.fci (exdev_ctl_b/u_gen_sp/sub1_syn_87) net (fanout = 1) 0.000 f 3.776 ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_b/u_gen_sp/sub1_syn_103.fco cell (ADDER) 0.132 r 3.908
- exdev_ctl_b/u_gen_sp/sub1_syn_104.fci (exdev_ctl_b/u_gen_sp/sub1_syn_91) net (fanout = 1) 0.000 f 3.908 ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_b/u_gen_sp/sub1_syn_104.fco cell (ADDER) 0.132 r 4.040
- exdev_ctl_b/u_gen_sp/sub1_syn_105.fci (exdev_ctl_b/u_gen_sp/sub1_syn_95) net (fanout = 1) 0.000 f 4.040 ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_b/u_gen_sp/sub1_syn_105.f[0] cell (ADDER) 0.198 r 4.238
- exdev_ctl_b/u_ADconfig/reg0_syn_140.a[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[11]) net (fanout = 1) 0.456 r 4.694
- exdev_ctl_b/u_ADconfig/reg0_syn_140.f[1] cell (LUT5) 0.424 r 5.118
- exdev_ctl_b/u_ADconfig/reg1_syn_173.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_137) net (fanout = 1) 0.456 r 5.574 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_ADconfig/reg1_syn_173.f[0] cell (LUT5) 0.424 r 5.998
- exdev_ctl_b/u_ADconfig/reg0_syn_140.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_143) net (fanout = 1) 0.757 r 6.755 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_ADconfig/reg0_syn_140.f[0] cell (LUT5) 0.424 r 7.179
- exdev_ctl_b/u_ADconfig/reg1_syn_176.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_145) net (fanout = 1) 0.594 r 7.773 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_ADconfig/reg1_syn_176.f[0] cell (LUT5) 0.424 r 8.197
- exdev_ctl_b/u_gen_sp/reg9_syn_107.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.757 r 8.954
- exdev_ctl_b/u_gen_sp/reg9_syn_107.f[0] cell (LUT5) 0.424 r 9.378
- exdev_ctl_b/u_gen_sp/reg2_syn_21.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2) net (fanout = 1) 0.503 r 9.881
- exdev_ctl_b/u_gen_sp/reg2_syn_21.f[0] cell (LUT5) 0.424 r 10.305
- exdev_ctl_b/u_gen_sp/reg0_syn_72.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net (fanout = 9) 0.782 r 11.087 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_gen_sp/reg0_syn_72 path2reg 0.143 11.230
- Arrival time 11.230 (8 lvl)
+ exdev_ctl_b/u_gen_sp/reg8_syn_107.q[0] clk2q 0.146 r 2.422
+ exdev_ctl_b/u_gen_sp/sub1_syn_104.a[1] (exdev_ctl_b/u_gen_sp/sp_t_d1[9]) net (fanout = 1) 0.765 r 3.187 ../../../../hg_mp/fe/gen_sp.v(87)
+ exdev_ctl_b/u_gen_sp/sub1_syn_104.fco cell (ADDER) 0.881 r 4.068
+ exdev_ctl_b/u_gen_sp/sub1_syn_105.fci (exdev_ctl_b/u_gen_sp/sub1_syn_95) net (fanout = 1) 0.000 f 4.068 ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_105.fx[0] cell (ADDER) 0.387 r 4.455
+ u_a_sp_sampling/reg0_syn_27.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12]) net (fanout = 1) 0.591 r 5.046
+ u_a_sp_sampling/reg0_syn_27.f[0] cell (LUT4) 0.424 r 5.470
+ exdev_ctl_b/u_gen_sp/reg9_syn_103.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_139) net (fanout = 1) 0.594 r 6.064 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_b/u_gen_sp/reg9_syn_103.f[0] cell (LUT5) 0.424 r 6.488
+ sampling_fe_a/u_ad_sampling/sp_1d_reg_syn_8.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_141) net (fanout = 1) 0.456 r 6.944 ../../../../hg_mp/fe/gen_sp.v(137)
+ sampling_fe_a/u_ad_sampling/sp_1d_reg_syn_8.f[0] cell (LUT5) 0.424 r 7.368
+ u_bus_top/u_local_bus_slve_cis/reg53_syn_51.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_149) net (fanout = 1) 0.594 r 7.962 ../../../../hg_mp/fe/gen_sp.v(137)
+ u_bus_top/u_local_bus_slve_cis/reg53_syn_51.f[0] cell (LUT5) 0.424 r 8.386
+ u_bus_top/u_local_bus_slve_cis/reg54_syn_47.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.456 r 8.842
+ u_bus_top/u_local_bus_slve_cis/reg54_syn_47.f[0] cell (LUT5) 0.424 r 9.266
+ u_bus_top/u_local_bus_slve_cis/reg55_syn_42.a[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2) net (fanout = 1) 0.738 r 10.004
+ u_bus_top/u_local_bus_slve_cis/reg55_syn_42.f[1] cell (LUT5) 0.424 r 10.428
+ exdev_ctl_b/u_gen_sp/reg0_syn_74.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net (fanout = 8) 0.625 r 11.053 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_b/u_gen_sp/reg0_syn_74 path2reg 0.143 11.196
+ Arrival time 11.196 (8 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- exdev_ctl_b/u_gen_sp/reg0_syn_72.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ exdev_ctl_b/u_gen_sp/reg0_syn_74.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 20.833 22.878
---------------------------------------------------------------------------------------------------------
cell setup -0.187 22.691
clock uncertainty -0.000 22.691
- clock recovergence pessimism 0.095 22.786
- Required time 22.786
+ clock recovergence pessimism 0.167 22.858
+ Required time 22.858
---------------------------------------------------------------------------------------------------------
- Slack 11.556ns
+ Slack 11.662ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 11.601 ns
- Start Point: exdev_ctl_b/u_gen_sp/reg9_syn_93.clk (rising edge triggered by clock b_pclk)
- End Point: exdev_ctl_b/u_gen_sp/reg0_syn_72.sr (rising edge triggered by clock b_pclk)
+ Slack (setup check): 11.726 ns
+ Start Point: exdev_ctl_b/u_gen_sp/reg9_syn_106.clk (rising edge triggered by clock b_pclk)
+ End Point: exdev_ctl_b/u_gen_sp/reg0_syn_74.sr (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 8.909ns (logic 4.131ns, net 4.778ns, 46% logic)
- Logic Levels: 8 ( LUT5=6 ADDER=2 )
+ Data Path Delay: 8.856ns (logic 4.320ns, net 4.536ns, 48% logic)
+ Logic Levels: 8 ( LUT5=5 ADDER=2 LUT4=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -1774,57 +1702,95 @@ Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_72 (214 paths)
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- exdev_ctl_b/u_gen_sp/reg9_syn_93.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ exdev_ctl_b/u_gen_sp/reg9_syn_106.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
- exdev_ctl_b/u_gen_sp/reg9_syn_93.q[1] clk2q 0.146 r 2.422
- exdev_ctl_b/u_gen_sp/sub1_syn_102.b[0] (exdev_ctl_b/u_gen_sp/sp_t_d1[0]) net (fanout = 1) 0.473 r 2.895 ../../../../hg_mp/fe/gen_sp.v(87)
- exdev_ctl_b/u_gen_sp/sub1_syn_102.fco cell (ADDER) 0.836 r 3.731
- exdev_ctl_b/u_gen_sp/sub1_syn_103.fci (exdev_ctl_b/u_gen_sp/sub1_syn_87) net (fanout = 1) 0.000 f 3.731 ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_b/u_gen_sp/sub1_syn_103.fco cell (ADDER) 0.132 r 3.863
- exdev_ctl_b/u_gen_sp/sub1_syn_104.fci (exdev_ctl_b/u_gen_sp/sub1_syn_91) net (fanout = 1) 0.000 f 3.863 ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_b/u_gen_sp/sub1_syn_104.fco cell (ADDER) 0.132 r 3.995
- exdev_ctl_b/u_gen_sp/sub1_syn_105.fci (exdev_ctl_b/u_gen_sp/sub1_syn_95) net (fanout = 1) 0.000 f 3.995 ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_b/u_gen_sp/sub1_syn_105.f[0] cell (ADDER) 0.198 r 4.193
- exdev_ctl_b/u_ADconfig/reg0_syn_140.a[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[11]) net (fanout = 1) 0.456 r 4.649
- exdev_ctl_b/u_ADconfig/reg0_syn_140.f[1] cell (LUT5) 0.424 r 5.073
- exdev_ctl_b/u_ADconfig/reg1_syn_173.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_137) net (fanout = 1) 0.456 r 5.529 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_ADconfig/reg1_syn_173.f[0] cell (LUT5) 0.424 r 5.953
- exdev_ctl_b/u_ADconfig/reg0_syn_140.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_143) net (fanout = 1) 0.757 r 6.710 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_ADconfig/reg0_syn_140.f[0] cell (LUT5) 0.424 r 7.134
- exdev_ctl_b/u_ADconfig/reg1_syn_176.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_145) net (fanout = 1) 0.594 r 7.728 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_ADconfig/reg1_syn_176.f[0] cell (LUT5) 0.424 r 8.152
- exdev_ctl_b/u_gen_sp/reg9_syn_107.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.757 r 8.909
- exdev_ctl_b/u_gen_sp/reg9_syn_107.f[0] cell (LUT5) 0.424 r 9.333
- exdev_ctl_b/u_gen_sp/reg2_syn_21.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2) net (fanout = 1) 0.503 r 9.836
- exdev_ctl_b/u_gen_sp/reg2_syn_21.f[0] cell (LUT5) 0.424 r 10.260
- exdev_ctl_b/u_gen_sp/reg0_syn_72.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net (fanout = 9) 0.782 r 11.042 ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_gen_sp/reg0_syn_72 path2reg 0.143 11.185
- Arrival time 11.185 (8 lvl)
+ exdev_ctl_b/u_gen_sp/reg9_syn_106.q[0] clk2q 0.146 r 2.422
+ exdev_ctl_b/u_gen_sp/sub1_syn_102.b[0] (exdev_ctl_b/u_gen_sp/sp_t_d1[0]) net (fanout = 1) 0.482 r 2.904 ../../../../hg_mp/fe/gen_sp.v(87)
+ exdev_ctl_b/u_gen_sp/sub1_syn_102.fco cell (ADDER) 0.836 r 3.740
+ exdev_ctl_b/u_gen_sp/sub1_syn_103.fci (exdev_ctl_b/u_gen_sp/sub1_syn_87) net (fanout = 1) 0.000 f 3.740 ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_103.fco cell (ADDER) 0.132 r 3.872
+ exdev_ctl_b/u_gen_sp/sub1_syn_104.fci (exdev_ctl_b/u_gen_sp/sub1_syn_91) net (fanout = 1) 0.000 f 3.872 ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_104.fco cell (ADDER) 0.132 r 4.004
+ exdev_ctl_b/u_gen_sp/sub1_syn_105.fci (exdev_ctl_b/u_gen_sp/sub1_syn_95) net (fanout = 1) 0.000 f 4.004 ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_105.fx[0] cell (ADDER) 0.387 r 4.391
+ u_a_sp_sampling/reg0_syn_27.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12]) net (fanout = 1) 0.591 r 4.982
+ u_a_sp_sampling/reg0_syn_27.f[0] cell (LUT4) 0.424 r 5.406
+ exdev_ctl_b/u_gen_sp/reg9_syn_103.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_139) net (fanout = 1) 0.594 r 6.000 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_b/u_gen_sp/reg9_syn_103.f[0] cell (LUT5) 0.424 r 6.424
+ sampling_fe_a/u_ad_sampling/sp_1d_reg_syn_8.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_141) net (fanout = 1) 0.456 r 6.880 ../../../../hg_mp/fe/gen_sp.v(137)
+ sampling_fe_a/u_ad_sampling/sp_1d_reg_syn_8.f[0] cell (LUT5) 0.424 r 7.304
+ u_bus_top/u_local_bus_slve_cis/reg53_syn_51.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_149) net (fanout = 1) 0.594 r 7.898 ../../../../hg_mp/fe/gen_sp.v(137)
+ u_bus_top/u_local_bus_slve_cis/reg53_syn_51.f[0] cell (LUT5) 0.424 r 8.322
+ u_bus_top/u_local_bus_slve_cis/reg54_syn_47.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.456 r 8.778
+ u_bus_top/u_local_bus_slve_cis/reg54_syn_47.f[0] cell (LUT5) 0.424 r 9.202
+ u_bus_top/u_local_bus_slve_cis/reg55_syn_42.a[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2) net (fanout = 1) 0.738 r 9.940
+ u_bus_top/u_local_bus_slve_cis/reg55_syn_42.f[1] cell (LUT5) 0.424 r 10.364
+ exdev_ctl_b/u_gen_sp/reg0_syn_74.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net (fanout = 8) 0.625 r 10.989 ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_b/u_gen_sp/reg0_syn_74 path2reg 0.143 11.132
+ Arrival time 11.132 (8 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- exdev_ctl_b/u_gen_sp/reg0_syn_72.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ exdev_ctl_b/u_gen_sp/reg0_syn_74.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 20.833 22.878
---------------------------------------------------------------------------------------------------------
cell setup -0.187 22.691
clock uncertainty -0.000 22.691
- clock recovergence pessimism 0.095 22.786
- Required time 22.786
+ clock recovergence pessimism 0.167 22.858
+ Required time 22.858
---------------------------------------------------------------------------------------------------------
- Slack 11.601ns
+ Slack 11.726ns
---------------------------------------------------------------------------------------------------------
Hold checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1 (10 paths)
+Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1 (10 paths)
---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.080 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_663.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.addra[3] (rising edge triggered by clock b_pclk)
+ Clock group: b_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.325ns (logic 0.109ns, net 0.216ns, 33% logic)
+ Logic Levels: 1 ( EMB=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_663.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_663.q[0] clk2q 0.109 r 2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.addra[3] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[100]) net (fanout = 2) 0.216 r 2.263 ../../../../hg_mp/fe/prebuffer_rev.v(329)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1 path2reg (EMB) 0.000 2.263
+ Arrival time 2.263 (1 lvl)
+
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.200 2.330
+ clock uncertainty 0.000 2.330
+ clock recovergence pessimism -0.147 2.183
+ Required time 2.183
+---------------------------------------------------------------------------------------------------------
+ Slack 0.080ns
+
+---------------------------------------------------------------------------------------------------------
+
Slack (hold check): 0.089 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_635.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[7] (rising edge triggered by clock b_pclk)
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_625.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.addra[6] (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Fast
Data Path Delay: 0.334ns (logic 0.109ns, net 0.225ns, 32% logic)
@@ -1836,19 +1802,19 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/in
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_635.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_625.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_635.q[1] clk2q 0.109 r 2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[7] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[24]) net (fanout = 2) 0.225 r 2.272 ../../../../hg_mp/fe/prebuffer_rev.v(329)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1 path2reg (EMB) 0.000 2.272
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_625.q[0] clk2q 0.109 r 2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.addra[6] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[103]) net (fanout = 2) 0.225 r 2.272 ../../../../hg_mp/fe/prebuffer_rev.v(329)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1 path2reg (EMB) 0.000 2.272
Arrival time 2.272 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell hold 0.200 2.330
@@ -1860,12 +1826,12 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/in
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.089 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[53]_syn_8.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[6] (rising edge triggered by clock b_pclk)
+ Slack (hold check): 0.234 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_665.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.addra[4] (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Fast
- Data Path Delay: 0.334ns (logic 0.109ns, net 0.225ns, 32% logic)
+ Data Path Delay: 0.479ns (logic 0.109ns, net 0.370ns, 22% logic)
Logic Levels: 1 ( EMB=1 )
Point Type Incr Path Info
@@ -1874,19 +1840,19 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/in
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[53]_syn_8.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_665.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[53]_syn_8.q[0] clk2q 0.109 r 2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[6] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[23]) net (fanout = 2) 0.225 r 2.272 ../../../../hg_mp/fe/prebuffer_rev.v(329)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1 path2reg (EMB) 0.000 2.272
- Arrival time 2.272 (1 lvl)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_665.q[0] clk2q 0.109 r 2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.addra[4] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[101]) net (fanout = 2) 0.370 r 2.417 ../../../../hg_mp/fe/prebuffer_rev.v(329)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1 path2reg (EMB) 0.000 2.417
+ Arrival time 2.417 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell hold 0.200 2.330
@@ -1894,16 +1860,18 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/in
clock recovergence pessimism -0.147 2.183
Required time 2.183
---------------------------------------------------------------------------------------------------------
- Slack 0.089ns
+ Slack 0.234ns
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.196 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_632.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[10] (rising edge triggered by clock b_pclk)
+Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1 (8 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.080 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_27.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.dia[0] (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Fast
- Data Path Delay: 0.441ns (logic 0.109ns, net 0.332ns, 24% logic)
+ Data Path Delay: 0.325ns (logic 0.109ns, net 0.216ns, 33% logic)
Logic Levels: 1 ( EMB=1 )
Point Type Incr Path Info
@@ -1912,19 +1880,19 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/in
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_632.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_27.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_632.q[1] clk2q 0.109 r 2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[10] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[27]) net (fanout = 2) 0.332 r 2.379 ../../../../hg_mp/fe/prebuffer_rev.v(329)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1 path2reg (EMB) 0.000 2.379
- Arrival time 2.379 (1 lvl)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_27.q[0] clk2q 0.109 r 2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.dia[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[80]) net (fanout = 2) 0.216 r 2.263 ../../../../hg_mp/fe/prebuffer_rev.v(327)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1 path2reg (EMB) 0.000 2.263
+ Arrival time 2.263 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell hold 0.200 2.330
@@ -1932,15 +1900,13 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/in
clock recovergence pessimism -0.147 2.183
Required time 2.183
---------------------------------------------------------------------------------------------------------
- Slack 0.196ns
+ Slack 0.080ns
---------------------------------------------------------------------------------------------------------
-Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1 (8 paths)
----------------------------------------------------------------------------------------------------------
Slack (hold check): 0.130 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_524.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[1] (rising edge triggered by clock b_pclk)
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_666.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.dia[2] (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Fast
Data Path Delay: 0.375ns (logic 0.109ns, net 0.266ns, 29% logic)
@@ -1952,19 +1918,19 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/in
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_524.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_666.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_524.q[1] clk2q 0.109 r 2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[41]) net (fanout = 2) 0.266 r 2.313 ../../../../hg_mp/fe/prebuffer_rev.v(327)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1 path2reg (EMB) 0.000 2.313
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_666.q[0] clk2q 0.109 r 2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.dia[2] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[82]) net (fanout = 2) 0.266 r 2.313 ../../../../hg_mp/fe/prebuffer_rev.v(327)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1 path2reg (EMB) 0.000 2.313
Arrival time 2.313 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell hold 0.200 2.330
@@ -1976,12 +1942,12 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/in
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.241 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_527.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[3] (rising edge triggered by clock b_pclk)
+ Slack (hold check): 0.186 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_543.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.dia[7] (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Fast
- Data Path Delay: 0.486ns (logic 0.109ns, net 0.377ns, 22% logic)
+ Data Path Delay: 0.431ns (logic 0.109ns, net 0.322ns, 25% logic)
Logic Levels: 1 ( EMB=1 )
Point Type Incr Path Info
@@ -1990,19 +1956,19 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/in
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_527.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_543.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_527.q[1] clk2q 0.109 r 2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[3] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[43]) net (fanout = 2) 0.377 r 2.424 ../../../../hg_mp/fe/prebuffer_rev.v(327)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1 path2reg (EMB) 0.000 2.424
- Arrival time 2.424 (1 lvl)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_543.q[0] clk2q 0.109 r 2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.dia[7] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[87]) net (fanout = 2) 0.322 r 2.369 ../../../../hg_mp/fe/prebuffer_rev.v(327)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1 path2reg (EMB) 0.000 2.369
+ Arrival time 2.369 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell hold 0.200 2.330
@@ -2010,16 +1976,18 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/in
clock recovergence pessimism -0.147 2.183
Required time 2.183
---------------------------------------------------------------------------------------------------------
- Slack 0.241ns
+ Slack 0.186ns
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.376 ns
- Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[87]_syn_26.clk (rising edge triggered by clock b_pclk)
- End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[2] (rising edge triggered by clock b_pclk)
+Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1 (10 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.114 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_712.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.addra[11] (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Fast
- Data Path Delay: 0.621ns (logic 0.109ns, net 0.512ns, 17% logic)
+ Data Path Delay: 0.359ns (logic 0.109ns, net 0.250ns, 30% logic)
Logic Levels: 1 ( EMB=1 )
Point Type Incr Path Info
@@ -2028,19 +1996,19 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/in
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[87]_syn_26.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_712.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[87]_syn_26.q[0] clk2q 0.109 r 2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[2] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[42]) net (fanout = 2) 0.512 r 2.559 ../../../../hg_mp/fe/prebuffer_rev.v(327)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1 path2reg (EMB) 0.000 2.559
- Arrival time 2.559 (1 lvl)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_712.q[0] clk2q 0.109 r 2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.addra[11] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[68]) net (fanout = 2) 0.250 r 2.297 ../../../../hg_mp/fe/prebuffer_rev.v(329)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1 path2reg (EMB) 0.000 2.297
+ Arrival time 2.297 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell hold 0.200 2.330
@@ -2048,45 +2016,83 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/in
clock recovergence pessimism -0.147 2.183
Required time 2.183
---------------------------------------------------------------------------------------------------------
- Slack 0.376ns
+ Slack 0.114ns
---------------------------------------------------------------------------------------------------------
-Paths for end point exdev_ctl_b/reg3_syn_179 (1 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.175 ns
- Start Point: u_bus_top/u_local_bus_slve_cis/reg39_syn_205.clk (rising edge triggered by clock clk_adc)
- End Point: exdev_ctl_b/reg3_syn_179.mi[0] (rising edge triggered by clock b_pclk)
+ Slack (hold check): 0.205 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_712.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.addra[10] (rising edge triggered by clock b_pclk)
Clock group: b_lvds_clk_p
Process: Fast
- Data Path Delay: 0.428ns (logic 0.204ns, net 0.224ns, 47% logic)
- Logic Levels: 0
+ Data Path Delay: 0.450ns (logic 0.109ns, net 0.341ns, 24% logic)
+ Logic Levels: 1 ( EMB=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
- u_pll/pll_inst.clkc[4] 0.000 0.000
- u_bus_top/u_local_bus_slve_cis/reg39_syn_205.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_712.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- u_bus_top/u_local_bus_slve_cis/reg39_syn_205.q[0] clk2q 0.109 r 2.047
- exdev_ctl_b/reg3_syn_179.mi[0] (u_bus_top/u_local_bus_slve_cis/reg19[25]) net (fanout = 3) 0.224 r 2.271 ../../../../hg_mp/local_bus/local_bus_slve_cis.v(73)
- exdev_ctl_b/reg3_syn_179 path2reg0 0.095 2.366
- Arrival time 2.366 (0 lvl)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_712.q[1] clk2q 0.109 r 2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.addra[10] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[67]) net (fanout = 2) 0.341 r 2.388 ../../../../hg_mp/fe/prebuffer_rev.v(329)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1 path2reg (EMB) 0.000 2.388
+ Arrival time 2.388 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- exdev_ctl_b/reg3_syn_179.clk (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
- cell hold 0.061 2.191
- clock uncertainty 0.000 2.191
- clock recovergence pessimism 0.000 2.191
- Required time 2.191
+ cell hold 0.200 2.330
+ clock uncertainty 0.000 2.330
+ clock recovergence pessimism -0.147 2.183
+ Required time 2.183
---------------------------------------------------------------------------------------------------------
- Slack 0.175ns
+ Slack 0.205ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check): 0.302 ns
+ Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_703.clk (rising edge triggered by clock b_pclk)
+ End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.addra[9] (rising edge triggered by clock b_pclk)
+ Clock group: b_lvds_clk_p
+ Process: Fast
+ Data Path Delay: 0.547ns (logic 0.109ns, net 0.438ns, 19% logic)
+ Logic Levels: 1 ( EMB=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_703.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_703.q[1] clk2q 0.109 r 2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.addra[9] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[66]) net (fanout = 2) 0.438 r 2.485 ../../../../hg_mp/fe/prebuffer_rev.v(329)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1 path2reg (EMB) 0.000 2.485
+ Arrival time 2.485 (1 lvl)
+
+ source latency 0.000 0.000
+ uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.200 2.330
+ clock uncertainty 0.000 2.330
+ clock recovergence pessimism -0.147 2.183
+ Required time 2.183
+---------------------------------------------------------------------------------------------------------
+ Slack 0.302ns
---------------------------------------------------------------------------------------------------------
@@ -2095,126 +2101,126 @@ Paths for end point exdev_ctl_b/reg3_syn_179 (1 paths)
Timing constraint: clock: b_sclk
Clock = b_sclk, period 5.952ns, rising at 0ns, falling at 2.976ns
-282 endpoints analyzed totally, and 730 paths analyzed
+282 endpoints analyzed totally, and 690 paths analyzed
0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 2.151ns
+Minimum period is 1.853ns
---------------------------------------------------------------------------------------------------------
Paths for end point ub_lvds_rx/rx_clk_sync_reg_syn_5 (7 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 3.801 ns
- Start Point: ub_lvds_rx/reg7_syn_28.clk (rising edge triggered by clock b_sclk)
+ Slack (setup check): 4.099 ns
+ Start Point: ub_lvds_rx/reg7_syn_32.clk (rising edge triggered by clock b_sclk)
End Point: ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 1.999ns (logic 0.941ns, net 1.058ns, 47% logic)
+ Data Path Delay: 1.701ns (logic 0.941ns, net 0.760ns, 55% logic)
Logic Levels: 2 ( LUT5=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg7_syn_28.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.276
+ ub_lvds_rx/reg7_syn_32.clk (ub_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg7_syn_28.q[1] clk2q 0.146 r 2.422
- ub_lvds_rx/rx_clk_sync_reg_syn_5.a[0] (ub_lvds_rx/rx_clk_sft[0]) net (fanout = 2) 0.602 r 3.024 encrypted_text(0)
- ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.424 r 3.448
- ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.456 r 3.904 encrypted_text(0)
- ub_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.275
- Arrival time 4.275 (2 lvl)
+ ub_lvds_rx/reg7_syn_32.q[1] clk2q 0.146 r 2.556
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.a[0] (ub_lvds_rx/rx_clk_sft[0]) net (fanout = 2) 0.602 r 3.158 encrypted_text(0)
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.424 r 3.582
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.158 r 3.740 encrypted_text(0)
+ ub_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.111
+ Arrival time 4.111 (2 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/rx_clk_sync_reg_syn_5.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 7.997
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.clk (ub_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 8.118
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 7.881
- clock uncertainty -0.000 7.881
- clock recovergence pessimism 0.195 8.076
- Required time 8.076
+ cell setup -0.116 8.002
+ clock uncertainty -0.000 8.002
+ clock recovergence pessimism 0.208 8.210
+ Required time 8.210
---------------------------------------------------------------------------------------------------------
- Slack 3.801ns
+ Slack 4.099ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 3.932 ns
- Start Point: ub_lvds_rx/reg7_syn_33.clk (rising edge triggered by clock b_sclk)
+ Slack (setup check): 4.175 ns
+ Start Point: ub_lvds_rx/reg7_syn_25.clk (rising edge triggered by clock b_sclk)
End Point: ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 1.883ns (logic 0.948ns, net 0.935ns, 50% logic)
+ Data Path Delay: 1.625ns (logic 0.865ns, net 0.760ns, 53% logic)
Logic Levels: 2 ( LUT5=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg7_syn_33.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.276
+ ub_lvds_rx/reg7_syn_25.clk (ub_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg7_syn_33.q[0] clk2q 0.146 r 2.422
- ub_lvds_rx/rx_clk_sync_reg_syn_5.b[0] (ub_lvds_rx/rx_clk_sft[1]) net (fanout = 2) 0.479 r 2.901 encrypted_text(0)
- ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.431 r 3.332
- ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.456 r 3.788 encrypted_text(0)
- ub_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.159
- Arrival time 4.159 (2 lvl)
+ ub_lvds_rx/reg7_syn_25.q[1] clk2q 0.146 r 2.556
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.c[0] (ub_lvds_rx/rx_clk_sft[2]) net (fanout = 2) 0.602 r 3.158 encrypted_text(0)
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.348 r 3.506
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.158 r 3.664 encrypted_text(0)
+ ub_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.035
+ Arrival time 4.035 (2 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/rx_clk_sync_reg_syn_5.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 7.997
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.clk (ub_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 8.118
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 7.881
- clock uncertainty -0.000 7.881
- clock recovergence pessimism 0.210 8.091
- Required time 8.091
+ cell setup -0.116 8.002
+ clock uncertainty -0.000 8.002
+ clock recovergence pessimism 0.208 8.210
+ Required time 8.210
---------------------------------------------------------------------------------------------------------
- Slack 3.932ns
+ Slack 4.175ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 3.963 ns
- Start Point: ub_lvds_rx/reg7_syn_28.clk (rising edge triggered by clock b_sclk)
+ Slack (setup check): 4.364 ns
+ Start Point: ub_lvds_rx/reg7_syn_32.clk (rising edge triggered by clock b_sclk)
End Point: ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 1.837ns (logic 0.779ns, net 1.058ns, 42% logic)
+ Data Path Delay: 1.436ns (logic 0.948ns, net 0.488ns, 66% logic)
Logic Levels: 2 ( LUT5=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg7_syn_28.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.276
+ ub_lvds_rx/reg7_syn_32.clk (ub_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg7_syn_28.q[0] clk2q 0.146 r 2.422
- ub_lvds_rx/rx_clk_sync_reg_syn_5.d[0] (ub_lvds_rx/rx_clk_sft[3]) net (fanout = 2) 0.602 r 3.024 encrypted_text(0)
- ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.262 r 3.286
- ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.456 r 3.742 encrypted_text(0)
- ub_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.113
- Arrival time 4.113 (2 lvl)
+ ub_lvds_rx/reg7_syn_32.q[0] clk2q 0.146 r 2.556
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.b[0] (ub_lvds_rx/rx_clk_sft[1]) net (fanout = 2) 0.330 r 2.886 encrypted_text(0)
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.431 r 3.317
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.158 r 3.475 encrypted_text(0)
+ ub_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 3.846
+ Arrival time 3.846 (2 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/rx_clk_sync_reg_syn_5.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 7.997
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.clk (ub_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 8.118
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 7.881
- clock uncertainty -0.000 7.881
- clock recovergence pessimism 0.195 8.076
- Required time 8.076
+ cell setup -0.116 8.002
+ clock uncertainty -0.000 8.002
+ clock recovergence pessimism 0.208 8.210
+ Required time 8.210
---------------------------------------------------------------------------------------------------------
- Slack 3.963ns
+ Slack 4.364ns
---------------------------------------------------------------------------------------------------------
-Paths for end point ub_lvds_rx/reg8_syn_163 (9 paths)
+Paths for end point ub_lvds_rx/reg8_syn_145 (9 paths)
---------------------------------------------------------------------------------------------------------
Slack (setup check): 4.145 ns
- Start Point: ub_lvds_rx/reg8_syn_163.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/reg8_syn_163.a[1] (rising edge triggered by clock b_sclk)
+ Start Point: ub_lvds_rx/reg8_syn_145.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/reg8_syn_145.a[1] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Slow
Data Path Delay: 1.691ns (logic 0.878ns, net 0.813ns, 51% logic)
@@ -2224,207 +2230,207 @@ Paths for end point ub_lvds_rx/reg8_syn_163 (9 paths)
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_163.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.276
+ ub_lvds_rx/reg8_syn_145.clk (ub_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg8_syn_163.q[0] clk2q 0.146 r 2.422
- ub_lvds_rx/reg8_syn_163.a[1] (ub_lvds_rx/para_data[19]) net (fanout = 3) 0.813 r 3.235 encrypted_text(0)
- ub_lvds_rx/reg8_syn_163 path2reg0 0.732 3.967
- Arrival time 3.967 (1 lvl)
+ ub_lvds_rx/reg8_syn_145.q[0] clk2q 0.146 r 2.556
+ ub_lvds_rx/reg8_syn_145.a[1] (ub_lvds_rx/para_data[25]) net (fanout = 3) 0.813 r 3.369 encrypted_text(0)
+ ub_lvds_rx/reg8_syn_145 path2reg0 0.732 4.101
+ Arrival time 4.101 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_163.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 7.997
+ ub_lvds_rx/reg8_syn_145.clk (ub_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 8.118
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 7.881
- clock uncertainty -0.000 7.881
- clock recovergence pessimism 0.231 8.112
- Required time 8.112
+ cell setup -0.116 8.002
+ clock uncertainty -0.000 8.002
+ clock recovergence pessimism 0.244 8.246
+ Required time 8.246
---------------------------------------------------------------------------------------------------------
Slack 4.145ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.525 ns
- Start Point: ub_lvds_rx/reg8_syn_151.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/reg8_syn_163.b[1] (rising edge triggered by clock b_sclk)
+ Slack (setup check): 4.156 ns
+ Start Point: ub_lvds_rx/reg8_syn_143.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/reg8_syn_145.b[1] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 1.290ns (logic 0.803ns, net 0.487ns, 62% logic)
+ Data Path Delay: 1.616ns (logic 0.803ns, net 0.813ns, 49% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_151.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.276
+ ub_lvds_rx/reg8_syn_143.clk (ub_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg8_syn_151.q[1] clk2q 0.146 r 2.422
- ub_lvds_rx/reg8_syn_163.b[1] (ub_lvds_rx/rx_data[21]) net (fanout = 5) 0.487 r 2.909 encrypted_text(0)
- ub_lvds_rx/reg8_syn_163 path2reg0 0.657 3.566
- Arrival time 3.566 (1 lvl)
+ ub_lvds_rx/reg8_syn_143.q[1] clk2q 0.146 r 2.556
+ ub_lvds_rx/reg8_syn_145.b[1] (ub_lvds_rx/rx_data[28]) net (fanout = 4) 0.813 r 3.369 encrypted_text(0)
+ ub_lvds_rx/reg8_syn_145 path2reg0 0.657 4.026
+ Arrival time 4.026 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_163.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 7.997
+ ub_lvds_rx/reg8_syn_145.clk (ub_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 8.118
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 7.881
- clock uncertainty -0.000 7.881
- clock recovergence pessimism 0.210 8.091
- Required time 8.091
+ cell setup -0.116 8.002
+ clock uncertainty -0.000 8.002
+ clock recovergence pessimism 0.180 8.182
+ Required time 8.182
---------------------------------------------------------------------------------------------------------
- Slack 4.525ns
+ Slack 4.156ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.525 ns
- Start Point: ub_lvds_rx/reg8_syn_151.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/reg8_syn_163.b[0] (rising edge triggered by clock b_sclk)
+ Slack (setup check): 4.156 ns
+ Start Point: ub_lvds_rx/reg8_syn_143.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/reg8_syn_145.b[0] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 1.290ns (logic 0.803ns, net 0.487ns, 62% logic)
+ Data Path Delay: 1.616ns (logic 0.803ns, net 0.813ns, 49% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_151.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.276
+ ub_lvds_rx/reg8_syn_143.clk (ub_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg8_syn_151.q[1] clk2q 0.146 r 2.422
- ub_lvds_rx/reg8_syn_163.b[0] (ub_lvds_rx/rx_data[21]) net (fanout = 5) 0.487 r 2.909 encrypted_text(0)
- ub_lvds_rx/reg8_syn_163 path2reg0 0.657 3.566
- Arrival time 3.566 (1 lvl)
+ ub_lvds_rx/reg8_syn_143.q[1] clk2q 0.146 r 2.556
+ ub_lvds_rx/reg8_syn_145.b[0] (ub_lvds_rx/rx_data[28]) net (fanout = 4) 0.813 r 3.369 encrypted_text(0)
+ ub_lvds_rx/reg8_syn_145 path2reg0 0.657 4.026
+ Arrival time 4.026 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_163.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 7.997
+ ub_lvds_rx/reg8_syn_145.clk (ub_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 8.118
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 7.881
- clock uncertainty -0.000 7.881
- clock recovergence pessimism 0.210 8.091
- Required time 8.091
+ cell setup -0.116 8.002
+ clock uncertainty -0.000 8.002
+ clock recovergence pessimism 0.180 8.182
+ Required time 8.182
---------------------------------------------------------------------------------------------------------
- Slack 4.525ns
+ Slack 4.156ns
---------------------------------------------------------------------------------------------------------
-Paths for end point ub_lvds_rx/reg8_syn_161 (9 paths)
+Paths for end point ub_lvds_rx/reg8_syn_149 (9 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.145 ns
- Start Point: ub_lvds_rx/reg8_syn_161.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/reg8_syn_161.a[1] (rising edge triggered by clock b_sclk)
+ Slack (setup check): 4.166 ns
+ Start Point: ub_lvds_rx/reg8_syn_131.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/reg8_syn_149.b[1] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 1.691ns (logic 0.878ns, net 0.813ns, 51% logic)
+ Data Path Delay: 1.606ns (logic 0.803ns, net 0.803ns, 49% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_161.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.276
+ ub_lvds_rx/reg8_syn_131.clk (ub_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg8_syn_161.q[0] clk2q 0.146 r 2.422
- ub_lvds_rx/reg8_syn_161.a[1] (ub_lvds_rx/para_data[14]) net (fanout = 3) 0.813 r 3.235 encrypted_text(0)
- ub_lvds_rx/reg8_syn_161 path2reg0 0.732 3.967
- Arrival time 3.967 (1 lvl)
+ ub_lvds_rx/reg8_syn_131.q[0] clk2q 0.146 r 2.556
+ ub_lvds_rx/reg8_syn_149.b[1] (ub_lvds_rx/rx_data[24]) net (fanout = 3) 0.803 r 3.359 encrypted_text(0)
+ ub_lvds_rx/reg8_syn_149 path2reg0 0.657 4.016
+ Arrival time 4.016 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_161.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 7.997
+ ub_lvds_rx/reg8_syn_149.clk (ub_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 8.118
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 7.881
- clock uncertainty -0.000 7.881
- clock recovergence pessimism 0.231 8.112
- Required time 8.112
+ cell setup -0.116 8.002
+ clock uncertainty -0.000 8.002
+ clock recovergence pessimism 0.180 8.182
+ Required time 8.182
---------------------------------------------------------------------------------------------------------
- Slack 4.145ns
+ Slack 4.166ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.475 ns
- Start Point: ub_lvds_rx/reg8_syn_204.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/reg8_syn_161.b[0] (rising edge triggered by clock b_sclk)
+ Slack (setup check): 4.166 ns
+ Start Point: ub_lvds_rx/reg8_syn_131.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/reg8_syn_149.b[0] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 1.297ns (logic 0.803ns, net 0.494ns, 61% logic)
+ Data Path Delay: 1.606ns (logic 0.803ns, net 0.803ns, 49% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_204.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.276
+ ub_lvds_rx/reg8_syn_131.clk (ub_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg8_syn_204.q[1] clk2q 0.146 r 2.422
- ub_lvds_rx/reg8_syn_161.b[0] (ub_lvds_rx/rx_data[16]) net (fanout = 3) 0.494 r 2.916 encrypted_text(0)
- ub_lvds_rx/reg8_syn_161 path2reg0 0.657 3.573
- Arrival time 3.573 (1 lvl)
+ ub_lvds_rx/reg8_syn_131.q[0] clk2q 0.146 r 2.556
+ ub_lvds_rx/reg8_syn_149.b[0] (ub_lvds_rx/rx_data[24]) net (fanout = 3) 0.803 r 3.359 encrypted_text(0)
+ ub_lvds_rx/reg8_syn_149 path2reg0 0.657 4.016
+ Arrival time 4.016 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_161.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 7.997
+ ub_lvds_rx/reg8_syn_149.clk (ub_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 8.118
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 7.881
- clock uncertainty -0.000 7.881
- clock recovergence pessimism 0.167 8.048
- Required time 8.048
+ cell setup -0.116 8.002
+ clock uncertainty -0.000 8.002
+ clock recovergence pessimism 0.180 8.182
+ Required time 8.182
---------------------------------------------------------------------------------------------------------
- Slack 4.475ns
+ Slack 4.166ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 4.475 ns
- Start Point: ub_lvds_rx/reg8_syn_204.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/reg8_syn_161.b[1] (rising edge triggered by clock b_sclk)
+ Slack (setup check): 4.324 ns
+ Start Point: ub_lvds_rx/sync0_reg_syn_4.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/reg8_syn_149.d[1] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Slow
- Data Path Delay: 1.297ns (logic 0.803ns, net 0.494ns, 61% logic)
+ Data Path Delay: 1.491ns (logic 0.655ns, net 0.836ns, 43% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_204.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 2.276
+ ub_lvds_rx/sync0_reg_syn_4.clk (ub_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg8_syn_204.q[1] clk2q 0.146 r 2.422
- ub_lvds_rx/reg8_syn_161.b[1] (ub_lvds_rx/rx_data[16]) net (fanout = 3) 0.494 r 2.916 encrypted_text(0)
- ub_lvds_rx/reg8_syn_161 path2reg0 0.657 3.573
- Arrival time 3.573 (1 lvl)
+ ub_lvds_rx/sync0_reg_syn_4.q[1] clk2q 0.146 r 2.556
+ ub_lvds_rx/reg8_syn_149.d[1] (ub_lvds_rx/sync0) net (fanout = 41) 0.836 r 3.392 encrypted_text(0)
+ ub_lvds_rx/reg8_syn_149 path2reg0 0.509 3.901
+ Arrival time 3.901 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_161.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 5.952 7.997
+ ub_lvds_rx/reg8_syn_149.clk (ub_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 5.952 8.118
---------------------------------------------------------------------------------------------------------
- cell setup -0.116 7.881
- clock uncertainty -0.000 7.881
- clock recovergence pessimism 0.167 8.048
- Required time 8.048
+ cell setup -0.116 8.002
+ clock uncertainty -0.000 8.002
+ clock recovergence pessimism 0.223 8.225
+ Required time 8.225
---------------------------------------------------------------------------------------------------------
- Slack 4.475ns
+ Slack 4.324ns
---------------------------------------------------------------------------------------------------------
Hold checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point ub_lvds_rx/ramread0_syn_32 (2 paths)
+Paths for end point ub_lvds_rx/ramread0_syn_74 (2 paths)
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.167 ns
- Start Point: ub_lvds_rx/reg3_syn_166.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/ramread0_syn_32.c[1] (rising edge triggered by clock b_sclk)
+ Slack (hold check): 0.104 ns
+ Start Point: ub_lvds_rx/reg3_syn_180.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/ramread0_syn_74.c[1] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Fast
Data Path Delay: 0.325ns (logic 0.109ns, net 0.216ns, 33% logic)
@@ -2434,199 +2440,165 @@ Paths for end point ub_lvds_rx/ramread0_syn_32 (2 paths)
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg3_syn_166.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 1.938
+ ub_lvds_rx/reg3_syn_180.clk (ub_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg3_syn_166.q[1] clk2q 0.109 r 2.047
- ub_lvds_rx/ramread0_syn_32.c[1] (ub_lvds_rx/para_data[6]) net (fanout = 2) 0.216 r 2.263 encrypted_text(0)
- ub_lvds_rx/ramread0_syn_32 path2reg 0.000 2.263
- Arrival time 2.263 (1 lvl)
+ ub_lvds_rx/reg3_syn_180.q[0] clk2q 0.109 r 2.138
+ ub_lvds_rx/ramread0_syn_74.c[1] (ub_lvds_rx/para_data[18]) net (fanout = 2) 0.216 r 2.354 encrypted_text(0)
+ ub_lvds_rx/ramread0_syn_74 path2reg 0.000 2.354
+ Arrival time 2.354 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/ramread0_syn_32.clk (ub_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.130
+ ub_lvds_rx/ramread0_syn_74.clk (ub_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.243
- clock uncertainty 0.000 2.243
- clock recovergence pessimism -0.147 2.096
- Required time 2.096
+ cell hold 0.113 2.343
+ clock uncertainty 0.000 2.343
+ clock recovergence pessimism -0.093 2.250
+ Required time 2.250
---------------------------------------------------------------------------------------------------------
- Slack 0.167ns
+ Slack 0.104ns
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.336 ns
+ Slack (hold check): 0.199 ns
Start Point: ub_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/ramread0_syn_32.c[0] (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/ramread0_syn_74.c[0] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Fast
- Data Path Delay: 0.464ns (logic 0.109ns, net 0.355ns, 23% logic)
+ Data Path Delay: 0.357ns (logic 0.109ns, net 0.248ns, 30% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg16_syn_31.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 1.938
+ ub_lvds_rx/reg16_syn_31.clk (ub_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg16_syn_31.q[0] clk2q 0.109 r 2.047
- ub_lvds_rx/ramread0_syn_32.c[0] (ub_lvds_rx/wcnt[2]) net (fanout = 9) 0.355 r 2.402 encrypted_text(0)
- ub_lvds_rx/ramread0_syn_32 path2reg 0.000 2.402
- Arrival time 2.402 (1 lvl)
+ ub_lvds_rx/reg16_syn_31.q[0] clk2q 0.109 r 2.138
+ ub_lvds_rx/ramread0_syn_74.c[0] (ub_lvds_rx/wcnt[2]) net (fanout = 9) 0.248 r 2.386 encrypted_text(0)
+ ub_lvds_rx/ramread0_syn_74 path2reg 0.000 2.386
+ Arrival time 2.386 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/ramread0_syn_32.clk (ub_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.130
+ ub_lvds_rx/ramread0_syn_74.clk (ub_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.243
- clock uncertainty 0.000 2.243
- clock recovergence pessimism -0.177 2.066
- Required time 2.066
+ cell hold 0.113 2.343
+ clock uncertainty 0.000 2.343
+ clock recovergence pessimism -0.156 2.187
+ Required time 2.187
---------------------------------------------------------------------------------------------------------
- Slack 0.336ns
+ Slack 0.199ns
---------------------------------------------------------------------------------------------------------
-Paths for end point ub_lvds_rx/ramread0_syn_18 (2 paths)
+Paths for end point ub_lvds_rx/ramread0_syn_102 (2 paths)
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.167 ns
- Start Point: ub_lvds_rx/reg8_syn_141.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/ramread0_syn_18.b[1] (rising edge triggered by clock b_sclk)
+ Slack (hold check): 0.113 ns
+ Start Point: ub_lvds_rx/reg3_syn_175.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/ramread0_syn_102.a[1] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Fast
- Data Path Delay: 0.325ns (logic 0.109ns, net 0.216ns, 33% logic)
+ Data Path Delay: 0.334ns (logic 0.109ns, net 0.225ns, 32% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_141.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 1.938
+ ub_lvds_rx/reg3_syn_175.clk (ub_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg8_syn_141.q[0] clk2q 0.109 r 2.047
- ub_lvds_rx/ramread0_syn_18.b[1] (ub_lvds_rx/para_data[1]) net (fanout = 3) 0.216 r 2.263 encrypted_text(0)
- ub_lvds_rx/ramread0_syn_18 path2reg 0.000 2.263
- Arrival time 2.263 (1 lvl)
+ ub_lvds_rx/reg3_syn_175.q[1] clk2q 0.109 r 2.138
+ ub_lvds_rx/ramread0_syn_102.a[1] (ub_lvds_rx/para_data[24]) net (fanout = 2) 0.225 r 2.363 encrypted_text(0)
+ ub_lvds_rx/ramread0_syn_102 path2reg 0.000 2.363
+ Arrival time 2.363 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/ramread0_syn_18.clk (ub_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.130
+ ub_lvds_rx/ramread0_syn_102.clk (ub_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.243
- clock uncertainty 0.000 2.243
- clock recovergence pessimism -0.147 2.096
- Required time 2.096
+ cell hold 0.113 2.343
+ clock uncertainty 0.000 2.343
+ clock recovergence pessimism -0.093 2.250
+ Required time 2.250
---------------------------------------------------------------------------------------------------------
- Slack 0.167ns
+ Slack 0.113ns
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.409 ns
- Start Point: ub_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/ramread0_syn_18.b[0] (rising edge triggered by clock b_sclk)
+ Slack (hold check): 0.345 ns
+ Start Point: ub_lvds_rx/reg16_syn_33.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/ramread0_syn_102.a[0] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Fast
- Data Path Delay: 0.551ns (logic 0.109ns, net 0.442ns, 19% logic)
+ Data Path Delay: 0.503ns (logic 0.109ns, net 0.394ns, 21% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg16_syn_31.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 1.938
+ ub_lvds_rx/reg16_syn_33.clk (ub_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg16_syn_31.q[1] clk2q 0.109 r 2.047
- ub_lvds_rx/ramread0_syn_18.b[0] (ub_lvds_rx/wcnt[1]) net (fanout = 10) 0.442 r 2.489 encrypted_text(0)
- ub_lvds_rx/ramread0_syn_18 path2reg 0.000 2.489
- Arrival time 2.489 (1 lvl)
+ ub_lvds_rx/reg16_syn_33.q[0] clk2q 0.109 r 2.138
+ ub_lvds_rx/ramread0_syn_102.a[0] (ub_lvds_rx/wcnt[0]) net (fanout = 11) 0.394 r 2.532 encrypted_text(0)
+ ub_lvds_rx/ramread0_syn_102 path2reg 0.000 2.532
+ Arrival time 2.532 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/ramread0_syn_18.clk (ub_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.130
+ ub_lvds_rx/ramread0_syn_102.clk (ub_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.243
- clock uncertainty 0.000 2.243
- clock recovergence pessimism -0.163 2.080
- Required time 2.080
+ cell hold 0.113 2.343
+ clock uncertainty 0.000 2.343
+ clock recovergence pessimism -0.156 2.187
+ Required time 2.187
---------------------------------------------------------------------------------------------------------
- Slack 0.409ns
+ Slack 0.345ns
---------------------------------------------------------------------------------------------------------
-Paths for end point ub_lvds_rx/ramread0_syn_116 (2 paths)
+Paths for end point ub_lvds_rx/ramread0_syn_74 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.167 ns
- Start Point: ub_lvds_rx/reg8_syn_169.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/ramread0_syn_116.b[1] (rising edge triggered by clock b_sclk)
+ Slack (hold check): 0.113 ns
+ Start Point: ub_lvds_rx/reg3_syn_180.clk (rising edge triggered by clock b_sclk)
+ End Point: ub_lvds_rx/ramread0_syn_74.d[1] (rising edge triggered by clock b_sclk)
Clock group: b_lvds_clk_p
Process: Fast
- Data Path Delay: 0.325ns (logic 0.109ns, net 0.216ns, 33% logic)
+ Data Path Delay: 0.334ns (logic 0.109ns, net 0.225ns, 32% logic)
Logic Levels: 1
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg8_syn_169.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 1.938
+ ub_lvds_rx/reg3_syn_180.clk (ub_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg8_syn_169.q[0] clk2q 0.109 r 2.047
- ub_lvds_rx/ramread0_syn_116.b[1] (ub_lvds_rx/para_data[33]) net (fanout = 3) 0.216 r 2.263 encrypted_text(0)
- ub_lvds_rx/ramread0_syn_116 path2reg 0.000 2.263
- Arrival time 2.263 (1 lvl)
+ ub_lvds_rx/reg3_syn_180.q[1] clk2q 0.109 r 2.138
+ ub_lvds_rx/ramread0_syn_74.d[1] (ub_lvds_rx/para_data[19]) net (fanout = 2) 0.225 r 2.363 encrypted_text(0)
+ ub_lvds_rx/ramread0_syn_74 path2reg 0.000 2.363
+ Arrival time 2.363 (1 lvl)
source latency 0.000 0.000
uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/ramread0_syn_116.clk (ub_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.130
+ ub_lvds_rx/ramread0_syn_74.clk (ub_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.243
- clock uncertainty 0.000 2.243
- clock recovergence pessimism -0.147 2.096
- Required time 2.096
+ cell hold 0.113 2.343
+ clock uncertainty 0.000 2.343
+ clock recovergence pessimism -0.093 2.250
+ Required time 2.250
---------------------------------------------------------------------------------------------------------
- Slack 0.167ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check): 0.306 ns
- Start Point: ub_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock b_sclk)
- End Point: ub_lvds_rx/ramread0_syn_116.b[0] (rising edge triggered by clock b_sclk)
- Clock group: b_lvds_clk_p
- Process: Fast
- Data Path Delay: 0.464ns (logic 0.109ns, net 0.355ns, 23% logic)
- Logic Levels: 1
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/reg16_syn_31.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge 0.000 1.938
----------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg16_syn_31.q[1] clk2q 0.109 r 2.047
- ub_lvds_rx/ramread0_syn_116.b[0] (ub_lvds_rx/wcnt[1]) net (fanout = 10) 0.355 r 2.402 encrypted_text(0)
- ub_lvds_rx/ramread0_syn_116 path2reg 0.000 2.402
- Arrival time 2.402 (1 lvl)
-
- source latency 0.000 0.000
- uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000
- ub_lvds_rx/ramread0_syn_116.clk (ub_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge 0.000 2.130
----------------------------------------------------------------------------------------------------------
- cell hold 0.113 2.243
- clock uncertainty 0.000 2.243
- clock recovergence pessimism -0.147 2.096
- Required time 2.096
----------------------------------------------------------------------------------------------------------
- Slack 0.306ns
+ Slack 0.113ns
---------------------------------------------------------------------------------------------------------
@@ -2645,19 +2617,323 @@ Minimum period is 0ns
Timing constraint: clock: S_clk
Clock = S_clk, period 9.258ns, rising at 0ns, falling at 4.63ns
-8592 endpoints analyzed totally, and 109546 paths analyzed
+8572 endpoints analyzed totally, and 111938 paths analyzed
0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 9.243ns
+Minimum period is 9.15ns
---------------------------------------------------------------------------------------------------------
-Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_93 (1 paths)
+Paths for end point reg7_syn_149 (188 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 0.015 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk (rising edge triggered by clock a_pclk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_93.mi[0] (rising edge triggered by clock S_clk)
+ Slack (setup check): 0.108 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb (rising edge triggered by clock S_clk)
+ End Point: reg7_syn_149.a[0] (rising edge triggered by clock S_clk)
Clock group: clock_source
Process: Slow
- Data Path Delay: 2.026ns (logic 0.720ns, net 1.306ns, 35% logic)
+ Data Path Delay: 8.970ns (logic 4.127ns, net 4.843ns, 46% logic)
+ Logic Levels: 7 ( LUT5=5 LUT3=2 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge 0.000 2.410
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dob[2] clk2q 0.833 r 3.243
+ adj_datao_b1[2]_syn_73.b[1] (sampling_fe_a/u_sort/u_data_prebuffer/dou_i[1][18]) net (fanout = 2) 1.170 r 4.413 ../../../../hg_mp/fe/prebuffer.v(279)
+ adj_datao_b1[2]_syn_73.f[1] cell (LUT5) 0.431 r 4.844
+ adj_datao_b1[2]_syn_79.a[1] (adj_datao_b1[2]_syn_16) net (fanout = 1) 0.689 r 5.533
+ adj_datao_b1[2]_syn_79.f[1] cell (LUT3) 0.424 r 5.957
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_79.a[1] (adj_datao_b1[2]_syn_18) net (fanout = 1) 0.456 r 6.413
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_79.f[1] cell (LUT3) 0.424 r 6.837
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_488.a[1] (adj_datao_b1[2]_syn_32) net (fanout = 2) 0.608 r 7.445
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_488.fx[0] cell (LUT5) 0.618 r 8.063
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg10_syn_128.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[2]) net (fanout = 1) 0.567 r 8.630 ../../../../hg_mp/fe/read_ram_data.v(47)
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg10_syn_128.f[0] cell (LUT5) 0.431 r 9.061
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_59.a[0] (adj_datao_b1[2]_syn_39) net (fanout = 1) 0.615 r 9.676
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_59.f[0] cell (LUT5) 0.424 r 10.100
+ reg7_syn_149.a[0] (adj_datao_b1[2]_syn_43) net (fanout = 1) 0.738 r 10.838 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1044)
+ reg7_syn_149 path2reg0 (LUT5) 0.542 11.380
+ Arrival time 11.380 (7 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ reg7_syn_149.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ capture clock edge 9.258 11.424
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.116 11.308
+ clock uncertainty -0.000 11.308
+ clock recovergence pessimism 0.180 11.488
+ Required time 11.488
+---------------------------------------------------------------------------------------------------------
+ Slack 0.108ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check): 0.108 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb (rising edge triggered by clock S_clk)
+ End Point: reg7_syn_149.a[0] (rising edge triggered by clock S_clk)
+ Clock group: clock_source
+ Process: Slow
+ Data Path Delay: 8.970ns (logic 4.127ns, net 4.843ns, 46% logic)
+ Logic Levels: 7 ( LUT5=5 LUT3=2 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge 0.000 2.410
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dob[2] clk2q 0.833 r 3.243
+ adj_datao_b1[2]_syn_73.b[1] (sampling_fe_a/u_sort/u_data_prebuffer/dou_i[1][18]) net (fanout = 2) 1.170 r 4.413 ../../../../hg_mp/fe/prebuffer.v(279)
+ adj_datao_b1[2]_syn_73.f[1] cell (LUT5) 0.431 r 4.844
+ adj_datao_b1[2]_syn_79.a[1] (adj_datao_b1[2]_syn_16) net (fanout = 1) 0.689 r 5.533
+ adj_datao_b1[2]_syn_79.f[1] cell (LUT3) 0.424 r 5.957
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_79.a[1] (adj_datao_b1[2]_syn_18) net (fanout = 1) 0.456 r 6.413
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_79.f[1] cell (LUT3) 0.424 r 6.837
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_488.a[0] (adj_datao_b1[2]_syn_32) net (fanout = 2) 0.608 r 7.445
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_488.fx[0] cell (LUT5) 0.618 r 8.063
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg10_syn_128.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[2]) net (fanout = 1) 0.567 r 8.630 ../../../../hg_mp/fe/read_ram_data.v(47)
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg10_syn_128.f[0] cell (LUT5) 0.431 r 9.061
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_59.a[0] (adj_datao_b1[2]_syn_39) net (fanout = 1) 0.615 r 9.676
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_59.f[0] cell (LUT5) 0.424 r 10.100
+ reg7_syn_149.a[0] (adj_datao_b1[2]_syn_43) net (fanout = 1) 0.738 r 10.838 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1044)
+ reg7_syn_149 path2reg0 (LUT5) 0.542 11.380
+ Arrival time 11.380 (7 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ reg7_syn_149.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ capture clock edge 9.258 11.424
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.116 11.308
+ clock uncertainty -0.000 11.308
+ clock recovergence pessimism 0.180 11.488
+ Required time 11.488
+---------------------------------------------------------------------------------------------------------
+ Slack 0.108ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check): 0.415 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb (rising edge triggered by clock S_clk)
+ End Point: reg7_syn_149.a[0] (rising edge triggered by clock S_clk)
+ Clock group: clock_source
+ Process: Slow
+ Data Path Delay: 8.663ns (logic 4.120ns, net 4.543ns, 47% logic)
+ Logic Levels: 7 ( LUT5=5 LUT3=2 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge 0.000 2.410
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dob[2] clk2q 0.833 r 3.243
+ adj_datao_b1[2]_syn_73.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/dou_i[0][18]) net (fanout = 2) 0.870 r 4.113 ../../../../hg_mp/fe/prebuffer.v(279)
+ adj_datao_b1[2]_syn_73.f[1] cell (LUT5) 0.424 r 4.537
+ adj_datao_b1[2]_syn_79.a[1] (adj_datao_b1[2]_syn_16) net (fanout = 1) 0.689 r 5.226
+ adj_datao_b1[2]_syn_79.f[1] cell (LUT3) 0.424 r 5.650
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_79.a[1] (adj_datao_b1[2]_syn_18) net (fanout = 1) 0.456 r 6.106
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_79.f[1] cell (LUT3) 0.424 r 6.530
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_488.a[1] (adj_datao_b1[2]_syn_32) net (fanout = 2) 0.608 r 7.138
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_488.fx[0] cell (LUT5) 0.618 r 7.756
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg10_syn_128.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[2]) net (fanout = 1) 0.567 r 8.323 ../../../../hg_mp/fe/read_ram_data.v(47)
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg10_syn_128.f[0] cell (LUT5) 0.431 r 8.754
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_59.a[0] (adj_datao_b1[2]_syn_39) net (fanout = 1) 0.615 r 9.369
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_59.f[0] cell (LUT5) 0.424 r 9.793
+ reg7_syn_149.a[0] (adj_datao_b1[2]_syn_43) net (fanout = 1) 0.738 r 10.531 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1044)
+ reg7_syn_149 path2reg0 (LUT5) 0.542 11.073
+ Arrival time 11.073 (7 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ reg7_syn_149.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ capture clock edge 9.258 11.424
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.116 11.308
+ clock uncertainty -0.000 11.308
+ clock recovergence pessimism 0.180 11.488
+ Required time 11.488
+---------------------------------------------------------------------------------------------------------
+ Slack 0.415ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point reg7_syn_152 (114 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check): 0.309 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clkb (rising edge triggered by clock S_clk)
+ End Point: reg7_syn_152.a[0] (rising edge triggered by clock S_clk)
+ Clock group: clock_source
+ Process: Slow
+ Data Path Delay: 8.769ns (logic 3.926ns, net 4.843ns, 44% logic)
+ Logic Levels: 7 ( LUT5=4 LUT4=3 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clkb (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge 0.000 2.410
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.dob[5] clk2q 0.833 r 3.243
+ reg6_syn_164.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/dou_i[1][45]) net (fanout = 1) 0.852 r 4.095 ../../../../hg_mp/fe/prebuffer.v(279)
+ reg6_syn_164.f[0] cell (LUT4) 0.431 r 4.526
+ adj_datao_b1[21]_syn_70.a[1] (adj_datao_b1[21]_syn_22) net (fanout = 1) 0.918 r 5.444
+ adj_datao_b1[21]_syn_70.f[1] cell (LUT4) 0.424 r 5.868
+ u_bus_top/u_local_bus_slve_cis/sel23_syn_6787.a[0] (adj_datao_b1[21]_syn_26) net (fanout = 2) 0.794 r 6.662
+ u_bus_top/u_local_bus_slve_cis/sel23_syn_6787.f[0] cell (LUT4) 0.424 r 7.086
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_491.a[0] (adj_datao_b1[5]_syn_20) net (fanout = 1) 0.468 r 7.554
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_491.f[0] cell (LUT5) 0.424 r 7.978
+ u_bus_top/reg15_syn_186.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[5]) net (fanout = 1) 0.672 r 8.650 ../../../../hg_mp/fe/read_ram_data.v(47)
+ u_bus_top/reg15_syn_186.f[1] cell (LUT5) 0.424 r 9.074
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_56.a[1] (adj_datao_b1[5]_syn_27) net (fanout = 1) 0.468 r 9.542
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_56.f[1] cell (LUT5) 0.424 r 9.966
+ reg7_syn_152.a[0] (adj_datao_b1[5]_syn_31) net (fanout = 1) 0.671 r 10.637 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1044)
+ reg7_syn_152 path2reg0 (LUT5) 0.542 11.179
+ Arrival time 11.179 (7 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ reg7_syn_152.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ capture clock edge 9.258 11.424
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.116 11.308
+ clock uncertainty -0.000 11.308
+ clock recovergence pessimism 0.180 11.488
+ Required time 11.488
+---------------------------------------------------------------------------------------------------------
+ Slack 0.309ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check): 0.591 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb (rising edge triggered by clock S_clk)
+ End Point: reg7_syn_152.a[0] (rising edge triggered by clock S_clk)
+ Clock group: clock_source
+ Process: Slow
+ Data Path Delay: 8.487ns (logic 3.764ns, net 4.723ns, 44% logic)
+ Logic Levels: 7 ( LUT5=4 LUT4=2 LUT3=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge 0.000 2.410
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dob[5] clk2q 0.833 r 3.243
+ clkmipi_rstn_reg_syn_13.d[0] (sampling_fe_a/u_sort/u_data_prebuffer/dou_i[0][21]) net (fanout = 1) 0.673 r 3.916 ../../../../hg_mp/fe/prebuffer.v(279)
+ clkmipi_rstn_reg_syn_13.f[0] cell (LUT3) 0.262 r 4.178
+ adj_datao_b1[21]_syn_70.b[1] (adj_datao_b1[21]_syn_24) net (fanout = 1) 0.977 r 5.155
+ adj_datao_b1[21]_syn_70.f[1] cell (LUT4) 0.431 r 5.586
+ u_bus_top/u_local_bus_slve_cis/sel23_syn_6787.a[0] (adj_datao_b1[21]_syn_26) net (fanout = 2) 0.794 r 6.380
+ u_bus_top/u_local_bus_slve_cis/sel23_syn_6787.f[0] cell (LUT4) 0.424 r 6.804
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_491.a[0] (adj_datao_b1[5]_syn_20) net (fanout = 1) 0.468 r 7.272
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_491.f[0] cell (LUT5) 0.424 r 7.696
+ u_bus_top/reg15_syn_186.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[5]) net (fanout = 1) 0.672 r 8.368 ../../../../hg_mp/fe/read_ram_data.v(47)
+ u_bus_top/reg15_syn_186.f[1] cell (LUT5) 0.424 r 8.792
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_56.a[1] (adj_datao_b1[5]_syn_27) net (fanout = 1) 0.468 r 9.260
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_56.f[1] cell (LUT5) 0.424 r 9.684
+ reg7_syn_152.a[0] (adj_datao_b1[5]_syn_31) net (fanout = 1) 0.671 r 10.355 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1044)
+ reg7_syn_152 path2reg0 (LUT5) 0.542 10.897
+ Arrival time 10.897 (7 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ reg7_syn_152.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ capture clock edge 9.258 11.424
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.116 11.308
+ clock uncertainty -0.000 11.308
+ clock recovergence pessimism 0.180 11.488
+ Required time 11.488
+---------------------------------------------------------------------------------------------------------
+ Slack 0.591ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check): 0.607 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst_syn_1.clkb (rising edge triggered by clock S_clk)
+ End Point: reg7_syn_152.a[0] (rising edge triggered by clock S_clk)
+ Clock group: clock_source
+ Process: Slow
+ Data Path Delay: 8.471ns (logic 3.919ns, net 4.552ns, 46% logic)
+ Logic Levels: 7 ( LUT5=4 LUT4=3 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst_syn_1.clkb (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge 0.000 2.410
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst_syn_1.dob[5] clk2q 0.833 r 3.243
+ reg6_syn_164.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/dou_i[0][45]) net (fanout = 1) 0.561 r 3.804 ../../../../hg_mp/fe/prebuffer.v(279)
+ reg6_syn_164.f[0] cell (LUT4) 0.424 r 4.228
+ adj_datao_b1[21]_syn_70.a[1] (adj_datao_b1[21]_syn_22) net (fanout = 1) 0.918 r 5.146
+ adj_datao_b1[21]_syn_70.f[1] cell (LUT4) 0.424 r 5.570
+ u_bus_top/u_local_bus_slve_cis/sel23_syn_6787.a[0] (adj_datao_b1[21]_syn_26) net (fanout = 2) 0.794 r 6.364
+ u_bus_top/u_local_bus_slve_cis/sel23_syn_6787.f[0] cell (LUT4) 0.424 r 6.788
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_491.a[0] (adj_datao_b1[5]_syn_20) net (fanout = 1) 0.468 r 7.256
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_491.f[0] cell (LUT5) 0.424 r 7.680
+ u_bus_top/reg15_syn_186.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[5]) net (fanout = 1) 0.672 r 8.352 ../../../../hg_mp/fe/read_ram_data.v(47)
+ u_bus_top/reg15_syn_186.f[1] cell (LUT5) 0.424 r 8.776
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_56.a[1] (adj_datao_b1[5]_syn_27) net (fanout = 1) 0.468 r 9.244
+ sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_56.f[1] cell (LUT5) 0.424 r 9.668
+ reg7_syn_152.a[0] (adj_datao_b1[5]_syn_31) net (fanout = 1) 0.671 r 10.339 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1044)
+ reg7_syn_152 path2reg0 (LUT5) 0.542 10.881
+ Arrival time 10.881 (7 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ reg7_syn_152.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ capture clock edge 9.258 11.424
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.116 11.308
+ clock uncertainty -0.000 11.308
+ clock recovergence pessimism 0.180 11.488
+ Required time 11.488
+---------------------------------------------------------------------------------------------------------
+ Slack 0.607ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_97 (1 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check): 0.353 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk (rising edge triggered by clock a_pclk)
+ End Point: sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_97.mi[0] (rising edge triggered by clock S_clk)
+ Clock group: clock_source
+ Process: Slow
+ Data Path Delay: 1.688ns (logic 0.720ns, net 0.968ns, 42% logic)
Logic Levels: 1 ( LUT5=1 )
Point Type Incr Path Info
@@ -2670,17 +2946,17 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_93 (1 paths)
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.q[1] clk2q 0.146 r 2.422
- sampling_fe_a/u_sort/frame_start_rd_d0_reg_syn_12.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0]) net (fanout = 14) 0.660 r 3.082 ../../../../hg_mp/fe/prebuffer.v(268)
- sampling_fe_a/u_sort/frame_start_rd_d0_reg_syn_12.f[0] cell (LUT5) 0.431 r 3.513
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_93.mi[0] (sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13) net (fanout = 8) 0.646 r 4.159 ../../../../hg_mp/fe/prebuffer.v(297)
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_93 path2reg0 0.143 4.302
- Arrival time 4.302 (1 lvl)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_75.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0]) net (fanout = 14) 0.257 r 2.679 ../../../../hg_mp/fe/prebuffer.v(268)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_75.f[0] cell (LUT5) 0.431 r 3.110
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_97.mi[0] (sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13) net (fanout = 7) 0.711 r 3.821 ../../../../hg_mp/fe/prebuffer.v(297)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_97 path2reg0 0.143 3.964
+ Arrival time 3.964 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_93.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_97.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
capture clock edge 2.267 4.433
---------------------------------------------------------------------------------------------------------
cell setup -0.116 4.317
@@ -2688,101 +2964,17 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_93 (1 paths)
clock recovergence pessimism 0.000 4.317
Required time 4.317
---------------------------------------------------------------------------------------------------------
- Slack 0.015ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point U_rgb_to_csi_pakage/S_rgb_de_1d_reg_syn_6_syn_2 (1 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check): 0.162 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk (rising edge triggered by clock a_pclk)
- End Point: U_rgb_to_csi_pakage/S_rgb_de_1d_reg_syn_6_syn_2.mi[0] (rising edge triggered by clock S_clk)
- Clock group: clock_source
- Process: Slow
- Data Path Delay: 1.879ns (logic 0.720ns, net 1.159ns, 38% logic)
- Logic Levels: 1 ( LUT5=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 2.276
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.q[1] clk2q 0.146 r 2.422
- sampling_fe_a/u_sort/frame_start_rd_d0_reg_syn_12.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0]) net (fanout = 14) 0.660 r 3.082 ../../../../hg_mp/fe/prebuffer.v(268)
- sampling_fe_a/u_sort/frame_start_rd_d0_reg_syn_12.f[0] cell (LUT5) 0.431 r 3.513
- U_rgb_to_csi_pakage/S_rgb_de_1d_reg_syn_6_syn_2.mi[0] (sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13) net (fanout = 8) 0.499 r 4.012 ../../../../hg_mp/fe/prebuffer.v(297)
- U_rgb_to_csi_pakage/S_rgb_de_1d_reg_syn_6_syn_2 path2reg0 0.143 4.155
- Arrival time 4.155 (1 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- U_rgb_to_csi_pakage/S_rgb_de_1d_reg_syn_6_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- capture clock edge 2.267 4.433
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 4.317
- clock uncertainty -0.000 4.317
- clock recovergence pessimism 0.000 4.317
- Required time 4.317
----------------------------------------------------------------------------------------------------------
- Slack 0.162ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_87 (1 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check): 0.162 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk (rising edge triggered by clock a_pclk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_87.mi[1] (rising edge triggered by clock S_clk)
- Clock group: clock_source
- Process: Slow
- Data Path Delay: 1.879ns (logic 0.720ns, net 1.159ns, 38% logic)
- Logic Levels: 1 ( LUT5=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge 0.000 2.276
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.q[1] clk2q 0.146 r 2.422
- sampling_fe_a/u_sort/frame_start_rd_d0_reg_syn_12.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0]) net (fanout = 14) 0.660 r 3.082 ../../../../hg_mp/fe/prebuffer.v(268)
- sampling_fe_a/u_sort/frame_start_rd_d0_reg_syn_12.f[0] cell (LUT5) 0.431 r 3.513
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_87.mi[1] (sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13) net (fanout = 8) 0.499 r 4.012 ../../../../hg_mp/fe/prebuffer.v(297)
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_87 path2reg1 0.143 4.155
- Arrival time 4.155 (1 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_87.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- capture clock edge 2.267 4.433
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 4.317
- clock uncertainty -0.000 4.317
- clock recovergence pessimism 0.000 4.317
- Required time 4.317
----------------------------------------------------------------------------------------------------------
- Slack 0.162ns
+ Slack 0.353ns
---------------------------------------------------------------------------------------------------------
Hold checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point u_mipi_sot_min/reg1_syn_323 (1 paths)
+Paths for end point u_mipi_sot_min/reg1_syn_265 (1 paths)
---------------------------------------------------------------------------------------------------------
Slack (hold check): 0.067 ns
- Start Point: u_bus_top/reg18_syn_86.clk (rising edge triggered by clock clk_adc)
- End Point: u_mipi_sot_min/reg1_syn_323.mi[0] (rising edge triggered by clock S_clk)
+ Start Point: u_bus_top/reg19_syn_84.clk (rising edge triggered by clock clk_adc)
+ End Point: u_mipi_sot_min/reg1_syn_265.mi[1] (rising edge triggered by clock S_clk)
Clock group: clock_source
Process: Fast
Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic)
@@ -2792,19 +2984,19 @@ Paths for end point u_mipi_sot_min/reg1_syn_323 (1 paths)
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
- u_bus_top/reg18_syn_86.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ u_bus_top/reg19_syn_84.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- u_bus_top/reg18_syn_86.q[0] clk2q 0.109 r 2.047
- u_mipi_sot_min/reg1_syn_323.mi[0] (u_mipi_sot_min/signal_from[0]) net (fanout = 1) 0.216 r 2.263 ../../../../hg_mp/cdc/cdc_sync.v(9)
- u_mipi_sot_min/reg1_syn_323 path2reg0 0.095 2.358
+ u_bus_top/reg19_syn_84.q[1] clk2q 0.109 r 2.047
+ u_mipi_sot_min/reg1_syn_265.mi[1] (u_mipi_sot_min/signal_from[3]) net (fanout = 1) 0.216 r 2.263 ../../../../hg_mp/cdc/cdc_sync.v(9)
+ u_mipi_sot_min/reg1_syn_265 path2reg1 0.095 2.358
Arrival time 2.358 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- u_mipi_sot_min/reg1_syn_323.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ u_mipi_sot_min/reg1_syn_265.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
cell hold 0.061 2.291
@@ -2816,11 +3008,11 @@ Paths for end point u_mipi_sot_min/reg1_syn_323 (1 paths)
---------------------------------------------------------------------------------------------------------
-Paths for end point u_mipi_sot_min/reg1_syn_303 (1 paths)
+Paths for end point u_mipi_sot_min/reg1_syn_283 (1 paths)
---------------------------------------------------------------------------------------------------------
Slack (hold check): 0.067 ns
- Start Point: u_bus_top/reg19_syn_77.clk (rising edge triggered by clock clk_adc)
- End Point: u_mipi_sot_min/reg1_syn_303.mi[0] (rising edge triggered by clock S_clk)
+ Start Point: u_bus_top/reg18_syn_72.clk (rising edge triggered by clock clk_adc)
+ End Point: u_mipi_sot_min/reg1_syn_283.mi[1] (rising edge triggered by clock S_clk)
Clock group: clock_source
Process: Fast
Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic)
@@ -2830,19 +3022,19 @@ Paths for end point u_mipi_sot_min/reg1_syn_303 (1 paths)
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
- u_bus_top/reg19_syn_77.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ u_bus_top/reg18_syn_72.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- u_bus_top/reg19_syn_77.q[0] clk2q 0.109 r 2.047
- u_mipi_sot_min/reg1_syn_303.mi[0] (u_mipi_sot_min/signal_from[10]) net (fanout = 1) 0.216 r 2.263 ../../../../hg_mp/cdc/cdc_sync.v(9)
- u_mipi_sot_min/reg1_syn_303 path2reg0 0.095 2.358
+ u_bus_top/reg18_syn_72.q[0] clk2q 0.109 r 2.047
+ u_mipi_sot_min/reg1_syn_283.mi[1] (u_mipi_sot_min/signal_from[2]) net (fanout = 1) 0.216 r 2.263 ../../../../hg_mp/cdc/cdc_sync.v(9)
+ u_mipi_sot_min/reg1_syn_283 path2reg1 0.095 2.358
Arrival time 2.358 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- u_mipi_sot_min/reg1_syn_303.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ u_mipi_sot_min/reg1_syn_283.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
cell hold 0.061 2.291
@@ -2854,33 +3046,35 @@ Paths for end point u_mipi_sot_min/reg1_syn_303 (1 paths)
---------------------------------------------------------------------------------------------------------
-Paths for end point u_mipi_eot_min/reg1_syn_307 (1 paths)
+Paths for end point reg13_syn_43 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.067 ns
- Start Point: u_bus_top/reg18_syn_69.clk (rising edge triggered by clock clk_adc)
- End Point: u_mipi_eot_min/reg1_syn_307.mi[1] (rising edge triggered by clock S_clk)
+ Slack (hold check): 0.075 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/channelPart/wr_end_reg_syn_8.clk (rising edge triggered by clock a_pclk)
+ End Point: reg13_syn_43.mi[0] (rising edge triggered by clock S_clk)
Clock group: clock_source
Process: Fast
- Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic)
+ Data Path Delay: 0.428ns (logic 0.204ns, net 0.224ns, 47% logic)
Logic Levels: 0
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
- u_pll/pll_inst.clkc[4] 0.000 0.000
- u_bus_top/reg18_syn_69.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ u_pll_lvds/pll_inst.clkc[0] 0.000 0.000
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ sampling_fe_a/u_sort/u_data_prebuffer/channelPart/wr_end_reg_syn_8.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
- u_bus_top/reg18_syn_69.q[1] clk2q 0.109 r 2.047
- u_mipi_eot_min/reg1_syn_307.mi[1] (u_mipi_eot_min/signal_from[6]) net (fanout = 1) 0.216 r 2.263 ../../../../hg_mp/cdc/cdc_sync.v(9)
- u_mipi_eot_min/reg1_syn_307 path2reg1 0.095 2.358
- Arrival time 2.358 (0 lvl)
+ sampling_fe_a/u_sort/u_data_prebuffer/channelPart/wr_end_reg_syn_8.q[0] clk2q 0.109 r 2.047
+ reg13_syn_43.mi[0] (sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/u0_rdsoft_n/signal_from[0]) net (fanout = 7) 0.224 r 2.271 ../../../../hg_mp/cdc/cdc_sync.v(9)
+ reg13_syn_43 path2reg0 0.095 2.366
+ Arrival time 2.366 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- u_mipi_eot_min/reg1_syn_307.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ reg13_syn_43.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
cell hold 0.061 2.291
@@ -2888,62 +3082,20 @@ Paths for end point u_mipi_eot_min/reg1_syn_307 (1 paths)
clock recovergence pessimism 0.000 2.291
Required time 2.291
---------------------------------------------------------------------------------------------------------
- Slack 0.067ns
+ Slack 0.075ns
---------------------------------------------------------------------------------------------------------
Recovery checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point debug[2]_syn_4 (1 paths)
+Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070 (2 paths)
---------------------------------------------------------------------------------------------------------
- Slack (recovery check): 5.048 ns
+ Slack (recovery check): 5.584 ns
Start Point: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
- End Point: debug[2]_syn_4.rst (rising edge triggered by clock S_clk)
+ End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070.sr (rising edge triggered by clock S_clk)
Clock group: clock_source
Process: Slow
- Data Path Delay: 3.916ns (logic 0.351ns, net 3.565ns, 8% logic)
- Logic Levels: 1 ( LUT2=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge 0.000 2.410
----------------------------------------------------------------------------------------------------------
- U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0] clk2q 0.146 r 2.556
- U_rgb_to_csi_pakage/reg9_syn_19_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 6) 1.143 r 3.699 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
- U_rgb_to_csi_pakage/reg9_syn_19_syn_2.f[0] cell (LUT2) 0.205 r 3.904
- debug[2]_syn_4.rst (U_rgb_to_csi_pakage/S_rst_n) net (fanout = 1) 2.422 r 6.326 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
- debug[2]_syn_4 path2reg 0.000 6.326
- Arrival time 6.326 (1 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- debug[2]_syn_4.osclk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 1.978 1.978 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- capture clock edge 9.258 11.236
----------------------------------------------------------------------------------------------------------
- cell recovery 0.030 11.266
- clock uncertainty -0.000 11.266
- clock recovergence pessimism 0.108 11.374
- Required time 11.374
----------------------------------------------------------------------------------------------------------
- Slack 5.048ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1127_syn_2 (2 paths)
----------------------------------------------------------------------------------------------------------
- Slack (recovery check): 5.167 ns
- Start Point: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
- End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1127_syn_2.sr (rising edge triggered by clock S_clk)
- Clock group: clock_source
- Process: Slow
- Data Path Delay: 3.727ns (logic 0.699ns, net 3.028ns, 18% logic)
+ Data Path Delay: 3.310ns (logic 0.699ns, net 2.611ns, 21% logic)
Logic Levels: 2 ( LUT2=2 )
Point Type Incr Path Info
@@ -2956,19 +3108,19 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1127_
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0] clk2q 0.146 r 2.556
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_535_syn_2.d[1] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 6) 0.703 r 3.259 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_535_syn_2.f[1] cell (LUT2) 0.262 r 3.521
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.d[0] (U_rgb_to_csi_pakage/S_rst_n_dup_4) net (fanout = 30) 1.090 r 4.611 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.f[0] cell (LUT2) 0.205 r 4.816
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1127_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst) net (fanout = 18) 1.235 r 6.051 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1127_syn_2 path2reg 0.086 6.137
- Arrival time 6.137 (2 lvl)
+ reg21_syn_52_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.378 r 2.934 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
+ reg21_syn_52_syn_2.f[0] cell (LUT2) 0.262 r 3.196
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.d[0] (U_rgb_to_csi_pakage/S_rst_n) net (fanout = 29) 0.751 r 3.947 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.f[0] cell (LUT2) 0.205 r 4.152
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net (fanout = 18) 1.482 r 5.634 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070 path2reg 0.086 5.720
+ Arrival time 5.720 (2 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1127_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
capture clock edge 9.258 11.424
---------------------------------------------------------------------------------------------------------
cell recovery -0.300 11.124
@@ -2976,16 +3128,16 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1127_
clock recovergence pessimism 0.180 11.304
Required time 11.304
---------------------------------------------------------------------------------------------------------
- Slack 5.167ns
+ Slack 5.584ns
---------------------------------------------------------------------------------------------------------
- Slack (recovery check): 6.190 ns
+ Slack (recovery check): 5.858 ns
Start Point: adj_vsynco_reg_syn_5.clk (rising edge triggered by clock S_clk)
- End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1127_syn_2.sr (rising edge triggered by clock S_clk)
+ End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070.sr (rising edge triggered by clock S_clk)
Clock group: clock_source
Process: Slow
- Data Path Delay: 2.704ns (logic 0.483ns, net 2.221ns, 17% logic)
+ Data Path Delay: 3.036ns (logic 0.483ns, net 2.553ns, 15% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
@@ -2997,18 +3149,18 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1127_
adj_vsynco_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- adj_vsynco_reg_syn_5.q[0] clk2q 0.146 r 2.556
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.c[0] (U_rgb_to_csi_pakage/I_rgb_vsync) net (fanout = 8) 0.986 r 3.542 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.f[0] cell (LUT2) 0.251 r 3.793
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1127_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst) net (fanout = 18) 1.235 r 5.028 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1127_syn_2 path2reg 0.086 5.114
- Arrival time 5.114 (1 lvl)
+ adj_vsynco_reg_syn_5.q[1] clk2q 0.146 r 2.556
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.c[0] (U_rgb_to_csi_pakage/I_rgb_vsync) net (fanout = 10) 1.071 r 3.627 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.f[0] cell (LUT2) 0.251 r 3.878
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net (fanout = 18) 1.482 r 5.360 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070 path2reg 0.086 5.446
+ Arrival time 5.446 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1127_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
capture clock edge 9.258 11.424
---------------------------------------------------------------------------------------------------------
cell recovery -0.300 11.124
@@ -3016,18 +3168,18 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1127_
clock recovergence pessimism 0.180 11.304
Required time 11.304
---------------------------------------------------------------------------------------------------------
- Slack 6.190ns
+ Slack 5.858ns
---------------------------------------------------------------------------------------------------------
-Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284 (2 paths)
+Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2 (2 paths)
---------------------------------------------------------------------------------------------------------
- Slack (recovery check): 5.259 ns
+ Slack (recovery check): 6.014 ns
Start Point: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
- End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.sr (rising edge triggered by clock S_clk)
+ End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2.sr (rising edge triggered by clock S_clk)
Clock group: clock_source
Process: Slow
- Data Path Delay: 3.635ns (logic 0.699ns, net 2.936ns, 19% logic)
+ Data Path Delay: 2.880ns (logic 0.699ns, net 2.181ns, 24% logic)
Logic Levels: 2 ( LUT2=2 )
Point Type Incr Path Info
@@ -3040,19 +3192,19 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0] clk2q 0.146 r 2.556
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_535_syn_2.d[1] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 6) 0.703 r 3.259 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_535_syn_2.f[1] cell (LUT2) 0.262 r 3.521
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.d[1] (U_rgb_to_csi_pakage/S_rst_n_dup_4) net (fanout = 30) 1.090 r 4.611 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.f[1] cell (LUT2) 0.205 r 4.816
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_20) net (fanout = 16) 1.143 r 5.959 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284 path2reg 0.086 6.045
- Arrival time 6.045 (2 lvl)
+ reg21_syn_52_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.378 r 2.934 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
+ reg21_syn_52_syn_2.f[0] cell (LUT2) 0.262 r 3.196
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.d[0] (U_rgb_to_csi_pakage/S_rst_n) net (fanout = 29) 0.751 r 3.947 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.f[0] cell (LUT2) 0.205 r 4.152
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net (fanout = 18) 1.052 r 5.204 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2 path2reg 0.086 5.290
+ Arrival time 5.290 (2 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
capture clock edge 9.258 11.424
---------------------------------------------------------------------------------------------------------
cell recovery -0.300 11.124
@@ -3060,16 +3212,16 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
clock recovergence pessimism 0.180 11.304
Required time 11.304
---------------------------------------------------------------------------------------------------------
- Slack 5.259ns
+ Slack 6.014ns
---------------------------------------------------------------------------------------------------------
- Slack (recovery check): 6.282 ns
+ Slack (recovery check): 6.288 ns
Start Point: adj_vsynco_reg_syn_5.clk (rising edge triggered by clock S_clk)
- End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.sr (rising edge triggered by clock S_clk)
+ End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2.sr (rising edge triggered by clock S_clk)
Clock group: clock_source
Process: Slow
- Data Path Delay: 2.612ns (logic 0.483ns, net 2.129ns, 18% logic)
+ Data Path Delay: 2.606ns (logic 0.483ns, net 2.123ns, 18% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
@@ -3081,18 +3233,18 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
adj_vsynco_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- adj_vsynco_reg_syn_5.q[0] clk2q 0.146 r 2.556
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.c[1] (U_rgb_to_csi_pakage/I_rgb_vsync) net (fanout = 8) 0.986 r 3.542 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.f[1] cell (LUT2) 0.251 r 3.793
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_20) net (fanout = 16) 1.143 r 4.936 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284 path2reg 0.086 5.022
- Arrival time 5.022 (1 lvl)
+ adj_vsynco_reg_syn_5.q[1] clk2q 0.146 r 2.556
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.c[0] (U_rgb_to_csi_pakage/I_rgb_vsync) net (fanout = 10) 1.071 r 3.627 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.f[0] cell (LUT2) 0.251 r 3.878
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net (fanout = 18) 1.052 r 4.930 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2 path2reg 0.086 5.016
+ Arrival time 5.016 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
capture clock edge 9.258 11.424
---------------------------------------------------------------------------------------------------------
cell recovery -0.300 11.124
@@ -3100,20 +3252,104 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
clock recovergence pessimism 0.180 11.304
Required time 11.304
---------------------------------------------------------------------------------------------------------
- Slack 6.282ns
+ Slack 6.288ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2 (2 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (recovery check): 6.026 ns
+ Start Point: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
+ End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2.sr (rising edge triggered by clock S_clk)
+ Clock group: clock_source
+ Process: Slow
+ Data Path Delay: 2.868ns (logic 0.699ns, net 2.169ns, 24% logic)
+ Logic Levels: 2 ( LUT2=2 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge 0.000 2.410
+---------------------------------------------------------------------------------------------------------
+ U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0] clk2q 0.146 r 2.556
+ reg21_syn_52_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.378 r 2.934 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
+ reg21_syn_52_syn_2.f[0] cell (LUT2) 0.262 r 3.196
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.d[0] (U_rgb_to_csi_pakage/S_rst_n) net (fanout = 29) 0.751 r 3.947 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.f[0] cell (LUT2) 0.205 r 4.152
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net (fanout = 18) 1.040 r 5.192 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2 path2reg 0.086 5.278
+ Arrival time 5.278 (2 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ capture clock edge 9.258 11.424
+---------------------------------------------------------------------------------------------------------
+ cell recovery -0.300 11.124
+ clock uncertainty -0.000 11.124
+ clock recovergence pessimism 0.180 11.304
+ Required time 11.304
+---------------------------------------------------------------------------------------------------------
+ Slack 6.026ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (recovery check): 6.300 ns
+ Start Point: adj_vsynco_reg_syn_5.clk (rising edge triggered by clock S_clk)
+ End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2.sr (rising edge triggered by clock S_clk)
+ Clock group: clock_source
+ Process: Slow
+ Data Path Delay: 2.594ns (logic 0.483ns, net 2.111ns, 18% logic)
+ Logic Levels: 1 ( LUT2=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ adj_vsynco_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge 0.000 2.410
+---------------------------------------------------------------------------------------------------------
+ adj_vsynco_reg_syn_5.q[1] clk2q 0.146 r 2.556
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.c[0] (U_rgb_to_csi_pakage/I_rgb_vsync) net (fanout = 10) 1.071 r 3.627 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.f[0] cell (LUT2) 0.251 r 3.878
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net (fanout = 18) 1.040 r 4.918 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2 path2reg 0.086 5.004
+ Arrival time 5.004 (1 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ capture clock edge 9.258 11.424
+---------------------------------------------------------------------------------------------------------
+ cell recovery -0.300 11.124
+ clock uncertainty -0.000 11.124
+ clock recovergence pessimism 0.180 11.304
+ Required time 11.304
+---------------------------------------------------------------------------------------------------------
+ Slack 6.300ns
---------------------------------------------------------------------------------------------------------
Removal checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point U_rgb_to_csi_pakage/reg2_syn_165_syn_2 (1 paths)
+Paths for end point U_rgb_to_csi_pakage/reg7_syn_145_syn_2 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (removal check): 0.915 ns
+ Slack (removal check): 0.773 ns
Start Point: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
- End Point: U_rgb_to_csi_pakage/reg2_syn_165_syn_2.sr (rising edge triggered by clock S_clk)
+ End Point: U_rgb_to_csi_pakage/reg7_syn_145_syn_2.sr (rising edge triggered by clock S_clk)
Clock group: clock_source
Process: Fast
- Data Path Delay: 1.213ns (logic 0.375ns, net 0.838ns, 30% logic)
+ Data Path Delay: 1.071ns (logic 0.375ns, net 0.696ns, 35% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
@@ -3126,17 +3362,17 @@ Paths for end point U_rgb_to_csi_pakage/reg2_syn_165_syn_2 (1 paths)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0] clk2q 0.109 r 2.138
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_445_syn_2.d[1] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 6) 0.374 r 2.512 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_445_syn_2.f[1] cell (LUT2) 0.179 r 2.691
- U_rgb_to_csi_pakage/reg2_syn_165_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n_dup_2) net (fanout = 17) 0.464 r 3.155 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
- U_rgb_to_csi_pakage/reg2_syn_165_syn_2 path2reg 0.087 3.242
- Arrival time 3.242 (1 lvl)
+ reg21_syn_54_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.355 r 2.493 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
+ reg21_syn_54_syn_2.f[0] cell (LUT2) 0.179 r 2.672
+ U_rgb_to_csi_pakage/reg7_syn_145_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n_dup_4) net (fanout = 36) 0.341 r 3.013 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
+ U_rgb_to_csi_pakage/reg7_syn_145_syn_2 path2reg 0.087 3.100
+ Arrival time 3.100 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- U_rgb_to_csi_pakage/reg2_syn_165_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ U_rgb_to_csi_pakage/reg7_syn_145_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
cell removal 0.253 2.483
@@ -3144,18 +3380,18 @@ Paths for end point U_rgb_to_csi_pakage/reg2_syn_165_syn_2 (1 paths)
clock recovergence pessimism -0.156 2.327
Required time 2.327
---------------------------------------------------------------------------------------------------------
- Slack 0.915ns
+ Slack 0.773ns
---------------------------------------------------------------------------------------------------------
-Paths for end point U_rgb_to_csi_pakage/reg2_syn_173_syn_2 (1 paths)
+Paths for end point U_rgb_to_csi_pakage/reg13_syn_67_syn_2 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (removal check): 0.915 ns
+ Slack (removal check): 0.775 ns
Start Point: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
- End Point: U_rgb_to_csi_pakage/reg2_syn_173_syn_2.sr (rising edge triggered by clock S_clk)
+ End Point: U_rgb_to_csi_pakage/reg13_syn_67_syn_2.sr (rising edge triggered by clock S_clk)
Clock group: clock_source
Process: Fast
- Data Path Delay: 1.213ns (logic 0.375ns, net 0.838ns, 30% logic)
+ Data Path Delay: 1.073ns (logic 0.375ns, net 0.698ns, 34% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
@@ -3168,17 +3404,17 @@ Paths for end point U_rgb_to_csi_pakage/reg2_syn_173_syn_2 (1 paths)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0] clk2q 0.109 r 2.138
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_445_syn_2.d[1] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 6) 0.374 r 2.512 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_445_syn_2.f[1] cell (LUT2) 0.179 r 2.691
- U_rgb_to_csi_pakage/reg2_syn_173_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n_dup_2) net (fanout = 17) 0.464 r 3.155 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
- U_rgb_to_csi_pakage/reg2_syn_173_syn_2 path2reg 0.087 3.242
- Arrival time 3.242 (1 lvl)
+ reg21_syn_52_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.240 r 2.378 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
+ reg21_syn_52_syn_2.f[0] cell (LUT2) 0.179 r 2.557
+ U_rgb_to_csi_pakage/reg13_syn_67_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n) net (fanout = 29) 0.458 r 3.015 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
+ U_rgb_to_csi_pakage/reg13_syn_67_syn_2 path2reg 0.087 3.102
+ Arrival time 3.102 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- U_rgb_to_csi_pakage/reg2_syn_173_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ U_rgb_to_csi_pakage/reg13_syn_67_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
cell removal 0.253 2.483
@@ -3186,18 +3422,18 @@ Paths for end point U_rgb_to_csi_pakage/reg2_syn_173_syn_2 (1 paths)
clock recovergence pessimism -0.156 2.327
Required time 2.327
---------------------------------------------------------------------------------------------------------
- Slack 0.915ns
+ Slack 0.775ns
---------------------------------------------------------------------------------------------------------
-Paths for end point U_rgb_to_csi_pakage/eot_flag_reg_syn_6_syn_2 (1 paths)
+Paths for end point U_rgb_to_csi_pakage/reg13_syn_79_syn_2 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (removal check): 0.927 ns
+ Slack (removal check): 0.805 ns
Start Point: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
- End Point: U_rgb_to_csi_pakage/eot_flag_reg_syn_6_syn_2.sr (rising edge triggered by clock S_clk)
+ End Point: U_rgb_to_csi_pakage/reg13_syn_79_syn_2.sr (rising edge triggered by clock S_clk)
Clock group: clock_source
Process: Fast
- Data Path Delay: 1.225ns (logic 0.375ns, net 0.850ns, 30% logic)
+ Data Path Delay: 1.103ns (logic 0.375ns, net 0.728ns, 33% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
@@ -3210,17 +3446,17 @@ Paths for end point U_rgb_to_csi_pakage/eot_flag_reg_syn_6_syn_2 (1 paths)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0] clk2q 0.109 r 2.138
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_535_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 6) 0.498 r 2.636 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_535_syn_2.f[0] cell (LUT2) 0.179 r 2.815
- U_rgb_to_csi_pakage/eot_flag_reg_syn_6_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n_dup_3) net (fanout = 27) 0.352 r 3.167 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
- U_rgb_to_csi_pakage/eot_flag_reg_syn_6_syn_2 path2reg 0.087 3.254
- Arrival time 3.254 (1 lvl)
+ reg21_syn_52_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.240 r 2.378 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
+ reg21_syn_52_syn_2.f[0] cell (LUT2) 0.179 r 2.557
+ U_rgb_to_csi_pakage/reg13_syn_79_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n) net (fanout = 29) 0.488 r 3.045 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
+ U_rgb_to_csi_pakage/reg13_syn_79_syn_2 path2reg 0.087 3.132
+ Arrival time 3.132 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- U_rgb_to_csi_pakage/eot_flag_reg_syn_6_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ U_rgb_to_csi_pakage/reg13_syn_79_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
capture clock edge 0.000 2.230
---------------------------------------------------------------------------------------------------------
cell removal 0.253 2.483
@@ -3228,7 +3464,7 @@ Paths for end point U_rgb_to_csi_pakage/eot_flag_reg_syn_6_syn_2 (1 paths)
clock recovergence pessimism -0.156 2.327
Required time 2.327
---------------------------------------------------------------------------------------------------------
- Slack 0.927ns
+ Slack 0.805ns
---------------------------------------------------------------------------------------------------------
@@ -3289,34 +3525,34 @@ Period checks:
Timing constraint: clock: clk_adc
Clock = clk_adc, period 166.664ns, rising at 0ns, falling at 83.332ns
-4244 endpoints analyzed totally, and 43444 paths analyzed
-3 errors detected : 3 setup errors (TNS = -3.421), 0 hold errors (TNS = 0.000)
-Minimum period is 168.723ns
+4282 endpoints analyzed totally, and 45638 paths analyzed
+3 errors detected : 3 setup errors (TNS = -3.307), 0 hold errors (TNS = 0.000)
+Minimum period is 168.461ns
---------------------------------------------------------------------------------------------------------
Paths for end point reg40_syn_14 (2 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): -2.059 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d_reg_syn_5.clk (rising edge triggered by clock S_clk_x2)
+ Slack (setup check): -1.797 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk (rising edge triggered by clock S_clk_x2)
End Point: reg40_syn_14.mi[0] (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Slow
- Data Path Delay: 1.598ns (logic 0.637ns, net 0.961ns, 39% logic)
+ Data Path Delay: 1.336ns (logic 0.540ns, net 0.796ns, 40% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d_reg_syn_5.q[1] clk2q 0.146 r 2.556
- reg29_syn_16.c[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d) net (fanout = 3) 0.493 r 3.049 encrypted_text(0)
- reg29_syn_16.f[0] cell (LUT2) 0.348 r 3.397
- reg40_syn_14.mi[0] (debug[3]_dup_1) net (fanout = 3) 0.468 r 3.865 ../../../../hg_mp/drx_top/huagao_mipi_top.v(57)
- reg40_syn_14 path2reg0 0.143 4.008
- Arrival time 4.008 (1 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.q[0] clk2q 0.146 r 2.556
+ reg29_syn_16.c[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d) net (fanout = 3) 0.489 r 3.045 encrypted_text(0)
+ reg29_syn_16.f[0] cell (LUT2) 0.251 r 3.296
+ reg40_syn_14.mi[0] (O_clk_lp_n_dup_1) net (fanout = 2) 0.307 r 3.603 ../../../../hg_mp/drx_top/huagao_mipi_top.v(42)
+ reg40_syn_14 path2reg0 0.143 3.746
+ Arrival time 3.746 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
@@ -3328,31 +3564,31 @@ Paths for end point reg40_syn_14 (2 paths)
clock recovergence pessimism 0.000 1.949
Required time 1.949
---------------------------------------------------------------------------------------------------------
- Slack -2.059ns
+ Slack -1.797ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): -1.810 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d_reg_syn_5.clk (rising edge triggered by clock S_clk_x2)
+ Slack (setup check): -1.738 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk (rising edge triggered by clock S_clk_x2)
End Point: reg40_syn_14.mi[0] (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Slow
- Data Path Delay: 1.349ns (logic 0.551ns, net 0.798ns, 40% logic)
+ Data Path Delay: 1.277ns (logic 0.494ns, net 0.783ns, 38% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d_reg_syn_5.q[0] clk2q 0.146 r 2.556
- reg29_syn_16.d[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d) net (fanout = 1) 0.330 r 2.886 encrypted_text(0)
- reg29_syn_16.f[0] cell (LUT2) 0.262 r 3.148
- reg40_syn_14.mi[0] (debug[3]_dup_1) net (fanout = 3) 0.468 r 3.616 ../../../../hg_mp/drx_top/huagao_mipi_top.v(57)
- reg40_syn_14 path2reg0 0.143 3.759
- Arrival time 3.759 (1 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.q[1] clk2q 0.146 r 2.556
+ reg29_syn_16.d[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d) net (fanout = 1) 0.476 r 3.032 encrypted_text(0)
+ reg29_syn_16.f[0] cell (LUT2) 0.205 r 3.237
+ reg40_syn_14.mi[0] (O_clk_lp_n_dup_1) net (fanout = 2) 0.307 r 3.544 ../../../../hg_mp/drx_top/huagao_mipi_top.v(42)
+ reg40_syn_14 path2reg0 0.143 3.687
+ Arrival time 3.687 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
@@ -3364,35 +3600,35 @@ Paths for end point reg40_syn_14 (2 paths)
clock recovergence pessimism 0.000 1.949
Required time 1.949
---------------------------------------------------------------------------------------------------------
- Slack -1.810ns
+ Slack -1.738ns
---------------------------------------------------------------------------------------------------------
-Paths for end point FV_MIPI_sync1_reg_syn_8 (1 paths)
+Paths for end point reg41_syn_15 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): -1.362 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d_reg_syn_5.clk (rising edge triggered by clock S_clk_x2)
- End Point: FV_MIPI_sync1_reg_syn_8.mi[0] (rising edge triggered by clock clk_adc)
+ Slack (setup check): -1.510 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk (rising edge triggered by clock S_clk_x2)
+ End Point: reg41_syn_15.mi[0] (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Slow
- Data Path Delay: 0.901ns (logic 0.289ns, net 0.612ns, 32% logic)
+ Data Path Delay: 1.049ns (logic 0.289ns, net 0.760ns, 27% logic)
Logic Levels: 0
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d_reg_syn_5.q[1] clk2q 0.146 r 2.556
- FV_MIPI_sync1_reg_syn_8.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d) net (fanout = 3) 0.612 r 3.168 encrypted_text(0)
- FV_MIPI_sync1_reg_syn_8 path2reg0 0.143 3.311
- Arrival time 3.311 (0 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.q[0] clk2q 0.146 r 2.556
+ reg41_syn_15.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d) net (fanout = 3) 0.760 r 3.316 encrypted_text(0)
+ reg41_syn_15 path2reg0 0.143 3.459
+ Arrival time 3.459 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
- FV_MIPI_sync1_reg_syn_8.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ reg41_syn_15.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4)
capture clock edge 0.020 2.065
---------------------------------------------------------------------------------------------------------
cell setup -0.116 1.949
@@ -3400,18 +3636,18 @@ Paths for end point FV_MIPI_sync1_reg_syn_8 (1 paths)
clock recovergence pessimism 0.000 1.949
Required time 1.949
---------------------------------------------------------------------------------------------------------
- Slack -1.362ns
+ Slack -1.510ns
---------------------------------------------------------------------------------------------------------
-Paths for end point u_bus_top/reg12_syn_208 (1 paths)
+Paths for end point u_bus_top/reg13_syn_216 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 7.375 ns
- Start Point: reg27_syn_241.clk (rising edge triggered by clock S_clk)
- End Point: u_bus_top/reg12_syn_208.mi[0] (rising edge triggered by clock clk_adc)
+ Slack (setup check): 6.926 ns
+ Start Point: reg26_syn_241.clk (rising edge triggered by clock S_clk)
+ End Point: u_bus_top/reg13_syn_216.mi[0] (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Slow
- Data Path Delay: 1.402ns (logic 0.289ns, net 1.113ns, 20% logic)
+ Data Path Delay: 1.851ns (logic 0.289ns, net 1.562ns, 15% logic)
Logic Levels: 0
Point Type Incr Path Info
@@ -3420,17 +3656,17 @@ Paths for end point u_bus_top/reg12_syn_208 (1 paths)
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- reg27_syn_241.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ reg26_syn_241.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- reg27_syn_241.q[0] clk2q 0.146 r 2.556
- u_bus_top/reg12_syn_208.mi[0] (lv_cnt_b[30]) net (fanout = 3) 1.113 r 3.669 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1072)
- u_bus_top/reg12_syn_208 path2reg0 0.143 3.812
- Arrival time 3.812 (0 lvl)
+ reg26_syn_241.q[1] clk2q 0.146 r 2.556
+ u_bus_top/reg13_syn_216.mi[0] (lv_cnt_a[31]) net (fanout = 3) 1.562 r 4.118 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1071)
+ u_bus_top/reg13_syn_216 path2reg0 0.143 4.261
+ Arrival time 4.261 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
- u_bus_top/reg12_syn_208.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ u_bus_top/reg13_syn_216.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4)
capture clock edge 9.258 11.303
---------------------------------------------------------------------------------------------------------
cell setup -0.116 11.187
@@ -3438,17 +3674,53 @@ Paths for end point u_bus_top/reg12_syn_208 (1 paths)
clock recovergence pessimism 0.000 11.187
Required time 11.187
---------------------------------------------------------------------------------------------------------
- Slack 7.375ns
+ Slack 6.926ns
---------------------------------------------------------------------------------------------------------
Hold checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point u_bus_top/reg1_syn_215 (1 paths)
+Paths for end point u_bus_top/reg5_syn_190 (1 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.251 ns
+ Start Point: u_bus_top/reg4_syn_178.clk (rising edge triggered by clock clk_adc)
+ End Point: u_bus_top/reg5_syn_190.mi[0] (rising edge triggered by clock clk_adc)
+ Clock group: clock_source
+ Process: Fast
+ Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[4] 0.000 0.000
+ u_bus_top/reg4_syn_178.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ launch clock edge 0.000 1.938
+---------------------------------------------------------------------------------------------------------
+ u_bus_top/reg4_syn_178.q[1] clk2q 0.109 r 2.047
+ u_bus_top/reg5_syn_190.mi[0] (u_bus_top/adc_cfg_data_o_sync2d_8m[2]) net (fanout = 2) 0.216 r 2.263 ../../../../hg_mp/local_bus/ubus_top.v(94)
+ u_bus_top/reg5_syn_190 path2reg0 0.095 2.358
+ Arrival time 2.358 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[4] 0.000 0.000
+ u_bus_top/reg5_syn_190.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ capture clock edge 0.000 2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.061 2.191
+ clock uncertainty 0.000 2.191
+ clock recovergence pessimism -0.084 2.107
+ Required time 2.107
+---------------------------------------------------------------------------------------------------------
+ Slack 0.251ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point u_bus_top/reg0_syn_220 (1 paths)
---------------------------------------------------------------------------------------------------------
Slack (hold check): 0.258 ns
- Start Point: reg1_syn_194.clk (rising edge triggered by clock S_clk)
- End Point: u_bus_top/reg1_syn_215.mi[0] (rising edge triggered by clock clk_adc)
+ Start Point: reg1_syn_184.clk (rising edge triggered by clock S_clk)
+ End Point: u_bus_top/reg0_syn_220.mi[1] (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Fast
Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic)
@@ -3460,17 +3732,17 @@ Paths for end point u_bus_top/reg1_syn_215 (1 paths)
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- reg1_syn_194.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ reg1_syn_184.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- reg1_syn_194.q[1] clk2q 0.109 r 2.138
- u_bus_top/reg1_syn_215.mi[0] (S_hs_data_reg[10]) net (fanout = 1) 0.216 r 2.354 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1274)
- u_bus_top/reg1_syn_215 path2reg0 0.095 2.449
+ reg1_syn_184.q[1] clk2q 0.109 r 2.138
+ u_bus_top/reg0_syn_220.mi[1] (S_hs_data_reg[19]) net (fanout = 1) 0.216 r 2.354 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1274)
+ u_bus_top/reg0_syn_220 path2reg1 0.095 2.449
Arrival time 2.449 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
- u_bus_top/reg1_syn_215.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ u_bus_top/reg0_syn_220.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell hold 0.061 2.191
@@ -3482,11 +3754,11 @@ Paths for end point u_bus_top/reg1_syn_215 (1 paths)
---------------------------------------------------------------------------------------------------------
-Paths for end point u_bus_top/reg0_syn_215 (1 paths)
+Paths for end point u_bus_top/reg0_syn_217 (1 paths)
---------------------------------------------------------------------------------------------------------
Slack (hold check): 0.258 ns
- Start Point: reg1_syn_218.clk (rising edge triggered by clock S_clk)
- End Point: u_bus_top/reg0_syn_215.mi[0] (rising edge triggered by clock clk_adc)
+ Start Point: reg1_syn_181.clk (rising edge triggered by clock S_clk)
+ End Point: u_bus_top/reg0_syn_217.mi[0] (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Fast
Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic)
@@ -3498,55 +3770,17 @@ Paths for end point u_bus_top/reg0_syn_215 (1 paths)
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- reg1_syn_218.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ reg1_syn_181.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- reg1_syn_218.q[1] clk2q 0.109 r 2.138
- u_bus_top/reg0_syn_215.mi[0] (S_hs_data_reg[16]) net (fanout = 1) 0.216 r 2.354 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1274)
- u_bus_top/reg0_syn_215 path2reg0 0.095 2.449
+ reg1_syn_181.q[0] clk2q 0.109 r 2.138
+ u_bus_top/reg0_syn_217.mi[0] (S_hs_data_reg[25]) net (fanout = 1) 0.216 r 2.354 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1274)
+ u_bus_top/reg0_syn_217 path2reg0 0.095 2.449
Arrival time 2.449 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
- u_bus_top/reg0_syn_215.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
- capture clock edge 0.000 2.130
----------------------------------------------------------------------------------------------------------
- cell hold 0.061 2.191
- clock uncertainty 0.000 2.191
- clock recovergence pessimism 0.000 2.191
- Required time 2.191
----------------------------------------------------------------------------------------------------------
- Slack 0.258ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point u_bus_top/reg0_syn_209 (1 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.258 ns
- Start Point: reg1_syn_194.clk (rising edge triggered by clock S_clk)
- End Point: u_bus_top/reg0_syn_209.mi[0] (rising edge triggered by clock clk_adc)
- Clock group: clock_source
- Process: Fast
- Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- reg1_syn_194.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge 0.000 2.029
----------------------------------------------------------------------------------------------------------
- reg1_syn_194.q[0] clk2q 0.109 r 2.138
- u_bus_top/reg0_syn_209.mi[0] (S_hs_data_reg[26]) net (fanout = 1) 0.216 r 2.354 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1274)
- u_bus_top/reg0_syn_209 path2reg0 0.095 2.449
- Arrival time 2.449 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[4] 0.000 0.000
- u_bus_top/reg0_syn_209.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ u_bus_top/reg0_syn_217.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell hold 0.061 2.191
@@ -3560,14 +3794,14 @@ Paths for end point u_bus_top/reg0_syn_209 (1 paths)
Recovery checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point scan_start_diff/reg1_syn_21 (1 paths)
+Paths for end point scan_start_diff/a_ex_frame_en_reg_syn_5 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (recovery check): 161.930 ns
+ Slack (recovery check): 163.286 ns
Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc)
- End Point: scan_start_diff/reg1_syn_21.sr (rising edge triggered by clock clk_adc)
+ End Point: scan_start_diff/a_ex_frame_en_reg_syn_5.sr (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Slow
- Data Path Delay: 4.298ns (logic 0.551ns, net 3.747ns, 12% logic)
+ Data Path Delay: 3.014ns (logic 0.551ns, net 2.463ns, 18% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
@@ -3578,72 +3812,34 @@ Paths for end point scan_start_diff/reg1_syn_21 (1 paths)
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
clkubus_rstn_reg_syn_8.q[0] clk2q 0.146 r 2.422
- BUSY_MIPI_sync_flag_reg_syn_12.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 12) 2.888 r 5.310 ../../../../hg_mp/cdc/cdc_sync.v(9)
- BUSY_MIPI_sync_flag_reg_syn_12.f[0] cell (LUT2) 0.262 r 5.572
- scan_start_diff/reg1_syn_21.sr (BUSY_MIPI_sync_d0_i_syn_7) net (fanout = 11) 0.859 r 6.431 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
- scan_start_diff/reg1_syn_21 path2reg 0.143 6.574
- Arrival time 6.574 (1 lvl)
+ u_bus_top/u_local_bus_slve_cis/reg59_syn_113.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 15) 1.734 r 4.156 ../../../../hg_mp/cdc/cdc_sync.v(9)
+ u_bus_top/u_local_bus_slve_cis/reg59_syn_113.f[0] cell (LUT2) 0.262 r 4.418
+ scan_start_diff/a_ex_frame_en_reg_syn_5.sr (BUSY_MIPI_sync_d0_i_syn_8) net (fanout = 3) 0.729 r 5.147 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
+ scan_start_diff/a_ex_frame_en_reg_syn_5 path2reg 0.143 5.290
+ Arrival time 5.290 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
- scan_start_diff/reg1_syn_21.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ scan_start_diff/a_ex_frame_en_reg_syn_5.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4)
capture clock edge 166.664 168.709
---------------------------------------------------------------------------------------------------------
cell recovery -0.300 168.409
clock uncertainty -0.000 168.409
- clock recovergence pessimism 0.095 168.504
- Required time 168.504
+ clock recovergence pessimism 0.167 168.576
+ Required time 168.576
---------------------------------------------------------------------------------------------------------
- Slack 161.930ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point scan_start_diff/reg1_syn_18 (1 paths)
----------------------------------------------------------------------------------------------------------
- Slack (recovery check): 161.930 ns
- Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc)
- End Point: scan_start_diff/reg1_syn_18.sr (rising edge triggered by clock clk_adc)
- Clock group: clock_source
- Process: Slow
- Data Path Delay: 4.298ns (logic 0.551ns, net 3.747ns, 12% logic)
- Logic Levels: 1 ( LUT2=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[4] 0.000 0.000
- clkubus_rstn_reg_syn_8.clk (exdev_ctl_a/clk_adc) net 2.276 2.276 ../../../../hg_mp/fe/exdev_ctl.v(4)
- launch clock edge 0.000 2.276
----------------------------------------------------------------------------------------------------------
- clkubus_rstn_reg_syn_8.q[0] clk2q 0.146 r 2.422
- BUSY_MIPI_sync_flag_reg_syn_12.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 12) 2.888 r 5.310 ../../../../hg_mp/cdc/cdc_sync.v(9)
- BUSY_MIPI_sync_flag_reg_syn_12.f[0] cell (LUT2) 0.262 r 5.572
- scan_start_diff/reg1_syn_18.sr (BUSY_MIPI_sync_d0_i_syn_7) net (fanout = 11) 0.859 r 6.431 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
- scan_start_diff/reg1_syn_18 path2reg 0.143 6.574
- Arrival time 6.574 (1 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[4] 0.000 0.000
- scan_start_diff/reg1_syn_18.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4)
- capture clock edge 166.664 168.709
----------------------------------------------------------------------------------------------------------
- cell recovery -0.300 168.409
- clock uncertainty -0.000 168.409
- clock recovergence pessimism 0.095 168.504
- Required time 168.504
----------------------------------------------------------------------------------------------------------
- Slack 161.930ns
+ Slack 163.286ns
---------------------------------------------------------------------------------------------------------
Paths for end point scan_start_diff/reg2_syn_19 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (recovery check): 161.953 ns
+ Slack (recovery check): 163.371 ns
Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc)
End Point: scan_start_diff/reg2_syn_19.sr (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Slow
- Data Path Delay: 4.275ns (logic 0.551ns, net 3.724ns, 12% logic)
+ Data Path Delay: 2.929ns (logic 0.494ns, net 2.435ns, 16% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
@@ -3654,11 +3850,11 @@ Paths for end point scan_start_diff/reg2_syn_19 (1 paths)
launch clock edge 0.000 2.276
---------------------------------------------------------------------------------------------------------
clkubus_rstn_reg_syn_8.q[0] clk2q 0.146 r 2.422
- BUSY_MIPI_sync_flag_reg_syn_12.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 12) 2.888 r 5.310 ../../../../hg_mp/cdc/cdc_sync.v(9)
- BUSY_MIPI_sync_flag_reg_syn_12.f[0] cell (LUT2) 0.262 r 5.572
- scan_start_diff/reg2_syn_19.sr (BUSY_MIPI_sync_d0_i_syn_7) net (fanout = 11) 0.836 r 6.408 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
- scan_start_diff/reg2_syn_19 path2reg 0.143 6.551
- Arrival time 6.551 (1 lvl)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 15) 1.524 r 3.946 ../../../../hg_mp/cdc/cdc_sync.v(9)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.205 r 4.151
+ scan_start_diff/reg2_syn_19.sr (BUSY_MIPI_sync_d0_i_syn_6) net (fanout = 9) 0.911 r 5.062 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
+ scan_start_diff/reg2_syn_19 path2reg 0.143 5.205
+ Arrival time 5.205 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
@@ -3667,23 +3863,61 @@ Paths for end point scan_start_diff/reg2_syn_19 (1 paths)
---------------------------------------------------------------------------------------------------------
cell recovery -0.300 168.409
clock uncertainty -0.000 168.409
- clock recovergence pessimism 0.095 168.504
- Required time 168.504
+ clock recovergence pessimism 0.167 168.576
+ Required time 168.576
---------------------------------------------------------------------------------------------------------
- Slack 161.953ns
+ Slack 163.371ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point scan_start_diff/a_ex_frame_reg_syn_5 (1 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (recovery check): 163.489 ns
+ Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc)
+ End Point: scan_start_diff/a_ex_frame_reg_syn_5.sr (rising edge triggered by clock clk_adc)
+ Clock group: clock_source
+ Process: Slow
+ Data Path Delay: 2.811ns (logic 0.494ns, net 2.317ns, 17% logic)
+ Logic Levels: 1 ( LUT2=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[4] 0.000 0.000
+ clkubus_rstn_reg_syn_8.clk (exdev_ctl_a/clk_adc) net 2.276 2.276 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ launch clock edge 0.000 2.276
+---------------------------------------------------------------------------------------------------------
+ clkubus_rstn_reg_syn_8.q[0] clk2q 0.146 r 2.422
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 15) 1.524 r 3.946 ../../../../hg_mp/cdc/cdc_sync.v(9)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.205 r 4.151
+ scan_start_diff/a_ex_frame_reg_syn_5.sr (BUSY_MIPI_sync_d0_i_syn_6) net (fanout = 9) 0.793 r 4.944 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
+ scan_start_diff/a_ex_frame_reg_syn_5 path2reg 0.143 5.087
+ Arrival time 5.087 (1 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[4] 0.000 0.000
+ scan_start_diff/a_ex_frame_reg_syn_5.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ capture clock edge 166.664 168.709
+---------------------------------------------------------------------------------------------------------
+ cell recovery -0.300 168.409
+ clock uncertainty -0.000 168.409
+ clock recovergence pessimism 0.167 168.576
+ Required time 168.576
+---------------------------------------------------------------------------------------------------------
+ Slack 163.489ns
---------------------------------------------------------------------------------------------------------
Removal checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point scan_start_diff/a_ex_frame_en_reg_syn_4 (1 paths)
+Paths for end point scan_start_diff/reg1_syn_18 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (removal check): 2.469 ns
+ Slack (removal check): 1.456 ns
Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc)
- End Point: scan_start_diff/a_ex_frame_en_reg_syn_4.sr (rising edge triggered by clock clk_adc)
+ End Point: scan_start_diff/reg1_syn_18.sr (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Fast
- Data Path Delay: 2.830ns (logic 0.375ns, net 2.455ns, 13% logic)
+ Data Path Delay: 1.754ns (logic 0.322ns, net 1.432ns, 18% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
@@ -3694,34 +3928,34 @@ Paths for end point scan_start_diff/a_ex_frame_en_reg_syn_4 (1 paths)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
clkubus_rstn_reg_syn_8.q[0] clk2q 0.109 r 2.047
- BUSY_MIPI_sync_flag_reg_syn_12.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 12) 2.088 r 4.135 ../../../../hg_mp/cdc/cdc_sync.v(9)
- BUSY_MIPI_sync_flag_reg_syn_12.f[0] cell (LUT2) 0.179 r 4.314
- scan_start_diff/a_ex_frame_en_reg_syn_4.sr (BUSY_MIPI_sync_d0_i_syn_7) net (fanout = 11) 0.367 r 4.681 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
- scan_start_diff/a_ex_frame_en_reg_syn_4 path2reg 0.087 4.768
- Arrival time 4.768 (1 lvl)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 15) 1.091 r 3.138 ../../../../hg_mp/cdc/cdc_sync.v(9)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.126 r 3.264
+ scan_start_diff/reg1_syn_18.sr (BUSY_MIPI_sync_d0_i_syn_6) net (fanout = 9) 0.341 r 3.605 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
+ scan_start_diff/reg1_syn_18 path2reg 0.087 3.692
+ Arrival time 3.692 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
- scan_start_diff/a_ex_frame_en_reg_syn_4.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ scan_start_diff/reg1_syn_18.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell removal 0.253 2.383
clock uncertainty 0.000 2.383
- clock recovergence pessimism -0.084 2.299
- Required time 2.299
+ clock recovergence pessimism -0.147 2.236
+ Required time 2.236
---------------------------------------------------------------------------------------------------------
- Slack 2.469ns
+ Slack 1.456ns
---------------------------------------------------------------------------------------------------------
-Paths for end point scan_start_diff/a_frame_pad_rog_reg_syn_5 (1 paths)
+Paths for end point scan_start_diff/reg1_syn_21 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (removal check): 2.618 ns
+ Slack (removal check): 1.562 ns
Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc)
- End Point: scan_start_diff/a_frame_pad_rog_reg_syn_5.sr (rising edge triggered by clock clk_adc)
+ End Point: scan_start_diff/reg1_syn_21.sr (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Fast
- Data Path Delay: 2.979ns (logic 0.375ns, net 2.604ns, 12% logic)
+ Data Path Delay: 1.860ns (logic 0.322ns, net 1.538ns, 17% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
@@ -3732,34 +3966,34 @@ Paths for end point scan_start_diff/a_frame_pad_rog_reg_syn_5 (1 paths)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
clkubus_rstn_reg_syn_8.q[0] clk2q 0.109 r 2.047
- BUSY_MIPI_sync_flag_reg_syn_12.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 12) 2.088 r 4.135 ../../../../hg_mp/cdc/cdc_sync.v(9)
- BUSY_MIPI_sync_flag_reg_syn_12.f[0] cell (LUT2) 0.179 r 4.314
- scan_start_diff/a_frame_pad_rog_reg_syn_5.sr (BUSY_MIPI_sync_d0_i_syn_7) net (fanout = 11) 0.516 r 4.830 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
- scan_start_diff/a_frame_pad_rog_reg_syn_5 path2reg 0.087 4.917
- Arrival time 4.917 (1 lvl)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 15) 1.091 r 3.138 ../../../../hg_mp/cdc/cdc_sync.v(9)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.126 r 3.264
+ scan_start_diff/reg1_syn_21.sr (BUSY_MIPI_sync_d0_i_syn_6) net (fanout = 9) 0.447 r 3.711 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
+ scan_start_diff/reg1_syn_21 path2reg 0.087 3.798
+ Arrival time 3.798 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
- scan_start_diff/a_frame_pad_rog_reg_syn_5.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ scan_start_diff/reg1_syn_21.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell removal 0.253 2.383
clock uncertainty 0.000 2.383
- clock recovergence pessimism -0.084 2.299
- Required time 2.299
+ clock recovergence pessimism -0.147 2.236
+ Required time 2.236
---------------------------------------------------------------------------------------------------------
- Slack 2.618ns
+ Slack 1.562ns
---------------------------------------------------------------------------------------------------------
-Paths for end point scan_start_diff/reg2_syn_19 (1 paths)
+Paths for end point scan_start_diff/enable_from_arm_rog_reg_syn_5 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (removal check): 2.681 ns
+ Slack (removal check): 1.579 ns
Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc)
- End Point: scan_start_diff/reg2_syn_19.sr (rising edge triggered by clock clk_adc)
+ End Point: scan_start_diff/enable_from_arm_rog_reg_syn_5.sr (rising edge triggered by clock clk_adc)
Clock group: clock_source
Process: Fast
- Data Path Delay: 3.042ns (logic 0.375ns, net 2.667ns, 12% logic)
+ Data Path Delay: 1.877ns (logic 0.322ns, net 1.555ns, 17% logic)
Logic Levels: 1 ( LUT2=1 )
Point Type Incr Path Info
@@ -3770,23 +4004,23 @@ Paths for end point scan_start_diff/reg2_syn_19 (1 paths)
launch clock edge 0.000 1.938
---------------------------------------------------------------------------------------------------------
clkubus_rstn_reg_syn_8.q[0] clk2q 0.109 r 2.047
- BUSY_MIPI_sync_flag_reg_syn_12.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 12) 2.088 r 4.135 ../../../../hg_mp/cdc/cdc_sync.v(9)
- BUSY_MIPI_sync_flag_reg_syn_12.f[0] cell (LUT2) 0.179 r 4.314
- scan_start_diff/reg2_syn_19.sr (BUSY_MIPI_sync_d0_i_syn_7) net (fanout = 11) 0.579 r 4.893 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
- scan_start_diff/reg2_syn_19 path2reg 0.087 4.980
- Arrival time 4.980 (1 lvl)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 15) 1.091 r 3.138 ../../../../hg_mp/cdc/cdc_sync.v(9)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.126 r 3.264
+ scan_start_diff/enable_from_arm_rog_reg_syn_5.sr (BUSY_MIPI_sync_d0_i_syn_6) net (fanout = 9) 0.464 r 3.728 ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
+ scan_start_diff/enable_from_arm_rog_reg_syn_5 path2reg 0.087 3.815
+ Arrival time 3.815 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[4] 0.000 0.000
- scan_start_diff/reg2_syn_19.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
+ scan_start_diff/enable_from_arm_rog_reg_syn_5.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4)
capture clock edge 0.000 2.130
---------------------------------------------------------------------------------------------------------
cell removal 0.253 2.383
clock uncertainty 0.000 2.383
- clock recovergence pessimism -0.084 2.299
- Required time 2.299
+ clock recovergence pessimism -0.147 2.236
+ Required time 2.236
---------------------------------------------------------------------------------------------------------
- Slack 2.681ns
+ Slack 1.579ns
---------------------------------------------------------------------------------------------------------
@@ -3795,20 +4029,20 @@ Paths for end point scan_start_diff/reg2_syn_19 (1 paths)
Timing constraint: clock: S_clk_x2
Clock = S_clk_x2, period 4.629ns, rising at 0ns, falling at 2.314ns
-80 endpoints analyzed totally, and 146 paths analyzed
+78 endpoints analyzed totally, and 144 paths analyzed
0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 2.748ns
+Minimum period is 2.179ns
---------------------------------------------------------------------------------------------------------
-Paths for end point debug[4]_syn_1 (1 paths)
+Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 (2 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 1.881 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.clk (rising edge triggered by clock S_clk)
- End Point: debug[4]_syn_1.do[0] (rising edge triggered by clock S_clk_x2)
+ Slack (setup check): 2.450 ns
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add12_syn_69.clk (rising edge triggered by clock S_clk)
+ End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.b[0] (rising edge triggered by clock S_clk_x2)
Clock group: clock_source
Process: Slow
- Data Path Delay: 2.255ns (logic 0.146ns, net 2.109ns, 6% logic)
- Logic Levels: 0
+ Data Path Delay: 1.819ns (logic 0.695ns, net 1.124ns, 38% logic)
+ Logic Levels: 1 ( LUT3=1 )
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
@@ -3816,33 +4050,31 @@ Paths for end point debug[4]_syn_1 (1 paths)
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add12_syn_69.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.q[0] clk2q 0.146 r 2.556
- debug[4]_syn_1.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_1d) net (fanout = 3) 2.109 r 4.665 encrypted_text(0)
- debug[4]_syn_1 path2reg 0.000 4.665
- Arrival time 4.665 (0 lvl)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add12_syn_69.q[1] clk2q 0.146 r 2.556
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.b[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[1]) net (fanout = 1) 1.124 r 3.680 encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 path2reg0 (LUT3) 0.549 4.229
+ Arrival time 4.229 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- debug[4]_syn_1.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 1.978 1.978 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- capture clock edge 4.629 6.607
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ capture clock edge 4.629 6.795
---------------------------------------------------------------------------------------------------------
- cell setup -0.061 6.546
- clock uncertainty -0.000 6.546
- clock recovergence pessimism 0.000 6.546
- Required time 6.546
+ cell setup -0.116 6.679
+ clock uncertainty -0.000 6.679
+ clock recovergence pessimism 0.000 6.679
+ Required time 6.679
---------------------------------------------------------------------------------------------------------
- Slack 1.881ns
+ Slack 2.450ns
---------------------------------------------------------------------------------------------------------
-Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2 (2 paths)
----------------------------------------------------------------------------------------------------------
Slack (setup check): 2.457 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47_syn_2.clk (rising edge triggered by clock S_clk)
- End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.c[1] (rising edge triggered by clock S_clk_x2)
+ Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add29_syn_70.clk (rising edge triggered by clock S_clk)
+ End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.c[0] (rising edge triggered by clock S_clk_x2)
Clock group: clock_source
Process: Slow
Data Path Delay: 1.812ns (logic 0.612ns, net 1.200ns, 33% logic)
@@ -3854,17 +4086,17 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapp
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add29_syn_70.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47_syn_2.q[0] clk2q 0.146 r 2.556
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.c[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[7]) net (fanout = 1) 1.200 r 3.756 encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2 path2reg1 (LUT3) 0.466 4.222
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add29_syn_70.q[0] clk2q 0.146 r 2.556
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.c[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[5]) net (fanout = 1) 1.200 r 3.756 encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 path2reg0 (LUT3) 0.466 4.222
Arrival time 4.222 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
capture clock edge 4.629 6.795
---------------------------------------------------------------------------------------------------------
cell setup -0.116 6.679
@@ -3876,9 +4108,11 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapp
---------------------------------------------------------------------------------------------------------
+Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2 (2 paths)
+---------------------------------------------------------------------------------------------------------
Slack (setup check): 2.518 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.clk (rising edge triggered by clock S_clk)
- End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.b[1] (rising edge triggered by clock S_clk_x2)
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk (rising edge triggered by clock S_clk)
+ End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.b[1] (rising edge triggered by clock S_clk_x2)
Clock group: clock_source
Process: Slow
Data Path Delay: 1.751ns (logic 0.695ns, net 1.056ns, 39% logic)
@@ -3890,17 +4124,17 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapp
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.q[1] clk2q 0.146 r 2.556
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.b[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3]) net (fanout = 1) 1.056 r 3.612 encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2 path2reg1 (LUT3) 0.549 4.161
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.q[1] clk2q 0.146 r 2.556
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.b[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3]) net (fanout = 1) 1.056 r 3.612 encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2 path2reg1 (LUT3) 0.549 4.161
Arrival time 4.161 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
capture clock edge 4.629 6.795
---------------------------------------------------------------------------------------------------------
cell setup -0.116 6.679
@@ -3912,50 +4146,12 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapp
---------------------------------------------------------------------------------------------------------
-Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2 (2 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check): 2.487 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.clk (rising edge triggered by clock S_clk)
- End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.b[1] (rising edge triggered by clock S_clk_x2)
- Clock group: clock_source
- Process: Slow
- Data Path Delay: 1.782ns (logic 0.597ns, net 1.185ns, 33% logic)
- Logic Levels: 1 ( LUT3=1 )
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge 0.000 2.410
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.q[1] clk2q 0.146 r 2.556
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.b[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3]) net (fanout = 1) 1.185 r 3.741 encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2 path2reg1 (LUT3) 0.451 4.192
- Arrival time 4.192 (1 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- capture clock edge 4.629 6.795
----------------------------------------------------------------------------------------------------------
- cell setup -0.116 6.679
- clock uncertainty -0.000 6.679
- clock recovergence pessimism 0.000 6.679
- Required time 6.679
----------------------------------------------------------------------------------------------------------
- Slack 2.487ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check): 2.831 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47_syn_2.clk (rising edge triggered by clock S_clk)
+ Slack (setup check): 2.611 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk (rising edge triggered by clock S_clk)
End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.c[1] (rising edge triggered by clock S_clk_x2)
Clock group: clock_source
Process: Slow
- Data Path Delay: 1.438ns (logic 0.506ns, net 0.932ns, 35% logic)
+ Data Path Delay: 1.658ns (logic 0.612ns, net 1.046ns, 36% logic)
Logic Levels: 1 ( LUT3=1 )
Point Type Incr Path Info
@@ -3964,13 +4160,13 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapp
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47_syn_2.q[0] clk2q 0.146 r 2.556
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.c[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[7]) net (fanout = 1) 0.932 r 3.488 encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2 path2reg1 (LUT3) 0.360 3.848
- Arrival time 3.848 (1 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.q[0] clk2q 0.146 r 2.556
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.c[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[7]) net (fanout = 1) 1.046 r 3.602 encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2 path2reg1 (LUT3) 0.466 4.068
+ Arrival time 4.068 (1 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
@@ -3982,96 +4178,94 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapp
clock recovergence pessimism 0.000 6.679
Required time 6.679
---------------------------------------------------------------------------------------------------------
- Slack 2.831ns
+ Slack 2.611ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2 (2 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check): 2.518 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_35_syn_2.clk (rising edge triggered by clock S_clk)
+ End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.b[0] (rising edge triggered by clock S_clk_x2)
+ Clock group: clock_source
+ Process: Slow
+ Data Path Delay: 1.751ns (logic 0.695ns, net 1.056ns, 39% logic)
+ Logic Levels: 1 ( LUT3=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_35_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge 0.000 2.410
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_35_syn_2.q[1] clk2q 0.146 r 2.556
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.b[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0]) net (fanout = 1) 1.056 r 3.612 encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2 path2reg0 (LUT3) 0.549 4.161
+ Arrival time 4.161 (1 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ capture clock edge 4.629 6.795
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.116 6.679
+ clock uncertainty -0.000 6.679
+ clock recovergence pessimism 0.000 6.679
+ Required time 6.679
+---------------------------------------------------------------------------------------------------------
+ Slack 2.518ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check): 2.761 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_43_syn_2.clk (rising edge triggered by clock S_clk)
+ End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.c[0] (rising edge triggered by clock S_clk_x2)
+ Clock group: clock_source
+ Process: Slow
+ Data Path Delay: 1.508ns (logic 0.612ns, net 0.896ns, 40% logic)
+ Logic Levels: 1 ( LUT3=1 )
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_43_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge 0.000 2.410
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_43_syn_2.q[1] clk2q 0.146 r 2.556
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.c[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4]) net (fanout = 1) 0.896 r 3.452 encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2 path2reg0 (LUT3) 0.466 3.918
+ Arrival time 3.918 (1 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ capture clock edge 4.629 6.795
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.116 6.679
+ clock uncertainty -0.000 6.679
+ clock recovergence pessimism 0.000 6.679
+ Required time 6.679
+---------------------------------------------------------------------------------------------------------
+ Slack 2.761ns
---------------------------------------------------------------------------------------------------------
Hold checks:
---------------------------------------------------------------------------------------------------------
-Paths for end point exdev_ctl_a/u_gen_sp/add2_syn_98 (1 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.167 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.clk (rising edge triggered by clock S_clk)
- End Point: exdev_ctl_a/u_gen_sp/add2_syn_98.mi[0] (rising edge triggered by clock S_clk_x2)
- Clock group: clock_source
- Process: Fast
- Data Path Delay: 0.429ns (logic 0.204ns, net 0.225ns, 47% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge 0.000 2.029
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.q[0] clk2q 0.109 r 2.138
- exdev_ctl_a/u_gen_sp/add2_syn_98.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_en) net (fanout = 2) 0.225 r 2.363 encrypted_text(0)
- exdev_ctl_a/u_gen_sp/add2_syn_98 path2reg0 0.095 2.458
- Arrival time 2.458 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[1] 0.000 0.000
- exdev_ctl_a/u_gen_sp/add2_syn_98.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- capture clock edge 0.000 2.230
----------------------------------------------------------------------------------------------------------
- cell hold 0.061 2.291
- clock uncertainty 0.000 2.291
- clock recovergence pessimism 0.000 2.291
- Required time 2.291
----------------------------------------------------------------------------------------------------------
- Slack 0.167ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[67]_syn_8 (1 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.190 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[77]_syn_23.clk (rising edge triggered by clock S_clk)
- End Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[67]_syn_8.mi[0] (rising edge triggered by clock S_clk_x2)
- Clock group: clock_source
- Process: Fast
- Data Path Delay: 0.452ns (logic 0.204ns, net 0.248ns, 45% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[0] 0.000 0.000
- u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[77]_syn_23.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge 0.000 2.029
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[77]_syn_23.q[0] clk2q 0.109 r 2.138
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[67]_syn_8.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d) net (fanout = 5) 0.248 r 2.386 encrypted_text(0)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[67]_syn_8 path2reg0 0.095 2.481
- Arrival time 2.481 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[1] 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[67]_syn_8.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- capture clock edge 0.000 2.230
----------------------------------------------------------------------------------------------------------
- cell hold 0.061 2.291
- clock uncertainty 0.000 2.291
- clock recovergence pessimism 0.000 2.291
- Required time 2.291
----------------------------------------------------------------------------------------------------------
- Slack 0.190ns
-
----------------------------------------------------------------------------------------------------------
-
Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5 (1 paths)
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.264 ns
- Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/adc_addr_gen/[5]$ch_addr_gen/add0_syn_62.clk (rising edge triggered by clock S_clk)
+ Slack (hold check): 0.158 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6_syn_2.clk (rising edge triggered by clock S_clk)
End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5.mi[0] (rising edge triggered by clock S_clk_x2)
Clock group: clock_source
Process: Fast
- Data Path Delay: 0.526ns (logic 0.204ns, net 0.322ns, 38% logic)
+ Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic)
Logic Levels: 0
Point Type Incr Path Info
@@ -4080,13 +4274,13 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapp
u_pll/pll_inst.clkc[0] 0.000 0.000
u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/adc_addr_gen/[5]$ch_addr_gen/add0_syn_62.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/adc_addr_gen/[5]$ch_addr_gen/add0_syn_62.q[0] clk2q 0.109 r 2.138
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d) net (fanout = 1) 0.322 r 2.460 encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5 path2reg0 0.095 2.555
- Arrival time 2.555 (0 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6_syn_2.q[0] clk2q 0.109 r 2.138
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d) net (fanout = 1) 0.216 r 2.354 encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5 path2reg0 0.095 2.449
+ Arrival time 2.449 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
@@ -4098,7 +4292,83 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapp
clock recovergence pessimism 0.000 2.291
Required time 2.291
---------------------------------------------------------------------------------------------------------
- Slack 0.264ns
+ Slack 0.158ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5 (1 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.274 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.clk (rising edge triggered by clock S_clk)
+ End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.mi[1] (rising edge triggered by clock S_clk_x2)
+ Clock group: clock_source
+ Process: Fast
+ Data Path Delay: 0.536ns (logic 0.204ns, net 0.332ns, 38% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge 0.000 2.029
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.q[1] clk2q 0.109 r 2.138
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.mi[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d) net (fanout = 1) 0.332 r 2.470 encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5 path2reg1 0.095 2.565
+ Arrival time 2.565 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ capture clock edge 0.000 2.230
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.061 2.291
+ clock uncertainty 0.000 2.291
+ clock recovergence pessimism 0.000 2.291
+ Required time 2.291
+---------------------------------------------------------------------------------------------------------
+ Slack 0.274ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5 (1 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.274 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.clk (rising edge triggered by clock S_clk)
+ End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.mi[0] (rising edge triggered by clock S_clk_x2)
+ Clock group: clock_source
+ Process: Fast
+ Data Path Delay: 0.536ns (logic 0.204ns, net 0.332ns, 38% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[0] 0.000 0.000
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge 0.000 2.029
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.q[0] clk2q 0.109 r 2.138
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_1d) net (fanout = 2) 0.332 r 2.470 encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5 path2reg0 0.095 2.565
+ Arrival time 2.565 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ capture clock edge 0.000 2.230
+---------------------------------------------------------------------------------------------------------
+ cell hold 0.061 2.291
+ clock uncertainty 0.000 2.291
+ clock recovergence pessimism 0.000 2.291
+ Required time 2.291
+---------------------------------------------------------------------------------------------------------
+ Slack 0.274ns
---------------------------------------------------------------------------------------------------------
@@ -4109,34 +4379,34 @@ Clock = S_clk_x4, period 2.314ns, rising at 0ns, falling at 1.157ns
8 endpoints analyzed totally, and 32 paths analyzed
0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 1.391ns
+Minimum period is 1.563ns
---------------------------------------------------------------------------------------------------------
-Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
+Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 0.923 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[1]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
+ Slack (setup check): 0.751 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[3]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
Clock group: clock_source
Process: Slow
- Data Path Delay: 0.777ns (logic 0.146ns, net 0.631ns, 18% logic)
+ Data Path Delay: 0.949ns (logic 0.146ns, net 0.803ns, 15% logic)
Logic Levels: 0
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q 0.146 r 2.556
- O_data_hs_p[1]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.631 r 3.187 encrypted_text(0)
- O_data_hs_p[1]_syn_2 path2reg 0.000 3.187
- Arrival time 3.187 (0 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[1] clk2q 0.146 r 2.556
+ O_data_hs_p[3]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.803 r 3.359 encrypted_text(0)
+ O_data_hs_p[3]_syn_2 path2reg 0.000 3.359
+ Arrival time 3.359 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ O_data_hs_p[3]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
capture clock edge 2.314 4.171
---------------------------------------------------------------------------------------------------------
cell setup -0.061 4.110
@@ -4144,33 +4414,33 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
clock recovergence pessimism 0.000 4.110
Required time 4.110
---------------------------------------------------------------------------------------------------------
- Slack 0.923ns
+ Slack 0.751ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 1.035 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[1]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
+ Slack (setup check): 0.751 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[3]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
Clock group: clock_source
Process: Slow
- Data Path Delay: 0.665ns (logic 0.146ns, net 0.519ns, 21% logic)
+ Data Path Delay: 0.949ns (logic 0.146ns, net 0.803ns, 15% logic)
Logic Levels: 0
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[0] clk2q 0.146 r 2.556
- O_data_hs_p[1]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.519 r 3.075 encrypted_text(0)
- O_data_hs_p[1]_syn_2 path2reg 0.000 3.075
- Arrival time 3.075 (0 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.146 r 2.556
+ O_data_hs_p[3]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.803 r 3.359 encrypted_text(0)
+ O_data_hs_p[3]_syn_2 path2reg 0.000 3.359
+ Arrival time 3.359 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ O_data_hs_p[3]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
capture clock edge 2.314 4.171
---------------------------------------------------------------------------------------------------------
cell setup -0.061 4.110
@@ -4178,33 +4448,33 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
clock recovergence pessimism 0.000 4.110
Required time 4.110
---------------------------------------------------------------------------------------------------------
- Slack 1.035ns
+ Slack 0.751ns
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 1.078 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[1]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
+ Slack (setup check): 0.952 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[3]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
Clock group: clock_source
Process: Slow
- Data Path Delay: 0.622ns (logic 0.146ns, net 0.476ns, 23% logic)
+ Data Path Delay: 0.748ns (logic 0.146ns, net 0.602ns, 19% logic)
Logic Levels: 0
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.146 r 2.556
- O_data_hs_p[1]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.476 r 3.032 encrypted_text(0)
- O_data_hs_p[1]_syn_2 path2reg 0.000 3.032
- Arrival time 3.032 (0 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q 0.146 r 2.556
+ O_data_hs_p[3]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.602 r 3.158 encrypted_text(0)
+ O_data_hs_p[3]_syn_2 path2reg 0.000 3.158
+ Arrival time 3.158 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ O_data_hs_p[3]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
capture clock edge 2.314 4.171
---------------------------------------------------------------------------------------------------------
cell setup -0.061 4.110
@@ -4212,15 +4482,83 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
clock recovergence pessimism 0.000 4.110
Required time 4.110
---------------------------------------------------------------------------------------------------------
- Slack 1.078ns
+ Slack 0.952ns
---------------------------------------------------------------------------------------------------------
Paths for end point O_data_hs_p[0]_syn_2 (4 paths)
---------------------------------------------------------------------------------------------------------
+ Slack (setup check): 1.028 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[0]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
+ Clock group: clock_source
+ Process: Slow
+ Data Path Delay: 0.672ns (logic 0.146ns, net 0.526ns, 21% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge 0.000 2.410
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[1] clk2q 0.146 r 2.556
+ O_data_hs_p[0]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.526 r 3.082 encrypted_text(0)
+ O_data_hs_p[0]_syn_2 path2reg 0.000 3.082
+ Arrival time 3.082 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[2] 0.000 0.000
+ O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge 2.314 4.171
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.061 4.110
+ clock uncertainty -0.000 4.110
+ clock recovergence pessimism 0.000 4.110
+ Required time 4.110
+---------------------------------------------------------------------------------------------------------
+ Slack 1.028ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check): 1.028 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[0]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
+ Clock group: clock_source
+ Process: Slow
+ Data Path Delay: 0.672ns (logic 0.146ns, net 0.526ns, 21% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge 0.000 2.410
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.146 r 2.556
+ O_data_hs_p[0]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.526 r 3.082 encrypted_text(0)
+ O_data_hs_p[0]_syn_2 path2reg 0.000 3.082
+ Arrival time 3.082 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[2] 0.000 0.000
+ O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge 2.314 4.171
+---------------------------------------------------------------------------------------------------------
+ cell setup -0.061 4.110
+ clock uncertainty -0.000 4.110
+ clock recovergence pessimism 0.000 4.110
+ Required time 4.110
+---------------------------------------------------------------------------------------------------------
+ Slack 1.028ns
+
+---------------------------------------------------------------------------------------------------------
+
Slack (setup check): 1.072 ns
Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[0]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
+ End Point: O_data_hs_p[0]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
Clock group: clock_source
Process: Slow
Data Path Delay: 0.628ns (logic 0.146ns, net 0.482ns, 23% logic)
@@ -4233,8 +4571,8 @@ Paths for end point O_data_hs_p[0]_syn_2 (4 paths)
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q 0.146 r 2.556
- O_data_hs_p[0]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.482 r 3.038 encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q 0.146 r 2.556
+ O_data_hs_p[0]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.482 r 3.038 encrypted_text(0)
O_data_hs_p[0]_syn_2 path2reg 0.000 3.038
Arrival time 3.038 (0 lvl)
@@ -4252,79 +4590,11 @@ Paths for end point O_data_hs_p[0]_syn_2 (4 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 1.075 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[0]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
- Clock group: clock_source
- Process: Slow
- Data Path Delay: 0.625ns (logic 0.146ns, net 0.479ns, 23% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge 0.000 2.410
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q 0.146 r 2.556
- O_data_hs_p[0]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.479 r 3.035 encrypted_text(0)
- O_data_hs_p[0]_syn_2 path2reg 0.000 3.035
- Arrival time 3.035 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge 2.314 4.171
----------------------------------------------------------------------------------------------------------
- cell setup -0.061 4.110
- clock uncertainty -0.000 4.110
- clock recovergence pessimism 0.000 4.110
- Required time 4.110
----------------------------------------------------------------------------------------------------------
- Slack 1.075ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check): 1.075 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[0]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
- Clock group: clock_source
- Process: Slow
- Data Path Delay: 0.625ns (logic 0.146ns, net 0.479ns, 23% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge 0.000 2.410
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.146 r 2.556
- O_data_hs_p[0]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.479 r 3.035 encrypted_text(0)
- O_data_hs_p[0]_syn_2 path2reg 0.000 3.035
- Arrival time 3.035 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge 2.314 4.171
----------------------------------------------------------------------------------------------------------
- cell setup -0.061 4.110
- clock uncertainty -0.000 4.110
- clock recovergence pessimism 0.000 4.110
- Required time 4.110
----------------------------------------------------------------------------------------------------------
- Slack 1.075ns
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
+Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
---------------------------------------------------------------------------------------------------------
Slack (setup check): 1.072 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[3]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[1]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
Clock group: clock_source
Process: Slow
Data Path Delay: 0.628ns (logic 0.146ns, net 0.482ns, 23% logic)
@@ -4334,17 +4604,17 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[1] clk2q 0.146 r 2.556
- O_data_hs_p[3]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.482 r 3.038 encrypted_text(0)
- O_data_hs_p[3]_syn_2 path2reg 0.000 3.038
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[1] clk2q 0.146 r 2.556
+ O_data_hs_p[1]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.482 r 3.038 encrypted_text(0)
+ O_data_hs_p[1]_syn_2 path2reg 0.000 3.038
Arrival time 3.038 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[3]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
capture clock edge 2.314 4.171
---------------------------------------------------------------------------------------------------------
cell setup -0.061 4.110
@@ -4357,8 +4627,8 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
---------------------------------------------------------------------------------------------------------
Slack (setup check): 1.072 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[3]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[1]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
Clock group: clock_source
Process: Slow
Data Path Delay: 0.628ns (logic 0.146ns, net 0.482ns, 23% logic)
@@ -4368,17 +4638,17 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.146 r 2.556
- O_data_hs_p[3]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.482 r 3.038 encrypted_text(0)
- O_data_hs_p[3]_syn_2 path2reg 0.000 3.038
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.146 r 2.556
+ O_data_hs_p[1]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.482 r 3.038 encrypted_text(0)
+ O_data_hs_p[1]_syn_2 path2reg 0.000 3.038
Arrival time 3.038 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[3]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
capture clock edge 2.314 4.171
---------------------------------------------------------------------------------------------------------
cell setup -0.061 4.110
@@ -4390,29 +4660,29 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
---------------------------------------------------------------------------------------------------------
- Slack (setup check): 1.075 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[3]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
+ Slack (setup check): 1.072 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[1]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
Clock group: clock_source
Process: Slow
- Data Path Delay: 0.625ns (logic 0.146ns, net 0.479ns, 23% logic)
+ Data Path Delay: 0.628ns (logic 0.146ns, net 0.482ns, 23% logic)
Logic Levels: 0
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q 0.146 r 2.556
- O_data_hs_p[3]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.479 r 3.035 encrypted_text(0)
- O_data_hs_p[3]_syn_2 path2reg 0.000 3.035
- Arrival time 3.035 (0 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q 0.146 r 2.556
+ O_data_hs_p[1]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.482 r 3.038 encrypted_text(0)
+ O_data_hs_p[1]_syn_2 path2reg 0.000 3.038
+ Arrival time 3.038 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[3]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
capture clock edge 2.314 4.171
---------------------------------------------------------------------------------------------------------
cell setup -0.061 4.110
@@ -4420,7 +4690,7 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
clock recovergence pessimism 0.000 4.110
Required time 4.110
---------------------------------------------------------------------------------------------------------
- Slack 1.075ns
+ Slack 1.072ns
---------------------------------------------------------------------------------------------------------
@@ -4428,12 +4698,12 @@ Hold checks:
---------------------------------------------------------------------------------------------------------
Paths for end point O_data_hs_p[2]_syn_2 (4 paths)
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.392 ns
+ Slack (hold check): 0.507 ns
Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
End Point: O_data_hs_p[2]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
Clock group: clock_source
Process: Fast
- Data Path Delay: 0.325ns (logic 0.109ns, net 0.216ns, 33% logic)
+ Data Path Delay: 0.440ns (logic 0.109ns, net 0.331ns, 24% logic)
Logic Levels: 0
Point Type Incr Path Info
@@ -4444,41 +4714,7 @@ Paths for end point O_data_hs_p[2]_syn_2 (4 paths)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q 0.109 r 2.138
- O_data_hs_p[2]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.216 r 2.354 encrypted_text(0)
- O_data_hs_p[2]_syn_2 path2reg 0.000 2.354
- Arrival time 2.354 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[2]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge 0.000 1.965
----------------------------------------------------------------------------------------------------------
- cell hold -0.003 1.962
- clock uncertainty 0.000 1.962
- clock recovergence pessimism 0.000 1.962
- Required time 1.962
----------------------------------------------------------------------------------------------------------
- Slack 0.392ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check): 0.507 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[2]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
- Clock group: clock_source
- Process: Fast
- Data Path Delay: 0.440ns (logic 0.109ns, net 0.331ns, 24% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge 0.000 2.029
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[1] clk2q 0.109 r 2.138
- O_data_hs_p[2]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.331 r 2.469 encrypted_text(0)
+ O_data_hs_p[2]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.331 r 2.469 encrypted_text(0)
O_data_hs_p[2]_syn_2 path2reg 0.000 2.469
Arrival time 2.469 (0 lvl)
@@ -4497,7 +4733,7 @@ Paths for end point O_data_hs_p[2]_syn_2 (4 paths)
---------------------------------------------------------------------------------------------------------
Slack (hold check): 0.508 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
End Point: O_data_hs_p[2]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
Clock group: clock_source
Process: Fast
@@ -4508,10 +4744,10 @@ Paths for end point O_data_hs_p[2]_syn_2 (4 paths)
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[0] clk2q 0.109 r 2.138
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.109 r 2.138
O_data_hs_p[2]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.332 r 2.470 encrypted_text(0)
O_data_hs_p[2]_syn_2 path2reg 0.000 2.470
Arrival time 2.470 (0 lvl)
@@ -4530,31 +4766,29 @@ Paths for end point O_data_hs_p[2]_syn_2 (4 paths)
---------------------------------------------------------------------------------------------------------
-Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.498 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[1]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
+ Slack (hold check): 0.508 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[2]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
Clock group: clock_source
Process: Fast
- Data Path Delay: 0.431ns (logic 0.109ns, net 0.322ns, 25% logic)
+ Data Path Delay: 0.441ns (logic 0.109ns, net 0.332ns, 24% logic)
Logic Levels: 0
Point Type Incr Path Info
---------------------------------------------------------------------------------------------------------
source latency 0.000 0.000
u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[1] clk2q 0.109 r 2.138
- O_data_hs_p[1]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.322 r 2.460 encrypted_text(0)
- O_data_hs_p[1]_syn_2 path2reg 0.000 2.460
- Arrival time 2.460 (0 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q 0.109 r 2.138
+ O_data_hs_p[2]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.332 r 2.470 encrypted_text(0)
+ O_data_hs_p[2]_syn_2 path2reg 0.000 2.470
+ Arrival time 2.470 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ O_data_hs_p[2]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
capture clock edge 0.000 1.965
---------------------------------------------------------------------------------------------------------
cell hold -0.003 1.962
@@ -4562,120 +4796,18 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
clock recovergence pessimism 0.000 1.962
Required time 1.962
---------------------------------------------------------------------------------------------------------
- Slack 0.498ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check): 0.507 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[1]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
- Clock group: clock_source
- Process: Fast
- Data Path Delay: 0.440ns (logic 0.109ns, net 0.331ns, 24% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge 0.000 2.029
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.109 r 2.138
- O_data_hs_p[1]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.331 r 2.469 encrypted_text(0)
- O_data_hs_p[1]_syn_2 path2reg 0.000 2.469
- Arrival time 2.469 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge 0.000 1.965
----------------------------------------------------------------------------------------------------------
- cell hold -0.003 1.962
- clock uncertainty 0.000 1.962
- clock recovergence pessimism 0.000 1.962
- Required time 1.962
----------------------------------------------------------------------------------------------------------
- Slack 0.507ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check): 0.530 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[1]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
- Clock group: clock_source
- Process: Fast
- Data Path Delay: 0.463ns (logic 0.109ns, net 0.354ns, 23% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge 0.000 2.029
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[0] clk2q 0.109 r 2.138
- O_data_hs_p[1]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.354 r 2.492 encrypted_text(0)
- O_data_hs_p[1]_syn_2 path2reg 0.000 2.492
- Arrival time 2.492 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge 0.000 1.965
----------------------------------------------------------------------------------------------------------
- cell hold -0.003 1.962
- clock uncertainty 0.000 1.962
- clock recovergence pessimism 0.000 1.962
- Required time 1.962
----------------------------------------------------------------------------------------------------------
- Slack 0.530ns
+ Slack 0.508ns
---------------------------------------------------------------------------------------------------------
Paths for end point O_data_hs_p[0]_syn_2 (4 paths)
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.507 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[0]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
- Clock group: clock_source
- Process: Fast
- Data Path Delay: 0.440ns (logic 0.109ns, net 0.331ns, 24% logic)
- Logic Levels: 0
-
- Point Type Incr Path Info
----------------------------------------------------------------------------------------------------------
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[1] 0.000 0.000
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge 0.000 2.029
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[1] clk2q 0.109 r 2.138
- O_data_hs_p[0]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.331 r 2.469 encrypted_text(0)
- O_data_hs_p[0]_syn_2 path2reg 0.000 2.469
- Arrival time 2.469 (0 lvl)
-
- source latency 0.000 0.000
- u_pll/pll_inst.clkc[2] 0.000 0.000
- O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge 0.000 1.965
----------------------------------------------------------------------------------------------------------
- cell hold -0.003 1.962
- clock uncertainty 0.000 1.962
- clock recovergence pessimism 0.000 1.962
- Required time 1.962
----------------------------------------------------------------------------------------------------------
- Slack 0.507ns
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check): 0.508 ns
+ Slack (hold check): 0.517 ns
Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
End Point: O_data_hs_p[0]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
Clock group: clock_source
Process: Fast
- Data Path Delay: 0.441ns (logic 0.109ns, net 0.332ns, 24% logic)
+ Data Path Delay: 0.450ns (logic 0.109ns, net 0.341ns, 24% logic)
Logic Levels: 0
Point Type Incr Path Info
@@ -4686,9 +4818,9 @@ Paths for end point O_data_hs_p[0]_syn_2 (4 paths)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q 0.109 r 2.138
- O_data_hs_p[0]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.332 r 2.470 encrypted_text(0)
- O_data_hs_p[0]_syn_2 path2reg 0.000 2.470
- Arrival time 2.470 (0 lvl)
+ O_data_hs_p[0]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.341 r 2.479 encrypted_text(0)
+ O_data_hs_p[0]_syn_2 path2reg 0.000 2.479
+ Arrival time 2.479 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[2] 0.000 0.000
@@ -4700,16 +4832,50 @@ Paths for end point O_data_hs_p[0]_syn_2 (4 paths)
clock recovergence pessimism 0.000 1.962
Required time 1.962
---------------------------------------------------------------------------------------------------------
- Slack 0.508ns
+ Slack 0.517ns
---------------------------------------------------------------------------------------------------------
- Slack (hold check): 0.508 ns
- Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point: O_data_hs_p[0]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
+ Slack (hold check): 0.517 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[0]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
Clock group: clock_source
Process: Fast
- Data Path Delay: 0.441ns (logic 0.109ns, net 0.332ns, 24% logic)
+ Data Path Delay: 0.450ns (logic 0.109ns, net 0.341ns, 24% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge 0.000 2.029
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q 0.109 r 2.138
+ O_data_hs_p[0]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.341 r 2.479 encrypted_text(0)
+ O_data_hs_p[0]_syn_2 path2reg 0.000 2.479
+ Arrival time 2.479 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[2] 0.000 0.000
+ O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge 0.000 1.965
+---------------------------------------------------------------------------------------------------------
+ cell hold -0.003 1.962
+ clock uncertainty 0.000 1.962
+ clock recovergence pessimism 0.000 1.962
+ Required time 1.962
+---------------------------------------------------------------------------------------------------------
+ Slack 0.517ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check): 0.546 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[0]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
+ Clock group: clock_source
+ Process: Fast
+ Data Path Delay: 0.479ns (logic 0.109ns, net 0.370ns, 22% logic)
Logic Levels: 0
Point Type Incr Path Info
@@ -4719,10 +4885,10 @@ Paths for end point O_data_hs_p[0]_syn_2 (4 paths)
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.109 r 2.138
- O_data_hs_p[0]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.332 r 2.470 encrypted_text(0)
- O_data_hs_p[0]_syn_2 path2reg 0.000 2.470
- Arrival time 2.470 (0 lvl)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[1] clk2q 0.109 r 2.138
+ O_data_hs_p[0]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.370 r 2.508 encrypted_text(0)
+ O_data_hs_p[0]_syn_2 path2reg 0.000 2.508
+ Arrival time 2.508 (0 lvl)
source latency 0.000 0.000
u_pll/pll_inst.clkc[2] 0.000 0.000
@@ -4734,7 +4900,111 @@ Paths for end point O_data_hs_p[0]_syn_2 (4 paths)
clock recovergence pessimism 0.000 1.962
Required time 1.962
---------------------------------------------------------------------------------------------------------
- Slack 0.508ns
+ Slack 0.546ns
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check): 0.517 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[1]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
+ Clock group: clock_source
+ Process: Fast
+ Data Path Delay: 0.450ns (logic 0.109ns, net 0.341ns, 24% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge 0.000 2.029
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[1] clk2q 0.109 r 2.138
+ O_data_hs_p[1]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.341 r 2.479 encrypted_text(0)
+ O_data_hs_p[1]_syn_2 path2reg 0.000 2.479
+ Arrival time 2.479 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[2] 0.000 0.000
+ O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge 0.000 1.965
+---------------------------------------------------------------------------------------------------------
+ cell hold -0.003 1.962
+ clock uncertainty 0.000 1.962
+ clock recovergence pessimism 0.000 1.962
+ Required time 1.962
+---------------------------------------------------------------------------------------------------------
+ Slack 0.517ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check): 0.517 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[1]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
+ Clock group: clock_source
+ Process: Fast
+ Data Path Delay: 0.450ns (logic 0.109ns, net 0.341ns, 24% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge 0.000 2.029
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.109 r 2.138
+ O_data_hs_p[1]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.341 r 2.479 encrypted_text(0)
+ O_data_hs_p[1]_syn_2 path2reg 0.000 2.479
+ Arrival time 2.479 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[2] 0.000 0.000
+ O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge 0.000 1.965
+---------------------------------------------------------------------------------------------------------
+ cell hold -0.003 1.962
+ clock uncertainty 0.000 1.962
+ clock recovergence pessimism 0.000 1.962
+ Required time 1.962
+---------------------------------------------------------------------------------------------------------
+ Slack 0.517ns
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check): 0.517 ns
+ Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point: O_data_hs_p[1]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
+ Clock group: clock_source
+ Process: Fast
+ Data Path Delay: 0.450ns (logic 0.109ns, net 0.341ns, 24% logic)
+ Logic Levels: 0
+
+ Point Type Incr Path Info
+---------------------------------------------------------------------------------------------------------
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[1] 0.000 0.000
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge 0.000 2.029
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q 0.109 r 2.138
+ O_data_hs_p[1]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.341 r 2.479 encrypted_text(0)
+ O_data_hs_p[1]_syn_2 path2reg 0.000 2.479
+ Arrival time 2.479 (0 lvl)
+
+ source latency 0.000 0.000
+ u_pll/pll_inst.clkc[2] 0.000 0.000
+ O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge 0.000 1.965
+---------------------------------------------------------------------------------------------------------
+ cell hold -0.003 1.962
+ clock uncertainty 0.000 1.962
+ clock recovergence pessimism 0.000 1.962
+ Required time 1.962
+---------------------------------------------------------------------------------------------------------
+ Slack 0.517ns
---------------------------------------------------------------------------------------------------------
@@ -4765,7 +5035,7 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths)
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[0] clk2q 0.146 r 2.556
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[1] clk2q 0.146 r 2.556
O_clk_hs_p_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net (fanout = 2) 0.479 r 3.035 encrypted_text(0)
O_clk_hs_p_syn_2 path2reg 0.000 3.035
Arrival time 3.035 (0 lvl)
@@ -4799,7 +5069,7 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths)
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.410
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[0] clk2q 0.146 r 2.556
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[1] clk2q 0.146 r 2.556
O_clk_hs_p_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net (fanout = 2) 0.476 r 3.032 encrypted_text(0)
O_clk_hs_p_syn_2 path2reg 0.000 3.032
Arrival time 3.032 (0 lvl)
@@ -4837,7 +5107,7 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths)
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[0] clk2q 0.109 r 2.138
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[1] clk2q 0.109 r 2.138
O_clk_hs_p_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net (fanout = 2) 0.331 r 2.469 encrypted_text(0)
O_clk_hs_p_syn_2 path2reg 0.000 2.469
Arrival time 2.469 (0 lvl)
@@ -4871,7 +5141,7 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths)
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
launch clock edge 0.000 2.029
---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[0] clk2q 0.109 r 2.138
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[1] clk2q 0.109 r 2.138
O_clk_hs_p_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net (fanout = 2) 0.332 r 2.470 encrypted_text(0)
O_clk_hs_p_syn_2 path2reg 0.000 2.470
Arrival time 2.470 (0 lvl)
@@ -4894,21 +5164,21 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths)
=========================================================================================================
Timing summary:
---------------------------------------------------------------------------------------------------------
-Constraint path number: 361226 (STA coverage = 91.90%)
+Constraint path number: 370860 (STA coverage = 91.86%)
Timing violations: 5 setup errors, and 0 hold errors.
-Minimal setup slack: -2.059, minimal hold slack: 0.067
+Minimal setup slack: -1.797, minimal hold slack: 0.067
Timing group statistics:
Clock constraints:
Clock Name Min Period Max Freq Skew Fanout TNS
- S_clk (108.0MHz) 9.243ns 108.190MHz 0.326ns 1785 0.000ns
- a_pclk (48.0MHz) 12.785ns 78.217MHz 0.326ns 1421 0.000ns
- b_pclk (48.0MHz) 10.495ns 95.283MHz 0.326ns 1348 0.000ns
- clk_adc (6.0MHz) 168.723ns 5.927MHz 0.326ns 951 -3.421ns
- a_sclk (168.0MHz) 2.151ns 464.900MHz 0.254ns 69 0.000ns
- b_sclk (168.0MHz) 2.151ns 464.900MHz 0.326ns 69 0.000ns
- S_clk_x2 (216.0MHz) 2.748ns 363.901MHz 0.480ns 22 0.000ns
- S_clk_x4 (432.0MHz) 1.391ns 718.907MHz 0.018ns 4 0.000ns
+ S_clk (108.0MHz) 9.150ns 109.290MHz 0.326ns 1795 0.000ns
+ a_pclk (48.0MHz) 13.964ns 71.613MHz 0.326ns 1417 0.000ns
+ b_pclk (48.0MHz) 10.242ns 97.637MHz 0.326ns 1355 0.000ns
+ clk_adc (6.0MHz) 168.461ns 5.936MHz 0.326ns 967 -3.307ns
+ b_sclk (168.0MHz) 1.853ns 539.665MHz 0.326ns 70 0.000ns
+ a_sclk (168.0MHz) 2.239ns 446.628MHz 0.326ns 69 0.000ns
+ S_clk_x2 (216.0MHz) 2.179ns 458.926MHz 0.480ns 20 0.000ns
+ S_clk_x4 (432.0MHz) 1.563ns 639.795MHz 0.018ns 4 0.000ns
S_clk_x4_90d (432.0MHz) 2.975ns 336.000MHz 0.000ns 1 -0.661ns
Minimum input arrival time before clock: no constraint path
Maximum output required time after clock: no constraint path
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.tsm b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.tsm
index 7a02db8..1e7ca45 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.tsm
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.tsm
@@ -1,1307 +1,1376 @@
eagle_s20
-13 4895 3297 2781 25564 361226 5 0
--2.059 0.067 huagao_mipi_top eagle_s20 EG4D20EG176 Detail NA 38 12
+13 5165 3533 2973 25612 370860 5 0
+-1.797 0.067 huagao_mipi_top eagle_s20 EG4D20EG176 Detail NA 38 12
clock: a_lvds_clk_p
15 0 0 0
clock: a_pclk
-23 104856 6214 2
+23 105934 6230 2
Setup check
33 3
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
-33 8.048000 659 3
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
-sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
-35 8.048000 22.929000 14.881000 7 9
-sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4] U_rgb_to_csi_pakage/mult0_syn_4.a[9]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg3_syn_51_syn_2.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_17.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_bus_top/reg0_syn_192.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1]
-
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
-sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
-89 8.048000 22.929000 14.881000 7 9
-sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4] U_rgb_to_csi_pakage/mult0_syn_4.a[9]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg3_syn_51_syn_2.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_17.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_bus_top/reg0_syn_192.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[0]
-
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
-sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
-143 8.053000 22.929000 14.876000 7 10
-sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4] U_rgb_to_csi_pakage/mult0_syn_4.a[9]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg3_syn_51_syn_2.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_17.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_bus_top/reg0_syn_192.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1]
-
-
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
-199 8.116000 691 3
+33 6.869000 691 3
Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
-201 8.116000 22.929000 14.813000 7 9
-sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4] U_rgb_to_csi_pakage/mult0_syn_4.a[9]
+35 6.869000 22.857000 15.988000 7 9
+sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4] U_rgb_to_csi_pakage/mult0_syn_4.a[12]
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg3_syn_51_syn_2.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_17.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_bus_top/reg0_syn_192.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_pixel_cdc/reg6_syn_65.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pixel_cdc/reg6_syn_67.b[0]
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1]
Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
-255 8.116000 22.929000 14.813000 7 9
-sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4] U_rgb_to_csi_pakage/mult0_syn_4.a[9]
+89 6.869000 22.857000 15.988000 7 9
+sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4] U_rgb_to_csi_pakage/mult0_syn_4.a[12]
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg3_syn_51_syn_2.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_17.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_bus_top/reg0_syn_192.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_pixel_cdc/reg6_syn_65.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pixel_cdc/reg6_syn_67.b[0]
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[0]
Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
-309 8.121000 22.929000 14.808000 7 10
-sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4] U_rgb_to_csi_pakage/mult0_syn_4.a[9]
+143 6.875000 22.857000 15.982000 7 10
+sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4] U_rgb_to_csi_pakage/mult0_syn_4.a[12]
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg3_syn_51_syn_2.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_17.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_bus_top/reg0_syn_192.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_pixel_cdc/reg6_syn_65.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pixel_cdc/reg6_syn_67.b[0]
sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1]
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216
-365 12.412000 20 3
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216
-sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.clk
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216
-367 12.412000 22.929000 10.517000 4 5
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[1] sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg0_syn_26_syn_2.c[0]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_15 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/adc_addr_gen/reg1_syn_22.b[1]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert_en_n reg42_syn_184.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_11 sampling_fe_a/u_sort/u_data_prebuffer/channelPart/reg1_syn_62.d[0]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_13 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216.mi[0]
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
+199 7.164000 659 3
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
+sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
+201 7.164000 22.857000 15.693000 7 9
+sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4] U_rgb_to_csi_pakage/mult0_syn_4.a[12]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_pixel_cdc/reg6_syn_65.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pixel_cdc/reg6_syn_67.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1]
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216
-sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.clk
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216
-413 12.431000 22.929000 10.498000 4 5
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[0] sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg0_syn_26_syn_2.d[0]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_15 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/adc_addr_gen/reg1_syn_22.b[1]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert_en_n reg42_syn_184.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_11 sampling_fe_a/u_sort/u_data_prebuffer/channelPart/reg1_syn_62.d[0]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_13 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216.mi[0]
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
+sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
+255 7.164000 22.857000 15.693000 7 9
+sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4] U_rgb_to_csi_pakage/mult0_syn_4.a[12]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_pixel_cdc/reg6_syn_65.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pixel_cdc/reg6_syn_67.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[0]
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/channelPart/reg0_syn_60.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216
-sampling_fe_a/u_sort/u_data_prebuffer/channelPart/reg0_syn_60.clk
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216
-459 13.227000 22.929000 9.702000 5 6
-sampling_fe_a/u_sort/u_data_prebuffer/channelPart/WR_addr[4] reg42_syn_187.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_20 reg42_syn_187.a[1]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_22 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/adc_addr_gen/reg1_syn_22.a[1]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert_en_n reg42_syn_184.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_11 sampling_fe_a/u_sort/u_data_prebuffer/channelPart/reg1_syn_62.d[0]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_13 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_216.mi[0]
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
+sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
+309 7.170000 22.857000 15.687000 7 10
+sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4] U_rgb_to_csi_pakage/mult0_syn_4.a[12]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_pixel_cdc/reg6_syn_65.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_625.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pixel_cdc/reg6_syn_67.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1]
+
+
+Endpoint: exdev_ctl_a/u_gen_sp/reg0_syn_81
+365 12.294000 217 3
+Timing path: exdev_ctl_a/u_gen_sp/reg9_syn_103.clk->exdev_ctl_a/u_gen_sp/reg0_syn_81
+exdev_ctl_a/u_gen_sp/reg9_syn_103.clk
+exdev_ctl_a/u_gen_sp/reg0_syn_81
+367 12.294000 22.786000 10.492000 7 9
+exdev_ctl_a/u_gen_sp/sp_t_d1[3] exdev_ctl_a/u_gen_sp/sub1_syn_103.a[0]
+exdev_ctl_a/u_gen_sp/sub1_syn_91 exdev_ctl_a/u_gen_sp/sub1_syn_104.fci
+exdev_ctl_a/u_gen_sp/sub1_syn_95 exdev_ctl_a/u_gen_sp/sub1_syn_105.fci
+exdev_ctl_a/u_gen_sp/cnt_one_line_b5[12] exdev_ctl_a/reg8_syn_103.a[1]
+exdev_ctl_a/u_gen_sp/mux31_syn_140 exdev_ctl_b/reg6_syn_103.a[1]
+exdev_ctl_a/u_gen_sp/mux31_syn_142 u_bus_top/reg5_syn_196.a[0]
+exdev_ctl_a/u_gen_sp/mux31_syn_150 exdev_ctl_a/reg8_syn_103.a[0]
+exdev_ctl_a/u_gen_sp/cnt_one_line_b3_n1 exdev_ctl_a/reg8_syn_109.d[1]
+exdev_ctl_a/u_gen_sp/mux31_syn_19 exdev_ctl_a/u_gen_sp/reg0_syn_81.sr
+
+Timing path: exdev_ctl_a/u_gen_sp/reg9_syn_100.clk->exdev_ctl_a/u_gen_sp/reg0_syn_81
+exdev_ctl_a/u_gen_sp/reg9_syn_100.clk
+exdev_ctl_a/u_gen_sp/reg0_syn_81
+421 12.405000 22.786000 10.381000 7 9
+exdev_ctl_a/u_gen_sp/sp_t_d1[4] exdev_ctl_a/u_gen_sp/sub1_syn_103.b[0]
+exdev_ctl_a/u_gen_sp/sub1_syn_91 exdev_ctl_a/u_gen_sp/sub1_syn_104.fci
+exdev_ctl_a/u_gen_sp/sub1_syn_95 exdev_ctl_a/u_gen_sp/sub1_syn_105.fci
+exdev_ctl_a/u_gen_sp/cnt_one_line_b5[12] exdev_ctl_a/reg8_syn_103.a[1]
+exdev_ctl_a/u_gen_sp/mux31_syn_140 exdev_ctl_b/reg6_syn_103.a[1]
+exdev_ctl_a/u_gen_sp/mux31_syn_142 u_bus_top/reg5_syn_196.a[0]
+exdev_ctl_a/u_gen_sp/mux31_syn_150 exdev_ctl_a/reg8_syn_103.a[0]
+exdev_ctl_a/u_gen_sp/cnt_one_line_b3_n1 exdev_ctl_a/reg8_syn_109.d[1]
+exdev_ctl_a/u_gen_sp/mux31_syn_19 exdev_ctl_a/u_gen_sp/reg0_syn_81.sr
+
+Timing path: exdev_ctl_a/u_gen_sp/reg9_syn_100.clk->exdev_ctl_a/u_gen_sp/reg0_syn_81
+exdev_ctl_a/u_gen_sp/reg9_syn_100.clk
+exdev_ctl_a/u_gen_sp/reg0_syn_81
+475 12.598000 22.786000 10.188000 7 8
+exdev_ctl_a/u_gen_sp/sp_t_d1[7] exdev_ctl_a/u_gen_sp/sub1_syn_104.a[0]
+exdev_ctl_a/u_gen_sp/sub1_syn_95 exdev_ctl_a/u_gen_sp/sub1_syn_105.fci
+exdev_ctl_a/u_gen_sp/cnt_one_line_b5[12] exdev_ctl_a/reg8_syn_103.a[1]
+exdev_ctl_a/u_gen_sp/mux31_syn_140 exdev_ctl_b/reg6_syn_103.a[1]
+exdev_ctl_a/u_gen_sp/mux31_syn_142 u_bus_top/reg5_syn_196.a[0]
+exdev_ctl_a/u_gen_sp/mux31_syn_150 exdev_ctl_a/reg8_syn_103.a[0]
+exdev_ctl_a/u_gen_sp/cnt_one_line_b3_n1 exdev_ctl_a/reg8_syn_109.d[1]
+exdev_ctl_a/u_gen_sp/mux31_syn_19 exdev_ctl_a/u_gen_sp/reg0_syn_81.sr
Hold check
-507 3
-Endpoint: u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_290
-509 0.183000 1 1
-Timing path: u_bus_top/u_local_bus_slve_cis/reg29_syn_166.clk->u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_290
-u_bus_top/u_local_bus_slve_cis/reg29_syn_166.clk
-u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_290
-511 0.183000 2.191000 2.374000 0 1
-u_pixel_cdc/u_clk_cis_frame_num/signal_from[15] u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_290.mi[0]
+527 3
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1
+529 0.114000 10 3
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_741.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_741.clk
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1
+531 0.114000 2.183000 2.297000 1 1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[34] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.addra[7]
+
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_652.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_652.clk
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1
+569 0.234000 2.183000 2.417000 1 1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[32] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.addra[5]
+
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_648.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_648.clk
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1
+607 0.311000 2.183000 2.494000 1 1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[39] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.addra[12]
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1
-547 0.186000 8 3
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_606.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_606.clk
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1
-549 0.186000 2.183000 2.369000 1 1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_data[2] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1.dia[2]
-
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_606.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_606.clk
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1
-587 0.195000 2.183000 2.378000 1 1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_data[1] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1.dia[1]
-
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_586.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_586.clk
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1
-625 0.195000 2.183000 2.378000 1 1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_data[0] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1.dia[0]
+Endpoint: u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_333
+645 0.183000 1 1
+Timing path: u_bus_top/u_local_bus_slve_cis/reg29_syn_227.clk->u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_333
+u_bus_top/u_local_bus_slve_cis/reg29_syn_227.clk
+u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_333
+647 0.183000 2.191000 2.374000 0 1
+u_pixel_cdc/u_clk_cis_frame_num/signal_from[4] u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_333.mi[0]
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1
-663 0.195000 8 3
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_618.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_618.clk
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1
-665 0.195000 2.183000 2.378000 1 1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_data[30] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1.dia[6]
-
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_620.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_620.clk
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1
-703 0.205000 2.183000 2.388000 1 1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_data[28] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1.dia[4]
-
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_541.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_541.clk
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1
-741 0.234000 2.183000 2.417000 1 1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_data[31] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1.dia[7]
+Endpoint: exdev_ctl_a/reg6_syn_89
+683 0.183000 1 1
+Timing path: u_bus_top/u_local_bus_slve_cis/reg40_syn_204.clk->exdev_ctl_a/reg6_syn_89
+u_bus_top/u_local_bus_slve_cis/reg40_syn_204.clk
+exdev_ctl_a/reg6_syn_89
+685 0.183000 2.191000 2.374000 0 1
+u_bus_top/u_local_bus_slve_cis/reg1[18] exdev_ctl_a/reg6_syn_89.mi[0]
clock: a_sclk
-779 690 282 2
+721 722 282 2
Setup check
-789 3
-Endpoint: ua_lvds_rx/rx_clk_sync_reg_syn_5
-789 3.801000 7 3
-Timing path: ua_lvds_rx/reg7_syn_32.clk->ua_lvds_rx/rx_clk_sync_reg_syn_5
-ua_lvds_rx/reg7_syn_32.clk
-ua_lvds_rx/rx_clk_sync_reg_syn_5
-791 3.801000 8.210000 4.409000 2 2
-ua_lvds_rx/rx_clk_sft[0] ua_lvds_rx/rx_clk_sync_reg_syn_5.a[0]
-ua_lvds_rx/rx_clk_sync_n_syn_2 ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1]
+731 3
+Endpoint: ua_lvds_rx/reg14_syn_64
+731 3.713000 7 3
+Timing path: ua_lvds_rx/reg7_syn_33.clk->ua_lvds_rx/reg14_syn_64
+ua_lvds_rx/reg7_syn_33.clk
+ua_lvds_rx/reg14_syn_64
+733 3.713000 8.076000 4.363000 2 2
+ua_lvds_rx/rx_clk_sft[1] ua_lvds_rx/reg14_syn_62.b[0]
+ua_lvds_rx/rx_clk_sync_n_syn_2 ua_lvds_rx/reg14_syn_64.d[0]
-Timing path: ua_lvds_rx/reg11_syn_17.clk->ua_lvds_rx/rx_clk_sync_reg_syn_5
-ua_lvds_rx/reg11_syn_17.clk
-ua_lvds_rx/rx_clk_sync_reg_syn_5
-827 3.877000 8.210000 4.333000 2 2
-ua_lvds_rx/rx_clk_sft[2] ua_lvds_rx/rx_clk_sync_reg_syn_5.c[0]
-ua_lvds_rx/rx_clk_sync_n_syn_2 ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1]
+Timing path: ua_lvds_rx/reg7_syn_28.clk->ua_lvds_rx/reg14_syn_64
+ua_lvds_rx/reg7_syn_28.clk
+ua_lvds_rx/reg14_syn_64
+769 3.811000 8.076000 4.265000 2 2
+ua_lvds_rx/rx_clk_sft[2] ua_lvds_rx/reg14_syn_62.c[0]
+ua_lvds_rx/rx_clk_sync_n_syn_2 ua_lvds_rx/reg14_syn_64.d[0]
-Timing path: ua_lvds_rx/reg7_syn_32.clk->ua_lvds_rx/rx_clk_sync_reg_syn_5
-ua_lvds_rx/reg7_syn_32.clk
-ua_lvds_rx/rx_clk_sync_reg_syn_5
-863 4.066000 8.210000 4.144000 2 2
-ua_lvds_rx/rx_clk_sft[1] ua_lvds_rx/rx_clk_sync_reg_syn_5.b[0]
-ua_lvds_rx/rx_clk_sync_n_syn_2 ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1]
+Timing path: ua_lvds_rx/reg7_syn_25.clk->ua_lvds_rx/reg14_syn_64
+ua_lvds_rx/reg7_syn_25.clk
+ua_lvds_rx/reg14_syn_64
+805 3.988000 8.076000 4.088000 2 2
+ua_lvds_rx/rx_clk_sft[4] ua_lvds_rx/reg14_syn_62.e[0]
+ua_lvds_rx/rx_clk_sync_n_syn_2 ua_lvds_rx/reg14_syn_64.d[0]
Endpoint: ua_lvds_rx/reg8_syn_155
-899 4.145000 9 3
-Timing path: ua_lvds_rx/reg8_syn_155.clk->ua_lvds_rx/reg8_syn_155
-ua_lvds_rx/reg8_syn_155.clk
+841 4.003000 9 3
+Timing path: ua_lvds_rx/reg8_syn_161.clk->ua_lvds_rx/reg8_syn_155
+ua_lvds_rx/reg8_syn_161.clk
ua_lvds_rx/reg8_syn_155
-901 4.145000 8.246000 4.101000 1 1
-ua_lvds_rx/para_data[12] ua_lvds_rx/reg8_syn_155.a[1]
+843 4.003000 8.076000 4.073000 1 1
+ua_lvds_rx/rx_data[37] ua_lvds_rx/reg8_syn_155.c[1]
-Timing path: ua_lvds_rx/reg8_syn_155.clk->ua_lvds_rx/reg8_syn_155
-ua_lvds_rx/reg8_syn_155.clk
+Timing path: ua_lvds_rx/reg8_syn_161.clk->ua_lvds_rx/reg8_syn_155
+ua_lvds_rx/reg8_syn_161.clk
ua_lvds_rx/reg8_syn_155
-935 4.492000 8.246000 3.754000 1 1
-ua_lvds_rx/rx_data[13] ua_lvds_rx/reg8_syn_155.b[1]
+877 4.003000 8.076000 4.073000 1 1
+ua_lvds_rx/rx_data[37] ua_lvds_rx/reg8_syn_155.c[0]
-Timing path: ua_lvds_rx/reg8_syn_155.clk->ua_lvds_rx/reg8_syn_155
-ua_lvds_rx/reg8_syn_155.clk
+Timing path: ua_lvds_rx/reg8_syn_166.clk->ua_lvds_rx/reg8_syn_155
+ua_lvds_rx/reg8_syn_166.clk
ua_lvds_rx/reg8_syn_155
-969 4.492000 8.246000 3.754000 1 1
-ua_lvds_rx/rx_data[13] ua_lvds_rx/reg8_syn_155.b[0]
+911 4.125000 8.076000 3.951000 1 1
+ua_lvds_rx/sync0 ua_lvds_rx/reg8_syn_155.d[1]
-Endpoint: ua_lvds_rx/reg8_syn_151
-1003 4.198000 9 3
-Timing path: ua_lvds_rx/reg8_syn_151.clk->ua_lvds_rx/reg8_syn_151
-ua_lvds_rx/reg8_syn_151.clk
-ua_lvds_rx/reg8_syn_151
-1005 4.198000 8.246000 4.048000 1 1
-ua_lvds_rx/para_data[22] ua_lvds_rx/reg8_syn_151.a[1]
+Endpoint: ua_lvds_rx/reg3_syn_198
+945 4.009000 5 3
+Timing path: ua_lvds_rx/reg8_syn_161.clk->ua_lvds_rx/reg3_syn_198
+ua_lvds_rx/reg8_syn_161.clk
+ua_lvds_rx/reg3_syn_198
+947 4.009000 8.076000 4.067000 1 1
+ua_lvds_rx/rx_data[37] ua_lvds_rx/reg3_syn_198.b[0]
-Timing path: add1_syn_65.clk->ua_lvds_rx/reg8_syn_151
-add1_syn_65.clk
-ua_lvds_rx/reg8_syn_151
-1039 4.320000 8.246000 3.926000 1 1
-ua_lvds_rx/rx_data[25] ua_lvds_rx/reg8_syn_151.b[1]
+Timing path: ua_lvds_rx/reg8_syn_198.clk->ua_lvds_rx/reg3_syn_198
+ua_lvds_rx/reg8_syn_198.clk
+ua_lvds_rx/reg3_syn_198
+981 4.454000 8.076000 3.622000 1 1
+ua_lvds_rx/rx_data[38] ua_lvds_rx/reg3_syn_198.c[0]
-Timing path: add1_syn_65.clk->ua_lvds_rx/reg8_syn_151
-add1_syn_65.clk
-ua_lvds_rx/reg8_syn_151
-1073 4.320000 8.246000 3.926000 1 1
-ua_lvds_rx/rx_data[25] ua_lvds_rx/reg8_syn_151.b[0]
+Timing path: ua_lvds_rx/reg14_syn_62.clk->ua_lvds_rx/reg3_syn_198
+ua_lvds_rx/reg14_syn_62.clk
+ua_lvds_rx/reg3_syn_198
+1015 4.486000 8.076000 3.590000 1 1
+ua_lvds_rx/sync1 ua_lvds_rx/reg3_syn_198.e[0]
Hold check
-1107 3
-Endpoint: ua_lvds_rx/ramread0_syn_46
-1109 0.167000 2 2
-Timing path: ua_lvds_rx/reg3_syn_174.clk->ua_lvds_rx/ramread0_syn_46
-ua_lvds_rx/reg3_syn_174.clk
-ua_lvds_rx/ramread0_syn_46
-1111 0.167000 2.187000 2.354000 1 1
-ua_lvds_rx/para_data[10] ua_lvds_rx/ramread0_syn_46.c[1]
+1049 3
+Endpoint: ua_lvds_rx/ramread0_syn_32
+1051 0.092000 2 2
+Timing path: ua_lvds_rx/reg3_syn_190.clk->ua_lvds_rx/ramread0_syn_32
+ua_lvds_rx/reg3_syn_190.clk
+ua_lvds_rx/ramread0_syn_32
+1053 0.092000 2.066000 2.158000 1 1
+ua_lvds_rx/para_data[6] ua_lvds_rx/ramread0_syn_32.c[1]
-Timing path: ua_lvds_rx/reg16_syn_31.clk->ua_lvds_rx/ramread0_syn_46
+Timing path: ua_lvds_rx/reg16_syn_31.clk->ua_lvds_rx/ramread0_syn_32
ua_lvds_rx/reg16_syn_31.clk
-ua_lvds_rx/ramread0_syn_46
-1145 0.306000 2.187000 2.493000 1 1
-ua_lvds_rx/wcnt[2] ua_lvds_rx/ramread0_syn_46.c[0]
+ua_lvds_rx/ramread0_syn_32
+1087 0.369000 2.066000 2.435000 1 1
+ua_lvds_rx/wcnt[2] ua_lvds_rx/ramread0_syn_32.c[0]
Endpoint: ua_lvds_rx/ramread0_syn_102
-1179 0.183000 2 2
-Timing path: ua_lvds_rx/reg3_syn_190.clk->ua_lvds_rx/ramread0_syn_102
-ua_lvds_rx/reg3_syn_190.clk
+1121 0.114000 2 2
+Timing path: ua_lvds_rx/reg16_syn_33.clk->ua_lvds_rx/ramread0_syn_102
+ua_lvds_rx/reg16_syn_33.clk
ua_lvds_rx/ramread0_syn_102
-1181 0.183000 2.171000 2.354000 1 1
-ua_lvds_rx/para_data[26] ua_lvds_rx/ramread0_syn_102.c[1]
+1123 0.114000 2.066000 2.180000 1 1
+ua_lvds_rx/wcnt[1] ua_lvds_rx/ramread0_syn_102.b[0]
-Timing path: ua_lvds_rx/reg16_syn_31.clk->ua_lvds_rx/ramread0_syn_102
-ua_lvds_rx/reg16_syn_31.clk
+Timing path: ua_lvds_rx/reg8_syn_147.clk->ua_lvds_rx/ramread0_syn_102
+ua_lvds_rx/reg8_syn_147.clk
ua_lvds_rx/ramread0_syn_102
-1215 0.306000 2.171000 2.477000 1 1
-ua_lvds_rx/wcnt[2] ua_lvds_rx/ramread0_syn_102.c[0]
+1157 0.289000 2.066000 2.355000 1 1
+ua_lvds_rx/para_data[25] ua_lvds_rx/ramread0_syn_102.b[1]
-Endpoint: ua_lvds_rx/ramread0_syn_18
-1249 0.183000 2 2
-Timing path: ua_lvds_rx/reg3_syn_166.clk->ua_lvds_rx/ramread0_syn_18
-ua_lvds_rx/reg3_syn_166.clk
-ua_lvds_rx/ramread0_syn_18
-1251 0.183000 2.171000 2.354000 1 1
-ua_lvds_rx/para_data[2] ua_lvds_rx/ramread0_syn_18.c[1]
+Endpoint: ua_lvds_rx/ramread0_syn_116
+1191 0.167000 2 2
+Timing path: ua_lvds_rx/reg3_syn_198.clk->ua_lvds_rx/ramread0_syn_116
+ua_lvds_rx/reg3_syn_198.clk
+ua_lvds_rx/ramread0_syn_116
+1193 0.167000 2.096000 2.263000 1 1
+ua_lvds_rx/para_data[34] ua_lvds_rx/ramread0_syn_116.c[1]
-Timing path: ua_lvds_rx/reg16_syn_31.clk->ua_lvds_rx/ramread0_syn_18
+Timing path: ua_lvds_rx/reg16_syn_31.clk->ua_lvds_rx/ramread0_syn_116
ua_lvds_rx/reg16_syn_31.clk
-ua_lvds_rx/ramread0_syn_18
-1285 0.306000 2.171000 2.477000 1 1
-ua_lvds_rx/wcnt[2] ua_lvds_rx/ramread0_syn_18.c[0]
+ua_lvds_rx/ramread0_syn_116
+1227 0.415000 2.096000 2.511000 1 1
+ua_lvds_rx/wcnt[2] ua_lvds_rx/ramread0_syn_116.c[0]
clock: b_lvds_clk_p
-1321 0 0 0
+1263 0 0 0
clock: b_pclk
-1329 101778 5860 2
+1271 105758 5876 2
Setup check
-1339 3
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494
-1339 10.338000 171 3
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494
+1281 3
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23
+1281 10.591000 171 3
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494
-1341 10.338000 22.857000 12.519000 6 9
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23
+1283 10.591000 22.929000 12.338000 6 6
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7] u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238 sampling_fe_a/reg1_syn_61.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.a[1]
+
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23
+1331 10.591000 22.929000 12.338000 6 6
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7] u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238 sampling_fe_a/reg1_syn_61.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.a[0]
+
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23
+1379 10.598000 22.929000 12.331000 6 7
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_386.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[1]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494.a[1]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7] u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238 sampling_fe_a/reg1_syn_61.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_23.a[1]
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514
+1429 10.711000 70 3
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494
-1395 10.338000 22.857000 12.519000 6 9
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514
+1431 10.711000 22.929000 12.218000 6 6
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7] u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238 sampling_fe_a/reg1_syn_61.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.a[0]
+
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514
+1479 10.718000 22.929000 12.211000 6 7
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_386.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[1]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7] u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238 sampling_fe_a/reg1_syn_61.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.a[0]
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494
-1449 10.434000 22.857000 12.423000 6 6
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[10] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.a[1]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_386.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[1]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_494.a[1]
-
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
-1497 10.717000 70 3
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
-1499 10.717000 22.857000 12.140000 6 9
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514
+1529 10.783000 22.929000 12.146000 6 6
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[6] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[1]
sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_386.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[1]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1]
-
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
-1553 10.813000 22.857000 12.044000 6 6
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[10] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.a[1]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_386.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[1]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1]
-
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
-1601 10.873000 22.857000 11.984000 6 7
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[8] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.a[1]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_386.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[1]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_323.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[7] u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[1]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1234 u_pixel_cdc/u_clk_cis_frame_num/reg1_syn_330.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1238 sampling_fe_a/reg1_syn_61.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_514.a[0]
-Endpoint: exdev_ctl_b/u_gen_sp/reg0_syn_72
-1651 11.454000 214 3
-Timing path: exdev_ctl_b/u_gen_sp/reg9_syn_93.clk->exdev_ctl_b/u_gen_sp/reg0_syn_72
-exdev_ctl_b/u_gen_sp/reg9_syn_93.clk
-exdev_ctl_b/u_gen_sp/reg0_syn_72
-1653 11.454000 22.786000 11.332000 7 8
-exdev_ctl_b/u_gen_sp/sp_t_d1[0] exdev_ctl_b/u_gen_sp/sub1_syn_102.b[0]
-exdev_ctl_b/u_gen_sp/cnt_one_line_b5[2] exdev_ctl_b/u_ADconfig/reg0_syn_140.b[1]
-exdev_ctl_b/u_gen_sp/mux31_syn_137 exdev_ctl_b/u_ADconfig/reg1_syn_173.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_143 exdev_ctl_b/u_ADconfig/reg0_syn_140.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_145 exdev_ctl_b/u_ADconfig/reg1_syn_176.a[0]
-exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 exdev_ctl_b/u_gen_sp/reg9_syn_107.a[0]
-exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2 exdev_ctl_b/u_gen_sp/reg2_syn_21.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_72.sr
-
-Timing path: exdev_ctl_b/u_gen_sp/reg9_syn_113.clk->exdev_ctl_b/u_gen_sp/reg0_syn_72
-exdev_ctl_b/u_gen_sp/reg9_syn_113.clk
-exdev_ctl_b/u_gen_sp/reg0_syn_72
-1705 11.556000 22.786000 11.230000 8 11
+Endpoint: exdev_ctl_b/u_gen_sp/reg0_syn_74
+1577 11.561000 214 3
+Timing path: exdev_ctl_b/u_gen_sp/reg9_syn_89.clk->exdev_ctl_b/u_gen_sp/reg0_syn_74
+exdev_ctl_b/u_gen_sp/reg9_syn_89.clk
+exdev_ctl_b/u_gen_sp/reg0_syn_74
+1579 11.561000 22.858000 11.297000 8 11
exdev_ctl_b/u_gen_sp/sp_t_d1[1] exdev_ctl_b/u_gen_sp/sub1_syn_102.a[1]
exdev_ctl_b/u_gen_sp/sub1_syn_87 exdev_ctl_b/u_gen_sp/sub1_syn_103.fci
exdev_ctl_b/u_gen_sp/sub1_syn_91 exdev_ctl_b/u_gen_sp/sub1_syn_104.fci
exdev_ctl_b/u_gen_sp/sub1_syn_95 exdev_ctl_b/u_gen_sp/sub1_syn_105.fci
-exdev_ctl_b/u_gen_sp/cnt_one_line_b5[11] exdev_ctl_b/u_ADconfig/reg0_syn_140.a[1]
-exdev_ctl_b/u_gen_sp/mux31_syn_137 exdev_ctl_b/u_ADconfig/reg1_syn_173.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_143 exdev_ctl_b/u_ADconfig/reg0_syn_140.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_145 exdev_ctl_b/u_ADconfig/reg1_syn_176.a[0]
-exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 exdev_ctl_b/u_gen_sp/reg9_syn_107.a[0]
-exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2 exdev_ctl_b/u_gen_sp/reg2_syn_21.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_72.sr
+exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12] u_a_sp_sampling/reg0_syn_27.a[0]
+exdev_ctl_b/u_gen_sp/mux31_syn_139 exdev_ctl_b/u_gen_sp/reg9_syn_103.a[0]
+exdev_ctl_b/u_gen_sp/mux31_syn_141 sampling_fe_a/u_ad_sampling/sp_1d_reg_syn_8.a[0]
+exdev_ctl_b/u_gen_sp/mux31_syn_149 u_bus_top/u_local_bus_slve_cis/reg53_syn_51.a[0]
+exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 u_bus_top/u_local_bus_slve_cis/reg54_syn_47.a[0]
+exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2 u_bus_top/u_local_bus_slve_cis/reg55_syn_42.a[1]
+exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_74.sr
-Timing path: exdev_ctl_b/u_gen_sp/reg9_syn_93.clk->exdev_ctl_b/u_gen_sp/reg0_syn_72
-exdev_ctl_b/u_gen_sp/reg9_syn_93.clk
-exdev_ctl_b/u_gen_sp/reg0_syn_72
-1763 11.601000 22.786000 11.185000 8 11
+Timing path: exdev_ctl_b/u_gen_sp/reg8_syn_107.clk->exdev_ctl_b/u_gen_sp/reg0_syn_74
+exdev_ctl_b/u_gen_sp/reg8_syn_107.clk
+exdev_ctl_b/u_gen_sp/reg0_syn_74
+1637 11.662000 22.858000 11.196000 8 9
+exdev_ctl_b/u_gen_sp/sp_t_d1[9] exdev_ctl_b/u_gen_sp/sub1_syn_104.a[1]
+exdev_ctl_b/u_gen_sp/sub1_syn_95 exdev_ctl_b/u_gen_sp/sub1_syn_105.fci
+exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12] u_a_sp_sampling/reg0_syn_27.a[0]
+exdev_ctl_b/u_gen_sp/mux31_syn_139 exdev_ctl_b/u_gen_sp/reg9_syn_103.a[0]
+exdev_ctl_b/u_gen_sp/mux31_syn_141 sampling_fe_a/u_ad_sampling/sp_1d_reg_syn_8.a[0]
+exdev_ctl_b/u_gen_sp/mux31_syn_149 u_bus_top/u_local_bus_slve_cis/reg53_syn_51.a[0]
+exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 u_bus_top/u_local_bus_slve_cis/reg54_syn_47.a[0]
+exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2 u_bus_top/u_local_bus_slve_cis/reg55_syn_42.a[1]
+exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_74.sr
+
+Timing path: exdev_ctl_b/u_gen_sp/reg9_syn_106.clk->exdev_ctl_b/u_gen_sp/reg0_syn_74
+exdev_ctl_b/u_gen_sp/reg9_syn_106.clk
+exdev_ctl_b/u_gen_sp/reg0_syn_74
+1691 11.726000 22.858000 11.132000 8 11
exdev_ctl_b/u_gen_sp/sp_t_d1[0] exdev_ctl_b/u_gen_sp/sub1_syn_102.b[0]
exdev_ctl_b/u_gen_sp/sub1_syn_87 exdev_ctl_b/u_gen_sp/sub1_syn_103.fci
exdev_ctl_b/u_gen_sp/sub1_syn_91 exdev_ctl_b/u_gen_sp/sub1_syn_104.fci
exdev_ctl_b/u_gen_sp/sub1_syn_95 exdev_ctl_b/u_gen_sp/sub1_syn_105.fci
-exdev_ctl_b/u_gen_sp/cnt_one_line_b5[11] exdev_ctl_b/u_ADconfig/reg0_syn_140.a[1]
-exdev_ctl_b/u_gen_sp/mux31_syn_137 exdev_ctl_b/u_ADconfig/reg1_syn_173.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_143 exdev_ctl_b/u_ADconfig/reg0_syn_140.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_145 exdev_ctl_b/u_ADconfig/reg1_syn_176.a[0]
-exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 exdev_ctl_b/u_gen_sp/reg9_syn_107.a[0]
-exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2 exdev_ctl_b/u_gen_sp/reg2_syn_21.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_72.sr
+exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12] u_a_sp_sampling/reg0_syn_27.a[0]
+exdev_ctl_b/u_gen_sp/mux31_syn_139 exdev_ctl_b/u_gen_sp/reg9_syn_103.a[0]
+exdev_ctl_b/u_gen_sp/mux31_syn_141 sampling_fe_a/u_ad_sampling/sp_1d_reg_syn_8.a[0]
+exdev_ctl_b/u_gen_sp/mux31_syn_149 u_bus_top/u_local_bus_slve_cis/reg53_syn_51.a[0]
+exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 u_bus_top/u_local_bus_slve_cis/reg54_syn_47.a[0]
+exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2 u_bus_top/u_local_bus_slve_cis/reg55_syn_42.a[1]
+exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_74.sr
Hold check
-1821 3
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1
-1823 0.089000 10 3
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_635.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_635.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1
-1825 0.089000 2.183000 2.272000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[24] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[7]
+1749 3
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
+1751 0.080000 10 3
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_663.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_663.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
+1753 0.080000 2.183000 2.263000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[100] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.addra[3]
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[53]_syn_8.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[53]_syn_8.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1
-1863 0.089000 2.183000 2.272000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[23] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[6]
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_625.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_625.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
+1791 0.089000 2.183000 2.272000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[103] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.addra[6]
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_632.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_632.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1
-1901 0.196000 2.183000 2.379000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[27] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[10]
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_665.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_665.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
+1829 0.234000 2.183000 2.417000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[101] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.addra[4]
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
-1939 0.130000 8 3
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_524.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_524.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
-1941 0.130000 2.183000 2.313000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[41] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[1]
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
+1867 0.080000 8 3
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_27.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[40]_syn_27.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
+1869 0.080000 2.183000 2.263000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[80] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.dia[0]
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_527.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_527.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
-1979 0.241000 2.183000 2.424000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[43] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[3]
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_666.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_666.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
+1907 0.130000 2.183000 2.313000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[82] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.dia[2]
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[87]_syn_26.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[87]_syn_26.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
-2017 0.376000 2.183000 2.559000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[42] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[2]
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_543.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_543.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1
+1945 0.186000 2.183000 2.369000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[87] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.dia[7]
-Endpoint: exdev_ctl_b/reg3_syn_179
-2055 0.175000 1 1
-Timing path: u_bus_top/u_local_bus_slve_cis/reg39_syn_205.clk->exdev_ctl_b/reg3_syn_179
-u_bus_top/u_local_bus_slve_cis/reg39_syn_205.clk
-exdev_ctl_b/reg3_syn_179
-2057 0.175000 2.191000 2.366000 0 1
-u_bus_top/u_local_bus_slve_cis/reg19[25] exdev_ctl_b/reg3_syn_179.mi[0]
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1
+1983 0.114000 10 3
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_712.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_712.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1
+1985 0.114000 2.183000 2.297000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[68] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.addra[11]
+
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_712.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_712.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1
+2023 0.205000 2.183000 2.388000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[67] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.addra[10]
+
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_703.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_703.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1
+2061 0.302000 2.183000 2.485000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[66] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.addra[9]
clock: b_sclk
-2093 730 282 2
+2099 690 282 2
Setup check
-2103 3
+2109 3
Endpoint: ub_lvds_rx/rx_clk_sync_reg_syn_5
-2103 3.801000 7 3
-Timing path: ub_lvds_rx/reg7_syn_28.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5
-ub_lvds_rx/reg7_syn_28.clk
+2109 4.099000 7 3
+Timing path: ub_lvds_rx/reg7_syn_32.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5
+ub_lvds_rx/reg7_syn_32.clk
ub_lvds_rx/rx_clk_sync_reg_syn_5
-2105 3.801000 8.076000 4.275000 2 2
+2111 4.099000 8.210000 4.111000 2 2
ub_lvds_rx/rx_clk_sft[0] ub_lvds_rx/rx_clk_sync_reg_syn_5.a[0]
ub_lvds_rx/rx_clk_sync_n_syn_2 ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1]
-Timing path: ub_lvds_rx/reg7_syn_33.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5
-ub_lvds_rx/reg7_syn_33.clk
+Timing path: ub_lvds_rx/reg7_syn_25.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5
+ub_lvds_rx/reg7_syn_25.clk
ub_lvds_rx/rx_clk_sync_reg_syn_5
-2141 3.932000 8.076000 4.144000 2 2
+2147 4.175000 8.210000 4.035000 2 2
+ub_lvds_rx/rx_clk_sft[2] ub_lvds_rx/rx_clk_sync_reg_syn_5.c[0]
+ub_lvds_rx/rx_clk_sync_n_syn_2 ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1]
+
+Timing path: ub_lvds_rx/reg7_syn_32.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5
+ub_lvds_rx/reg7_syn_32.clk
+ub_lvds_rx/rx_clk_sync_reg_syn_5
+2183 4.364000 8.210000 3.846000 2 2
ub_lvds_rx/rx_clk_sft[1] ub_lvds_rx/rx_clk_sync_reg_syn_5.b[0]
ub_lvds_rx/rx_clk_sync_n_syn_2 ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1]
-Timing path: ub_lvds_rx/reg7_syn_28.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5
-ub_lvds_rx/reg7_syn_28.clk
-ub_lvds_rx/rx_clk_sync_reg_syn_5
-2177 3.963000 8.076000 4.113000 2 2
-ub_lvds_rx/rx_clk_sft[3] ub_lvds_rx/rx_clk_sync_reg_syn_5.d[0]
-ub_lvds_rx/rx_clk_sync_n_syn_2 ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1]
+
+Endpoint: ub_lvds_rx/reg8_syn_145
+2219 4.145000 9 3
+Timing path: ub_lvds_rx/reg8_syn_145.clk->ub_lvds_rx/reg8_syn_145
+ub_lvds_rx/reg8_syn_145.clk
+ub_lvds_rx/reg8_syn_145
+2221 4.145000 8.246000 4.101000 1 1
+ub_lvds_rx/para_data[25] ub_lvds_rx/reg8_syn_145.a[1]
+
+Timing path: ub_lvds_rx/reg8_syn_143.clk->ub_lvds_rx/reg8_syn_145
+ub_lvds_rx/reg8_syn_143.clk
+ub_lvds_rx/reg8_syn_145
+2255 4.156000 8.246000 4.090000 1 1
+ub_lvds_rx/rx_data[28] ub_lvds_rx/reg8_syn_145.b[1]
+
+Timing path: ub_lvds_rx/reg8_syn_143.clk->ub_lvds_rx/reg8_syn_145
+ub_lvds_rx/reg8_syn_143.clk
+ub_lvds_rx/reg8_syn_145
+2289 4.156000 8.246000 4.090000 1 1
+ub_lvds_rx/rx_data[28] ub_lvds_rx/reg8_syn_145.b[0]
-Endpoint: ub_lvds_rx/reg8_syn_163
-2213 4.145000 9 3
-Timing path: ub_lvds_rx/reg8_syn_163.clk->ub_lvds_rx/reg8_syn_163
-ub_lvds_rx/reg8_syn_163.clk
-ub_lvds_rx/reg8_syn_163
-2215 4.145000 8.112000 3.967000 1 1
-ub_lvds_rx/para_data[19] ub_lvds_rx/reg8_syn_163.a[1]
+Endpoint: ub_lvds_rx/reg8_syn_149
+2323 4.166000 9 3
+Timing path: ub_lvds_rx/reg8_syn_131.clk->ub_lvds_rx/reg8_syn_149
+ub_lvds_rx/reg8_syn_131.clk
+ub_lvds_rx/reg8_syn_149
+2325 4.166000 8.182000 4.016000 1 1
+ub_lvds_rx/rx_data[24] ub_lvds_rx/reg8_syn_149.b[1]
-Timing path: ub_lvds_rx/reg8_syn_151.clk->ub_lvds_rx/reg8_syn_163
-ub_lvds_rx/reg8_syn_151.clk
-ub_lvds_rx/reg8_syn_163
-2249 4.525000 8.112000 3.587000 1 1
-ub_lvds_rx/rx_data[21] ub_lvds_rx/reg8_syn_163.b[1]
+Timing path: ub_lvds_rx/reg8_syn_131.clk->ub_lvds_rx/reg8_syn_149
+ub_lvds_rx/reg8_syn_131.clk
+ub_lvds_rx/reg8_syn_149
+2359 4.166000 8.182000 4.016000 1 1
+ub_lvds_rx/rx_data[24] ub_lvds_rx/reg8_syn_149.b[0]
-Timing path: ub_lvds_rx/reg8_syn_151.clk->ub_lvds_rx/reg8_syn_163
-ub_lvds_rx/reg8_syn_151.clk
-ub_lvds_rx/reg8_syn_163
-2283 4.525000 8.112000 3.587000 1 1
-ub_lvds_rx/rx_data[21] ub_lvds_rx/reg8_syn_163.b[0]
-
-
-Endpoint: ub_lvds_rx/reg8_syn_161
-2317 4.145000 9 3
-Timing path: ub_lvds_rx/reg8_syn_161.clk->ub_lvds_rx/reg8_syn_161
-ub_lvds_rx/reg8_syn_161.clk
-ub_lvds_rx/reg8_syn_161
-2319 4.145000 8.112000 3.967000 1 1
-ub_lvds_rx/para_data[14] ub_lvds_rx/reg8_syn_161.a[1]
-
-Timing path: ub_lvds_rx/reg8_syn_204.clk->ub_lvds_rx/reg8_syn_161
-ub_lvds_rx/reg8_syn_204.clk
-ub_lvds_rx/reg8_syn_161
-2353 4.475000 8.112000 3.637000 1 1
-ub_lvds_rx/rx_data[16] ub_lvds_rx/reg8_syn_161.b[0]
-
-Timing path: ub_lvds_rx/reg8_syn_204.clk->ub_lvds_rx/reg8_syn_161
-ub_lvds_rx/reg8_syn_204.clk
-ub_lvds_rx/reg8_syn_161
-2387 4.475000 8.112000 3.637000 1 1
-ub_lvds_rx/rx_data[16] ub_lvds_rx/reg8_syn_161.b[1]
+Timing path: ub_lvds_rx/sync0_reg_syn_4.clk->ub_lvds_rx/reg8_syn_149
+ub_lvds_rx/sync0_reg_syn_4.clk
+ub_lvds_rx/reg8_syn_149
+2393 4.324000 8.182000 3.858000 1 1
+ub_lvds_rx/sync0 ub_lvds_rx/reg8_syn_149.d[1]
Hold check
-2421 3
-Endpoint: ub_lvds_rx/ramread0_syn_32
-2423 0.167000 2 2
-Timing path: ub_lvds_rx/reg3_syn_166.clk->ub_lvds_rx/ramread0_syn_32
-ub_lvds_rx/reg3_syn_166.clk
-ub_lvds_rx/ramread0_syn_32
-2425 0.167000 2.096000 2.263000 1 1
-ub_lvds_rx/para_data[6] ub_lvds_rx/ramread0_syn_32.c[1]
+2427 3
+Endpoint: ub_lvds_rx/ramread0_syn_74
+2429 0.104000 2 2
+Timing path: ub_lvds_rx/reg3_syn_180.clk->ub_lvds_rx/ramread0_syn_74
+ub_lvds_rx/reg3_syn_180.clk
+ub_lvds_rx/ramread0_syn_74
+2431 0.104000 2.250000 2.354000 1 1
+ub_lvds_rx/para_data[18] ub_lvds_rx/ramread0_syn_74.c[1]
-Timing path: ub_lvds_rx/reg16_syn_31.clk->ub_lvds_rx/ramread0_syn_32
+Timing path: ub_lvds_rx/reg16_syn_31.clk->ub_lvds_rx/ramread0_syn_74
ub_lvds_rx/reg16_syn_31.clk
-ub_lvds_rx/ramread0_syn_32
-2459 0.336000 2.096000 2.432000 1 1
-ub_lvds_rx/wcnt[2] ub_lvds_rx/ramread0_syn_32.c[0]
+ub_lvds_rx/ramread0_syn_74
+2465 0.199000 2.250000 2.449000 1 1
+ub_lvds_rx/wcnt[2] ub_lvds_rx/ramread0_syn_74.c[0]
-Endpoint: ub_lvds_rx/ramread0_syn_18
-2493 0.167000 2 2
-Timing path: ub_lvds_rx/reg8_syn_141.clk->ub_lvds_rx/ramread0_syn_18
-ub_lvds_rx/reg8_syn_141.clk
-ub_lvds_rx/ramread0_syn_18
-2495 0.167000 2.096000 2.263000 1 1
-ub_lvds_rx/para_data[1] ub_lvds_rx/ramread0_syn_18.b[1]
+Endpoint: ub_lvds_rx/ramread0_syn_102
+2499 0.113000 2 2
+Timing path: ub_lvds_rx/reg3_syn_175.clk->ub_lvds_rx/ramread0_syn_102
+ub_lvds_rx/reg3_syn_175.clk
+ub_lvds_rx/ramread0_syn_102
+2501 0.113000 2.250000 2.363000 1 1
+ub_lvds_rx/para_data[24] ub_lvds_rx/ramread0_syn_102.a[1]
-Timing path: ub_lvds_rx/reg16_syn_31.clk->ub_lvds_rx/ramread0_syn_18
-ub_lvds_rx/reg16_syn_31.clk
-ub_lvds_rx/ramread0_syn_18
-2529 0.409000 2.096000 2.505000 1 1
-ub_lvds_rx/wcnt[1] ub_lvds_rx/ramread0_syn_18.b[0]
+Timing path: ub_lvds_rx/reg16_syn_33.clk->ub_lvds_rx/ramread0_syn_102
+ub_lvds_rx/reg16_syn_33.clk
+ub_lvds_rx/ramread0_syn_102
+2535 0.345000 2.250000 2.595000 1 1
+ub_lvds_rx/wcnt[0] ub_lvds_rx/ramread0_syn_102.a[0]
-Endpoint: ub_lvds_rx/ramread0_syn_116
-2563 0.167000 2 2
-Timing path: ub_lvds_rx/reg8_syn_169.clk->ub_lvds_rx/ramread0_syn_116
-ub_lvds_rx/reg8_syn_169.clk
-ub_lvds_rx/ramread0_syn_116
-2565 0.167000 2.096000 2.263000 1 1
-ub_lvds_rx/para_data[33] ub_lvds_rx/ramread0_syn_116.b[1]
-
-Timing path: ub_lvds_rx/reg16_syn_31.clk->ub_lvds_rx/ramread0_syn_116
-ub_lvds_rx/reg16_syn_31.clk
-ub_lvds_rx/ramread0_syn_116
-2599 0.306000 2.096000 2.402000 1 1
-ub_lvds_rx/wcnt[1] ub_lvds_rx/ramread0_syn_116.b[0]
+Endpoint: ub_lvds_rx/ramread0_syn_74
+2569 0.113000 1 1
+Timing path: ub_lvds_rx/reg3_syn_180.clk->ub_lvds_rx/ramread0_syn_74
+ub_lvds_rx/reg3_syn_180.clk
+ub_lvds_rx/ramread0_syn_74
+2571 0.113000 2.250000 2.363000 1 1
+ub_lvds_rx/para_data[19] ub_lvds_rx/ramread0_syn_74.d[1]
clock: clock_source
-2635 0 0 0
+2607 0 0 0
clock: S_clk
-2643 109546 8592 5
+2615 111938 8572 5
Setup check
-2653 3
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_93
-2653 0.015000 1 1
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk->sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_93
+2625 3
+Endpoint: reg7_syn_149
+2625 0.108000 188 3
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb->reg7_syn_149
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb
+reg7_syn_149
+2627 0.108000 11.488000 11.380000 7 7
+sampling_fe_a/u_sort/u_data_prebuffer/dou_i[1][18] adj_datao_b1[2]_syn_73.b[1]
+adj_datao_b1[2]_syn_16 adj_datao_b1[2]_syn_79.a[1]
+adj_datao_b1[2]_syn_18 sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_79.a[1]
+adj_datao_b1[2]_syn_32 sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_488.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[2] sampling_fe_a/u_sort/u_transfer_300_to_200/reg10_syn_128.b[0]
+adj_datao_b1[2]_syn_39 sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_59.a[0]
+adj_datao_b1[2]_syn_43 reg7_syn_149.a[0]
+
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb->reg7_syn_149
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb
+reg7_syn_149
+2677 0.108000 11.488000 11.380000 7 7
+sampling_fe_a/u_sort/u_data_prebuffer/dou_i[1][18] adj_datao_b1[2]_syn_73.b[1]
+adj_datao_b1[2]_syn_16 adj_datao_b1[2]_syn_79.a[1]
+adj_datao_b1[2]_syn_18 sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_79.a[1]
+adj_datao_b1[2]_syn_32 sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_488.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[2] sampling_fe_a/u_sort/u_transfer_300_to_200/reg10_syn_128.b[0]
+adj_datao_b1[2]_syn_39 sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_59.a[0]
+adj_datao_b1[2]_syn_43 reg7_syn_149.a[0]
+
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb->reg7_syn_149
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb
+reg7_syn_149
+2727 0.415000 11.488000 11.073000 7 7
+sampling_fe_a/u_sort/u_data_prebuffer/dou_i[0][18] adj_datao_b1[2]_syn_73.a[1]
+adj_datao_b1[2]_syn_16 adj_datao_b1[2]_syn_79.a[1]
+adj_datao_b1[2]_syn_18 sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_79.a[1]
+adj_datao_b1[2]_syn_32 sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_488.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[2] sampling_fe_a/u_sort/u_transfer_300_to_200/reg10_syn_128.b[0]
+adj_datao_b1[2]_syn_39 sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_59.a[0]
+adj_datao_b1[2]_syn_43 reg7_syn_149.a[0]
+
+
+Endpoint: reg7_syn_152
+2777 0.309000 114 3
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clkb->reg7_syn_152
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clkb
+reg7_syn_152
+2779 0.309000 11.488000 11.179000 7 7
+sampling_fe_a/u_sort/u_data_prebuffer/dou_i[1][45] reg6_syn_164.b[0]
+adj_datao_b1[21]_syn_22 adj_datao_b1[21]_syn_70.a[1]
+adj_datao_b1[21]_syn_26 u_bus_top/u_local_bus_slve_cis/sel23_syn_6787.a[0]
+adj_datao_b1[5]_syn_20 sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_491.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[5] u_bus_top/reg15_syn_186.a[1]
+adj_datao_b1[5]_syn_27 sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_56.a[1]
+adj_datao_b1[5]_syn_31 reg7_syn_152.a[0]
+
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb->reg7_syn_152
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb
+reg7_syn_152
+2829 0.591000 11.488000 10.897000 7 7
+sampling_fe_a/u_sort/u_data_prebuffer/dou_i[0][21] clkmipi_rstn_reg_syn_13.d[0]
+adj_datao_b1[21]_syn_24 adj_datao_b1[21]_syn_70.b[1]
+adj_datao_b1[21]_syn_26 u_bus_top/u_local_bus_slve_cis/sel23_syn_6787.a[0]
+adj_datao_b1[5]_syn_20 sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_491.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[5] u_bus_top/reg15_syn_186.a[1]
+adj_datao_b1[5]_syn_27 sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_56.a[1]
+adj_datao_b1[5]_syn_31 reg7_syn_152.a[0]
+
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst_syn_1.clkb->reg7_syn_152
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst_syn_1.clkb
+reg7_syn_152
+2879 0.607000 11.488000 10.881000 7 7
+sampling_fe_a/u_sort/u_data_prebuffer/dou_i[0][45] reg6_syn_164.a[0]
+adj_datao_b1[21]_syn_22 adj_datao_b1[21]_syn_70.a[1]
+adj_datao_b1[21]_syn_26 u_bus_top/u_local_bus_slve_cis/sel23_syn_6787.a[0]
+adj_datao_b1[5]_syn_20 sampling_fe_a/u_sort/u_transfer_300_to_200/reg11_syn_491.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/camdata_tmp[5] u_bus_top/reg15_syn_186.a[1]
+adj_datao_b1[5]_syn_27 sampling_fe_a/u_sort/u_transfer_300_to_200/reg16_syn_56.a[1]
+adj_datao_b1[5]_syn_31 reg7_syn_152.a[0]
+
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_97
+2929 0.353000 1 1
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk->sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_97
sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk
-sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_93
-2655 0.015000 4.317000 4.302000 1 2
-sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0] sampling_fe_a/u_sort/frame_start_rd_d0_reg_syn_12.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13 sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_93.mi[0]
-
-
-Endpoint: U_rgb_to_csi_pakage/S_rgb_de_1d_reg_syn_6_syn_2
-2695 0.162000 1 1
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk->U_rgb_to_csi_pakage/S_rgb_de_1d_reg_syn_6_syn_2
-sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk
-U_rgb_to_csi_pakage/S_rgb_de_1d_reg_syn_6_syn_2
-2697 0.162000 4.317000 4.155000 1 2
-sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0] sampling_fe_a/u_sort/frame_start_rd_d0_reg_syn_12.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13 U_rgb_to_csi_pakage/S_rgb_de_1d_reg_syn_6_syn_2.mi[0]
-
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_87
-2737 0.162000 1 1
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk->sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_87
-sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk
-sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_87
-2739 0.162000 4.317000 4.155000 1 2
-sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0] sampling_fe_a/u_sort/frame_start_rd_d0_reg_syn_12.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13 sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_87.mi[1]
+sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_97
+2931 0.353000 4.317000 3.964000 1 2
+sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0] sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_75.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13 sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_97.mi[0]
Hold check
-2779 3
-Endpoint: u_mipi_sot_min/reg1_syn_323
-2781 0.067000 1 1
-Timing path: u_bus_top/reg18_syn_86.clk->u_mipi_sot_min/reg1_syn_323
-u_bus_top/reg18_syn_86.clk
-u_mipi_sot_min/reg1_syn_323
-2783 0.067000 2.291000 2.358000 0 1
-u_mipi_sot_min/signal_from[0] u_mipi_sot_min/reg1_syn_323.mi[0]
+2971 3
+Endpoint: u_mipi_sot_min/reg1_syn_265
+2973 0.067000 1 1
+Timing path: u_bus_top/reg19_syn_84.clk->u_mipi_sot_min/reg1_syn_265
+u_bus_top/reg19_syn_84.clk
+u_mipi_sot_min/reg1_syn_265
+2975 0.067000 2.291000 2.358000 0 1
+u_mipi_sot_min/signal_from[3] u_mipi_sot_min/reg1_syn_265.mi[1]
-Endpoint: u_mipi_sot_min/reg1_syn_303
-2819 0.067000 1 1
-Timing path: u_bus_top/reg19_syn_77.clk->u_mipi_sot_min/reg1_syn_303
-u_bus_top/reg19_syn_77.clk
-u_mipi_sot_min/reg1_syn_303
-2821 0.067000 2.291000 2.358000 0 1
-u_mipi_sot_min/signal_from[10] u_mipi_sot_min/reg1_syn_303.mi[0]
+Endpoint: u_mipi_sot_min/reg1_syn_283
+3011 0.067000 1 1
+Timing path: u_bus_top/reg18_syn_72.clk->u_mipi_sot_min/reg1_syn_283
+u_bus_top/reg18_syn_72.clk
+u_mipi_sot_min/reg1_syn_283
+3013 0.067000 2.291000 2.358000 0 1
+u_mipi_sot_min/signal_from[2] u_mipi_sot_min/reg1_syn_283.mi[1]
-Endpoint: u_mipi_eot_min/reg1_syn_307
-2857 0.067000 1 1
-Timing path: u_bus_top/reg18_syn_69.clk->u_mipi_eot_min/reg1_syn_307
-u_bus_top/reg18_syn_69.clk
-u_mipi_eot_min/reg1_syn_307
-2859 0.067000 2.291000 2.358000 0 1
-u_mipi_eot_min/signal_from[6] u_mipi_eot_min/reg1_syn_307.mi[1]
+Endpoint: reg13_syn_43
+3049 0.075000 1 1
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/channelPart/wr_end_reg_syn_8.clk->reg13_syn_43
+sampling_fe_a/u_sort/u_data_prebuffer/channelPart/wr_end_reg_syn_8.clk
+reg13_syn_43
+3051 0.075000 2.291000 2.366000 0 1
+sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/u0_rdsoft_n/signal_from[0] reg13_syn_43.mi[0]
Recovery check
-2895 3
-Endpoint: debug[2]_syn_4
-2897 5.048000 1 1
-Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->debug[2]_syn_4
+3089 3
+Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070
+3091 5.584000 2 2
+Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
-debug[2]_syn_4
-2899 5.048000 11.374000 6.326000 1 2
-U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/reg9_syn_19_syn_2.d[0]
-U_rgb_to_csi_pakage/S_rst_n debug[2]_syn_4.rst
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070
+3093 5.584000 11.304000 5.720000 2 3
+U_rgb_to_csi_pakage/S_global_en reg21_syn_52_syn_2.d[0]
+U_rgb_to_csi_pakage/S_rst_n U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.d[0]
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070.sr
-
-Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1127_syn_2
-2939 5.167000 2 2
-Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1127_syn_2
-U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1127_syn_2
-2941 5.167000 11.304000 6.137000 2 3
-U_rgb_to_csi_pakage/S_global_en sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_535_syn_2.d[1]
-U_rgb_to_csi_pakage/S_rst_n_dup_4 U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.d[0]
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1127_syn_2.sr
-
-Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1127_syn_2
+Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070
adj_vsynco_reg_syn_5.clk
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1127_syn_2
-2983 6.190000 11.304000 5.114000 1 2
-U_rgb_to_csi_pakage/I_rgb_vsync U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.c[0]
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1127_syn_2.sr
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070
+3135 5.858000 11.304000 5.446000 1 2
+U_rgb_to_csi_pakage/I_rgb_vsync U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.c[0]
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1070.sr
-Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
-3023 5.259000 2 2
-Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
+Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2
+3175 6.014000 2 2
+Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
-3025 5.259000 11.304000 6.045000 2 3
-U_rgb_to_csi_pakage/S_global_en sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_535_syn_2.d[1]
-U_rgb_to_csi_pakage/S_rst_n_dup_4 U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.d[1]
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_20 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.sr
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2
+3177 6.014000 11.304000 5.290000 2 3
+U_rgb_to_csi_pakage/S_global_en reg21_syn_52_syn_2.d[0]
+U_rgb_to_csi_pakage/S_rst_n U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.d[0]
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2.sr
-Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
+Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2
adj_vsynco_reg_syn_5.clk
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
-3067 6.282000 11.304000 5.022000 1 2
-U_rgb_to_csi_pakage/I_rgb_vsync U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.c[1]
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_20 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.sr
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2
+3219 6.288000 11.304000 5.016000 1 2
+U_rgb_to_csi_pakage/I_rgb_vsync U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.c[0]
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1115_syn_2.sr
+
+
+Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2
+3259 6.026000 2 2
+Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2
+U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2
+3261 6.026000 11.304000 5.278000 2 3
+U_rgb_to_csi_pakage/S_global_en reg21_syn_52_syn_2.d[0]
+U_rgb_to_csi_pakage/S_rst_n U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.d[0]
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2.sr
+
+Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2
+adj_vsynco_reg_syn_5.clk
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2
+3303 6.300000 11.304000 5.004000 1 2
+U_rgb_to_csi_pakage/I_rgb_vsync U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1238_syn_2.c[0]
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1085_syn_2.sr
Removal check
-3107 3
-Endpoint: U_rgb_to_csi_pakage/reg2_syn_165_syn_2
-3109 0.915000 1 1
-Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/reg2_syn_165_syn_2
+3343 3
+Endpoint: U_rgb_to_csi_pakage/reg7_syn_145_syn_2
+3345 0.773000 1 1
+Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/reg7_syn_145_syn_2
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
-U_rgb_to_csi_pakage/reg2_syn_165_syn_2
-3111 0.915000 2.327000 3.242000 1 2
-U_rgb_to_csi_pakage/S_global_en sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_445_syn_2.d[1]
-U_rgb_to_csi_pakage/S_rst_n_dup_2 U_rgb_to_csi_pakage/reg2_syn_165_syn_2.sr
+U_rgb_to_csi_pakage/reg7_syn_145_syn_2
+3347 0.773000 2.327000 3.100000 1 2
+U_rgb_to_csi_pakage/S_global_en reg21_syn_54_syn_2.d[0]
+U_rgb_to_csi_pakage/S_rst_n_dup_4 U_rgb_to_csi_pakage/reg7_syn_145_syn_2.sr
-Endpoint: U_rgb_to_csi_pakage/reg2_syn_173_syn_2
-3151 0.915000 1 1
-Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/reg2_syn_173_syn_2
+Endpoint: U_rgb_to_csi_pakage/reg13_syn_67_syn_2
+3387 0.775000 1 1
+Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/reg13_syn_67_syn_2
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
-U_rgb_to_csi_pakage/reg2_syn_173_syn_2
-3153 0.915000 2.327000 3.242000 1 2
-U_rgb_to_csi_pakage/S_global_en sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_445_syn_2.d[1]
-U_rgb_to_csi_pakage/S_rst_n_dup_2 U_rgb_to_csi_pakage/reg2_syn_173_syn_2.sr
+U_rgb_to_csi_pakage/reg13_syn_67_syn_2
+3389 0.775000 2.327000 3.102000 1 2
+U_rgb_to_csi_pakage/S_global_en reg21_syn_52_syn_2.d[0]
+U_rgb_to_csi_pakage/S_rst_n U_rgb_to_csi_pakage/reg13_syn_67_syn_2.sr
-Endpoint: U_rgb_to_csi_pakage/eot_flag_reg_syn_6_syn_2
-3193 0.927000 1 1
-Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/eot_flag_reg_syn_6_syn_2
+Endpoint: U_rgb_to_csi_pakage/reg13_syn_79_syn_2
+3429 0.805000 1 1
+Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/reg13_syn_79_syn_2
U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
-U_rgb_to_csi_pakage/eot_flag_reg_syn_6_syn_2
-3195 0.927000 2.327000 3.254000 1 2
-U_rgb_to_csi_pakage/S_global_en sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_535_syn_2.d[0]
-U_rgb_to_csi_pakage/S_rst_n_dup_3 U_rgb_to_csi_pakage/eot_flag_reg_syn_6_syn_2.sr
+U_rgb_to_csi_pakage/reg13_syn_79_syn_2
+3431 0.805000 2.327000 3.132000 1 2
+U_rgb_to_csi_pakage/S_global_en reg21_syn_52_syn_2.d[0]
+U_rgb_to_csi_pakage/S_rst_n U_rgb_to_csi_pakage/reg13_syn_79_syn_2.sr
Period check
-3235 48
+3471 48
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst_syn_1.clkb
-3239 5.858000 1 0
+3475 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst_syn_1.clkb
-3240 5.858000 1 0
+3476 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst_syn_1.clkb
-3241 5.858000 1 0
+3477 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.clkb
-3242 5.858000 1 0
+3478 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst_syn_1.clkb
-3243 5.858000 1 0
+3479 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.clkb
-3244 5.858000 1 0
+3480 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst_syn_1.clkb
-3245 5.858000 1 0
+3481 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.clkb
-3246 5.858000 1 0
+3482 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst_syn_1.clkb
-3247 5.858000 1 0
+3483 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst_syn_1.clkb
-3248 5.858000 1 0
+3484 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst_syn_1.clkb
-3249 5.858000 1 0
+3485 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.clkb
-3250 5.858000 1 0
+3486 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst_syn_1.clkb
-3251 5.858000 1 0
+3487 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst_syn_1.clkb
-3252 5.858000 1 0
+3488 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst_syn_1.clkb
-3253 5.858000 1 0
+3489 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.clkb
-3254 5.858000 1 0
+3490 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst_syn_1.clkb
-3255 5.858000 1 0
+3491 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.clkb
-3256 5.858000 1 0
+3492 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clkb
-3257 5.858000 1 0
+3493 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clkb
-3258 5.858000 1 0
+3494 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst_syn_1.clkb
-3259 5.858000 1 0
+3495 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst_syn_1.clkb
-3260 5.858000 1 0
+3496 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.clkb
-3261 5.858000 1 0
+3497 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb
-3262 5.858000 1 0
+3498 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.clkb
-3263 5.858000 1 0
+3499 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.clkb
-3264 5.858000 1 0
+3500 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst_syn_1.clkb
-3265 5.858000 1 0
+3501 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst_syn_1.clkb
-3266 5.858000 1 0
+3502 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst_syn_1.clkb
-3267 5.858000 1 0
+3503 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst_syn_1.clkb
-3268 5.858000 1 0
+3504 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst_syn_1.clkb
-3269 5.858000 1 0
+3505 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.clkb
-3270 5.858000 1 0
+3506 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst_syn_1.clkb
-3271 5.858000 1 0
+3507 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst_syn_1.clkb
-3272 5.858000 1 0
+3508 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst_syn_1.clkb
-3273 5.858000 1 0
+3509 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst_syn_1.clkb
-3274 5.858000 1 0
+3510 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.clkb
-3275 5.858000 1 0
+3511 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst_syn_1.clkb
-3276 5.858000 1 0
+3512 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1.clkb
-3277 5.858000 1 0
+3513 5.858000 1 0
Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1.clkb
-3278 5.858000 1 0
+3514 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb
-3279 5.858000 1 0
+3515 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst_syn_1.clkb
-3280 5.858000 1 0
+3516 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.clkb
-3281 5.858000 1 0
+3517 5.858000 1 0
Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1.clkb
-3282 5.858000 1 0
+3518 5.858000 1 0
Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw
-3283 5.958000 1 0
+3519 5.958000 1 0
Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw
-3284 5.958000 1 0
+3520 5.958000 1 0
Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw
-3285 5.958000 1 0
+3521 5.958000 1 0
Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw
-3286 5.958000 1 0
+3522 5.958000 1 0
clock: clk_adc
-3287 43444 4244 4
+3523 45638 4282 4
Setup check
-3297 3
+3533 3
Endpoint: reg40_syn_14
-3297 -2.059000 2 2
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d_reg_syn_5.clk->reg40_syn_14
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d_reg_syn_5.clk
+3533 -1.797000 2 2
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk->reg40_syn_14
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk
reg40_syn_14
-3299 -2.059000 1.949000 4.008000 1 2
+3535 -1.797000 1.949000 3.746000 1 2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d reg29_syn_16.c[0]
-debug[3]_dup_1 reg40_syn_14.mi[0]
+O_clk_lp_n_dup_1 reg40_syn_14.mi[0]
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d_reg_syn_5.clk->reg40_syn_14
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d_reg_syn_5.clk
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk->reg40_syn_14
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk
reg40_syn_14
-3335 -1.810000 1.949000 3.759000 1 2
+3571 -1.738000 1.949000 3.687000 1 2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d reg29_syn_16.d[0]
-debug[3]_dup_1 reg40_syn_14.mi[0]
+O_clk_lp_n_dup_1 reg40_syn_14.mi[0]
-Endpoint: FV_MIPI_sync1_reg_syn_8
-3371 -1.362000 1 1
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d_reg_syn_5.clk->FV_MIPI_sync1_reg_syn_8
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d_reg_syn_5.clk
-FV_MIPI_sync1_reg_syn_8
-3373 -1.362000 1.949000 3.311000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d FV_MIPI_sync1_reg_syn_8.mi[0]
+Endpoint: reg41_syn_15
+3607 -1.510000 1 1
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk->reg41_syn_15
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.clk
+reg41_syn_15
+3609 -1.510000 1.949000 3.459000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d reg41_syn_15.mi[0]
-Endpoint: u_bus_top/reg12_syn_208
-3407 7.375000 1 1
-Timing path: reg27_syn_241.clk->u_bus_top/reg12_syn_208
-reg27_syn_241.clk
-u_bus_top/reg12_syn_208
-3409 7.375000 11.187000 3.812000 0 1
-lv_cnt_b[30] u_bus_top/reg12_syn_208.mi[0]
+Endpoint: u_bus_top/reg13_syn_216
+3643 6.926000 1 1
+Timing path: reg26_syn_241.clk->u_bus_top/reg13_syn_216
+reg26_syn_241.clk
+u_bus_top/reg13_syn_216
+3645 6.926000 11.187000 4.261000 0 1
+lv_cnt_a[31] u_bus_top/reg13_syn_216.mi[0]
Hold check
-3445 3
-Endpoint: u_bus_top/reg1_syn_215
-3447 0.258000 1 1
-Timing path: reg1_syn_194.clk->u_bus_top/reg1_syn_215
-reg1_syn_194.clk
-u_bus_top/reg1_syn_215
-3449 0.258000 2.191000 2.449000 0 1
-S_hs_data_reg[10] u_bus_top/reg1_syn_215.mi[0]
+3681 3
+Endpoint: u_bus_top/reg5_syn_190
+3683 0.251000 1 1
+Timing path: u_bus_top/reg4_syn_178.clk->u_bus_top/reg5_syn_190
+u_bus_top/reg4_syn_178.clk
+u_bus_top/reg5_syn_190
+3685 0.251000 2.107000 2.358000 0 1
+u_bus_top/adc_cfg_data_o_sync2d_8m[2] u_bus_top/reg5_syn_190.mi[0]
-Endpoint: u_bus_top/reg0_syn_215
-3485 0.258000 1 1
-Timing path: reg1_syn_218.clk->u_bus_top/reg0_syn_215
-reg1_syn_218.clk
-u_bus_top/reg0_syn_215
-3487 0.258000 2.191000 2.449000 0 1
-S_hs_data_reg[16] u_bus_top/reg0_syn_215.mi[0]
+Endpoint: u_bus_top/reg0_syn_220
+3719 0.258000 1 1
+Timing path: reg1_syn_184.clk->u_bus_top/reg0_syn_220
+reg1_syn_184.clk
+u_bus_top/reg0_syn_220
+3721 0.258000 2.191000 2.449000 0 1
+S_hs_data_reg[19] u_bus_top/reg0_syn_220.mi[1]
-Endpoint: u_bus_top/reg0_syn_209
-3523 0.258000 1 1
-Timing path: reg1_syn_194.clk->u_bus_top/reg0_syn_209
-reg1_syn_194.clk
-u_bus_top/reg0_syn_209
-3525 0.258000 2.191000 2.449000 0 1
-S_hs_data_reg[26] u_bus_top/reg0_syn_209.mi[0]
+Endpoint: u_bus_top/reg0_syn_217
+3757 0.258000 1 1
+Timing path: reg1_syn_181.clk->u_bus_top/reg0_syn_217
+reg1_syn_181.clk
+u_bus_top/reg0_syn_217
+3759 0.258000 2.191000 2.449000 0 1
+S_hs_data_reg[25] u_bus_top/reg0_syn_217.mi[0]
Recovery check
-3561 3
-Endpoint: scan_start_diff/reg1_syn_21
-3563 161.930000 1 1
-Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg1_syn_21
+3795 3
+Endpoint: scan_start_diff/a_ex_frame_en_reg_syn_5
+3797 163.286000 1 1
+Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/a_ex_frame_en_reg_syn_5
clkubus_rstn_reg_syn_8.clk
-scan_start_diff/reg1_syn_21
-3565 161.930000 168.504000 6.574000 1 2
-u_softrst_fan_ctrl/signal_from[0] BUSY_MIPI_sync_flag_reg_syn_12.d[0]
-BUSY_MIPI_sync_d0_i_syn_7 scan_start_diff/reg1_syn_21.sr
-
-
-Endpoint: scan_start_diff/reg1_syn_18
-3601 161.930000 1 1
-Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg1_syn_18
-clkubus_rstn_reg_syn_8.clk
-scan_start_diff/reg1_syn_18
-3603 161.930000 168.504000 6.574000 1 2
-u_softrst_fan_ctrl/signal_from[0] BUSY_MIPI_sync_flag_reg_syn_12.d[0]
-BUSY_MIPI_sync_d0_i_syn_7 scan_start_diff/reg1_syn_18.sr
+scan_start_diff/a_ex_frame_en_reg_syn_5
+3799 163.286000 168.576000 5.290000 1 2
+u_softrst_fan_ctrl/signal_from[0] u_bus_top/u_local_bus_slve_cis/reg59_syn_113.d[0]
+BUSY_MIPI_sync_d0_i_syn_8 scan_start_diff/a_ex_frame_en_reg_syn_5.sr
Endpoint: scan_start_diff/reg2_syn_19
-3639 161.953000 1 1
+3835 163.371000 1 1
Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg2_syn_19
clkubus_rstn_reg_syn_8.clk
scan_start_diff/reg2_syn_19
-3641 161.953000 168.504000 6.551000 1 2
-u_softrst_fan_ctrl/signal_from[0] BUSY_MIPI_sync_flag_reg_syn_12.d[0]
-BUSY_MIPI_sync_d0_i_syn_7 scan_start_diff/reg2_syn_19.sr
+3837 163.371000 168.576000 5.205000 1 2
+u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
+BUSY_MIPI_sync_d0_i_syn_6 scan_start_diff/reg2_syn_19.sr
+
+
+Endpoint: scan_start_diff/a_ex_frame_reg_syn_5
+3873 163.489000 1 1
+Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/a_ex_frame_reg_syn_5
+clkubus_rstn_reg_syn_8.clk
+scan_start_diff/a_ex_frame_reg_syn_5
+3875 163.489000 168.576000 5.087000 1 2
+u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
+BUSY_MIPI_sync_d0_i_syn_6 scan_start_diff/a_ex_frame_reg_syn_5.sr
Removal check
-3677 3
-Endpoint: scan_start_diff/a_ex_frame_en_reg_syn_4
-3679 2.469000 1 1
-Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/a_ex_frame_en_reg_syn_4
+3911 3
+Endpoint: scan_start_diff/reg1_syn_18
+3913 1.456000 1 1
+Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg1_syn_18
clkubus_rstn_reg_syn_8.clk
-scan_start_diff/a_ex_frame_en_reg_syn_4
-3681 2.469000 2.299000 4.768000 1 2
-u_softrst_fan_ctrl/signal_from[0] BUSY_MIPI_sync_flag_reg_syn_12.d[0]
-BUSY_MIPI_sync_d0_i_syn_7 scan_start_diff/a_ex_frame_en_reg_syn_4.sr
+scan_start_diff/reg1_syn_18
+3915 1.456000 2.236000 3.692000 1 2
+u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
+BUSY_MIPI_sync_d0_i_syn_6 scan_start_diff/reg1_syn_18.sr
-Endpoint: scan_start_diff/a_frame_pad_rog_reg_syn_5
-3717 2.618000 1 1
-Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/a_frame_pad_rog_reg_syn_5
+Endpoint: scan_start_diff/reg1_syn_21
+3951 1.562000 1 1
+Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg1_syn_21
clkubus_rstn_reg_syn_8.clk
-scan_start_diff/a_frame_pad_rog_reg_syn_5
-3719 2.618000 2.299000 4.917000 1 2
-u_softrst_fan_ctrl/signal_from[0] BUSY_MIPI_sync_flag_reg_syn_12.d[0]
-BUSY_MIPI_sync_d0_i_syn_7 scan_start_diff/a_frame_pad_rog_reg_syn_5.sr
+scan_start_diff/reg1_syn_21
+3953 1.562000 2.236000 3.798000 1 2
+u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
+BUSY_MIPI_sync_d0_i_syn_6 scan_start_diff/reg1_syn_21.sr
-Endpoint: scan_start_diff/reg2_syn_19
-3755 2.681000 1 1
-Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg2_syn_19
+Endpoint: scan_start_diff/enable_from_arm_rog_reg_syn_5
+3989 1.579000 1 1
+Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/enable_from_arm_rog_reg_syn_5
clkubus_rstn_reg_syn_8.clk
-scan_start_diff/reg2_syn_19
-3757 2.681000 2.299000 4.980000 1 2
-u_softrst_fan_ctrl/signal_from[0] BUSY_MIPI_sync_flag_reg_syn_12.d[0]
-BUSY_MIPI_sync_d0_i_syn_7 scan_start_diff/reg2_syn_19.sr
+scan_start_diff/enable_from_arm_rog_reg_syn_5
+3991 1.579000 2.236000 3.815000 1 2
+u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
+BUSY_MIPI_sync_d0_i_syn_6 scan_start_diff/enable_from_arm_rog_reg_syn_5.sr
clock: S_clk_x2
-3793 146 80 2
+4027 144 78 2
Setup check
-3803 3
-Endpoint: debug[4]_syn_1
-3803 1.881000 1 1
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.clk->debug[4]_syn_1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.clk
-debug[4]_syn_1
-3805 1.881000 6.546000 4.665000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_1d debug[4]_syn_1.do[0]
+4037 3
+Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
+4037 2.450000 2 2
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add12_syn_69.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add12_syn_69.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
+4039 2.450000 6.679000 4.229000 1 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[1] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.b[0]
-
-Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2
-3841 2.457000 2 2
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47_syn_2.clk
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2
-3843 2.457000 6.679000 4.222000 1 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[7] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.c[1]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.clk
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2
-3879 2.518000 6.679000 4.161000 1 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.b[1]
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add29_syn_70.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add29_syn_70.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
+4075 2.457000 6.679000 4.222000 1 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[5] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.c[0]
Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2
-3915 2.487000 2 2
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.clk
+4111 2.518000 2 2
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2
-3917 2.487000 6.679000 4.192000 1 1
+4113 2.518000 6.679000 4.161000 1 1
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.b[1]
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47_syn_2.clk
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2
-3953 2.831000 6.679000 3.848000 1 1
+4149 2.611000 6.679000 4.068000 1 1
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[7] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.c[1]
+Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2
+4185 2.518000 2 2
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_35_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_35_syn_2.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2
+4187 2.518000 6.679000 4.161000 1 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.b[0]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_43_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_43_syn_2.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2
+4223 2.761000 6.679000 3.918000 1 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.c[0]
+
+
Hold check
-3989 3
-Endpoint: exdev_ctl_a/u_gen_sp/add2_syn_98
-3991 0.167000 1 1
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.clk->exdev_ctl_a/u_gen_sp/add2_syn_98
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.clk
-exdev_ctl_a/u_gen_sp/add2_syn_98
-3993 0.167000 2.291000 2.458000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_en exdev_ctl_a/u_gen_sp/add2_syn_98.mi[0]
-
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[67]_syn_8
-4029 0.190000 1 1
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[77]_syn_23.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[67]_syn_8
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[77]_syn_23.clk
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[67]_syn_8
-4031 0.190000 2.291000 2.481000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[67]_syn_8.mi[0]
-
-
+4259 3
Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5
-4067 0.264000 1 1
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/adc_addr_gen/[5]$ch_addr_gen/add0_syn_62.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/adc_addr_gen/[5]$ch_addr_gen/add0_syn_62.clk
+4261 0.158000 1 1
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6_syn_2.clk
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5
-4069 0.264000 2.291000 2.555000 0 1
+4263 0.158000 2.291000 2.449000 0 1
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5.mi[0]
+Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5
+4299 0.274000 1 1
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5
+4301 0.274000 2.291000 2.565000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.mi[1]
+
+
+Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5
+4337 0.274000 1 1
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_1d_reg_syn_6_syn_2.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5
+4339 0.274000 2.291000 2.565000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_1d u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5.mi[0]
+
+
clock: S_clk_x4
-4105 32 8 2
+4375 32 8 2
Setup check
-4115 3
-Endpoint: O_data_hs_p[1]_syn_2
-4115 0.923000 4 3
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[1]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
-O_data_hs_p[1]_syn_2
-4117 0.923000 4.110000 3.187000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[1]_syn_2.do[3]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[1]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
-O_data_hs_p[1]_syn_2
-4151 1.035000 4.110000 3.075000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[1]_syn_2.do[1]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[1]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
-O_data_hs_p[1]_syn_2
-4185 1.078000 4.110000 3.032000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[1]_syn_2.do[0]
-
-
-Endpoint: O_data_hs_p[0]_syn_2
-4219 1.072000 4 3
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[0]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
-O_data_hs_p[0]_syn_2
-4221 1.072000 4.110000 3.038000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[0]_syn_2.do[0]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[0]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
-O_data_hs_p[0]_syn_2
-4255 1.075000 4.110000 3.035000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[0]_syn_2.do[3]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[0]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
-O_data_hs_p[0]_syn_2
-4289 1.075000 4.110000 3.035000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[0]_syn_2.do[1]
-
-
+4385 3
Endpoint: O_data_hs_p[3]_syn_2
-4323 1.072000 4 3
+4385 0.751000 4 3
Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[3]_syn_2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
O_data_hs_p[3]_syn_2
-4325 1.072000 4.110000 3.038000 0 1
+4387 0.751000 4.110000 3.359000 0 1
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[3]_syn_2.do[2]
Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[3]_syn_2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
O_data_hs_p[3]_syn_2
-4359 1.072000 4.110000 3.038000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[3]_syn_2.do[0]
+4421 0.751000 4.110000 3.359000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[3]_syn_2.do[1]
Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[3]_syn_2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
O_data_hs_p[3]_syn_2
-4393 1.075000 4.110000 3.035000 0 1
+4455 0.952000 4.110000 3.158000 0 1
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[3]_syn_2.do[3]
+Endpoint: O_data_hs_p[0]_syn_2
+4489 1.028000 4 3
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[0]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
+O_data_hs_p[0]_syn_2
+4491 1.028000 4.110000 3.082000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[0]_syn_2.do[2]
-Hold check
-4427 3
-Endpoint: O_data_hs_p[2]_syn_2
-4429 0.392000 4 3
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[2]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
-O_data_hs_p[2]_syn_2
-4431 0.392000 1.962000 2.354000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[2]_syn_2.do[3]
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[0]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
+O_data_hs_p[0]_syn_2
+4525 1.028000 4.110000 3.082000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[0]_syn_2.do[1]
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[2]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
-O_data_hs_p[2]_syn_2
-4465 0.507000 1.962000 2.469000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[2]_syn_2.do[2]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[2]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
-O_data_hs_p[2]_syn_2
-4499 0.508000 1.962000 2.470000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[2]_syn_2.do[1]
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[0]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
+O_data_hs_p[0]_syn_2
+4559 1.072000 4.110000 3.038000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[0]_syn_2.do[3]
Endpoint: O_data_hs_p[1]_syn_2
-4533 0.498000 4 3
+4593 1.072000 4 3
Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[1]_syn_2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
O_data_hs_p[1]_syn_2
-4535 0.498000 1.962000 2.460000 0 1
+4595 1.072000 4.110000 3.038000 0 1
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[1]_syn_2.do[2]
Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[1]_syn_2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
O_data_hs_p[1]_syn_2
-4569 0.507000 1.962000 2.469000 0 1
+4629 1.072000 4.110000 3.038000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[1]_syn_2.do[1]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[1]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
+O_data_hs_p[1]_syn_2
+4663 1.072000 4.110000 3.038000 0 1
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[1]_syn_2.do[0]
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[1]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
-O_data_hs_p[1]_syn_2
-4603 0.530000 1.962000 2.492000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[1]_syn_2.do[1]
+
+
+Hold check
+4697 3
+Endpoint: O_data_hs_p[2]_syn_2
+4699 0.507000 4 3
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[2]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
+O_data_hs_p[2]_syn_2
+4701 0.507000 1.962000 2.469000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[2]_syn_2.do[3]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[2]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
+O_data_hs_p[2]_syn_2
+4735 0.508000 1.962000 2.470000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[2]_syn_2.do[1]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[2]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
+O_data_hs_p[2]_syn_2
+4769 0.508000 1.962000 2.470000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[2]_syn_2.do[0]
Endpoint: O_data_hs_p[0]_syn_2
-4637 0.507000 4 3
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[0]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
+4803 0.517000 4 3
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[0]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
O_data_hs_p[0]_syn_2
-4639 0.507000 1.962000 2.469000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[0]_syn_2.do[2]
+4805 0.517000 1.962000 2.479000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[0]_syn_2.do[3]
Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[0]_syn_2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
O_data_hs_p[0]_syn_2
-4673 0.508000 1.962000 2.470000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[0]_syn_2.do[3]
+4839 0.517000 1.962000 2.479000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[0]_syn_2.do[0]
Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[0]_syn_2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
O_data_hs_p[0]_syn_2
-4707 0.508000 1.962000 2.470000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[0]_syn_2.do[1]
+4873 0.546000 1.962000 2.508000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[0]_syn_2.do[2]
+
+
+Endpoint: O_data_hs_p[1]_syn_2
+4907 0.517000 4 3
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[1]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
+O_data_hs_p[1]_syn_2
+4909 0.517000 1.962000 2.479000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[1]_syn_2.do[2]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[1]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
+O_data_hs_p[1]_syn_2
+4943 0.517000 1.962000 2.479000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[1]_syn_2.do[1]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[1]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
+O_data_hs_p[1]_syn_2
+4977 0.517000 1.962000 2.479000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[1]_syn_2.do[0]
clock: S_clk_x4_90d
-4741 4 2 2
+5011 4 2 2
Setup check
-4751 1
+5021 1
Endpoint: O_clk_hs_p_syn_2
-4751 -0.661000 2 2
+5021 -0.661000 2 2
Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk->O_clk_hs_p_syn_2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk
O_clk_hs_p_syn_2
-4753 -0.661000 2.374000 3.035000 0 1
+5023 -0.661000 2.374000 3.035000 0 1
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[2]
Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk->O_clk_hs_p_syn_2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk
O_clk_hs_p_syn_2
-4787 -0.658000 2.374000 3.032000 0 1
+5057 -0.658000 2.374000 3.032000 0 1
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[0]
Hold check
-4821 1
+5091 1
Endpoint: O_clk_hs_p_syn_2
-4823 2.243000 2 2
+5093 2.243000 2 2
Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk->O_clk_hs_p_syn_2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk
O_clk_hs_p_syn_2
-4825 2.243000 0.226000 2.469000 0 1
+5095 2.243000 0.226000 2.469000 0 1
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[0]
Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk->O_clk_hs_p_syn_2
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk
O_clk_hs_p_syn_2
-4859 2.244000 0.226000 2.470000 0 1
+5129 2.244000 0.226000 2.470000 0 1
u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[2]
@@ -1311,14 +1380,14 @@ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_cl
Timing group statistics:
Clock constraints:
Clock Name Min Period Max Freq Skew Fanout TNS
- S_clk (108.0MHz) 9.243ns 108.190MHz 0.326ns 1785 0.000ns
- a_pclk (48.0MHz) 12.785ns 78.217MHz 0.326ns 1421 0.000ns
- b_pclk (48.0MHz) 10.495ns 95.283MHz 0.326ns 1348 0.000ns
- clk_adc (6.0MHz) 168.723ns 5.927MHz 0.326ns 951 -3.421ns
- a_sclk (168.0MHz) 2.151ns 464.900MHz 0.254ns 69 0.000ns
- b_sclk (168.0MHz) 2.151ns 464.900MHz 0.326ns 69 0.000ns
- S_clk_x2 (216.0MHz) 2.748ns 363.901MHz 0.480ns 22 0.000ns
- S_clk_x4 (432.0MHz) 1.391ns 718.907MHz 0.018ns 4 0.000ns
+ S_clk (108.0MHz) 9.150ns 109.290MHz 0.326ns 1795 0.000ns
+ a_pclk (48.0MHz) 13.964ns 71.613MHz 0.326ns 1417 0.000ns
+ b_pclk (48.0MHz) 10.242ns 97.637MHz 0.326ns 1355 0.000ns
+ clk_adc (6.0MHz) 168.461ns 5.936MHz 0.326ns 967 -3.307ns
+ b_sclk (168.0MHz) 1.853ns 539.665MHz 0.326ns 70 0.000ns
+ a_sclk (168.0MHz) 2.239ns 446.628MHz 0.326ns 69 0.000ns
+ S_clk_x2 (216.0MHz) 2.179ns 458.926MHz 0.480ns 20 0.000ns
+ S_clk_x4 (432.0MHz) 1.563ns 639.795MHz 0.018ns 4 0.000ns
S_clk_x4_90d (432.0MHz) 2.975ns 336.000MHz 0.000ns 1 -0.661ns
Minimum input arrival time before clock: no constraint path
Maximum output required time after clock: no constraint path
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db
index cb63a17..0b89331 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db and b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db
index 87a7e67..00432b3 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db and b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/run.log b/src/prj/td_project/hg_anlogic_Runs/phy_1/run.log
index 36e1e11..eb5e064 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/run.log
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/run.log
@@ -4,7 +4,7 @@
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
Built at = 20:34:38 Mar 21 2023
Run by = holdtecs
- Run Date = Tue Jan 23 14:17:17 2024
+ Run Date = Sun Feb 18 16:12:24 2024
Run on = DESKTOP-5MQL5VE
============================================================
@@ -207,9 +207,9 @@ RUN-1001 : Import timing constraints
RUN-1001 : Import IO constraints
RUN-1001 : Import Inst constraints
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
-RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.132127s wall, 2.078125s user + 0.062500s system = 2.140625s CPU (100.4%)
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.252502s wall, 2.234375s user + 0.015625s system = 2.250000s CPU (99.9%)
-RUN-1004 : used memory is 336 MB, reserved memory is 314 MB, peak memory is 340 MB
+RUN-1004 : used memory is 337 MB, reserved memory is 315 MB, peak memory is 341 MB
RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
RUN-1002 : start command "get_ports clock_source"
RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
@@ -308,7 +308,7 @@ SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be m
SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
SYN-5055 Similar messages will be suppressed.
RUN-1002 : start command "phys_opt -simplify_lut"
-SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2946 clock/control pins, 1 other pins).
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2945 clock/control pins, 1 other pins).
SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
@@ -346,15 +346,15 @@ SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to
SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
PHY-1001 : Populate physical database on model huagao_mipi_top.
-RUN-1001 : There are total 17751 instances
-RUN-0007 : 7488 luts, 9040 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
-RUN-1001 : There are total 20329 nets
+RUN-1001 : There are total 17703 instances
+RUN-0007 : 7440 luts, 9040 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20281 nets
RUN-6004 WARNING: There are 20 nets with only 1 pin.
-RUN-1001 : 13320 nets have 2 pins
-RUN-1001 : 5543 nets have [3 - 5] pins
-RUN-1001 : 1047 nets have [6 - 10] pins
-RUN-1001 : 168 nets have [11 - 20] pins
-RUN-1001 : 177 nets have [21 - 99] pins
+RUN-1001 : 13180 nets have 2 pins
+RUN-1001 : 5799 nets have [3 - 5] pins
+RUN-1001 : 882 nets have [6 - 10] pins
+RUN-1001 : 171 nets have [11 - 20] pins
+RUN-1001 : 175 nets have [21 - 99] pins
RUN-1001 : 54 nets have 100+ pins
PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
RUN-1001 : Report Control nets information:
@@ -377,20 +377,20 @@ RUN-0007 : 12 | 76 | 56
RUN-0007 : ---------------------------
RUN-0007 : Control Set = 141
PHY-3001 : Initial placement ...
-PHY-3001 : design contains 17749 instances, 7488 luts, 9040 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1179 with 5913 pins
-PHY-0007 : Cell area utilization is 49%
+PHY-3001 : design contains 17701 instances, 7440 luts, 9040 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 5915 pins
+PHY-0007 : Cell area utilization is 48%
PHY-3001 : Start timing update ...
RUN-1002 : start command "start_timer -report"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85053, tnet num: 20151, tinst num: 17749, tnode num: 115138, tedge num: 136535.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84691, tnet num: 20103, tinst num: 17701, tnode num: 114767, tedge num: 135907.
TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in 1.151288s wall, 1.140625s user + 0.015625s system = 1.156250s CPU (100.4%)
+RUN-1003 : finish command "start_timer -report" in 1.209763s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (99.5%)
RUN-1004 : used memory is 529 MB, reserved memory is 514 MB, peak memory is 529 MB
TMR-2503 : Start to update net delay, extr mode = 2.
-TMR-2504 : Update delay of 20151 nets completely.
+TMR-2504 : Update delay of 20103 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 2.
TMR-3001 : Initiate 12 clocks from SDC.
TMR-3004 : Map sdc constraints, there are 6 constraints in total.
@@ -401,249 +401,215 @@ TMR-3003 : Constraints initiated successfully.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update; 1.944147s wall, 1.921875s user + 0.031250s system = 1.953125s CPU (100.5%)
+PHY-3001 : End timing update; 2.034946s wall, 2.015625s user + 0.015625s system = 2.031250s CPU (99.8%)
-PHY-3001 : Found 1221 cells with 2 region constraints.
+PHY-3001 : Found 1228 cells with 2 region constraints.
PHY-3001 : Global placement ...
-PHY-3001 : Initial: Len = 3.87272e+06
+PHY-3001 : Initial: Len = 3.80961e+06
PHY-3001 : Clustering ...
-PHY-3001 : Level 0 #clusters 17749.
-PHY-3001 : Level 1 #clusters 1994.
-PHY-3001 : End clustering; 0.136764s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (137.1%)
+PHY-3001 : Level 0 #clusters 17701.
+PHY-3001 : Level 1 #clusters 2034.
+PHY-3001 : End clustering; 0.139674s wall, 0.125000s user + 0.015625s system = 0.140625s CPU (100.7%)
PHY-3001 : Run with size of 4
-PHY-3001 : Cell area utilization is 49%
+PHY-3001 : Cell area utilization is 48%
PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
-PHY-3002 : Step(1): len = 1.30601e+06, overlap = 474.562
-PHY-3002 : Step(2): len = 1.18493e+06, overlap = 506.281
-PHY-3002 : Step(3): len = 888608, overlap = 546.469
-PHY-3002 : Step(4): len = 760675, overlap = 630.156
-PHY-3002 : Step(5): len = 597521, overlap = 780.781
-PHY-3002 : Step(6): len = 542110, overlap = 875.5
-PHY-3002 : Step(7): len = 477561, overlap = 954.188
-PHY-3002 : Step(8): len = 423131, overlap = 994
-PHY-3002 : Step(9): len = 382447, overlap = 1043.81
-PHY-3002 : Step(10): len = 347359, overlap = 1076.69
-PHY-3002 : Step(11): len = 310049, overlap = 1145.16
-PHY-3002 : Step(12): len = 282647, overlap = 1159.47
-PHY-3002 : Step(13): len = 258010, overlap = 1250.56
-PHY-3002 : Step(14): len = 235004, overlap = 1332.06
-PHY-3002 : Step(15): len = 212533, overlap = 1393.38
-PHY-3002 : Step(16): len = 191032, overlap = 1431.53
-PHY-3002 : Step(17): len = 176467, overlap = 1474.12
-PHY-3002 : Step(18): len = 161078, overlap = 1493.84
-PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.32138e-07
-PHY-3002 : Step(19): len = 161497, overlap = 1471
-PHY-3002 : Step(20): len = 191425, overlap = 1320.41
-PHY-3002 : Step(21): len = 194383, overlap = 1278.19
-PHY-3002 : Step(22): len = 197916, overlap = 1245.69
-PHY-3002 : Step(23): len = 191835, overlap = 1229.03
-PHY-3002 : Step(24): len = 187214, overlap = 1208.31
-PHY-3002 : Step(25): len = 183936, overlap = 1195.72
-PHY-3002 : Step(26): len = 182483, overlap = 1194.12
-PHY-3002 : Step(27): len = 181134, overlap = 1192.22
-PHY-3002 : Step(28): len = 180886, overlap = 1189.34
-PHY-3002 : Step(29): len = 179762, overlap = 1188.03
-PHY-3002 : Step(30): len = 178349, overlap = 1177.09
-PHY-3002 : Step(31): len = 177243, overlap = 1168.34
-PHY-3002 : Step(32): len = 176445, overlap = 1172.78
-PHY-3002 : Step(33): len = 174887, overlap = 1164.47
-PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.66428e-06
-PHY-3002 : Step(34): len = 178044, overlap = 1161.06
-PHY-3002 : Step(35): len = 190742, overlap = 1105.47
-PHY-3002 : Step(36): len = 195116, overlap = 1081.25
-PHY-3002 : Step(37): len = 199702, overlap = 1079.12
-PHY-3002 : Step(38): len = 201879, overlap = 1081.72
-PHY-3002 : Step(39): len = 203026, overlap = 1072.66
-PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.32855e-06
-PHY-3002 : Step(40): len = 208643, overlap = 1038.78
-PHY-3002 : Step(41): len = 222726, overlap = 1013.44
-PHY-3002 : Step(42): len = 229484, overlap = 963.5
-PHY-3002 : Step(43): len = 235024, overlap = 933.188
-PHY-3002 : Step(44): len = 236984, overlap = 913.344
-PHY-3002 : Step(45): len = 237318, overlap = 903.75
-PHY-3002 : Step(46): len = 235368, overlap = 904.75
-PHY-3001 : :::4::: Try harder cell spreading with beta_ = 6.65711e-06
-PHY-3002 : Step(47): len = 248210, overlap = 851.719
-PHY-3002 : Step(48): len = 278918, overlap = 737.625
-PHY-3002 : Step(49): len = 294865, overlap = 687.688
-PHY-3002 : Step(50): len = 301984, overlap = 639.062
-PHY-3002 : Step(51): len = 302296, overlap = 618.125
-PHY-3002 : Step(52): len = 298996, overlap = 601.25
-PHY-3002 : Step(53): len = 295627, overlap = 576.25
-PHY-3002 : Step(54): len = 293903, overlap = 572
-PHY-3002 : Step(55): len = 293415, overlap = 574.125
-PHY-3002 : Step(56): len = 294138, overlap = 580.719
-PHY-3002 : Step(57): len = 293661, overlap = 600.375
-PHY-3002 : Step(58): len = 293536, overlap = 604.656
-PHY-3002 : Step(59): len = 292948, overlap = 602.594
-PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.33142e-05
-PHY-3002 : Step(60): len = 308507, overlap = 550.5
-PHY-3002 : Step(61): len = 324193, overlap = 495.312
-PHY-3002 : Step(62): len = 327686, overlap = 449.531
-PHY-3002 : Step(63): len = 330410, overlap = 425.75
-PHY-3002 : Step(64): len = 330241, overlap = 422.875
-PHY-3002 : Step(65): len = 331715, overlap = 413.938
-PHY-3002 : Step(66): len = 331402, overlap = 424.812
-PHY-3002 : Step(67): len = 332689, overlap = 410.812
-PHY-3002 : Step(68): len = 333251, overlap = 424.719
-PHY-3002 : Step(69): len = 334428, overlap = 416
-PHY-3002 : Step(70): len = 333987, overlap = 411.344
-PHY-3001 : :::6::: Try harder cell spreading with beta_ = 2.66284e-05
-PHY-3002 : Step(71): len = 350858, overlap = 395.031
-PHY-3002 : Step(72): len = 366710, overlap = 356.281
-PHY-3002 : Step(73): len = 372324, overlap = 330.531
-PHY-3002 : Step(74): len = 373258, overlap = 322.625
-PHY-3002 : Step(75): len = 374614, overlap = 329.219
-PHY-3002 : Step(76): len = 376600, overlap = 324.75
-PHY-3002 : Step(77): len = 375732, overlap = 315.25
-PHY-3002 : Step(78): len = 375685, overlap = 313.156
-PHY-3002 : Step(79): len = 375713, overlap = 330.125
-PHY-3002 : Step(80): len = 377146, overlap = 328.531
-PHY-3002 : Step(81): len = 377875, overlap = 321.656
-PHY-3002 : Step(82): len = 378086, overlap = 327.344
-PHY-3002 : Step(83): len = 377607, overlap = 329.281
-PHY-3002 : Step(84): len = 378911, overlap = 329.75
-PHY-3002 : Step(85): len = 379833, overlap = 331.062
-PHY-3002 : Step(86): len = 379099, overlap = 325.656
-PHY-3002 : Step(87): len = 377846, overlap = 336
-PHY-3002 : Step(88): len = 379514, overlap = 345.781
-PHY-3002 : Step(89): len = 379723, overlap = 340.781
-PHY-3002 : Step(90): len = 378264, overlap = 328.031
-PHY-3002 : Step(91): len = 376984, overlap = 312.312
-PHY-3002 : Step(92): len = 377082, overlap = 303.562
-PHY-3001 : :::7::: Try harder cell spreading with beta_ = 5.32569e-05
-PHY-3002 : Step(93): len = 392649, overlap = 267.156
-PHY-3002 : Step(94): len = 401156, overlap = 257.219
-PHY-3002 : Step(95): len = 399349, overlap = 253.625
-PHY-3002 : Step(96): len = 400584, overlap = 252.25
-PHY-3002 : Step(97): len = 405095, overlap = 243.656
-PHY-3002 : Step(98): len = 407456, overlap = 248.375
-PHY-3002 : Step(99): len = 405200, overlap = 249.156
-PHY-3002 : Step(100): len = 405964, overlap = 241.562
-PHY-3002 : Step(101): len = 408588, overlap = 239.031
-PHY-3002 : Step(102): len = 410648, overlap = 236.75
-PHY-3002 : Step(103): len = 408651, overlap = 253.25
-PHY-3002 : Step(104): len = 409698, overlap = 239.938
-PHY-3002 : Step(105): len = 410964, overlap = 225.375
-PHY-3002 : Step(106): len = 411994, overlap = 224.438
-PHY-3002 : Step(107): len = 410657, overlap = 240.094
-PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000100885
-PHY-3002 : Step(108): len = 424786, overlap = 192.031
-PHY-3002 : Step(109): len = 433350, overlap = 178.344
-PHY-3002 : Step(110): len = 431515, overlap = 194.531
-PHY-3002 : Step(111): len = 431726, overlap = 195.469
-PHY-3002 : Step(112): len = 433899, overlap = 186.469
-PHY-3002 : Step(113): len = 436013, overlap = 183.812
-PHY-3002 : Step(114): len = 434689, overlap = 184.969
-PHY-3002 : Step(115): len = 435618, overlap = 188.438
-PHY-3002 : Step(116): len = 438352, overlap = 179.25
-PHY-3002 : Step(117): len = 440041, overlap = 177.219
-PHY-3002 : Step(118): len = 437621, overlap = 182.281
-PHY-3002 : Step(119): len = 437311, overlap = 186.656
-PHY-3002 : Step(120): len = 438832, overlap = 188.656
-PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.00020177
-PHY-3002 : Step(121): len = 452573, overlap = 166.75
-PHY-3002 : Step(122): len = 463883, overlap = 160.531
-PHY-3002 : Step(123): len = 463057, overlap = 164.375
-PHY-3002 : Step(124): len = 463732, overlap = 162.938
-PHY-3002 : Step(125): len = 467568, overlap = 155.625
-PHY-3002 : Step(126): len = 469787, overlap = 147.625
-PHY-3002 : Step(127): len = 467186, overlap = 154.875
-PHY-3002 : Step(128): len = 467498, overlap = 160.344
-PHY-3002 : Step(129): len = 471916, overlap = 159.938
-PHY-3002 : Step(130): len = 476564, overlap = 158.031
-PHY-3002 : Step(131): len = 475316, overlap = 157.656
-PHY-3002 : Step(132): len = 476957, overlap = 151.562
-PHY-3002 : Step(133): len = 480076, overlap = 137.531
-PHY-3002 : Step(134): len = 481577, overlap = 143.375
-PHY-3002 : Step(135): len = 478954, overlap = 144.094
-PHY-3002 : Step(136): len = 478190, overlap = 151.031
-PHY-3002 : Step(137): len = 479214, overlap = 143.906
-PHY-3002 : Step(138): len = 479721, overlap = 136.656
-PHY-3002 : Step(139): len = 477756, overlap = 143.375
-PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000386982
-PHY-3002 : Step(140): len = 485476, overlap = 141.969
-PHY-3002 : Step(141): len = 490130, overlap = 140.094
-PHY-3002 : Step(142): len = 490142, overlap = 138.562
-PHY-3002 : Step(143): len = 490546, overlap = 138.25
-PHY-3002 : Step(144): len = 493148, overlap = 136.219
-PHY-3002 : Step(145): len = 494805, overlap = 136.406
-PHY-3002 : Step(146): len = 493651, overlap = 134.281
-PHY-3002 : Step(147): len = 494099, overlap = 131.25
-PHY-3002 : Step(148): len = 496842, overlap = 135.188
-PHY-3002 : Step(149): len = 497787, overlap = 131.844
-PHY-3002 : Step(150): len = 496249, overlap = 128.438
-PHY-3002 : Step(151): len = 495742, overlap = 126.25
-PHY-3002 : Step(152): len = 497768, overlap = 128.281
-PHY-3002 : Step(153): len = 500219, overlap = 121.375
-PHY-3002 : Step(154): len = 498341, overlap = 121.656
-PHY-3002 : Step(155): len = 497917, overlap = 120.594
-PHY-3002 : Step(156): len = 498871, overlap = 124.438
-PHY-3002 : Step(157): len = 499321, overlap = 122.438
-PHY-3002 : Step(158): len = 497960, overlap = 120
-PHY-3002 : Step(159): len = 497620, overlap = 119.312
-PHY-3002 : Step(160): len = 498664, overlap = 111.344
-PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000742668
-PHY-3002 : Step(161): len = 503009, overlap = 114.906
-PHY-3002 : Step(162): len = 509106, overlap = 109.906
-PHY-3002 : Step(163): len = 511173, overlap = 108.875
-PHY-3002 : Step(164): len = 513152, overlap = 111.062
-PHY-3002 : Step(165): len = 515282, overlap = 108.969
-PHY-3002 : Step(166): len = 516304, overlap = 108.844
-PHY-3002 : Step(167): len = 515433, overlap = 105.344
-PHY-3002 : Step(168): len = 515361, overlap = 107.125
-PHY-3002 : Step(169): len = 515851, overlap = 108.031
-PHY-3002 : Step(170): len = 516005, overlap = 107.719
-PHY-3002 : Step(171): len = 516141, overlap = 106.219
-PHY-3002 : Step(172): len = 516523, overlap = 106.594
-PHY-3002 : Step(173): len = 517028, overlap = 106.844
-PHY-3002 : Step(174): len = 517144, overlap = 108.719
-PHY-3002 : Step(175): len = 516992, overlap = 101.969
-PHY-3002 : Step(176): len = 517020, overlap = 102.719
-PHY-3002 : Step(177): len = 517600, overlap = 106.25
-PHY-3002 : Step(178): len = 517953, overlap = 106.625
-PHY-3002 : Step(179): len = 518160, overlap = 104.312
-PHY-3002 : Step(180): len = 518291, overlap = 101.75
-PHY-3002 : Step(181): len = 519237, overlap = 104.812
-PHY-3002 : Step(182): len = 520219, overlap = 108.5
-PHY-3002 : Step(183): len = 520115, overlap = 106.375
-PHY-3002 : Step(184): len = 520095, overlap = 106.312
-PHY-3002 : Step(185): len = 519921, overlap = 106.875
-PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00124578
-PHY-3002 : Step(186): len = 522739, overlap = 106.906
-PHY-3002 : Step(187): len = 526133, overlap = 105.469
-PHY-3002 : Step(188): len = 526360, overlap = 103.844
-PHY-3002 : Step(189): len = 526641, overlap = 106.594
-PHY-3002 : Step(190): len = 527781, overlap = 107.656
-PHY-3002 : Step(191): len = 528332, overlap = 107.344
-PHY-3002 : Step(192): len = 527947, overlap = 107.625
-PHY-3002 : Step(193): len = 527903, overlap = 106.562
-PHY-3002 : Step(194): len = 529107, overlap = 108.312
-PHY-3002 : Step(195): len = 529741, overlap = 106.438
-PHY-3002 : Step(196): len = 529501, overlap = 106.219
-PHY-3002 : Step(197): len = 529490, overlap = 106.719
-PHY-3002 : Step(198): len = 530139, overlap = 106
-PHY-3002 : Step(199): len = 530782, overlap = 104.594
-PHY-3002 : Step(200): len = 530670, overlap = 105.5
-PHY-3002 : Step(201): len = 530708, overlap = 105.656
-PHY-3002 : Step(202): len = 531472, overlap = 104.75
-PHY-3002 : Step(203): len = 532282, overlap = 105.062
-PHY-3002 : Step(204): len = 532287, overlap = 104.875
-PHY-3002 : Step(205): len = 532448, overlap = 105.25
-PHY-3002 : Step(206): len = 532959, overlap = 100.25
-PHY-3002 : Step(207): len = 533182, overlap = 100.594
-PHY-3002 : Step(208): len = 533715, overlap = 98.4062
-PHY-3002 : Step(209): len = 534982, overlap = 102.031
-PHY-3002 : Step(210): len = 536265, overlap = 99.8125
-PHY-3002 : Step(211): len = 536721, overlap = 97.6875
-PHY-3002 : Step(212): len = 536982, overlap = 100.156
-PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00203865
-PHY-3002 : Step(213): len = 538210, overlap = 98.1875
-PHY-3002 : Step(214): len = 538767, overlap = 100.219
-PHY-3002 : Step(215): len = 539065, overlap = 100.781
+PHY-3002 : Step(1): len = 1.28216e+06, overlap = 479.625
+PHY-3002 : Step(2): len = 1.16629e+06, overlap = 466.594
+PHY-3002 : Step(3): len = 879184, overlap = 563.188
+PHY-3002 : Step(4): len = 778763, overlap = 603.531
+PHY-3002 : Step(5): len = 610007, overlap = 698.5
+PHY-3002 : Step(6): len = 553353, overlap = 793.531
+PHY-3002 : Step(7): len = 483397, overlap = 865.125
+PHY-3002 : Step(8): len = 428045, overlap = 948.875
+PHY-3002 : Step(9): len = 387650, overlap = 1027.94
+PHY-3002 : Step(10): len = 347429, overlap = 1091.44
+PHY-3002 : Step(11): len = 320060, overlap = 1115.94
+PHY-3002 : Step(12): len = 291839, overlap = 1155.03
+PHY-3002 : Step(13): len = 261286, overlap = 1162.31
+PHY-3002 : Step(14): len = 241329, overlap = 1257.91
+PHY-3002 : Step(15): len = 218162, overlap = 1327.19
+PHY-3002 : Step(16): len = 201977, overlap = 1380.91
+PHY-3002 : Step(17): len = 188610, overlap = 1409.34
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.17875e-06
+PHY-3002 : Step(18): len = 192522, overlap = 1393.97
+PHY-3002 : Step(19): len = 219286, overlap = 1267.19
+PHY-3002 : Step(20): len = 216608, overlap = 1219.03
+PHY-3002 : Step(21): len = 221491, overlap = 1189.69
+PHY-3002 : Step(22): len = 217335, overlap = 1176.91
+PHY-3002 : Step(23): len = 213907, overlap = 1169
+PHY-3002 : Step(24): len = 207477, overlap = 1155.03
+PHY-3002 : Step(25): len = 204839, overlap = 1121.84
+PHY-3002 : Step(26): len = 201758, overlap = 1095.22
+PHY-3002 : Step(27): len = 199103, overlap = 1074.72
+PHY-3002 : Step(28): len = 195864, overlap = 1068.25
+PHY-3002 : Step(29): len = 194181, overlap = 1056.53
+PHY-3002 : Step(30): len = 190914, overlap = 1055.34
+PHY-3002 : Step(31): len = 190364, overlap = 1063.09
+PHY-3002 : Step(32): len = 189352, overlap = 1080.78
+PHY-3002 : Step(33): len = 188271, overlap = 1086.03
+PHY-3002 : Step(34): len = 187676, overlap = 1096.19
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.35749e-06
+PHY-3002 : Step(35): len = 191338, overlap = 1089.16
+PHY-3002 : Step(36): len = 206908, overlap = 1048.03
+PHY-3002 : Step(37): len = 212447, overlap = 1036.25
+PHY-3002 : Step(38): len = 216650, overlap = 1013.75
+PHY-3002 : Step(39): len = 217121, overlap = 1007.72
+PHY-3002 : Step(40): len = 218523, overlap = 984.438
+PHY-3002 : Step(41): len = 218264, overlap = 975.406
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.71498e-06
+PHY-3002 : Step(42): len = 226950, overlap = 968.812
+PHY-3002 : Step(43): len = 245710, overlap = 872.906
+PHY-3002 : Step(44): len = 257664, overlap = 797.438
+PHY-3002 : Step(45): len = 266586, overlap = 762.031
+PHY-3002 : Step(46): len = 271617, overlap = 731.906
+PHY-3002 : Step(47): len = 274607, overlap = 691.5
+PHY-3002 : Step(48): len = 276377, overlap = 653.438
+PHY-3002 : Step(49): len = 276817, overlap = 646.938
+PHY-3002 : Step(50): len = 276581, overlap = 660.125
+PHY-3002 : Step(51): len = 276637, overlap = 682.438
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.42996e-06
+PHY-3002 : Step(52): len = 292794, overlap = 631.031
+PHY-3002 : Step(53): len = 315192, overlap = 541.281
+PHY-3002 : Step(54): len = 325580, overlap = 488.906
+PHY-3002 : Step(55): len = 330349, overlap = 470.656
+PHY-3002 : Step(56): len = 330984, overlap = 479.5
+PHY-3002 : Step(57): len = 329740, overlap = 469.5
+PHY-3002 : Step(58): len = 328432, overlap = 476.188
+PHY-3002 : Step(59): len = 329101, overlap = 476
+PHY-3002 : Step(60): len = 327860, overlap = 473.656
+PHY-3002 : Step(61): len = 327626, overlap = 460.375
+PHY-3002 : Step(62): len = 326421, overlap = 465.219
+PHY-3002 : Step(63): len = 326449, overlap = 460.844
+PHY-3002 : Step(64): len = 325947, overlap = 463.781
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.88599e-05
+PHY-3002 : Step(65): len = 345594, overlap = 405.844
+PHY-3002 : Step(66): len = 358504, overlap = 380.375
+PHY-3002 : Step(67): len = 361349, overlap = 342.25
+PHY-3002 : Step(68): len = 363338, overlap = 326.031
+PHY-3002 : Step(69): len = 363377, overlap = 309.844
+PHY-3002 : Step(70): len = 364627, overlap = 326.219
+PHY-3002 : Step(71): len = 365087, overlap = 328.219
+PHY-3002 : Step(72): len = 365792, overlap = 333.594
+PHY-3002 : Step(73): len = 364897, overlap = 330.188
+PHY-3002 : Step(74): len = 365206, overlap = 329.875
+PHY-3002 : Step(75): len = 363871, overlap = 332.094
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.77199e-05
+PHY-3002 : Step(76): len = 383140, overlap = 311.875
+PHY-3002 : Step(77): len = 395177, overlap = 289.969
+PHY-3002 : Step(78): len = 395172, overlap = 281.938
+PHY-3002 : Step(79): len = 396342, overlap = 263.188
+PHY-3002 : Step(80): len = 399773, overlap = 272.594
+PHY-3002 : Step(81): len = 403999, overlap = 252.812
+PHY-3002 : Step(82): len = 402545, overlap = 237.156
+PHY-3002 : Step(83): len = 402877, overlap = 213.281
+PHY-3002 : Step(84): len = 404121, overlap = 220.188
+PHY-3002 : Step(85): len = 405404, overlap = 208.75
+PHY-3002 : Step(86): len = 404198, overlap = 210.375
+PHY-3002 : Step(87): len = 404719, overlap = 206.062
+PHY-3002 : Step(88): len = 405666, overlap = 203.531
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.54397e-05
+PHY-3002 : Step(89): len = 422768, overlap = 199
+PHY-3002 : Step(90): len = 433682, overlap = 201.625
+PHY-3002 : Step(91): len = 431641, overlap = 196.031
+PHY-3002 : Step(92): len = 430725, overlap = 188.062
+PHY-3002 : Step(93): len = 432978, overlap = 187.25
+PHY-3002 : Step(94): len = 435457, overlap = 191.875
+PHY-3002 : Step(95): len = 433279, overlap = 195.875
+PHY-3002 : Step(96): len = 435016, overlap = 188.656
+PHY-3002 : Step(97): len = 438049, overlap = 188.688
+PHY-3002 : Step(98): len = 438940, overlap = 184.656
+PHY-3002 : Step(99): len = 437194, overlap = 189.844
+PHY-3002 : Step(100): len = 437650, overlap = 189.219
+PHY-3002 : Step(101): len = 438669, overlap = 183.594
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000150879
+PHY-3002 : Step(102): len = 451568, overlap = 191.656
+PHY-3002 : Step(103): len = 458537, overlap = 182.375
+PHY-3002 : Step(104): len = 458416, overlap = 164.906
+PHY-3002 : Step(105): len = 459084, overlap = 159.875
+PHY-3002 : Step(106): len = 460562, overlap = 160.438
+PHY-3002 : Step(107): len = 461926, overlap = 168.562
+PHY-3002 : Step(108): len = 460202, overlap = 162.594
+PHY-3002 : Step(109): len = 461085, overlap = 163.625
+PHY-3002 : Step(110): len = 463855, overlap = 157.969
+PHY-3002 : Step(111): len = 466293, overlap = 153.281
+PHY-3002 : Step(112): len = 465161, overlap = 163.906
+PHY-3002 : Step(113): len = 465966, overlap = 159.062
+PHY-3002 : Step(114): len = 468286, overlap = 147.875
+PHY-3002 : Step(115): len = 469272, overlap = 143.812
+PHY-3002 : Step(116): len = 467852, overlap = 146.781
+PHY-3002 : Step(117): len = 468130, overlap = 146.781
+PHY-3002 : Step(118): len = 470349, overlap = 145.562
+PHY-3002 : Step(119): len = 471970, overlap = 149.188
+PHY-3002 : Step(120): len = 470240, overlap = 150.781
+PHY-3002 : Step(121): len = 470218, overlap = 152.906
+PHY-3002 : Step(122): len = 471502, overlap = 158.875
+PHY-3002 : Step(123): len = 472437, overlap = 157
+PHY-3002 : Step(124): len = 471668, overlap = 161.594
+PHY-3002 : Step(125): len = 471740, overlap = 160.219
+PHY-3002 : Step(126): len = 472430, overlap = 161.719
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000301759
+PHY-3002 : Step(127): len = 481561, overlap = 157.75
+PHY-3002 : Step(128): len = 491291, overlap = 148.5
+PHY-3002 : Step(129): len = 495046, overlap = 138.031
+PHY-3002 : Step(130): len = 496710, overlap = 134.188
+PHY-3002 : Step(131): len = 498607, overlap = 129.844
+PHY-3002 : Step(132): len = 499874, overlap = 130.438
+PHY-3002 : Step(133): len = 498023, overlap = 130.094
+PHY-3002 : Step(134): len = 497863, overlap = 133
+PHY-3002 : Step(135): len = 499555, overlap = 133
+PHY-3002 : Step(136): len = 500548, overlap = 124.969
+PHY-3002 : Step(137): len = 499129, overlap = 125.719
+PHY-3002 : Step(138): len = 498751, overlap = 127
+PHY-3002 : Step(139): len = 499579, overlap = 130.312
+PHY-3002 : Step(140): len = 500234, overlap = 129.875
+PHY-3002 : Step(141): len = 499512, overlap = 130.406
+PHY-3002 : Step(142): len = 499876, overlap = 132.219
+PHY-3002 : Step(143): len = 501054, overlap = 132.281
+PHY-3002 : Step(144): len = 501728, overlap = 135.094
+PHY-3002 : Step(145): len = 500931, overlap = 129.344
+PHY-3002 : Step(146): len = 500875, overlap = 130.469
+PHY-3002 : Step(147): len = 501276, overlap = 127.719
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000595753
+PHY-3002 : Step(148): len = 508170, overlap = 120.156
+PHY-3002 : Step(149): len = 513247, overlap = 115.562
+PHY-3002 : Step(150): len = 513677, overlap = 112.656
+PHY-3002 : Step(151): len = 514601, overlap = 115.906
+PHY-3002 : Step(152): len = 515876, overlap = 109.062
+PHY-3002 : Step(153): len = 517064, overlap = 110.969
+PHY-3002 : Step(154): len = 517158, overlap = 109.438
+PHY-3002 : Step(155): len = 517550, overlap = 115.094
+PHY-3002 : Step(156): len = 518867, overlap = 109.156
+PHY-3002 : Step(157): len = 519944, overlap = 101.531
+PHY-3002 : Step(158): len = 519809, overlap = 102.156
+PHY-3002 : Step(159): len = 519917, overlap = 104.344
+PHY-3002 : Step(160): len = 519662, overlap = 104.531
+PHY-3002 : Step(161): len = 519991, overlap = 106
+PHY-3002 : Step(162): len = 520598, overlap = 107.938
+PHY-3002 : Step(163): len = 521229, overlap = 101.469
+PHY-3002 : Step(164): len = 520862, overlap = 102.031
+PHY-3002 : Step(165): len = 520876, overlap = 102.094
+PHY-3002 : Step(166): len = 520991, overlap = 99.8438
+PHY-3002 : Step(167): len = 521046, overlap = 102.344
+PHY-3002 : Step(168): len = 520694, overlap = 104.531
+PHY-3002 : Step(169): len = 521123, overlap = 105.562
+PHY-3002 : Step(170): len = 521670, overlap = 103.312
+PHY-3002 : Step(171): len = 521936, overlap = 103.594
+PHY-3002 : Step(172): len = 521952, overlap = 101.719
+PHY-3002 : Step(173): len = 522327, overlap = 104.531
+PHY-3002 : Step(174): len = 522609, overlap = 104.156
+PHY-3002 : Step(175): len = 522585, overlap = 104.156
+PHY-3002 : Step(176): len = 521950, overlap = 103.969
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00101933
+PHY-3002 : Step(177): len = 524620, overlap = 106.344
+PHY-3002 : Step(178): len = 527198, overlap = 104.719
+PHY-3002 : Step(179): len = 528003, overlap = 102.719
+PHY-3002 : Step(180): len = 528529, overlap = 101.5
+PHY-3002 : Step(181): len = 529519, overlap = 101.969
+PHY-3002 : Step(182): len = 529809, overlap = 102
+PHY-3002 : Step(183): len = 529605, overlap = 102.531
PHY-3001 : Legalization ...
-PHY-3001 : End legalization; 0.012220s wall, 0.031250s user + 0.031250s system = 0.062500s CPU (511.5%)
+PHY-3001 : End legalization; 0.019461s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (80.3%)
PHY-3001 : Run with size of 4
PHY-3001 : Cell area utilization is 56%
@@ -651,128 +617,126 @@ PHY-3001 : Analyzing congestion ...
RUN-1001 : Generating global routing grids ...
RUN-1001 : Building simple global routing graph ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 0/20329.
+PHY-1001 : Reuse net number 0/20281.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 703024, over cnt = 1596(4%), over = 7137, worst = 30
-PHY-1001 : End global iterations; 0.678343s wall, 0.875000s user + 0.046875s system = 0.921875s CPU (135.9%)
+PHY-1002 : len = 683856, over cnt = 1540(4%), over = 6849, worst = 32
+PHY-1001 : End global iterations; 0.806200s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (133.7%)
-PHY-1001 : Congestion index: top1 = 77.74, top5 = 59.26, top10 = 50.61, top15 = 45.51.
-PHY-3001 : End congestion estimation; 0.910671s wall, 1.109375s user + 0.046875s system = 1.156250s CPU (127.0%)
+PHY-1001 : Congestion index: top1 = 72.93, top5 = 56.93, top10 = 49.43, top15 = 44.73.
+PHY-3001 : End congestion estimation; 1.057142s wall, 1.312500s user + 0.015625s system = 1.328125s CPU (125.6%)
PHY-3001 : Update density targets...
PHY-3001 : Update congestion history...
PHY-3001 : Update timing in global mode ...
TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 20151 nets completely.
+TMR-2504 : Update delay of 20103 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 5.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update; 0.834517s wall, 0.812500s user + 0.031250s system = 0.843750s CPU (101.1%)
+PHY-3001 : End timing update; 0.906378s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (100.0%)
-PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000123338
-PHY-3002 : Step(216): len = 636013, overlap = 55.25
-PHY-3002 : Step(217): len = 643950, overlap = 56.0312
-PHY-3002 : Step(218): len = 640757, overlap = 58.4062
-PHY-3002 : Step(219): len = 641452, overlap = 57.875
-PHY-3002 : Step(220): len = 641226, overlap = 54.8125
-PHY-3002 : Step(221): len = 640747, overlap = 47.6562
-PHY-3002 : Step(222): len = 638327, overlap = 45.625
-PHY-3002 : Step(223): len = 638249, overlap = 39.3438
-PHY-3002 : Step(224): len = 638212, overlap = 36.0312
-PHY-3002 : Step(225): len = 635699, overlap = 34.4062
-PHY-3002 : Step(226): len = 634217, overlap = 33
-PHY-3002 : Step(227): len = 631546, overlap = 32.1562
-PHY-3002 : Step(228): len = 630418, overlap = 34.9688
-PHY-3002 : Step(229): len = 628930, overlap = 33.3438
-PHY-3002 : Step(230): len = 627735, overlap = 31.4688
-PHY-3002 : Step(231): len = 627632, overlap = 30.0625
-PHY-3002 : Step(232): len = 626140, overlap = 33.4688
-PHY-3002 : Step(233): len = 624809, overlap = 29.5938
-PHY-3002 : Step(234): len = 623738, overlap = 30.0625
-PHY-3002 : Step(235): len = 622396, overlap = 28.3438
-PHY-3002 : Step(236): len = 622091, overlap = 27.7812
-PHY-3002 : Step(237): len = 620449, overlap = 25.5938
-PHY-3002 : Step(238): len = 619583, overlap = 26.5
-PHY-3002 : Step(239): len = 618849, overlap = 23.9375
-PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000246677
-PHY-3002 : Step(240): len = 620967, overlap = 23.0625
-PHY-3002 : Step(241): len = 622322, overlap = 23.4375
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000117893
+PHY-3002 : Step(184): len = 619912, overlap = 37.3125
+PHY-3002 : Step(185): len = 625258, overlap = 40.3438
+PHY-3002 : Step(186): len = 619999, overlap = 41.1875
+PHY-3002 : Step(187): len = 618039, overlap = 46.5
+PHY-3002 : Step(188): len = 619855, overlap = 48.0625
+PHY-3002 : Step(189): len = 617680, overlap = 44.5625
+PHY-3002 : Step(190): len = 615660, overlap = 44.2812
+PHY-3002 : Step(191): len = 615121, overlap = 38.375
+PHY-3002 : Step(192): len = 613095, overlap = 32.5625
+PHY-3002 : Step(193): len = 612369, overlap = 32.7812
+PHY-3002 : Step(194): len = 609716, overlap = 31.7812
+PHY-3002 : Step(195): len = 608656, overlap = 30.7188
+PHY-3002 : Step(196): len = 606789, overlap = 31.4062
+PHY-3002 : Step(197): len = 606288, overlap = 31.5938
+PHY-3002 : Step(198): len = 604330, overlap = 28.7188
+PHY-3002 : Step(199): len = 603101, overlap = 25.875
+PHY-3002 : Step(200): len = 601975, overlap = 24.9062
+PHY-3002 : Step(201): len = 601508, overlap = 23.7188
+PHY-3002 : Step(202): len = 601148, overlap = 23.3125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000235786
+PHY-3002 : Step(203): len = 602900, overlap = 22.1875
+PHY-3002 : Step(204): len = 605450, overlap = 21.625
+PHY-3002 : Step(205): len = 610775, overlap = 20.875
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000463887
+PHY-3002 : Step(206): len = 619828, overlap = 19.5625
+PHY-3002 : Step(207): len = 630216, overlap = 18.0312
+PHY-3002 : Step(208): len = 635697, overlap = 17.0938
+PHY-3002 : Step(209): len = 638971, overlap = 16.0625
+PHY-3002 : Step(210): len = 643006, overlap = 15.0312
+PHY-3002 : Step(211): len = 644334, overlap = 13.4062
+PHY-3002 : Step(212): len = 646449, overlap = 14
+PHY-3002 : Step(213): len = 648472, overlap = 12.4375
PHY-3001 : Run with size of 2
PHY-3001 : Cell area utilization is 56%
PHY-3001 : Analyzing congestion ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 87/20329.
+PHY-1001 : Reuse net number 73/20281.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 714912, over cnt = 2587(7%), over = 10815, worst = 40
-PHY-1001 : End global iterations; 1.735002s wall, 2.187500s user + 0.000000s system = 2.187500s CPU (126.1%)
+PHY-1002 : len = 735472, over cnt = 2714(7%), over = 12154, worst = 36
+PHY-1001 : End global iterations; 1.745193s wall, 2.343750s user + 0.031250s system = 2.375000s CPU (136.1%)
-PHY-1001 : Congestion index: top1 = 78.66, top5 = 62.56, top10 = 54.88, top15 = 50.20.
-PHY-3001 : End congestion estimation; 2.005304s wall, 2.468750s user + 0.000000s system = 2.468750s CPU (123.1%)
+PHY-1001 : Congestion index: top1 = 80.47, top5 = 65.06, top10 = 57.39, top15 = 52.62.
+PHY-3001 : End congestion estimation; 2.034568s wall, 2.640625s user + 0.031250s system = 2.671875s CPU (131.3%)
PHY-3001 : Update density targets...
PHY-3001 : Update congestion history...
PHY-3001 : Update timing in global mode ...
TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 20151 nets completely.
+TMR-2504 : Update delay of 20103 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 5.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update; 1.061254s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (100.1%)
+PHY-3001 : End timing update; 0.926961s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (99.5%)
-PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.60391e-05
-PHY-3002 : Step(242): len = 620665, overlap = 248.531
-PHY-3002 : Step(243): len = 624625, overlap = 204.375
-PHY-3002 : Step(244): len = 622386, overlap = 179.219
-PHY-3002 : Step(245): len = 620594, overlap = 166.312
-PHY-3002 : Step(246): len = 621554, overlap = 154.219
-PHY-3002 : Step(247): len = 617100, overlap = 146.406
-PHY-3002 : Step(248): len = 614371, overlap = 144.625
-PHY-3002 : Step(249): len = 611794, overlap = 143.844
-PHY-3002 : Step(250): len = 608880, overlap = 141.625
-PHY-3002 : Step(251): len = 606596, overlap = 140.75
-PHY-3002 : Step(252): len = 604151, overlap = 142.594
-PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000192078
-PHY-3002 : Step(253): len = 604228, overlap = 141.25
-PHY-3002 : Step(254): len = 605307, overlap = 139.594
-PHY-3002 : Step(255): len = 608528, overlap = 132.844
-PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000384156
-PHY-3002 : Step(256): len = 614231, overlap = 120.531
-PHY-3002 : Step(257): len = 620121, overlap = 111.188
-PHY-3002 : Step(258): len = 625256, overlap = 105.062
-PHY-3002 : Step(259): len = 625448, overlap = 101.094
-PHY-3002 : Step(260): len = 626224, overlap = 106.938
-PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000768313
-PHY-3002 : Step(261): len = 629764, overlap = 100.938
-PHY-3002 : Step(262): len = 637326, overlap = 99
-PHY-3002 : Step(263): len = 643260, overlap = 99.4062
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000126876
+PHY-3002 : Step(214): len = 641840, overlap = 242.125
+PHY-3002 : Step(215): len = 643778, overlap = 194.875
+PHY-3002 : Step(216): len = 636240, overlap = 186.906
+PHY-3002 : Step(217): len = 631784, overlap = 173.156
+PHY-3002 : Step(218): len = 627649, overlap = 166.156
+PHY-3002 : Step(219): len = 625175, overlap = 157.625
+PHY-3002 : Step(220): len = 620478, overlap = 156.344
+PHY-3002 : Step(221): len = 617497, overlap = 143.594
+PHY-3002 : Step(222): len = 614855, overlap = 138.469
+PHY-3002 : Step(223): len = 610915, overlap = 137.188
+PHY-3002 : Step(224): len = 608956, overlap = 135.125
+PHY-3002 : Step(225): len = 606719, overlap = 138.219
+PHY-3002 : Step(226): len = 603712, overlap = 136.312
+PHY-3002 : Step(227): len = 602610, overlap = 126.375
+PHY-3002 : Step(228): len = 599637, overlap = 126.562
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000253752
+PHY-3002 : Step(229): len = 601163, overlap = 119.375
+PHY-3002 : Step(230): len = 602373, overlap = 117.344
OPT-1001 : Start physical optimization ...
RUN-1002 : start command "start_timer -report"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85053, tnet num: 20151, tinst num: 17749, tnode num: 115138, tedge num: 136535.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84691, tnet num: 20103, tinst num: 17701, tnode num: 114767, tedge num: 135907.
TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in 1.411653s wall, 1.343750s user + 0.062500s system = 1.406250s CPU (99.6%)
+RUN-1003 : finish command "start_timer -report" in 1.566564s wall, 1.484375s user + 0.078125s system = 1.562500s CPU (99.7%)
-RUN-1004 : used memory is 572 MB, reserved memory is 562 MB, peak memory is 709 MB
-OPT-1001 : Total overflow 419.75 peak overflow 3.97
+RUN-1004 : used memory is 574 MB, reserved memory is 563 MB, peak memory is 709 MB
+OPT-1001 : Total overflow 449.03 peak overflow 8.34
OPT-1001 : Start high-fanout net optimization ...
OPT-1001 : Update timing in global mode
PHY-1001 : Start incremental global routing, caller is place ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 1271/20329.
+PHY-1001 : Reuse net number 857/20281.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 748544, over cnt = 3189(9%), over = 11299, worst = 23
-PHY-1001 : End global iterations; 1.088839s wall, 1.703125s user + 0.046875s system = 1.750000s CPU (160.7%)
+PHY-1002 : len = 699552, over cnt = 2835(8%), over = 10043, worst = 25
+PHY-1001 : End global iterations; 1.393356s wall, 1.921875s user + 0.031250s system = 1.953125s CPU (140.2%)
-PHY-1001 : Congestion index: top1 = 72.18, top5 = 58.80, top10 = 52.44, top15 = 48.48.
-PHY-1001 : End incremental global routing; 1.420261s wall, 2.031250s user + 0.062500s system = 2.093750s CPU (147.4%)
+PHY-1001 : Congestion index: top1 = 66.31, top5 = 55.55, top10 = 50.15, top15 = 46.60.
+PHY-1001 : End incremental global routing; 1.754026s wall, 2.281250s user + 0.031250s system = 2.312500s CPU (131.8%)
TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 20151 nets completely.
+TMR-2504 : Update delay of 20103 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 5.
TMR-3001 : Initiate 12 clocks from SDC.
TMR-3004 : Map sdc constraints, there are 6 constraints in total.
@@ -783,7 +747,7 @@ TMR-3003 : Constraints initiated successfully.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update; 0.927883s wall, 0.890625s user + 0.031250s system = 0.921875s CPU (99.4%)
+OPT-1001 : End timing update; 1.143365s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (98.4%)
OPT-1001 : 49 high-fanout net processed.
PHY-3001 : Start incremental placement ...
@@ -791,38 +755,38 @@ PHY-1001 : Populate physical database on model huagao_mipi_top.
PHY-3001 : Initial placement ...
PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
-PHY-3001 : eco cells: 17615 has valid locations, 323 needs to be replaced
-PHY-3001 : design contains 18023 instances, 7585 luts, 9217 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1179 with 6038 pins
-PHY-3001 : Found 1233 cells with 2 region constraints.
+PHY-3001 : eco cells: 17567 has valid locations, 322 needs to be replaced
+PHY-3001 : design contains 17974 instances, 7534 luts, 9219 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 6039 pins
+PHY-3001 : Found 1242 cells with 2 region constraints.
PHY-3001 : Global placement ...
-PHY-3001 : Initial: Len = 667488
+PHY-3001 : Initial: Len = 625679
PHY-3001 : Run with size of 4
PHY-3001 : Cell area utilization is 56%
PHY-3001 : Analyzing congestion ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 16819/20603.
+PHY-1001 : Reuse net number 16052/20554.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 762024, over cnt = 3226(9%), over = 11355, worst = 23
-PHY-1001 : End global iterations; 0.253234s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (135.7%)
+PHY-1002 : len = 714888, over cnt = 2876(8%), over = 10033, worst = 26
+PHY-1001 : End global iterations; 0.257696s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (121.3%)
-PHY-1001 : Congestion index: top1 = 72.05, top5 = 59.12, top10 = 52.76, top15 = 48.95.
-PHY-3001 : End congestion estimation; 0.511451s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (113.0%)
+PHY-1001 : Congestion index: top1 = 66.66, top5 = 55.46, top10 = 50.11, top15 = 46.70.
+PHY-3001 : End congestion estimation; 0.515356s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (112.2%)
PHY-3001 : Update density targets...
PHY-3001 : Update congestion history...
PHY-3001 : Update timing in global mode ...
RUN-1002 : start command "start_timer -report"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86155, tnet num: 20425, tinst num: 18023, tnode num: 116775, tedge num: 138191.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85780, tnet num: 20376, tinst num: 17974, tnode num: 116409, tedge num: 137539.
TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in 1.427053s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (100.7%)
+RUN-1003 : finish command "start_timer -report" in 1.515021s wall, 1.468750s user + 0.046875s system = 1.515625s CPU (100.0%)
-RUN-1004 : used memory is 620 MB, reserved memory is 623 MB, peak memory is 714 MB
+RUN-1004 : used memory is 618 MB, reserved memory is 621 MB, peak memory is 713 MB
TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 20425 nets completely.
+TMR-2504 : Update delay of 20376 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 5.
TMR-3001 : Initiate 12 clocks from SDC.
TMR-3004 : Map sdc constraints, there are 6 constraints in total.
@@ -833,145 +797,145 @@ TMR-3003 : Constraints initiated successfully.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update; 2.407306s wall, 2.359375s user + 0.046875s system = 2.406250s CPU (100.0%)
+PHY-3001 : End timing update; 2.511787s wall, 2.468750s user + 0.046875s system = 2.515625s CPU (100.2%)
PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
-PHY-3002 : Step(264): len = 666471, overlap = 0
-PHY-3002 : Step(265): len = 666093, overlap = 0
-PHY-3002 : Step(266): len = 665930, overlap = 0
-PHY-3002 : Step(267): len = 665817, overlap = 0
+PHY-3002 : Step(231): len = 624841, overlap = 1.84375
+PHY-3002 : Step(232): len = 624485, overlap = 1.875
+PHY-3002 : Step(233): len = 624208, overlap = 1.9375
PHY-3001 : Run with size of 2
PHY-3001 : Cell area utilization is 56%
PHY-3001 : Analyzing congestion ...
PHY-1001 : Generate routing nets ...
PHY-1001 : Incremental mode ON
-PHY-1001 : Reuse net number 16917/20603.
+PHY-1001 : Reuse net number 16167/20554.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 760216, over cnt = 3236(9%), over = 11405, worst = 23
-PHY-1001 : End global iterations; 0.203216s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (123.0%)
+PHY-1002 : len = 712584, over cnt = 2884(8%), over = 10123, worst = 26
+PHY-1001 : End global iterations; 0.214491s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (109.3%)
-PHY-1001 : Congestion index: top1 = 73.12, top5 = 59.60, top10 = 53.11, top15 = 49.15.
-PHY-3001 : End congestion estimation; 0.455439s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (109.8%)
+PHY-1001 : Congestion index: top1 = 67.16, top5 = 55.92, top10 = 50.46, top15 = 46.96.
+PHY-3001 : End congestion estimation; 0.497612s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (103.6%)
PHY-3001 : Update density targets...
PHY-3001 : Update congestion history...
PHY-3001 : Update timing in global mode ...
TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 20425 nets completely.
+TMR-2504 : Update delay of 20376 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 5.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update; 0.929612s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (100.8%)
+PHY-3001 : End timing update; 0.982352s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (100.2%)
-PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00045159
-PHY-3002 : Step(268): len = 665744, overlap = 102.062
-PHY-3002 : Step(269): len = 665776, overlap = 102.156
-PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00090318
-PHY-3002 : Step(270): len = 666141, overlap = 102.375
-PHY-3002 : Step(271): len = 666604, overlap = 102.25
-PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00176571
-PHY-3002 : Step(272): len = 666761, overlap = 102.406
-PHY-3002 : Step(273): len = 667541, overlap = 102.062
-PHY-3001 : Final: Len = 667541, Over = 102.062
-PHY-3001 : End incremental placement; 5.027058s wall, 5.171875s user + 0.250000s system = 5.421875s CPU (107.9%)
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000234242
+PHY-3002 : Step(234): len = 624067, overlap = 118.844
+PHY-3002 : Step(235): len = 624142, overlap = 118.875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000468484
+PHY-3002 : Step(236): len = 624150, overlap = 119.438
+PHY-3002 : Step(237): len = 624515, overlap = 119.781
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000936969
+PHY-3002 : Step(238): len = 624747, overlap = 119.469
+PHY-3002 : Step(239): len = 625394, overlap = 119.125
+PHY-3001 : Final: Len = 625394, Over = 119.125
+PHY-3001 : End incremental placement; 5.297590s wall, 5.406250s user + 0.156250s system = 5.562500s CPU (105.0%)
-OPT-1001 : Total overflow 425.44 peak overflow 3.97
-OPT-1001 : End high-fanout net optimization; 7.900339s wall, 8.625000s user + 0.343750s system = 8.968750s CPU (113.5%)
+OPT-1001 : Total overflow 455.03 peak overflow 8.34
+OPT-1001 : End high-fanout net optimization; 8.784785s wall, 9.484375s user + 0.187500s system = 9.671875s CPU (110.1%)
-OPT-1001 : Current memory(MB): used = 716, reserve = 711, peak = 733.
+OPT-1001 : Current memory(MB): used = 715, reserve = 710, peak = 733.
OPT-1001 : Start global optimization ...
OPT-1001 : Start congestion update ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 16841/20603.
+PHY-1001 : Reuse net number 16083/20554.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 764712, over cnt = 3164(8%), over = 10252, worst = 23
-PHY-1002 : len = 818192, over cnt = 2145(6%), over = 5172, worst = 23
-PHY-1002 : len = 859872, over cnt = 893(2%), over = 1893, worst = 17
-PHY-1002 : len = 878248, over cnt = 405(1%), over = 771, worst = 14
-PHY-1002 : len = 894816, over cnt = 3(0%), over = 4, worst = 2
-PHY-1001 : End global iterations; 1.614079s wall, 2.437500s user + 0.015625s system = 2.453125s CPU (152.0%)
+PHY-1002 : len = 715384, over cnt = 2806(7%), over = 9025, worst = 25
+PHY-1002 : len = 749816, over cnt = 2175(6%), over = 5692, worst = 18
+PHY-1002 : len = 797800, over cnt = 922(2%), over = 2171, worst = 15
+PHY-1002 : len = 829904, over cnt = 103(0%), over = 176, worst = 10
+PHY-1002 : len = 833304, over cnt = 8(0%), over = 8, worst = 1
+PHY-1001 : End global iterations; 1.858928s wall, 2.453125s user + 0.093750s system = 2.546875s CPU (137.0%)
-PHY-1001 : Congestion index: top1 = 60.02, top5 = 52.14, top10 = 48.54, top15 = 46.16.
-OPT-1001 : End congestion update; 1.883298s wall, 2.687500s user + 0.015625s system = 2.703125s CPU (143.5%)
+PHY-1001 : Congestion index: top1 = 56.66, top5 = 49.86, top10 = 46.49, top15 = 44.26.
+OPT-1001 : End congestion update; 2.143489s wall, 2.734375s user + 0.093750s system = 2.828125s CPU (131.9%)
OPT-1001 : Update timing in Manhattan mode
TMR-2503 : Start to update net delay, extr mode = 3.
-TMR-2504 : Update delay of 20425 nets completely.
+TMR-2504 : Update delay of 20376 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 3.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update; 0.793468s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.4%)
+OPT-1001 : End timing update; 0.845385s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (99.8%)
-OPT-0007 : Start: WNS -1168 TNS -1628 NUM_FEPS 2
-OPT-0007 : Iter 1: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 84 cells processed and 6884 slack improved
-OPT-0007 : Iter 2: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 17 cells processed and 1458 slack improved
-OPT-0007 : Iter 3: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 11 cells processed and 450 slack improved
-OPT-1001 : End global optimization; 2.715462s wall, 3.531250s user + 0.015625s system = 3.546875s CPU (130.6%)
+OPT-0007 : Start: WNS -1068 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 69 cells processed and 4172 slack improved
+OPT-0007 : Iter 2: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 37 cells processed and 2642 slack improved
+OPT-0007 : Iter 3: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 18 cells processed and 1540 slack improved
+OPT-0007 : Iter 4: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 8 cells processed and 700 slack improved
+OPT-1001 : End global optimization; 3.028918s wall, 3.609375s user + 0.109375s system = 3.718750s CPU (122.8%)
-OPT-1001 : Current memory(MB): used = 695, reserve = 696, peak = 733.
-OPT-1001 : End physical optimization; 12.637581s wall, 14.203125s user + 0.437500s system = 14.640625s CPU (115.8%)
+OPT-1001 : Current memory(MB): used = 693, reserve = 692, peak = 733.
+OPT-1001 : End physical optimization; 14.149479s wall, 15.406250s user + 0.406250s system = 15.812500s CPU (111.8%)
PHY-3001 : Start packing ...
SYN-4007 : Packing 0 MUX to BLE ...
SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
-SYN-4007 : Packing 7585 LUT to BLE ...
-SYN-4008 : Packed 7585 LUT and 3081 SEQ to BLE.
-SYN-4003 : Packing 6136 remaining SEQ's ...
-SYN-4005 : Packed 3937 SEQ with LUT/SLICE
-SYN-4006 : 847 single LUT's are left
-SYN-4006 : 2199 single SEQ's are left
-SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9784/13515 primitive instances ...
-PHY-3001 : End packing; 1.606850s wall, 1.578125s user + 0.015625s system = 1.593750s CPU (99.2%)
+SYN-4007 : Packing 7534 LUT to BLE ...
+SYN-4008 : Packed 7534 LUT and 3081 SEQ to BLE.
+SYN-4003 : Packing 6138 remaining SEQ's ...
+SYN-4005 : Packed 3728 SEQ with LUT/SLICE
+SYN-4006 : 1033 single LUT's are left
+SYN-4006 : 2410 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9944/13675 primitive instances ...
+PHY-3001 : End packing; 1.768773s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (99.8%)
PHY-1001 : Populate physical database on model huagao_mipi_top.
-RUN-1001 : There are total 6848 instances
-RUN-1001 : 3350 mslices, 3350 lslices, 75 pads, 58 brams, 3 dsps
-RUN-1001 : There are total 17653 nets
+RUN-1001 : There are total 6908 instances
+RUN-1001 : 3380 mslices, 3380 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17605 nets
RUN-6004 WARNING: There are 20 nets with only 1 pin.
-RUN-1001 : 9990 nets have 2 pins
-RUN-1001 : 5824 nets have [3 - 5] pins
-RUN-1001 : 1143 nets have [6 - 10] pins
+RUN-1001 : 9882 nets have 2 pins
+RUN-1001 : 6039 nets have [3 - 5] pins
+RUN-1001 : 996 nets have [6 - 10] pins
RUN-1001 : 319 nets have [11 - 20] pins
-RUN-1001 : 344 nets have [21 - 99] pins
+RUN-1001 : 336 nets have [21 - 99] pins
RUN-1001 : 13 nets have 100+ pins
-PHY-3001 : design contains 6846 instances, 6700 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1179 with 3573 pins
-PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : design contains 6906 instances, 6760 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3598 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
PHY-3001 : Cell area utilization is 74%
-PHY-3001 : After packing: Len = 677688, Over = 278.75
+PHY-3001 : After packing: Len = 639903, Over = 311.75
PHY-3001 : Run with size of 2
PHY-3001 : Cell area utilization is 74%
PHY-3001 : Analyzing congestion ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 7360/17653.
+PHY-1001 : Reuse net number 7236/17605.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 835424, over cnt = 2031(5%), over = 3263, worst = 9
-PHY-1002 : len = 840664, over cnt = 1494(4%), over = 2226, worst = 9
-PHY-1002 : len = 859256, over cnt = 503(1%), over = 693, worst = 9
-PHY-1002 : len = 866664, over cnt = 153(0%), over = 197, worst = 4
-PHY-1002 : len = 870312, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations; 1.643231s wall, 2.203125s user + 0.046875s system = 2.250000s CPU (136.9%)
+PHY-1002 : len = 789120, over cnt = 1925(5%), over = 3253, worst = 8
+PHY-1002 : len = 798072, over cnt = 1216(3%), over = 1800, worst = 7
+PHY-1002 : len = 811296, over cnt = 503(1%), over = 716, worst = 6
+PHY-1002 : len = 820752, over cnt = 125(0%), over = 177, worst = 6
+PHY-1002 : len = 824224, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.739831s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (143.7%)
-PHY-1001 : Congestion index: top1 = 58.71, top5 = 52.05, top10 = 47.94, top15 = 45.36.
-PHY-3001 : End congestion estimation; 2.041712s wall, 2.609375s user + 0.046875s system = 2.656250s CPU (130.1%)
+PHY-1001 : Congestion index: top1 = 57.07, top5 = 50.13, top10 = 46.41, top15 = 44.00.
+PHY-3001 : End congestion estimation; 2.153004s wall, 2.921875s user + 0.000000s system = 2.921875s CPU (135.7%)
PHY-3001 : Update density targets...
PHY-3001 : Update congestion history...
PHY-3001 : Update timing in global mode ...
RUN-1002 : start command "start_timer -report"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74266, tnet num: 17475, tinst num: 6846, tnode num: 96696, tedge num: 124693.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74010, tnet num: 17427, tinst num: 6906, tnode num: 96499, tedge num: 124264.
TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in 1.666459s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (100.3%)
+RUN-1003 : finish command "start_timer -report" in 1.721909s wall, 1.703125s user + 0.015625s system = 1.718750s CPU (99.8%)
-RUN-1004 : used memory is 609 MB, reserved memory is 608 MB, peak memory is 733 MB
+RUN-1004 : used memory is 611 MB, reserved memory is 612 MB, peak memory is 733 MB
TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 17475 nets completely.
+TMR-2504 : Update delay of 17427 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 5.
TMR-3001 : Initiate 12 clocks from SDC.
TMR-3004 : Map sdc constraints, there are 6 constraints in total.
@@ -981,118 +945,116 @@ TMR-3003 : Constraints initiated successfully.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update; 2.768116s wall, 2.765625s user + 0.000000s system = 2.765625s CPU (99.9%)
+PHY-3001 : End timing update; 2.682779s wall, 2.656250s user + 0.015625s system = 2.671875s CPU (99.6%)
-PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.92706e-05
-PHY-3002 : Step(274): len = 663813, overlap = 278
-PHY-3002 : Step(275): len = 656989, overlap = 274
-PHY-3002 : Step(276): len = 652804, overlap = 269.75
-PHY-3002 : Step(277): len = 650188, overlap = 275
-PHY-3002 : Step(278): len = 647911, overlap = 272.75
-PHY-3002 : Step(279): len = 646645, overlap = 274.25
-PHY-3002 : Step(280): len = 643841, overlap = 276
-PHY-3002 : Step(281): len = 641700, overlap = 274
-PHY-3002 : Step(282): len = 639307, overlap = 273.5
-PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.85411e-05
-PHY-3002 : Step(283): len = 641598, overlap = 270.75
-PHY-3002 : Step(284): len = 648034, overlap = 260
-PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000197082
-PHY-3002 : Step(285): len = 654845, overlap = 252.5
-PHY-3002 : Step(286): len = 668916, overlap = 232.25
-PHY-3002 : Step(287): len = 669197, overlap = 223.25
-PHY-3002 : Step(288): len = 669384, overlap = 220.25
-PHY-3002 : Step(289): len = 669586, overlap = 220.75
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.06879e-05
+PHY-3002 : Step(240): len = 631140, overlap = 311.75
+PHY-3002 : Step(241): len = 627745, overlap = 297.5
+PHY-3002 : Step(242): len = 626822, overlap = 291.5
+PHY-3002 : Step(243): len = 626753, overlap = 288.75
+PHY-3002 : Step(244): len = 626765, overlap = 289
+PHY-3002 : Step(245): len = 625140, overlap = 294.75
+PHY-3002 : Step(246): len = 623501, overlap = 289.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.13758e-05
+PHY-3002 : Step(247): len = 625054, overlap = 285.75
+PHY-3002 : Step(248): len = 628153, overlap = 280.5
+PHY-3002 : Step(249): len = 629867, overlap = 274.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000162752
+PHY-3002 : Step(250): len = 636527, overlap = 270.25
+PHY-3002 : Step(251): len = 646126, overlap = 260.75
+PHY-3002 : Step(252): len = 647192, overlap = 257
+PHY-3002 : Step(253): len = 648901, overlap = 249.75
+PHY-3002 : Step(254): len = 650656, overlap = 243.75
PHY-3001 : Legalization ...
-PHY-3001 : End legalization; 0.372949s wall, 0.312500s user + 0.515625s system = 0.828125s CPU (222.0%)
+PHY-3001 : End legalization; 0.373026s wall, 0.328125s user + 0.546875s system = 0.875000s CPU (234.6%)
-PHY-3001 : Trial Legalized: Len = 760274
+PHY-3001 : Trial Legalized: Len = 743394
PHY-3001 : Run with size of 2
-PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Cell area utilization is 74%
PHY-3001 : Analyzing congestion ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 797/17653.
+PHY-1001 : Reuse net number 860/17605.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 886056, over cnt = 2845(8%), over = 4808, worst = 8
-PHY-1002 : len = 902912, over cnt = 1840(5%), over = 2764, worst = 8
-PHY-1002 : len = 926256, over cnt = 694(1%), over = 1052, worst = 7
-PHY-1002 : len = 936600, over cnt = 286(0%), over = 438, worst = 5
-PHY-1002 : len = 943968, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations; 2.341160s wall, 3.390625s user + 0.000000s system = 3.390625s CPU (144.8%)
+PHY-1002 : len = 863992, over cnt = 2790(7%), over = 4770, worst = 9
+PHY-1002 : len = 879488, over cnt = 1790(5%), over = 2791, worst = 9
+PHY-1002 : len = 898056, over cnt = 932(2%), over = 1462, worst = 9
+PHY-1002 : len = 915752, over cnt = 266(0%), over = 437, worst = 5
+PHY-1002 : len = 922712, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.471592s wall, 3.671875s user + 0.015625s system = 3.687500s CPU (149.2%)
-PHY-1001 : Congestion index: top1 = 57.35, top5 = 52.16, top10 = 49.28, top15 = 47.23.
-PHY-3001 : End congestion estimation; 2.784217s wall, 3.843750s user + 0.000000s system = 3.843750s CPU (138.1%)
+PHY-1001 : Congestion index: top1 = 55.62, top5 = 50.45, top10 = 47.79, top15 = 45.92.
+PHY-3001 : End congestion estimation; 2.962224s wall, 4.171875s user + 0.015625s system = 4.187500s CPU (141.4%)
PHY-3001 : Update density targets...
PHY-3001 : Update congestion history...
PHY-3001 : Update timing in global mode ...
TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 17475 nets completely.
+TMR-2504 : Update delay of 17427 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 5.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update; 0.985216s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (99.9%)
+PHY-3001 : End timing update; 0.933765s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (100.4%)
-PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000160075
-PHY-3002 : Step(290): len = 731170, overlap = 46.75
-PHY-3002 : Step(291): len = 715477, overlap = 73.5
-PHY-3002 : Step(292): len = 701504, overlap = 99.25
-PHY-3002 : Step(293): len = 692938, overlap = 120.5
-PHY-3002 : Step(294): len = 686075, overlap = 149
-PHY-3002 : Step(295): len = 683281, overlap = 155.5
-PHY-3002 : Step(296): len = 681605, overlap = 159.75
-PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000320151
-PHY-3002 : Step(297): len = 686514, overlap = 158.5
-PHY-3002 : Step(298): len = 693478, overlap = 154.75
-PHY-3002 : Step(299): len = 697623, overlap = 148
-PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000640302
-PHY-3002 : Step(300): len = 703226, overlap = 144.5
-PHY-3002 : Step(301): len = 715989, overlap = 143.75
-PHY-3002 : Step(302): len = 720218, overlap = 142.75
-PHY-3002 : Step(303): len = 720731, overlap = 142.75
-PHY-3002 : Step(304): len = 721887, overlap = 142.5
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000164287
+PHY-3002 : Step(255): len = 712986, overlap = 53.5
+PHY-3002 : Step(256): len = 696944, overlap = 79.75
+PHY-3002 : Step(257): len = 682333, overlap = 116
+PHY-3002 : Step(258): len = 674623, overlap = 137.75
+PHY-3002 : Step(259): len = 668996, overlap = 153.25
+PHY-3002 : Step(260): len = 665196, overlap = 165.5
+PHY-3002 : Step(261): len = 663411, overlap = 179.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000328575
+PHY-3002 : Step(262): len = 669297, overlap = 175.25
+PHY-3002 : Step(263): len = 675703, overlap = 176
+PHY-3002 : Step(264): len = 679816, overlap = 173.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00065715
+PHY-3002 : Step(265): len = 684396, overlap = 170
+PHY-3002 : Step(266): len = 694418, overlap = 160.25
+PHY-3002 : Step(267): len = 698782, overlap = 155
+PHY-3002 : Step(268): len = 701898, overlap = 155.75
PHY-3001 : Legalization ...
-PHY-3001 : End legalization; 0.034690s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (90.1%)
+PHY-3001 : End legalization; 0.037784s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (82.7%)
-PHY-3001 : Legalized: Len = 748503, Over = 0
-PHY-3001 : Spreading special nets. 468 overflows in 2952 tiles.
-PHY-3001 : End spreading; 0.103487s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (105.7%)
+PHY-3001 : Legalized: Len = 730065, Over = 0
+PHY-3001 : Spreading special nets. 447 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.109370s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (100.0%)
-PHY-3001 : 689 instances has been re-located, deltaX = 254, deltaY = 381, maxDist = 3.
-PHY-3001 : Final: Len = 758271, Over = 0
+PHY-3001 : 660 instances has been re-located, deltaX = 210, deltaY = 407, maxDist = 2.
+PHY-3001 : Final: Len = 740629, Over = 0
PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
OPT-1001 : Start physical optimization ...
RUN-1002 : start command "start_timer -report"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74266, tnet num: 17475, tinst num: 6849, tnode num: 96696, tedge num: 124693.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74010, tnet num: 17427, tinst num: 6909, tnode num: 96499, tedge num: 124264.
TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in 1.844010s wall, 1.828125s user + 0.015625s system = 1.843750s CPU (100.0%)
+RUN-1003 : finish command "start_timer -report" in 1.972104s wall, 1.937500s user + 0.031250s system = 1.968750s CPU (99.8%)
-RUN-1004 : used memory is 622 MB, reserved memory is 641 MB, peak memory is 733 MB
+RUN-1004 : used memory is 635 MB, reserved memory is 653 MB, peak memory is 733 MB
OPT-1001 : Total overflow 0.00 peak overflow 0.00
OPT-1001 : Start high-fanout net optimization ...
OPT-1001 : Update timing in global mode
PHY-1001 : Start incremental global routing, caller is place ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 3196/17653.
+PHY-1001 : Reuse net number 3203/17605.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 894616, over cnt = 2612(7%), over = 4292, worst = 7
-PHY-1002 : len = 908408, over cnt = 1661(4%), over = 2484, worst = 6
-PHY-1002 : len = 921576, over cnt = 864(2%), over = 1331, worst = 6
-PHY-1002 : len = 934896, over cnt = 292(0%), over = 473, worst = 6
-PHY-1002 : len = 943744, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations; 2.078093s wall, 3.015625s user + 0.000000s system = 3.015625s CPU (145.1%)
+PHY-1002 : len = 874136, over cnt = 2608(7%), over = 4302, worst = 9
+PHY-1002 : len = 888584, over cnt = 1473(4%), over = 2234, worst = 7
+PHY-1002 : len = 905280, over cnt = 568(1%), over = 888, worst = 7
+PHY-1002 : len = 919032, over cnt = 51(0%), over = 69, worst = 5
+PHY-1002 : len = 920176, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.311184s wall, 3.625000s user + 0.000000s system = 3.625000s CPU (156.8%)
-PHY-1001 : Congestion index: top1 = 56.94, top5 = 51.26, top10 = 48.22, top15 = 46.18.
-PHY-1001 : End incremental global routing; 2.470629s wall, 3.406250s user + 0.000000s system = 3.406250s CPU (137.9%)
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.41, top10 = 46.68, top15 = 44.80.
+PHY-1001 : End incremental global routing; 2.720139s wall, 4.031250s user + 0.000000s system = 4.031250s CPU (148.2%)
TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 17475 nets completely.
+TMR-2504 : Update delay of 17427 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 5.
TMR-3001 : Initiate 12 clocks from SDC.
TMR-3004 : Map sdc constraints, there are 6 constraints in total.
@@ -1100,7 +1062,7 @@ TMR-3003 : Constraints initiated successfully.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update; 0.860135s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.9%)
+OPT-1001 : End timing update; 0.945794s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.1%)
OPT-1001 : 5 high-fanout net processed.
PHY-3001 : Start incremental placement ...
@@ -1108,41 +1070,42 @@ PHY-1001 : Populate physical database on model huagao_mipi_top.
PHY-3001 : Initial placement ...
PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
-PHY-3001 : eco cells: 6756 has valid locations, 22 needs to be replaced
-PHY-3001 : design contains 6866 instances, 6717 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1179 with 3655 pins
-PHY-3001 : Found 503 cells with 2 region constraints.
+PHY-3001 : eco cells: 6816 has valid locations, 26 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
PHY-3001 : Global placement ...
-PHY-3001 : Initial: Len = 761110
+PHY-3001 : Initial: Len = 744426
PHY-3001 : Run with size of 4
PHY-3001 : Cell area utilization is 74%
PHY-3001 : Analyzing congestion ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 16070/17671.
+PHY-1001 : Reuse net number 16034/17630.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 946400, over cnt = 77(0%), over = 95, worst = 4
-PHY-1002 : len = 946672, over cnt = 26(0%), over = 26, worst = 1
-PHY-1002 : len = 946864, over cnt = 8(0%), over = 8, worst = 1
-PHY-1002 : len = 947048, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations; 0.676409s wall, 0.671875s user + 0.015625s system = 0.687500s CPU (101.6%)
+PHY-1002 : len = 924200, over cnt = 82(0%), over = 95, worst = 3
+PHY-1002 : len = 924280, over cnt = 38(0%), over = 39, worst = 2
+PHY-1002 : len = 924576, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 924704, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 924736, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.828284s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (111.3%)
-PHY-1001 : Congestion index: top1 = 56.94, top5 = 51.28, top10 = 48.25, top15 = 46.22.
-PHY-3001 : End congestion estimation; 0.984859s wall, 0.984375s user + 0.015625s system = 1.000000s CPU (101.5%)
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.39, top10 = 46.67, top15 = 44.80.
+PHY-3001 : End congestion estimation; 1.163709s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (107.4%)
PHY-3001 : Update density targets...
PHY-3001 : Update congestion history...
PHY-3001 : Update timing in global mode ...
RUN-1002 : start command "start_timer -report"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74418, tnet num: 17493, tinst num: 6866, tnode num: 96890, tedge num: 124901.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74216, tnet num: 17452, tinst num: 6930, tnode num: 96760, tedge num: 124559.
TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in 1.804387s wall, 1.796875s user + 0.000000s system = 1.796875s CPU (99.6%)
+RUN-1003 : finish command "start_timer -report" in 1.993424s wall, 1.984375s user + 0.015625s system = 2.000000s CPU (100.3%)
-RUN-1004 : used memory is 684 MB, reserved memory is 685 MB, peak memory is 733 MB
+RUN-1004 : used memory is 645 MB, reserved memory is 641 MB, peak memory is 733 MB
TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 17493 nets completely.
+TMR-2504 : Update delay of 17452 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 5.
TMR-3001 : Initiate 12 clocks from SDC.
TMR-3004 : Map sdc constraints, there are 6 constraints in total.
@@ -1150,150 +1113,361 @@ TMR-3003 : Constraints initiated successfully.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update; 2.720800s wall, 2.718750s user + 0.000000s system = 2.718750s CPU (99.9%)
+PHY-3001 : End timing update; 2.971579s wall, 2.937500s user + 0.031250s system = 2.968750s CPU (99.9%)
PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
-PHY-3002 : Step(305): len = 760722, overlap = 0
-PHY-3002 : Step(306): len = 760048, overlap = 0
+PHY-3002 : Step(269): len = 743276, overlap = 0
+PHY-3002 : Step(270): len = 742723, overlap = 0
+PHY-3002 : Step(271): len = 742706, overlap = 0
PHY-3001 : Run with size of 2
PHY-3001 : Cell area utilization is 74%
PHY-3001 : Analyzing congestion ...
PHY-1001 : Generate routing nets ...
PHY-1001 : Incremental mode ON
-PHY-1001 : Reuse net number 16058/17671.
+PHY-1001 : Reuse net number 16022/17630.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 945440, over cnt = 65(0%), over = 74, worst = 3
-PHY-1002 : len = 945488, over cnt = 20(0%), over = 21, worst = 2
-PHY-1002 : len = 945616, over cnt = 8(0%), over = 8, worst = 1
-PHY-1002 : len = 945728, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations; 0.600673s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (111.9%)
+PHY-1002 : len = 921320, over cnt = 94(0%), over = 112, worst = 5
+PHY-1002 : len = 921496, over cnt = 44(0%), over = 48, worst = 4
+PHY-1002 : len = 922000, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 922184, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.657432s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (104.6%)
-PHY-1001 : Congestion index: top1 = 56.94, top5 = 51.34, top10 = 48.26, top15 = 46.20.
-PHY-3001 : End congestion estimation; 0.917718s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (107.3%)
+PHY-1001 : Congestion index: top1 = 55.04, top5 = 49.39, top10 = 46.68, top15 = 44.83.
+PHY-3001 : End congestion estimation; 1.000205s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (103.1%)
PHY-3001 : Update density targets...
PHY-3001 : Update congestion history...
PHY-3001 : Update timing in global mode ...
TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 17493 nets completely.
+TMR-2504 : Update delay of 17452 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 5.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update; 0.906571s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.0%)
+PHY-3001 : End timing update; 0.919630s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (100.2%)
-PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00185655
-PHY-3002 : Step(307): len = 760048, overlap = 0.5
-PHY-3002 : Step(308): len = 760036, overlap = 0
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00045968
+PHY-3002 : Step(272): len = 742691, overlap = 1.75
+PHY-3002 : Step(273): len = 742734, overlap = 1.5
PHY-3001 : Legalization ...
-PHY-3001 : End legalization; 0.006091s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+PHY-3001 : End legalization; 0.005744s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
-PHY-3001 : Legalized: Len = 760167, Over = 0
-PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
-PHY-3001 : End spreading; 0.062219s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.5%)
+PHY-3001 : Legalized: Len = 742783, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.067353s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (92.8%)
-PHY-3001 : 10 instances has been re-located, deltaX = 3, deltaY = 8, maxDist = 2.
-PHY-3001 : Final: Len = 760311, Over = 0
-PHY-3001 : End incremental placement; 6.012200s wall, 6.156250s user + 0.109375s system = 6.265625s CPU (104.2%)
+PHY-3001 : 2 instances has been re-located, deltaX = 4, deltaY = 0, maxDist = 2.
+PHY-3001 : Final: Len = 742827, Over = 0
+PHY-3001 : End incremental placement; 6.623341s wall, 6.890625s user + 0.093750s system = 6.984375s CPU (105.5%)
OPT-1001 : Total overflow 0.00 peak overflow 0.00
-OPT-1001 : End high-fanout net optimization; 9.827324s wall, 10.921875s user + 0.109375s system = 11.031250s CPU (112.3%)
+OPT-1001 : End high-fanout net optimization; 10.816412s wall, 12.390625s user + 0.093750s system = 12.484375s CPU (115.4%)
-OPT-1001 : Current memory(MB): used = 737, reserve = 737, peak = 740.
+OPT-1001 : Current memory(MB): used = 739, reserve = 742, peak = 743.
OPT-1001 : Start path based optimization ...
OPT-1001 : Start congestion update ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 16031/17671.
+PHY-1001 : Reuse net number 16016/17630.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 945776, over cnt = 55(0%), over = 69, worst = 5
-PHY-1002 : len = 945848, over cnt = 31(0%), over = 33, worst = 2
-PHY-1002 : len = 946080, over cnt = 14(0%), over = 14, worst = 1
-PHY-1002 : len = 946216, over cnt = 6(0%), over = 6, worst = 1
-PHY-1002 : len = 946336, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations; 0.813919s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (101.7%)
+PHY-1002 : len = 922168, over cnt = 57(0%), over = 74, worst = 4
+PHY-1002 : len = 922344, over cnt = 24(0%), over = 27, worst = 2
+PHY-1002 : len = 922616, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 922736, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 922752, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.912525s wall, 1.000000s user + 0.015625s system = 1.015625s CPU (111.3%)
-PHY-1001 : Congestion index: top1 = 56.72, top5 = 51.26, top10 = 48.21, top15 = 46.17.
-OPT-1001 : End congestion update; 1.195232s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (102.0%)
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.38, top10 = 46.62, top15 = 44.79.
+OPT-1001 : End congestion update; 1.275360s wall, 1.359375s user + 0.015625s system = 1.375000s CPU (107.8%)
OPT-1001 : Update timing in Manhattan mode
TMR-2503 : Start to update net delay, extr mode = 3.
-TMR-2504 : Update delay of 17493 nets completely.
+TMR-2504 : Update delay of 17452 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 3.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update; 0.726103s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.0%)
+OPT-1001 : End timing update; 0.774240s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (98.9%)
-OPT-0007 : Start: WNS -1233 TNS -1997 NUM_FEPS 3
+OPT-0007 : Start: WNS -1086 TNS -1721 NUM_FEPS 2
PHY-3001 : Start incremental legalization ...
PHY-1001 : Populate physical database on model huagao_mipi_top.
PHY-3001 : Initial placement ...
PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
-PHY-3001 : eco cells: 6778 has valid locations, 0 needs to be replaced
-PHY-3001 : design contains 6866 instances, 6717 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1179 with 3655 pins
-PHY-3001 : Found 503 cells with 2 region constraints.
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
PHY-3001 : Cell area utilization is 74%
-PHY-3001 : Initial: Len = 764107, Over = 0
-PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles.
-PHY-3001 : End spreading; 0.061783s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.2%)
+PHY-3001 : Initial: Len = 746757, Over = 0
+PHY-3001 : Spreading special nets. 28 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.078671s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (99.3%)
-PHY-3001 : 27 instances has been re-located, deltaX = 24, deltaY = 14, maxDist = 3.
-PHY-3001 : Final: Len = 764645, Over = 0
-PHY-3001 : End incremental legalization; 0.382720s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (102.1%)
+PHY-3001 : 35 instances has been re-located, deltaX = 19, deltaY = 20, maxDist = 6.
+PHY-3001 : Final: Len = 747093, Over = 0
+PHY-3001 : End incremental legalization; 0.451923s wall, 0.437500s user + 0.015625s system = 0.453125s CPU (100.3%)
-OPT-0007 : Iter 1: improved WNS -1033 TNS -1568 NUM_FEPS 2 with 42 cells processed and 10270 slack improved
-OPT-0007 : Iter 2: improved WNS -1033 TNS -1568 NUM_FEPS 2 with 0 cells processed and 0 slack improved
-OPT-1001 : End path based optimization; 2.481029s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (100.8%)
+OPT-0007 : Iter 1: improved WNS -986 TNS -1521 NUM_FEPS 2 with 53 cells processed and 9773 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747839, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.067305s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (92.9%)
-OPT-1001 : Current memory(MB): used = 738, reserve = 738, peak = 741.
+PHY-3001 : 15 instances has been re-located, deltaX = 9, deltaY = 10, maxDist = 5.
+PHY-3001 : Final: Len = 747939, Over = 0
+PHY-3001 : End incremental legalization; 0.449954s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.7%)
+
+OPT-0007 : Iter 2: improved WNS -936 TNS -1471 NUM_FEPS 2 with 20 cells processed and 1573 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 748129, Over = 0
+PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064779s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.5%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 12, deltaY = 7, maxDist = 7.
+PHY-3001 : Final: Len = 747949, Over = 0
+PHY-3001 : End incremental legalization; 0.418141s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.9%)
+
+OPT-0007 : Iter 3: improved WNS -936 TNS -1471 NUM_FEPS 2 with 15 cells processed and 349 slack improved
+OPT-1001 : End path based optimization; 3.906012s wall, 3.953125s user + 0.046875s system = 4.000000s CPU (102.4%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 742, peak = 743.
OPT-1001 : Update timing in Manhattan mode
TMR-2503 : Start to update net delay, extr mode = 3.
-TMR-2504 : Update delay of 17493 nets completely.
+TMR-2504 : Update delay of 17452 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 3.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update; 0.723290s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.4%)
+OPT-1001 : End timing update; 0.806124s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (96.9%)
OPT-1001 : Start pin optimization...
OPT-1001 : skip pin optimization...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 15862/17671.
+PHY-1001 : Reuse net number 15705/17630.
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 950288, over cnt = 138(0%), over = 158, worst = 3
-PHY-1002 : len = 950288, over cnt = 79(0%), over = 86, worst = 3
-PHY-1002 : len = 951080, over cnt = 12(0%), over = 12, worst = 1
-PHY-1002 : len = 951240, over cnt = 5(0%), over = 5, worst = 1
-PHY-1002 : len = 951256, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations; 0.876342s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (103.4%)
+PHY-1002 : len = 926848, over cnt = 191(0%), over = 258, worst = 4
+PHY-1002 : len = 927192, over cnt = 104(0%), over = 111, worst = 2
+PHY-1002 : len = 927784, over cnt = 33(0%), over = 34, worst = 2
+PHY-1002 : len = 928328, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 928456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.961342s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (102.4%)
-PHY-1001 : Congestion index: top1 = 56.62, top5 = 51.31, top10 = 48.20, top15 = 46.17.
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.55, top10 = 46.70, top15 = 44.82.
OPT-1001 : Update timing in Manhattan mode
TMR-2503 : Start to update net delay, extr mode = 3.
-TMR-2504 : Update delay of 17493 nets completely.
+TMR-2504 : Update delay of 17452 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 3.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update; 0.850921s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.2%)
+OPT-1001 : End timing update; 0.787686s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.2%)
RUN-1001 : QoR Analysis:
-OPT-0007 : WNS -1133 TNS -1668 NUM_FEPS 2
-RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 56.172414
+OPT-0007 : WNS -986 TNS -1571 NUM_FEPS 2
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.482759
RUN-1001 : Top critical paths
-RUN-1001 : #1 path slack -1133ps with logic level 2
-RUN-1001 : #2 path slack -1047ps with logic level 2
-RUN-1001 : 0 HFN exist on timing critical paths out of 17671 nets
-RUN-1001 : 0 long nets exist on timing critical paths out of 17671 nets
-OPT-1001 : End physical optimization; 17.282283s wall, 18.406250s user + 0.125000s system = 18.531250s CPU (107.2%)
+RUN-1001 : #1 path slack -986ps with logic level 2
+RUN-1001 : #2 path slack -940ps with logic level 2
+RUN-1001 : extra opt step will be enabled to improve QoR
+RUN-1001 : 0 HFN exist on timing critical paths out of 17630 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 17630 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747949, Over = 0
+PHY-3001 : End spreading; 0.065259s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.8%)
-RUN-1003 : finish command "place" in 59.568108s wall, 84.453125s user + 5.562500s system = 90.015625s CPU (151.1%)
+PHY-3001 : Final: Len = 747949, Over = 0
+PHY-3001 : End incremental legalization; 0.421445s wall, 0.515625s user + 0.031250s system = 0.546875s CPU (129.8%)
-RUN-1004 : used memory is 645 MB, reserved memory is 646 MB, peak memory is 741 MB
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.805812s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (100.8%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16057/17630.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.141990s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.0%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.55, top10 = 46.70, top15 = 44.82.
+OPT-1001 : End congestion update; 0.475537s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (98.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.760751s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.6%)
+
+OPT-0007 : Start: WNS -986 TNS -1571 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747889, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.075859s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (103.0%)
+
+PHY-3001 : 3 instances has been re-located, deltaX = 3, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 747949, Over = 0
+PHY-3001 : End incremental legalization; 0.485966s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (135.0%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1471 NUM_FEPS 2 with 3 cells processed and 150 slack improved
+OPT-0007 : Iter 2: improved WNS -936 TNS -1471 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.855841s wall, 2.093750s user + 0.000000s system = 2.093750s CPU (112.8%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 742, peak = 743.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16057/17630.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.169442s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (92.2%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.55, top10 = 46.70, top15 = 44.82.
+OPT-1001 : End congestion update; 0.590557s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (97.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.833191s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (101.3%)
+
+OPT-0007 : Start: WNS -986 TNS -1571 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747909, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066075s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.6%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 2, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 747949, Over = 0
+PHY-3001 : End incremental legalization; 0.428158s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (124.1%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1471 NUM_FEPS 2 with 2 cells processed and 100 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6842 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6930 instances, 6781 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1179 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747909, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064488s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.9%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 2, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 747949, Over = 0
+PHY-3001 : End incremental legalization; 0.424749s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (125.1%)
+
+OPT-0007 : Iter 2: improved WNS -936 TNS -1471 NUM_FEPS 2 with 2 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS -936 TNS -1471 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 2.628235s wall, 2.812500s user + 0.000000s system = 2.812500s CPU (107.0%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 742, peak = 743.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.803381s wall, 0.781250s user + 0.015625s system = 0.796875s CPU (99.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 739, reserve = 742, peak = 743.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17452 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.128367s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.7%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16057/17630.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.145366s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.7%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.55, top10 = 46.70, top15 = 44.82.
+RUN-1001 : End congestion update; 0.482550s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (97.1%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.614286s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.7%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 742, peak = 743.
+OPT-1001 : End physical optimization; 28.258080s wall, 30.453125s user + 0.250000s system = 30.703125s CPU (108.7%)
+
+RUN-1003 : finish command "place" in 71.802909s wall, 100.937500s user + 5.593750s system = 106.531250s CPU (148.4%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 619 MB, peak memory is 743 MB
RUN-1002 : start command "export_db hg_anlogic_place.db"
RUN-1001 : Exported /
RUN-1001 : Exported flow parameters
@@ -1310,9 +1484,9 @@ RUN-1001 : Exported violations
RUN-1001 : Exported timing constraints
RUN-1001 : Exported IO constraints
RUN-1001 : Exported Inst constraints
-RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.675582s wall, 2.906250s user + 0.000000s system = 2.906250s CPU (173.4%)
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.768222s wall, 3.109375s user + 0.015625s system = 3.125000s CPU (176.7%)
-RUN-1004 : used memory is 645 MB, reserved memory is 646 MB, peak memory is 741 MB
+RUN-1004 : used memory is 611 MB, reserved memory is 620 MB, peak memory is 743 MB
RUN-1002 : start command "route"
RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
RUN-1001 : Print Global Property
@@ -1337,27 +1511,27 @@ RUN-1001 : priority | timing | timing |
RUN-1001 : swap_pin | on | on |
RUN-1001 : -------------------------------------------------------
PHY-1001 : Route runs in 8 thread(s)
-RUN-1001 : There are total 6868 instances
-RUN-1001 : 3353 mslices, 3364 lslices, 75 pads, 58 brams, 3 dsps
-RUN-1001 : There are total 17671 nets
+RUN-1001 : There are total 6932 instances
+RUN-1001 : 3392 mslices, 3389 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17630 nets
RUN-6004 WARNING: There are 20 nets with only 1 pin.
-RUN-1001 : 9991 nets have 2 pins
-RUN-1001 : 5821 nets have [3 - 5] pins
-RUN-1001 : 1147 nets have [6 - 10] pins
-RUN-1001 : 323 nets have [11 - 20] pins
-RUN-1001 : 361 nets have [21 - 99] pins
+RUN-1001 : 9886 nets have 2 pins
+RUN-1001 : 6040 nets have [3 - 5] pins
+RUN-1001 : 1001 nets have [6 - 10] pins
+RUN-1001 : 321 nets have [11 - 20] pins
+RUN-1001 : 354 nets have [21 - 99] pins
RUN-1001 : 8 nets have 100+ pins
RUN-1002 : start command "start_timer -report"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74418, tnet num: 17493, tinst num: 6866, tnode num: 96890, tedge num: 124901.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74216, tnet num: 17452, tinst num: 6930, tnode num: 96760, tedge num: 124559.
TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in 1.642431s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (98.9%)
+RUN-1003 : finish command "start_timer -report" in 1.769299s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (99.8%)
-RUN-1004 : used memory is 626 MB, reserved memory is 621 MB, peak memory is 741 MB
-PHY-1001 : 3353 mslices, 3364 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1004 : used memory is 604 MB, reserved memory is 605 MB, peak memory is 743 MB
+PHY-1001 : 3392 mslices, 3389 lslices, 75 pads, 58 brams, 3 dsps
TMR-2503 : Start to update net delay, extr mode = 3.
-TMR-2504 : Update delay of 17493 nets completely.
+TMR-2504 : Update delay of 17452 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 3.
TMR-3001 : Initiate 12 clocks from SDC.
TMR-3004 : Map sdc constraints, there are 6 constraints in total.
@@ -1369,18 +1543,18 @@ PHY-1001 : Start global routing, caller is route ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 880208, over cnt = 2800(7%), over = 4534, worst = 8
-PHY-1002 : len = 896544, over cnt = 1776(5%), over = 2560, worst = 8
-PHY-1002 : len = 912936, over cnt = 925(2%), over = 1298, worst = 6
-PHY-1002 : len = 933744, over cnt = 1(0%), over = 1, worst = 1
-PHY-1002 : len = 933792, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations; 3.219168s wall, 4.125000s user + 0.031250s system = 4.156250s CPU (129.1%)
+PHY-1002 : len = 861432, over cnt = 2754(7%), over = 4563, worst = 8
+PHY-1002 : len = 876872, over cnt = 1730(4%), over = 2557, worst = 6
+PHY-1002 : len = 899896, over cnt = 526(1%), over = 774, worst = 6
+PHY-1002 : len = 912264, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 912440, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.203294s wall, 4.343750s user + 0.078125s system = 4.421875s CPU (138.0%)
-PHY-1001 : Congestion index: top1 = 56.23, top5 = 50.92, top10 = 47.76, top15 = 45.65.
-PHY-1001 : End global routing; 3.572163s wall, 4.468750s user + 0.031250s system = 4.500000s CPU (126.0%)
+PHY-1001 : Congestion index: top1 = 54.20, top5 = 49.29, top10 = 46.64, top15 = 44.74.
+PHY-1001 : End global routing; 3.574955s wall, 4.718750s user + 0.078125s system = 4.796875s CPU (134.2%)
PHY-1001 : Start detail routing ...
-PHY-1001 : Current memory(MB): used = 710, reserve = 713, peak = 741.
+PHY-1001 : Current memory(MB): used = 710, reserve = 717, peak = 743.
PHY-1001 : Detailed router is running in normal mode.
PHY-1001 : Generate detailed routing grids ...
PHY-1001 : Generate nets ...
@@ -1410,171 +1584,131 @@ PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock me
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
-PHY-1001 : Current memory(MB): used = 986, reserve = 990, peak = 986.
-PHY-1001 : End build detailed router design. 3.963360s wall, 3.906250s user + 0.062500s system = 3.968750s CPU (100.1%)
+PHY-1001 : Current memory(MB): used = 985, reserve = 991, peak = 985.
+PHY-1001 : End build detailed router design. 4.285590s wall, 4.250000s user + 0.046875s system = 4.296875s CPU (100.3%)
PHY-1001 : Detail Route ...
PHY-1001 : ===== Detail Route Phase 1 =====
PHY-1001 : Clock net routing.....
PHY-1001 : Routed 0% nets.
-PHY-1022 : len = 267216, over cnt = 4(0%), over = 4, worst = 1, crit = 0
-PHY-1001 : End initial clock net routed; 5.663463s wall, 5.640625s user + 0.015625s system = 5.656250s CPU (99.9%)
+PHY-1022 : len = 266520, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.543466s wall, 5.515625s user + 0.000000s system = 5.515625s CPU (99.5%)
PHY-1001 : Ripup-reroute.....
PHY-1001 : ===== DR Iter 1 =====
-PHY-1022 : len = 267272, over cnt = 0(0%), over = 0, worst = 0, crit = 0
-PHY-1001 : End DR Iter 1; 0.563984s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (99.7%)
+PHY-1022 : len = 266576, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.456184s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (102.8%)
-PHY-1001 : Current memory(MB): used = 1021, reserve = 1026, peak = 1021.
-PHY-1001 : End phase 1; 6.240417s wall, 6.218750s user + 0.015625s system = 6.234375s CPU (99.9%)
+PHY-1001 : Current memory(MB): used = 1021, reserve = 1028, peak = 1021.
+PHY-1001 : End phase 1; 6.012081s wall, 5.984375s user + 0.000000s system = 5.984375s CPU (99.5%)
PHY-1001 : ===== Detail Route Phase 2 =====
PHY-1001 : Initial routing.....
-PHY-1001 : Routed 45% nets.
-PHY-1001 : Routed 51% nets.
-PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
PHY-1001 : Routed 73% nets.
PHY-1001 : Routed 93% nets.
-PHY-1022 : len = 2.37964e+06, over cnt = 1971(0%), over = 1977, worst = 2, crit = 0
-PHY-1001 : Current memory(MB): used = 1039, reserve = 1043, peak = 1039.
-PHY-1001 : End initial routed; 26.926601s wall, 59.921875s user + 0.296875s system = 60.218750s CPU (223.6%)
+PHY-1022 : len = 2.38544e+06, over cnt = 1940(0%), over = 1945, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1038, reserve = 1042, peak = 1038.
+PHY-1001 : End initial routed; 31.065055s wall, 66.125000s user + 0.296875s system = 66.421875s CPU (213.8%)
PHY-1001 : Update timing.....
-PHY-1001 : 15/16594(0%) critical/total net(s).
+PHY-1001 : 11/16553(0%) critical/total net(s).
RUN-1001 : --------------------------------------
RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
RUN-1001 : --------------------------------------
-RUN-1001 : Setup | -2.183 | -4.924 | 5
+RUN-1001 : Setup | -1.799 | -4.467 | 4
RUN-1001 : Hold | 0.067 | 0.000 | 0
RUN-1001 : --------------------------------------
-PHY-1001 : End update timing; 3.198522s wall, 3.187500s user + 0.015625s system = 3.203125s CPU (100.1%)
+PHY-1001 : End update timing; 3.475285s wall, 3.468750s user + 0.000000s system = 3.468750s CPU (99.8%)
PHY-1001 : Current memory(MB): used = 1054, reserve = 1059, peak = 1054.
-PHY-1001 : End phase 2; 30.125190s wall, 63.109375s user + 0.312500s system = 63.421875s CPU (210.5%)
+PHY-1001 : End phase 2; 34.540448s wall, 69.593750s user + 0.296875s system = 69.890625s CPU (202.3%)
PHY-1001 : ===== Detail Route Phase 3 =====
PHY-1001 : Optimize timing.....
PHY-1001 : ===== OPT Iter 1 =====
-PHY-1001 : Processed 7 pins with SWNS -2.059ns STNS -4.082ns FEP 3.
-PHY-1001 : End OPT Iter 1; 0.158643s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (98.5%)
+PHY-1001 : Processed 4 pins with SWNS -1.797ns STNS -3.968ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.160822s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (106.9%)
-PHY-1022 : len = 2.37967e+06, over cnt = 1980(0%), over = 1986, worst = 2, crit = 0
-PHY-1001 : End optimize timing; 0.412551s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (98.5%)
+PHY-1022 : len = 2.38541e+06, over cnt = 1942(0%), over = 1947, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.456183s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (102.8%)
PHY-1001 : Ripup-reroute.....
PHY-1001 : ===== DR Iter 1 =====
-PHY-1022 : len = 2.34211e+06, over cnt = 870(0%), over = 871, worst = 2, crit = 0
-PHY-1001 : End DR Iter 1; 1.731552s wall, 2.687500s user + 0.015625s system = 2.703125s CPU (156.1%)
+PHY-1022 : len = 2.35104e+06, over cnt = 800(0%), over = 801, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.258916s wall, 4.187500s user + 0.000000s system = 4.187500s CPU (185.4%)
PHY-1001 : ===== DR Iter 2 =====
-PHY-1022 : len = 2.33666e+06, over cnt = 161(0%), over = 161, worst = 1, crit = 0
-PHY-1001 : End DR Iter 2; 1.004691s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (133.7%)
+PHY-1022 : len = 2.34865e+06, over cnt = 253(0%), over = 254, worst = 2, crit = 0
+PHY-1001 : End DR Iter 2; 0.761614s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (141.6%)
PHY-1001 : ===== DR Iter 3 =====
-PHY-1022 : len = 2.3379e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
-PHY-1001 : End DR Iter 3; 0.435064s wall, 0.437500s user + 0.015625s system = 0.453125s CPU (104.2%)
+PHY-1022 : len = 2.34642e+06, over cnt = 33(0%), over = 33, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.752782s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (128.7%)
PHY-1001 : ===== DR Iter 4 =====
-PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
-PHY-1001 : End DR Iter 4; 0.187505s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (100.0%)
+PHY-1022 : len = 2.34658e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.332144s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (98.8%)
PHY-1001 : ===== DR Iter 5 =====
-PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
-PHY-1001 : End DR Iter 5; 0.182317s wall, 0.203125s user + 0.031250s system = 0.234375s CPU (128.6%)
-
-PHY-1001 : ===== DR Iter 6 =====
-PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
-PHY-1001 : End DR Iter 6; 0.206544s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (105.9%)
-
-PHY-1001 : ===== DR Iter 7 =====
-PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
-PHY-1001 : End DR Iter 7; 0.248191s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (100.7%)
-
-PHY-1001 : ===== DR Iter 8 =====
-PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
-PHY-1001 : End DR Iter 8; 0.167488s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (102.6%)
-
-PHY-1001 : ==== DR Iter 9 ====
-PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
-PHY-1001 : End DR Iter 9; 0.160728s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (97.2%)
-
-PHY-1001 : ==== DR Iter 10 ====
-PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
-PHY-1001 : End DR Iter 10; 0.169262s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.5%)
-
-PHY-1001 : ==== DR Iter 11 ====
-PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
-PHY-1001 : End DR Iter 11; 0.205771s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (98.7%)
-
-PHY-1001 : ==== DR Iter 12 ====
-PHY-1022 : len = 2.33794e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
-PHY-1001 : End DR Iter 12; 0.242679s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (103.0%)
-
-PHY-1001 : ===== DR Iter 13 =====
-PHY-1022 : len = 2.33796e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
-PHY-1001 : End DR Iter 13; 0.173905s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.8%)
-
-PHY-1001 : ==== DR Iter 14 ====
-PHY-1022 : len = 2.33796e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
-PHY-1001 : End DR Iter 14; 0.170132s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (101.0%)
-
-PHY-1001 : ==== DR Iter 15 ====
-PHY-1022 : len = 2.33794e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
-PHY-1001 : End DR Iter 15; 0.184759s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (101.5%)
+PHY-1022 : len = 2.34667e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.188044s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.7%)
PHY-1001 : Update timing.....
-PHY-1001 : 4/16594(0%) critical/total net(s).
+PHY-1001 : 4/16553(0%) critical/total net(s).
RUN-1001 : --------------------------------------
RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
RUN-1001 : --------------------------------------
-RUN-1001 : Setup | -2.059 | -4.082 | 3
+RUN-1001 : Setup | -1.797 | -3.968 | 3
RUN-1001 : Hold | 0.067 | 0.000 | 0
RUN-1001 : --------------------------------------
-PHY-1001 : End update timing; 3.208139s wall, 3.203125s user + 0.000000s system = 3.203125s CPU (99.8%)
+PHY-1001 : End update timing; 3.491980s wall, 3.484375s user + 0.000000s system = 3.484375s CPU (99.8%)
PHY-1001 : Commit to database.....
-PHY-1001 : 627 feed throughs used by 436 nets
-PHY-1001 : End commit to database; 2.229244s wall, 2.203125s user + 0.015625s system = 2.218750s CPU (99.5%)
+PHY-1001 : 586 feed throughs used by 421 nets
+PHY-1001 : End commit to database; 2.400501s wall, 2.406250s user + 0.000000s system = 2.406250s CPU (100.2%)
-PHY-1001 : Current memory(MB): used = 1156, reserve = 1165, peak = 1156.
-PHY-1001 : End phase 3; 11.731169s wall, 13.031250s user + 0.093750s system = 13.125000s CPU (111.9%)
+PHY-1001 : Current memory(MB): used = 1157, reserve = 1166, peak = 1157.
+PHY-1001 : End phase 3; 11.067591s wall, 13.500000s user + 0.000000s system = 13.500000s CPU (122.0%)
PHY-1001 : ===== Detail Route Phase 4 =====
PHY-1001 : Optimize timing.....
PHY-1001 : ===== OPT Iter 1 =====
-PHY-1001 : Processed 3 pins with SWNS -2.059ns STNS -4.082ns FEP 3.
-PHY-1001 : End OPT Iter 1; 0.138168s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.8%)
+PHY-1001 : Processed 3 pins with SWNS -1.797ns STNS -3.968ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.151432s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (103.2%)
-PHY-1022 : len = 2.33794e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
-PHY-1001 : End optimize timing; 0.375480s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (104.0%)
+PHY-1022 : len = 2.34667e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.409648s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.2%)
-PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-2.059ns, -4.082ns, 3}
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.797ns, -3.968ns, 3}
PHY-1001 : Update timing.....
-PHY-1001 : 4/16594(0%) critical/total net(s).
+PHY-1001 : 4/16553(0%) critical/total net(s).
RUN-1001 : --------------------------------------
RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
RUN-1001 : --------------------------------------
-RUN-1001 : Setup | -2.059 | -4.082 | 3
+RUN-1001 : Setup | -1.797 | -3.968 | 3
RUN-1001 : Hold | 0.067 | 0.000 | 0
RUN-1001 : --------------------------------------
-PHY-1001 : End update timing; 3.180221s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (99.7%)
+PHY-1001 : End update timing; 3.554722s wall, 3.562500s user + 0.000000s system = 3.562500s CPU (100.2%)
PHY-1001 : Commit to database.....
-PHY-1001 : 627 feed throughs used by 436 nets
-PHY-1001 : End commit to database; 2.343285s wall, 2.343750s user + 0.000000s system = 2.343750s CPU (100.0%)
+PHY-1001 : 586 feed throughs used by 421 nets
+PHY-1001 : End commit to database; 2.510793s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (99.6%)
-PHY-1001 : Current memory(MB): used = 1165, reserve = 1174, peak = 1165.
-PHY-1001 : End phase 4; 5.924018s wall, 5.921875s user + 0.000000s system = 5.921875s CPU (100.0%)
+PHY-1001 : Current memory(MB): used = 1166, reserve = 1175, peak = 1166.
+PHY-1001 : End phase 4; 6.505379s wall, 6.500000s user + 0.000000s system = 6.500000s CPU (99.9%)
-PHY-1003 : Routed, final wirelength = 2.33794e+06
-PHY-1001 : Current memory(MB): used = 1167, reserve = 1176, peak = 1167.
-PHY-1001 : End export database. 0.060953s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.5%)
+PHY-1003 : Routed, final wirelength = 2.34667e+06
+PHY-1001 : Current memory(MB): used = 1169, reserve = 1177, peak = 1169.
+PHY-1001 : End export database. 0.065920s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.8%)
-PHY-1001 : End detail routing; 58.440281s wall, 92.640625s user + 0.484375s system = 93.125000s CPU (159.4%)
+PHY-1001 : End detail routing; 62.899885s wall, 100.312500s user + 0.343750s system = 100.656250s CPU (160.0%)
-RUN-1003 : finish command "route" in 64.741994s wall, 99.812500s user + 0.531250s system = 100.343750s CPU (155.0%)
+RUN-1003 : finish command "route" in 69.437223s wall, 107.968750s user + 0.453125s system = 108.421875s CPU (156.1%)
-RUN-1004 : used memory is 1093 MB, reserved memory is 1106 MB, peak memory is 1167 MB
+RUN-1004 : used memory is 1090 MB, reserved memory is 1098 MB, peak memory is 1169 MB
RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
RUN-1001 : standard
***Report Model: huagao_mipi_top Device: EG4D20EG176***
@@ -1586,12 +1720,12 @@ IO Statistics
#inout 0
Utilization Statistics
-#lut 10345 out of 19600 52.78%
-#reg 9356 out of 19600 47.73%
-#le 12483
- #lut only 3127 out of 12483 25.05%
- #reg only 2138 out of 12483 17.13%
- #lut® 7218 out of 12483 57.82%
+#lut 10320 out of 19600 52.65%
+#reg 9363 out of 19600 47.77%
+#le 12661
+ #lut only 3298 out of 12661 26.05%
+ #reg only 2341 out of 12661 18.49%
+ #lut® 7022 out of 12661 55.46%
#dsp 3 out of 29 10.34%
#bram 54 out of 64 84.38%
#bram9k 50
@@ -1599,24 +1733,24 @@ Utilization Statistics
#bram32k 4 out of 16 25.00%
#pad 75 out of 130 57.69%
#ireg 13
- #oreg 21
+ #oreg 18
#treg 0
#pll 3 out of 4 75.00%
#gclk 6 out of 16 37.50%
Clock Resource Statistics
Index ClockNet Type DriverType Driver Fanout
-#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1785
-#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1421
-#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1348
-#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 951
-#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 144
-#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
-#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
-#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1795
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1417
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1355
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 967
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 139
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24
#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
-#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg40_syn_225.f1 3
-#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg50_syn_208.f1 2
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg42_syn_219.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_b/u_ADconfig/reg1_syn_191.f0 2
#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
@@ -1626,36 +1760,36 @@ Index ClockNet Type
Detailed IO Report
Name Direction Location IOStandard DriveStrength PullType PackReg
- a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
- a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
- a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
- a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
- b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
- b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
- b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
- b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ a_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
- onoff_in INPUT P140 LVCMOS33 N/A N/A NONE
- paper_in INPUT P17 LVCMOS25 N/A N/A NONE
+ onoff_in INPUT P133 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P4 LVCMOS25 N/A N/A NONE
rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
@@ -1677,76 +1811,78 @@ Detailed IO Report
O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
- a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
- a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
- a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
- a_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ a_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
- b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
- b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
- b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
- b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ b_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
- debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
- debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
- debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
- fan_pwm OUTPUT P25 LVCMOS25 8 N/A NONE
+ fan_pwm OUTPUT P138 LVCMOS33 8 N/A NONE
frame_indicator OUTPUT P16 LVCMOS25 8 N/A OREG
- onoff_out OUTPUT P118 LVCMOS25 8 N/A NONE
- paper_out OUTPUT P104 LVCMOS25 8 N/A NONE
- scan_out OUTPUT P83 LVCMOS25 8 N/A NONE
- sys_initial_done OUTPUT P32 LVCMOS25 8 N/A NONE
+ onoff_out OUTPUT P152 LVCMOS33 8 N/A NONE
+ paper_out OUTPUT P17 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P15 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P104 LVCMOS25 8 N/A NONE
txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
Report Hierarchy Area:
+---------------------------------------------------------------------------------------------------------+
|Instance |Module |le |lut |ripple |seq |bram |dsp |
+---------------------------------------------------------------------------------------------------------+
-|top |huagao_mipi_top |12483 |9318 |1027 |9390 |58 |3 |
-| U_rgb_to_csi_pakage |rgb_to_csi_pakage |558 |470 |23 |457 |4 |1 |
-| U_fifo_w32_d8192 |fifo_w32_d8192 |103 |85 |4 |91 |4 |0 |
-| U_crc16_24b |crc16_24b |34 |34 |0 |21 |0 |0 |
-| U_ecc_gen |ecc_gen |9 |9 |0 |8 |0 |0 |
-| exdev_ctl_a |exdev_ctl |785 |405 |96 |577 |0 |0 |
-| u_ADconfig |AD_config |191 |139 |25 |145 |0 |0 |
-| u_gen_sp |gen_sp |276 |185 |71 |114 |0 |0 |
-| exdev_ctl_b |exdev_ctl |761 |400 |96 |555 |0 |0 |
-| u_ADconfig |AD_config |186 |137 |25 |123 |0 |0 |
-| u_gen_sp |gen_sp |259 |173 |71 |116 |0 |0 |
-| sampling_fe_a |sampling_fe |2929 |2427 |306 |1994 |25 |0 |
-| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
-| u_ad_sampling |ad_sampling |187 |138 |17 |141 |0 |0 |
+|top |huagao_mipi_top |12661 |9293 |1027 |9394 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |545 |451 |23 |442 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |98 |83 |4 |90 |4 |0 |
+| U_crc16_24b |crc16_24b |29 |29 |0 |19 |0 |0 |
+| U_ecc_gen |ecc_gen |14 |14 |0 |10 |0 |0 |
+| exdev_ctl_a |exdev_ctl |767 |373 |96 |581 |0 |0 |
+| u_ADconfig |AD_config |188 |139 |25 |142 |0 |0 |
+| u_gen_sp |gen_sp |263 |160 |71 |123 |0 |0 |
+| exdev_ctl_b |exdev_ctl |752 |423 |96 |556 |0 |0 |
+| u_ADconfig |AD_config |178 |140 |25 |126 |0 |0 |
+| u_gen_sp |gen_sp |262 |168 |71 |118 |0 |0 |
+| sampling_fe_a |sampling_fe |3094 |2433 |306 |2032 |25 |0 |
+| u0_soft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |183 |97 |17 |141 |0 |0 |
| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
-| u_sort |sort |2708 |2271 |289 |1819 |25 |0 |
-| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
-| u0_wrsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
-| u_data_prebuffer |data_prebuffer |2358 |1986 |253 |1518 |22 |0 |
-| channelPart |channel_part_8478 |154 |151 |3 |138 |0 |0 |
-| fifo_adc |fifo_adc |61 |52 |9 |42 |0 |0 |
-| ram_switch |ram_switch |1853 |1549 |197 |1126 |0 |0 |
-| adc_addr_gen |adc_addr_gen |250 |223 |27 |124 |0 |0 |
-| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |8 |0 |0 |
-| [1]$ch_addr_gen |ch_addr_gen |27 |24 |3 |16 |0 |0 |
-| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
-| [3]$ch_addr_gen |ch_addr_gen |21 |18 |3 |9 |0 |0 |
-| [4]$ch_addr_gen |ch_addr_gen |29 |26 |3 |14 |0 |0 |
-| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
-| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
-| [7]$ch_addr_gen |ch_addr_gen |27 |24 |3 |12 |0 |0 |
-| [8]$ch_addr_gen |ch_addr_gen |30 |27 |3 |13 |0 |0 |
-| insert |insert |962 |685 |170 |654 |0 |0 |
-| ram_switch_state |ram_switch_state |641 |641 |0 |348 |0 |0 |
-| read_ram_i |read_ram |263 |208 |44 |185 |0 |0 |
-| read_ram_addr |read_ram_addr |210 |170 |40 |146 |0 |0 |
-| read_ram_data |read_ram_data |51 |36 |4 |37 |0 |0 |
-| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_sort |sort |2875 |2311 |289 |1855 |25 |0 |
+| rddpram_ctl |rddpram_ctl |5 |5 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2499 |2063 |253 |1538 |22 |0 |
+| channelPart |channel_part_8478 |133 |130 |3 |122 |0 |0 |
+| fifo_adc |fifo_adc |62 |53 |9 |44 |0 |0 |
+| ram_switch |ram_switch |1994 |1633 |197 |1144 |0 |0 |
+| adc_addr_gen |adc_addr_gen |244 |217 |27 |114 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |8 |5 |3 |4 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |29 |26 |3 |14 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |9 |0 |0 |
+| insert |insert |953 |620 |170 |654 |0 |0 |
+| ram_switch_state |ram_switch_state |797 |796 |0 |376 |0 |0 |
+| read_ram_i |read_ram |265 |209 |44 |186 |0 |0 |
+| read_ram_addr |read_ram_addr |213 |173 |40 |147 |0 |0 |
+| read_ram_data |read_ram_data |51 |35 |4 |38 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
@@ -1761,42 +1897,42 @@ Report Hierarchy Area:
| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u_transfer_300_to_200 |transfer_300_to_200 |316 |259 |36 |267 |3 |0 |
-| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |339 |233 |36 |280 |3 |0 |
+| u0_soft_n |cdc_sync |7 |7 |0 |7 |0 |0 |
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
-| sampling_fe_b |sampling_fe_rev |3306 |2572 |349 |2092 |25 |1 |
-| u0_soft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
-| u_ad_sampling |ad_sampling |185 |101 |17 |148 |0 |0 |
-| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
-| u_sort |sort_rev |3087 |2458 |332 |1910 |25 |1 |
-| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
-| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
-| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
-| u0_wrsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
-| u_data_prebuffer_rev |data_prebuffer_rev |2665 |2161 |290 |1546 |22 |1 |
-| channelPart |channel_part_8478 |232 |228 |3 |136 |0 |0 |
-| fifo_adc |fifo_adc |60 |51 |9 |44 |0 |1 |
-| ram_switch |ram_switch |1981 |1613 |197 |1120 |0 |0 |
-| adc_addr_gen |adc_addr_gen |228 |201 |27 |105 |0 |0 |
-| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |4 |0 |0 |
-| [1]$ch_addr_gen |ch_addr_gen |28 |25 |3 |14 |0 |0 |
-| [2]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
-| [3]$ch_addr_gen |ch_addr_gen |21 |18 |3 |12 |0 |0 |
-| [4]$ch_addr_gen |ch_addr_gen |21 |18 |3 |8 |0 |0 |
-| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |6 |0 |0 |
-| [6]$ch_addr_gen |ch_addr_gen |27 |24 |3 |12 |0 |0 |
-| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
-| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 |
-| insert |insert |1007 |668 |170 |696 |0 |0 |
-| ram_switch_state |ram_switch_state |746 |744 |0 |319 |0 |0 |
-| read_ram_i |read_ram_rev |359 |248 |81 |213 |0 |0 |
-| read_ram_addr |read_ram_addr_rev |286 |202 |73 |160 |0 |0 |
-| read_ram_data |read_ram_data_rev |73 |46 |8 |53 |0 |0 |
+| sampling_fe_b |sampling_fe_rev |3367 |2648 |349 |2114 |25 |1 |
+| u0_soft_n |cdc_sync |6 |1 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |166 |113 |17 |130 |0 |0 |
+| u0_soft_n |cdc_sync |6 |1 |0 |6 |0 |0 |
+| u_sort |sort_rev |3165 |2522 |332 |1948 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |3 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |7 |2 |0 |7 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2731 |2228 |290 |1587 |22 |1 |
+| channelPart |channel_part_8478 |238 |235 |3 |135 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
+| ram_switch |ram_switch |1983 |1621 |197 |1142 |0 |0 |
+| adc_addr_gen |adc_addr_gen |221 |194 |27 |105 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |30 |27 |3 |18 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |8 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |21 |18 |3 |10 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| insert |insert |974 |641 |170 |669 |0 |0 |
+| ram_switch_state |ram_switch_state |788 |786 |0 |368 |0 |0 |
+| read_ram_i |read_ram_rev |424 |303 |81 |240 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |291 |206 |73 |159 |0 |0 |
+| read_ram_data |read_ram_data_rev |133 |97 |8 |81 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
@@ -1805,8 +1941,6 @@ Report Hierarchy Area:
| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
-| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|...... |...... |- |- |- |- |- |- |
+---------------------------------------------------------------------------------------------------------+
@@ -1814,15 +1948,15 @@ Report Hierarchy Area:
DataNet Average Fanout:
Index Fanout Nets
- #1 1 9929
- #2 2 3890
- #3 3 1404
- #4 4 524
- #5 5-10 1204
- #6 11-50 601
- #7 51-100 23
+ #1 1 9824
+ #2 2 3937
+ #3 3 1458
+ #4 4 642
+ #5 5-10 1062
+ #6 11-50 587
+ #7 51-100 24
#8 >500 1
- Average 2.92
+ Average 2.91
RUN-1002 : start command "export_db hg_anlogic_pr.db"
RUN-1001 : Exported /
@@ -1840,20 +1974,20 @@ RUN-1001 : Exported violations
RUN-1001 : Exported timing constraints
RUN-1001 : Exported IO constraints
RUN-1001 : Exported Inst constraints
-RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.065898s wall, 3.546875s user + 0.031250s system = 3.578125s CPU (173.2%)
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.179280s wall, 3.765625s user + 0.015625s system = 3.781250s CPU (173.5%)
-RUN-1004 : used memory is 1094 MB, reserved memory is 1107 MB, peak memory is 1167 MB
+RUN-1004 : used memory is 1091 MB, reserved memory is 1099 MB, peak memory is 1169 MB
RUN-1002 : start command "start_timer"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74418, tnet num: 17493, tinst num: 6866, tnode num: 96890, tedge num: 124901.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74216, tnet num: 17452, tinst num: 6930, tnode num: 96760, tedge num: 124559.
TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer" in 1.580097s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (99.9%)
+RUN-1003 : finish command "start_timer" in 1.739411s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (100.6%)
-RUN-1004 : used memory is 1098 MB, reserved memory is 1111 MB, peak memory is 1167 MB
+RUN-1004 : used memory is 1096 MB, reserved memory is 1104 MB, peak memory is 1169 MB
RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
TMR-2503 : Start to update net delay, extr mode = 6.
-TMR-2504 : Update delay of 17493 nets completely.
+TMR-2504 : Update delay of 17452 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 6.
TMR-3001 : Initiate 12 clocks from SDC.
TMR-3004 : Map sdc constraints, there are 6 constraints in total.
@@ -1869,27 +2003,27 @@ TMR-5009 WARNING: No clock constraint on 3 clock net(s):
exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
TMR-3508 : Export timing summary.
TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
-RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.431673s wall, 1.406250s user + 0.015625s system = 1.421875s CPU (99.3%)
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.583424s wall, 1.562500s user + 0.015625s system = 1.578125s CPU (99.7%)
-RUN-1004 : used memory is 1101 MB, reserved memory is 1113 MB, peak memory is 1167 MB
+RUN-1004 : used memory is 1099 MB, reserved memory is 1106 MB, peak memory is 1169 MB
RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
PRG-1000 :
RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
BIT-1003 : Start to generate bitstream.
BIT-1002 : Init instances with 8 threads.
-BIT-1002 : Init instances completely, inst num: 6866
+BIT-1002 : Init instances completely, inst num: 6930
BIT-1002 : Init pips with 8 threads.
-BIT-1002 : Init pips completely, net num: 17671, pip num: 175043
+BIT-1002 : Init pips completely, net num: 17630, pip num: 174550
BIT-1002 : Init feedthrough with 8 threads.
-BIT-1002 : Init feedthrough completely, num: 627
+BIT-1002 : Init feedthrough completely, num: 586
BIT-1003 : Multithreading accelaration with 8 threads.
-BIT-1003 : Generate bitstream completely, there are 3247 valid insts, and 483910 bits set as '1'.
+BIT-1003 : Generate bitstream completely, there are 3249 valid insts, and 483475 bits set as '1'.
BIT-1004 : the usercode register value: 00000000101110110000000000000000
BIT-1004 : PLL setting string = 1011
BIT-1004 : Generate bits file hg_anlogic.bit.
BIT-1004 : Generate bin file hg_anlogic.bin.
-RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.708607s wall, 66.218750s user + 0.125000s system = 66.343750s CPU (683.3%)
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.850289s wall, 64.062500s user + 0.187500s system = 64.250000s CPU (652.3%)
-RUN-1004 : used memory is 1267 MB, reserved memory is 1270 MB, peak memory is 1382 MB
-RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240123_141717.log"
+RUN-1004 : used memory is 1267 MB, reserved memory is 1270 MB, peak memory is 1383 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240218_161224.log"
RUN-1001 : Backing up run's log file succeed.
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_gate.begin.f b/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_gate.begin.f
index b51d5ec..1a9c951 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_gate.begin.f
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_gate.begin.f
@@ -1,5 +1,5 @@
-
+
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_rtl.begin.f b/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_rtl.begin.f
index b51d5ec..1a9c951 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_rtl.begin.f
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_rtl.begin.f
@@ -1,5 +1,5 @@
-
+
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/.read_design.begin.f b/src/prj/td_project/hg_anlogic_Runs/syn_1/.read_design.begin.f
index b51d5ec..1a9c951 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/.read_design.begin.f
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/.read_design.begin.f
@@ -1,5 +1,5 @@
-
+
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic.prj b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic.prj
index 84159ad..3c08349 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic.prj
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic.prj
@@ -1,5 +1,5 @@
-
+
UTF-8
5.6.71036
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db
index f60896f..88fcdd3 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db and b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.area b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.area
index 13d7253..a586c41 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.area
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.area
@@ -8,15 +8,15 @@ IO Statistics
#inout 0
LUT Statistics
-#Total_luts 10043
- #lut4 5250
- #lut5 2238
+#Total_luts 9995
+ #lut4 5129
+ #lut5 2311
#lut6 0
#lut5_mx41 0
#lut4_alu1b 2555
Utilization Statistics
-#lut 10043 out of 19600 51.24%
+#lut 9995 out of 19600 50.99%
#reg 9170 out of 19600 46.79%
#le 0
#dsp 3 out of 29 10.34%
@@ -27,7 +27,7 @@ Utilization Statistics
#dram 16
#pad 75 out of 130 57.69%
#ireg 13
- #oreg 21
+ #oreg 18
#treg 0
#pll 3 out of 4 75.00%
@@ -35,30 +35,30 @@ Report Hierarchy Area:
+-------------------------------------------------------------------------------------------------+
|Instance |Module |lut |ripple |seq |bram |dsp |
+-------------------------------------------------------------------------------------------------+
-|top |huagao_mipi_top |7488 |2555 |9204 |58 |3 |
+|top |huagao_mipi_top |7440 |2555 |9201 |58 |3 |
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |339 |81 |441 |4 |1 |
| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 |
| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
-| exdev_ctl_a |exdev_ctl |287 |234 |559 |0 |0 |
-| u_ADconfig |AD_config |100 |49 |138 |0 |0 |
-| u_gen_sp |gen_sp |129 |185 |104 |0 |0 |
-| exdev_ctl_b |exdev_ctl |275 |234 |546 |0 |0 |
+| exdev_ctl_a |exdev_ctl |282 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |99 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |125 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |279 |234 |546 |0 |0 |
| u_ADconfig |AD_config |91 |49 |125 |0 |0 |
-| u_gen_sp |gen_sp |126 |185 |104 |0 |0 |
-| sampling_fe_a |sampling_fe |2108 |738 |1894 |25 |0 |
+| u_gen_sp |gen_sp |130 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2067 |738 |1894 |25 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
-| u_sort |sort |2038 |691 |1712 |25 |0 |
+| u_sort |sort |1997 |691 |1712 |25 |0 |
| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
-| u_data_prebuffer |data_prebuffer |1909 |615 |1391 |22 |0 |
+| u_data_prebuffer |data_prebuffer |1868 |615 |1391 |22 |0 |
| channelPart |channel_part_8478 |147 |11 |144 |0 |0 |
| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
-| ram_switch |ram_switch |1483 |422 |1023 |0 |0 |
+| ram_switch |ram_switch |1448 |422 |1023 |0 |0 |
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
@@ -70,10 +70,10 @@ Report Hierarchy Area:
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| insert |insert |265 |323 |692 |0 |0 |
-| ram_switch_state |ram_switch_state |1089 |0 |216 |0 |0 |
-| read_ram_i |read_ram |192 |158 |164 |0 |0 |
-| read_ram_addr |read_ram_addr |161 |145 |127 |0 |0 |
-| read_ram_data |read_ram_data |30 |13 |32 |0 |0 |
+| ram_switch_state |ram_switch_state |1054 |0 |216 |0 |0 |
+| read_ram_i |read_ram |186 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |158 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |27 |13 |32 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
@@ -100,19 +100,19 @@ Report Hierarchy Area:
| u_transfer_300_to_200 |transfer_300_to_200 |122 |76 |276 |3 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
-| sampling_fe_b |sampling_fe_rev |2299 |751 |1958 |25 |1 |
+| sampling_fe_b |sampling_fe_rev |2261 |751 |1958 |25 |1 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
-| u_sort |sort_rev |2229 |704 |1776 |25 |1 |
+| u_sort |sort_rev |2191 |704 |1776 |25 |1 |
| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
-| u_data_prebuffer_rev |data_prebuffer_rev |2104 |628 |1405 |22 |1 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2066 |628 |1405 |22 |1 |
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
-| ram_switch |ram_switch |1478 |422 |1023 |0 |0 |
+| ram_switch |ram_switch |1441 |422 |1023 |0 |0 |
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
@@ -124,9 +124,9 @@ Report Hierarchy Area:
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| insert |insert |265 |323 |692 |0 |0 |
-| ram_switch_state |ram_switch_state |1084 |0 |216 |0 |0 |
-| read_ram_i |read_ram_rev |391 |171 |178 |0 |0 |
-| read_ram_addr |read_ram_addr_rev |177 |145 |136 |0 |0 |
+| ram_switch_state |ram_switch_state |1047 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |390 |171 |178 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |176 |145 |136 |0 |0 |
| read_ram_data |read_ram_data_rev |214 |26 |42 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
@@ -165,16 +165,16 @@ Report Hierarchy Area:
| u_b_sp_sampling |cdc_sync |1 |0 |5 |0 |0 |
| u_b_sp_sampling_cam |cdc_sync |1 |0 |5 |0 |0 |
| u_b_sp_sampling_last |cdc_sync |1 |0 |5 |0 |0 |
-| u_bus_top |ubus_top |809 |50 |1248 |0 |0 |
-| u_local_bus_slve_cis |local_bus_slve_cis |715 |50 |721 |0 |0 |
-| u_uart_2dsp |uart_2dsp |115 |31 |52 |0 |0 |
+| u_bus_top |ubus_top |826 |50 |1248 |0 |0 |
+| u_local_bus_slve_cis |local_bus_slve_cis |732 |50 |721 |0 |0 |
+| u_uart_2dsp |uart_2dsp |119 |31 |52 |0 |0 |
| u_dpi_mode |cdc_sync |2 |0 |10 |0 |0 |
| u_eot |cdc_sync |1 |0 |5 |0 |0 |
| u_lv_en_flag |cdc_sync |1 |0 |5 |0 |0 |
-| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |163 |61 |226 |4 |0 |
-| u_hs_tx_wrapper |hs_tx_wrapper |108 |61 |198 |4 |0 |
-| [0]$u_data_lane_wrapper |data_lane_wrapper |50 |52 |93 |1 |0 |
-| u_data_hs_generate |data_hs_generate |46 |52 |87 |1 |0 |
+| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |170 |61 |226 |4 |0 |
+| u_hs_tx_wrapper |hs_tx_wrapper |111 |61 |198 |4 |0 |
+| [0]$u_data_lane_wrapper |data_lane_wrapper |54 |52 |93 |1 |0 |
+| u_data_hs_generate |data_hs_generate |50 |52 |87 |1 |0 |
| u_dphy_tx_fifo |dphy_tx_fifo |2 |0 |0 |1 |0 |
| u_d1024_w8_fifo |d1024_w8_fifo |2 |0 |0 |1 |0 |
| u_data_lp_generate |data_lp_generate |4 |0 |6 |0 |0 |
@@ -193,7 +193,7 @@ Report Hierarchy Area:
| u_clk_lane_wrapper |clk_lane_wrapper |3 |0 |8 |0 |0 |
| u_clk_hs_generate |clk_hs_generate |3 |0 |4 |0 |0 |
| u_clk_lp_generate |clk_lp_generate |0 |0 |4 |0 |0 |
-| u_hs_tx_controler |hs_tx_controler |25 |9 |12 |0 |0 |
+| u_hs_tx_controler |hs_tx_controler |24 |9 |12 |0 |0 |
| u_mipi_eot_min |cdc_sync |20 |0 |65 |0 |0 |
| u_mipi_sot_min |cdc_sync |20 |0 |65 |0 |0 |
| u_pic_cnt |cdc_sync |38 |0 |120 |0 |0 |
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.db b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.db
index 4a4451f..e433079 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.db and b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.db differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.area b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.area
index 2b18259..fc61d5a 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.area
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.area
@@ -43,16 +43,16 @@ Report Hierarchy Area:
| exdev_ctl_b |exdev_ctl |158 |546 |41 |
| u_ADconfig |AD_config |81 |125 |18 |
| u_gen_sp |gen_sp |76 |104 |19 |
-| sampling_fe_a |sampling_fe |1837 |1894 |269 |
+| sampling_fe_a |sampling_fe |1838 |1894 |269 |
| u0_soft_n |cdc_sync |2 |5 |0 |
| u_ad_sampling |ad_sampling |40 |147 |10 |
| u0_soft_n |cdc_sync |2 |5 |0 |
-| u_sort |sort |1793 |1712 |258 |
+| u_sort |sort |1794 |1712 |258 |
| rddpram_ctl |rddpram_ctl |2 |5 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_wrsoft_n |cdc_sync |2 |5 |0 |
-| u_data_prebuffer |data_prebuffer |1538 |1391 |118 |
+| u_data_prebuffer |data_prebuffer |1539 |1391 |118 |
| channelPart |channel_part_8478 |865 |144 |8 |
| fifo_adc |fifo_adc |112 |41 |4 |
| ram_switch |ram_switch |60 |1023 |52 |
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db
index fcee46f..dbf23a3 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db and b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/run.log b/src/prj/td_project/hg_anlogic_Runs/syn_1/run.log
index 555cbec..fccedda 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/run.log
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/run.log
@@ -4,7 +4,7 @@
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
Built at = 20:34:38 Mar 21 2023
Run by = holdtecs
- Run Date = Tue Jan 23 14:15:59 2024
+ Run Date = Sun Feb 18 16:10:55 2024
Run on = DESKTOP-5MQL5VE
============================================================
@@ -422,9 +422,9 @@ HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been re
HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
HDL-1200 : Current top model is huagao_mipi_top
HDL-1100 : Inferred 1 RAMs.
-RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.034104s wall, 1.031250s user + 0.015625s system = 1.046875s CPU (101.2%)
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.135611s wall, 1.109375s user + 0.015625s system = 1.125000s CPU (99.1%)
-RUN-1004 : used memory is 192 MB, reserved memory is 170 MB, peak memory is 232 MB
+RUN-1004 : used memory is 193 MB, reserved memory is 171 MB, peak memory is 233 MB
RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
RUN-1001 : Exported /
RUN-1001 : Exported flow parameters
@@ -456,28 +456,28 @@ RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; I
RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
-RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
-RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
-RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
-RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
@@ -654,7 +654,7 @@ RUN-1001 : ub_lvds_rx | false | lvds_rx |
RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
RUN-1001 : ------------------------------------------------------------------------------------------------
-SYN-1032 : 53811/19108 useful/useless nets, 20667/1811 useful/useless insts
+SYN-1032 : 53810/19109 useful/useless nets, 20666/1812 useful/useless insts
SYN-1001 : Optimize 156 less-than instances
SYN-1016 : Merged 38313 instances.
SYN-1025 : Merged 24 RAM ports.
@@ -1318,9 +1318,9 @@ SYN-1032 : 25138/20 useful/useless nets, 22488/2 useful/useless insts
SYN-1015 : Optimize round 2, 2 better
SYN-1014 : Optimize round 3
SYN-1015 : Optimize round 3, 0 better
-RUN-1003 : finish command "optimize_rtl" in 18.095703s wall, 16.078125s user + 2.015625s system = 18.093750s CPU (100.0%)
+RUN-1003 : finish command "optimize_rtl" in 19.412269s wall, 17.515625s user + 1.875000s system = 19.390625s CPU (99.9%)
-RUN-1004 : used memory is 330 MB, reserved memory is 303 MB, peak memory is 349 MB
+RUN-1004 : used memory is 330 MB, reserved memory is 302 MB, peak memory is 350 MB
RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
RUN-1001 : standard
***Report Model: huagao_mipi_top Device: EG4D20EG176***
@@ -1367,16 +1367,16 @@ Report Hierarchy Area:
| exdev_ctl_b |exdev_ctl |158 |546 |41 |
| u_ADconfig |AD_config |81 |125 |18 |
| u_gen_sp |gen_sp |76 |104 |19 |
-| sampling_fe_a |sampling_fe |1837 |1894 |269 |
+| sampling_fe_a |sampling_fe |1838 |1894 |269 |
| u0_soft_n |cdc_sync |2 |5 |0 |
| u_ad_sampling |ad_sampling |40 |147 |10 |
| u0_soft_n |cdc_sync |2 |5 |0 |
-| u_sort |sort |1793 |1712 |258 |
+| u_sort |sort |1794 |1712 |258 |
| rddpram_ctl |rddpram_ctl |2 |5 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
| u0_wrsoft_n |cdc_sync |2 |5 |0 |
-| u_data_prebuffer |data_prebuffer |1538 |1391 |118 |
+| u_data_prebuffer |data_prebuffer |1539 |1391 |118 |
| channelPart |channel_part_8478 |865 |144 |8 |
| fifo_adc |fifo_adc |112 |41 |4 |
| ram_switch |ram_switch |60 |1023 |52 |
@@ -1475,9 +1475,9 @@ RUN-1001 : Exported congestions
RUN-1001 : Exported violations
RUN-1001 : Exported IO constraints
RUN-1001 : Exported Inst constraints
-RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.046767s wall, 1.703125s user + 0.015625s system = 1.718750s CPU (164.2%)
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.150280s wall, 1.781250s user + 0.015625s system = 1.796875s CPU (156.2%)
-RUN-1004 : used memory is 324 MB, reserved memory is 297 MB, peak memory is 398 MB
+RUN-1004 : used memory is 339 MB, reserved memory is 312 MB, peak memory is 399 MB
RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
RUN-1002 : start command "get_ports clock_source"
RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
@@ -1673,12 +1673,12 @@ SYN-1016 : Merged 12104 instances.
SYN-1032 : 36464/295 useful/useless nets, 33740/0 useful/useless insts
RUN-1002 : start command "start_timer -prepack"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121626, tnet num: 36466, tinst num: 33740, tnode num: 155591, tedge num: 179075.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121620, tnet num: 36466, tinst num: 33740, tnode num: 155576, tedge num: 179063.
TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -prepack" in 1.250589s wall, 1.234375s user + 0.015625s system = 1.250000s CPU (100.0%)
+RUN-1003 : finish command "start_timer -prepack" in 1.483913s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (99.0%)
-RUN-1004 : used memory is 515 MB, reserved memory is 494 MB, peak memory is 515 MB
+RUN-1004 : used memory is 518 MB, reserved memory is 495 MB, peak memory is 518 MB
TMR-2503 : Start to update net delay, extr mode = 2.
TMR-2504 : Update delay of 36466 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 2.
@@ -1689,11 +1689,11 @@ TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
SYN-3001 : Running gate level optimization.
-SYN-2581 : Mapping with K=5, #lut = 7522 (3.86), #lev = 9 (3.14)
+SYN-2581 : Mapping with K=5, #lut = 7519 (3.86), #lev = 10 (3.15)
SYN-2551 : Post LUT mapping optimization.
-SYN-2581 : Mapping with K=5, #lut = 7440 (3.97), #lev = 7 (3.07)
-SYN-3001 : Logic optimization runtime opt = 1.25 sec, map = 0.00 sec
-SYN-3001 : Mapper mapped 18898 instances into 7468 LUTs, name keeping = 56%.
+SYN-2581 : Mapping with K=5, #lut = 7392 (3.95), #lev = 8 (3.06)
+SYN-3001 : Logic optimization runtime opt = 1.35 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 18898 instances into 7420 LUTs, name keeping = 59%.
SYN-3001 : Mapper removed 2 lut buffers
RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
RUN-1001 : standard
@@ -1706,15 +1706,15 @@ IO Statistics
#inout 0
LUT Statistics
-#Total_luts 10043
- #lut4 5250
- #lut5 2238
+#Total_luts 9995
+ #lut4 5129
+ #lut5 2311
#lut6 0
#lut5_mx41 0
#lut4_alu1b 2555
Utilization Statistics
-#lut 10043 out of 19600 51.24%
+#lut 9995 out of 19600 50.99%
#reg 9170 out of 19600 46.79%
#le 0
#dsp 3 out of 29 10.34%
@@ -1725,7 +1725,7 @@ Utilization Statistics
#dram 16
#pad 75 out of 130 57.69%
#ireg 13
- #oreg 21
+ #oreg 18
#treg 0
#pll 3 out of 4 75.00%
@@ -1733,30 +1733,30 @@ Report Hierarchy Area:
+-------------------------------------------------------------------------------------------------+
|Instance |Module |lut |ripple |seq |bram |dsp |
+-------------------------------------------------------------------------------------------------+
-|top |huagao_mipi_top |7488 |2555 |9204 |58 |3 |
+|top |huagao_mipi_top |7440 |2555 |9201 |58 |3 |
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |339 |81 |441 |4 |1 |
| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 |
| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
-| exdev_ctl_a |exdev_ctl |287 |234 |559 |0 |0 |
-| u_ADconfig |AD_config |100 |49 |138 |0 |0 |
-| u_gen_sp |gen_sp |129 |185 |104 |0 |0 |
-| exdev_ctl_b |exdev_ctl |275 |234 |546 |0 |0 |
+| exdev_ctl_a |exdev_ctl |282 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |99 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |125 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |279 |234 |546 |0 |0 |
| u_ADconfig |AD_config |91 |49 |125 |0 |0 |
-| u_gen_sp |gen_sp |126 |185 |104 |0 |0 |
-| sampling_fe_a |sampling_fe |2108 |738 |1894 |25 |0 |
+| u_gen_sp |gen_sp |130 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2067 |738 |1894 |25 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
-| u_sort |sort |2038 |691 |1712 |25 |0 |
+| u_sort |sort |1997 |691 |1712 |25 |0 |
| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
-| u_data_prebuffer |data_prebuffer |1909 |615 |1391 |22 |0 |
+| u_data_prebuffer |data_prebuffer |1868 |615 |1391 |22 |0 |
| channelPart |channel_part_8478 |147 |11 |144 |0 |0 |
| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
-| ram_switch |ram_switch |1483 |422 |1023 |0 |0 |
+| ram_switch |ram_switch |1448 |422 |1023 |0 |0 |
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
@@ -1768,10 +1768,10 @@ Report Hierarchy Area:
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| insert |insert |265 |323 |692 |0 |0 |
-| ram_switch_state |ram_switch_state |1089 |0 |216 |0 |0 |
-| read_ram_i |read_ram |192 |158 |164 |0 |0 |
-| read_ram_addr |read_ram_addr |161 |145 |127 |0 |0 |
-| read_ram_data |read_ram_data |30 |13 |32 |0 |0 |
+| ram_switch_state |ram_switch_state |1054 |0 |216 |0 |0 |
+| read_ram_i |read_ram |186 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |158 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |27 |13 |32 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
@@ -1798,19 +1798,19 @@ Report Hierarchy Area:
| u_transfer_300_to_200 |transfer_300_to_200 |122 |76 |276 |3 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
-| sampling_fe_b |sampling_fe_rev |2299 |751 |1958 |25 |1 |
+| sampling_fe_b |sampling_fe_rev |2261 |751 |1958 |25 |1 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
-| u_sort |sort_rev |2229 |704 |1776 |25 |1 |
+| u_sort |sort_rev |2191 |704 |1776 |25 |1 |
| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
-| u_data_prebuffer_rev |data_prebuffer_rev |2104 |628 |1405 |22 |1 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2066 |628 |1405 |22 |1 |
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
-| ram_switch |ram_switch |1478 |422 |1023 |0 |0 |
+| ram_switch |ram_switch |1441 |422 |1023 |0 |0 |
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
@@ -1822,9 +1822,9 @@ Report Hierarchy Area:
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
| insert |insert |265 |323 |692 |0 |0 |
-| ram_switch_state |ram_switch_state |1084 |0 |216 |0 |0 |
-| read_ram_i |read_ram_rev |391 |171 |178 |0 |0 |
-| read_ram_addr |read_ram_addr_rev |177 |145 |136 |0 |0 |
+| ram_switch_state |ram_switch_state |1047 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |390 |171 |178 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |176 |145 |136 |0 |0 |
| read_ram_data |read_ram_data_rev |214 |26 |42 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
@@ -1849,9 +1849,9 @@ SYN-4007 : Packing 0 gate4 to BLE ...
SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
SYN-4012 : Packed 0 FxMUX
SYN-4013 : Packed 16 DRAM and 4 SEQ.
-RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 54.425753s wall, 54.062500s user + 0.343750s system = 54.406250s CPU (100.0%)
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 63.896196s wall, 63.531250s user + 0.296875s system = 63.828125s CPU (99.9%)
-RUN-1004 : used memory is 396 MB, reserved memory is 390 MB, peak memory is 698 MB
+RUN-1004 : used memory is 395 MB, reserved memory is 386 MB, peak memory is 698 MB
RUN-1002 : start command "legalize_phy_inst"
SYN-1011 : Flatten model huagao_mipi_top
SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
@@ -1871,8 +1871,8 @@ RUN-1001 : Exported violations
RUN-1001 : Exported timing constraints
RUN-1001 : Exported IO constraints
RUN-1001 : Exported Inst constraints
-RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.531390s wall, 2.640625s user + 0.031250s system = 2.671875s CPU (174.5%)
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.634628s wall, 2.843750s user + 0.031250s system = 2.875000s CPU (175.9%)
-RUN-1004 : used memory is 403 MB, reserved memory is 389 MB, peak memory is 698 MB
-RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240123_141559.log"
+RUN-1004 : used memory is 401 MB, reserved memory is 385 MB, peak memory is 698 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240218_161055.log"
RUN-1001 : Backing up run's log file succeed.
diff --git a/src/prj/td_project/td_2024-01-22_16-49-54.log b/src/prj/td_project/td_2024-01-22_16-49-54.log
index e69de29..b68379e 100644
--- a/src/prj/td_project/td_2024-01-22_16-49-54.log
+++ b/src/prj/td_project/td_2024-01-22_16-49-54.log
@@ -0,0 +1,2843 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Jan 22 16:49:54 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 542 feed throughs used by 410 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 11.553190s wall, 11.390625s user + 0.437500s system = 11.828125s CPU (102.4%)
+
+RUN-1004 : used memory is 862 MB, reserved memory is 848 MB, peak memory is 873 MB
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ad_sampling.v
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/ad_sampling.v(131)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/ad_sampling.v(131)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ad_sampling.v
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/ad_sampling.v(132)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/ad_sampling.v(132)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(378)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(379)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(378)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(379)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-8007 ERROR: 'PBUFF_RD_DONE_300DPI' is already declared in ../../hg_mp/fe/prebuffer.v(50)
+HDL-1007 : previous declaration of 'PBUFF_RD_DONE_300DPI' is from here in ../../hg_mp/fe/prebuffer.v(49)
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(210)
+HDL-8007 ERROR: ignore module module due to previous errors in ../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : Verilog file '../../hg_mp/fe/prebuffer.v' ignored due to errors
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(378)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(379)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(210)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(378)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(379)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(211)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(378)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(379)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-8007 ERROR: module 'adc_addr_gen' does not have a parameter named DPIset_200DPI in ../../hg_mp/fe/ram_switch.v(58)
+HDL-8007 ERROR: module 'adc_addr_gen' does not have a parameter named PBUFF_LENGTH_200DPI in ../../hg_mp/fe/ram_switch.v(64)
+HDL-8007 ERROR: module 'mapping' does not have a parameter named DPIset_200DPI in ../../hg_mp/fe/ram_switch.v(82)
+HDL-8007 ERROR: module 'mapping' does not have a parameter named PBUFF_LENGTH_200DPI in ../../hg_mp/fe/ram_switch.v(88)
+HDL-8007 ERROR: module 'insert' does not have a parameter named DPIset_200DPI in ../../hg_mp/fe/ram_switch.v(124)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mapping.v
+HDL-8007 ERROR: module 'adc_addr_gen' does not have a parameter named DPIset_200DPI in ../../hg_mp/fe/ram_switch.v(58)
+HDL-8007 ERROR: module 'adc_addr_gen' does not have a parameter named PBUFF_LENGTH_200DPI in ../../hg_mp/fe/ram_switch.v(64)
+HDL-8007 ERROR: module 'insert' does not have a parameter named DPIset_200DPI in ../../hg_mp/fe/ram_switch.v(124)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-8007 ERROR: module 'insert' does not have a parameter named DPIset_200DPI in ../../hg_mp/fe/ram_switch.v(124)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-1007 : undeclared symbol 'cis_sel', assumed default net type 'wire' in ../../hg_mp/fe/ram_switch.v(77)
+HDL-8007 ERROR: module 'insert' does not have a parameter named DPIset_200DPI in ../../hg_mp/fe/ram_switch.v(126)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(76)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(82)
+HDL-8007 ERROR: module 'insert' does not have a parameter named DPIset_200DPI in ../../hg_mp/fe/ram_switch.v(126)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(83)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(378)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(379)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-1007 : undeclared symbol 'cis_sel', assumed default net type 'wire' in ../../hg_mp/fe/ram_switch.v(77)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(378)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(379)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mapping.v
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(378)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(379)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(211)
+HDL-8007 ERROR: 'cis_sel' is not a port in ../../hg_mp/fe/prebuffer.v(363)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(378)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(379)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-8007 ERROR: syntax error near 'non-printable character with the hex value '0xef'' in ../../hg_mp/fe/prebuffer_rev.v(27)
+HDL-1007 : Verilog file '../../hg_mp/fe/prebuffer_rev.v' ignored due to errors
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(378)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(379)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(378)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(379)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'cis_sel', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(371)
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(398)
+HDL-8007 ERROR: cannot find port 'cis_sel' on this module in ../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(177)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(378)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(379)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 Similar messages will be suppressed.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(399)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(378)
+HDL-5007 WARNING: 'cis_sel' is not declared in ../../hg_mp/fe/sort.v(379)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(151)
+HDL-5007 Similar messages will be suppressed.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(177)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(177)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(177)
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(732)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(734)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(743)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(914)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1003)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1304)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1315)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1513)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1909)
+HDL-8007 ERROR: 'WIRE' is an unknown type in ../../hg_mp/drx_top/huagao_mipi_top.v(884)
+HDL-8007 ERROR: ignore module module due to previous errors in ../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : Verilog file '../../hg_mp/drx_top/huagao_mipi_top.v' ignored due to errors
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(177)
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(732)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(734)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(743)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(914)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1003)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1304)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1315)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1513)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1909)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(177)
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(732)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(734)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(743)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(914)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1003)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1304)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1315)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-8007 ERROR: cannot find port 'cis_sel' on this module in ../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-5007 WARNING: assignment to input 'cis_sel' in ../../hg_mp/local_bus/ubus_top.v(302)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(165)
+HDL-5007 Similar messages will be suppressed.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(177)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(177)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-6001 WARNING: Failed to reset phy_1: some files can't be removed in D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1
+RUN-6001 WARNING: Failed to reset syn_1: some files can't be removed in D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/syn_1
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(732)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(734)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(743)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(914)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1003)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1304)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1315)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(177)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(177)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'sync_soft_n' is not declared in ../../hg_mp/fe/rddpram_ctl.v(136)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-5007 Similar messages will be suppressed.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl.v(177)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(151)
+HDL-5007 Similar messages will be suppressed.
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(151)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(165)
+HDL-5007 WARNING: 'DPI200_DEPTH' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(177)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(211)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+RUN-1001 : open_run syn_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db" in 1.349347s wall, 1.062500s user + 0.171875s system = 1.234375s CPU (91.5%)
+
+RUN-1004 : used memory is 516 MB, reserved memory is 498 MB, peak memory is 984 MB
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-5010 WARNING: Net S_hs_last is skipped due to 0 input or output
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 676 feed throughs used by 476 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 8.725861s wall, 8.671875s user + 0.406250s system = 9.078125s CPU (104.0%)
+
+RUN-1004 : used memory is 1065 MB, reserved memory is 1050 MB, peak memory is 1077 MB
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.631412s wall, 0.187500s user + 0.437500s system = 0.625000s CPU (4.0%)
+
+RUN-1004 : used memory is 1114 MB, reserved memory is 1077 MB, peak memory is 1133 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.851573s wall, 0.296875s user + 0.468750s system = 0.765625s CPU (4.8%)
+
+RUN-1004 : used memory is 1114 MB, reserved memory is 1077 MB, peak memory is 1133 MB
+GUI-1001 : Downloading succeeded!
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.647278s wall, 0.093750s user + 0.046875s system = 0.140625s CPU (0.9%)
+
+RUN-1004 : used memory is 1116 MB, reserved memory is 1082 MB, peak memory is 1135 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.870171s wall, 0.203125s user + 0.046875s system = 0.250000s CPU (1.6%)
+
+RUN-1004 : used memory is 1116 MB, reserved memory is 1082 MB, peak memory is 1135 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(732)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(734)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(743)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(914)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1003)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1304)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1315)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1513)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1909)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 623 feed throughs used by 441 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 10.203826s wall, 10.265625s user + 0.265625s system = 10.531250s CPU (103.2%)
+
+RUN-1004 : used memory is 1141 MB, reserved memory is 1111 MB, peak memory is 1147 MB
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.723448s wall, 0.125000s user + 0.078125s system = 0.203125s CPU (1.3%)
+
+RUN-1004 : used memory is 1146 MB, reserved memory is 1113 MB, peak memory is 1165 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.941246s wall, 0.265625s user + 0.078125s system = 0.343750s CPU (2.2%)
+
+RUN-1004 : used memory is 1146 MB, reserved memory is 1113 MB, peak memory is 1165 MB
+GUI-1001 : Downloading succeeded!
+TMR-3509 : Import timing summary.
+TMR-3509 : Import timing summary.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(399)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-8007 ERROR: syntax error near 'assign' in ../../hg_mp/local_bus/ubus_top.v(272)
+HDL-8007 ERROR: Verilog 2000 keyword 'assign' used in incorrect context in ../../hg_mp/local_bus/ubus_top.v(272)
+HDL-8007 ERROR: ignore module module due to previous errors in ../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : Verilog file '../../hg_mp/local_bus/ubus_top.v' ignored due to errors
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(399)
+HDL-5007 WARNING: data object 'dval_o_tmp' is already declared in ../../hg_mp/fe/sort_rev.v(417)
+HDL-1007 : previous declaration of 'dval_o_tmp' is from here in ../../hg_mp/fe/sort_rev.v(86)
+HDL-5007 WARNING: second declaration of 'dval_o_tmp' is ignored in ../../hg_mp/fe/sort_rev.v(417)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(399)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 608 feed throughs used by 448 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 8.979264s wall, 8.953125s user + 0.421875s system = 9.375000s CPU (104.4%)
+
+RUN-1004 : used memory is 1186 MB, reserved memory is 1158 MB, peak memory is 1192 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.671798s wall, 0.171875s user + 0.375000s system = 0.546875s CPU (3.5%)
+
+RUN-1004 : used memory is 1195 MB, reserved memory is 1165 MB, peak memory is 1214 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.900767s wall, 0.296875s user + 0.375000s system = 0.671875s CPU (4.2%)
+
+RUN-1004 : used memory is 1195 MB, reserved memory is 1165 MB, peak memory is 1214 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 481 feed throughs used by 360 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 8.276481s wall, 8.281250s user + 0.375000s system = 8.656250s CPU (104.6%)
+
+RUN-1004 : used memory is 1185 MB, reserved memory is 1155 MB, peak memory is 1214 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.496312s wall, 0.156250s user + 0.234375s system = 0.390625s CPU (2.5%)
+
+RUN-1004 : used memory is 1191 MB, reserved memory is 1161 MB, peak memory is 1214 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.719468s wall, 0.265625s user + 0.250000s system = 0.515625s CPU (3.3%)
+
+RUN-1004 : used memory is 1191 MB, reserved memory is 1161 MB, peak memory is 1214 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(211)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 653 feed throughs used by 483 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 8.879086s wall, 8.828125s user + 0.453125s system = 9.281250s CPU (104.5%)
+
+RUN-1004 : used memory is 1236 MB, reserved memory is 1210 MB, peak memory is 1244 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.672185s wall, 0.062500s user + 0.109375s system = 0.171875s CPU (1.1%)
+
+RUN-1004 : used memory is 1242 MB, reserved memory is 1215 MB, peak memory is 1261 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.892790s wall, 0.171875s user + 0.140625s system = 0.312500s CPU (2.0%)
+
+RUN-1004 : used memory is 1242 MB, reserved memory is 1215 MB, peak memory is 1261 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1513)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1909)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 628 feed throughs used by 444 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 8.606634s wall, 8.578125s user + 0.390625s system = 8.968750s CPU (104.2%)
+
+RUN-1004 : used memory is 1260 MB, reserved memory is 1239 MB, peak memory is 1266 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.630147s wall, 0.093750s user + 0.093750s system = 0.187500s CPU (1.2%)
+
+RUN-1004 : used memory is 1269 MB, reserved memory is 1245 MB, peak memory is 1288 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.848564s wall, 0.234375s user + 0.109375s system = 0.343750s CPU (2.2%)
+
+RUN-1004 : used memory is 1269 MB, reserved memory is 1245 MB, peak memory is 1288 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1513)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1909)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1513)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1909)
+HDL-5007 WARNING: 'line_sync_a' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-5007 WARNING: 'line_sync_a' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1513)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1909)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 557 feed throughs used by 404 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 8.752691s wall, 8.703125s user + 0.468750s system = 9.171875s CPU (104.8%)
+
+RUN-1004 : used memory is 1280 MB, reserved memory is 1259 MB, peak memory is 1288 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.656136s wall, 0.078125s user + 0.343750s system = 0.421875s CPU (2.7%)
+
+RUN-1004 : used memory is 1287 MB, reserved memory is 1264 MB, peak memory is 1306 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.880581s wall, 0.187500s user + 0.359375s system = 0.546875s CPU (3.4%)
+
+RUN-1004 : used memory is 1287 MB, reserved memory is 1264 MB, peak memory is 1306 MB
+GUI-1001 : Downloading succeeded!
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.654258s wall, 0.093750s user + 0.140625s system = 0.234375s CPU (1.5%)
+
+RUN-1004 : used memory is 1282 MB, reserved memory is 1261 MB, peak memory is 1306 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.874098s wall, 0.187500s user + 0.171875s system = 0.359375s CPU (2.3%)
+
+RUN-1004 : used memory is 1282 MB, reserved memory is 1261 MB, peak memory is 1306 MB
+GUI-1001 : Downloading succeeded!
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.686417s wall, 0.078125s user + 0.031250s system = 0.109375s CPU (0.7%)
+
+RUN-1004 : used memory is 1282 MB, reserved memory is 1261 MB, peak memory is 1306 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.903922s wall, 0.171875s user + 0.062500s system = 0.234375s CPU (1.5%)
+
+RUN-1004 : used memory is 1282 MB, reserved memory is 1261 MB, peak memory is 1306 MB
+GUI-1001 : Downloading succeeded!
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-9525 ERROR: Chip validation failed! Please check the connection or type of chip!
+GUI-8702 ERROR: Downloading failed!
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.656273s wall, 0.062500s user + 0.015625s system = 0.078125s CPU (0.5%)
+
+RUN-1004 : used memory is 1282 MB, reserved memory is 1261 MB, peak memory is 1306 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.873017s wall, 0.140625s user + 0.062500s system = 0.203125s CPU (1.3%)
+
+RUN-1004 : used memory is 1282 MB, reserved memory is 1261 MB, peak memory is 1306 MB
+GUI-1001 : Downloading succeeded!
+TMR-3509 : Import timing summary.
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1513)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1909)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 628 feed throughs used by 444 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 8.636032s wall, 8.578125s user + 0.453125s system = 9.031250s CPU (104.6%)
+
+RUN-1004 : used memory is 1303 MB, reserved memory is 1285 MB, peak memory is 1309 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.635393s wall, 0.109375s user + 0.265625s system = 0.375000s CPU (2.4%)
+
+RUN-1004 : used memory is 1312 MB, reserved memory is 1293 MB, peak memory is 1331 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.852976s wall, 0.218750s user + 0.265625s system = 0.484375s CPU (3.1%)
+
+RUN-1004 : used memory is 1312 MB, reserved memory is 1293 MB, peak memory is 1331 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1513)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1909)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 638 feed throughs used by 451 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 11.262492s wall, 11.312500s user + 0.250000s system = 11.562500s CPU (102.7%)
+
+RUN-1004 : used memory is 1314 MB, reserved memory is 1296 MB, peak memory is 1331 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.647543s wall, 0.109375s user + 0.062500s system = 0.171875s CPU (1.1%)
+
+RUN-1004 : used memory is 1316 MB, reserved memory is 1299 MB, peak memory is 1335 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.865448s wall, 0.218750s user + 0.062500s system = 0.281250s CPU (1.8%)
+
+RUN-1004 : used memory is 1316 MB, reserved memory is 1299 MB, peak memory is 1335 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(211)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mapping.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 701 feed throughs used by 508 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 9.008559s wall, 9.062500s user + 0.359375s system = 9.421875s CPU (104.6%)
+
+RUN-1004 : used memory is 1358 MB, reserved memory is 1343 MB, peak memory is 1364 MB
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.638023s wall, 0.109375s user + 0.078125s system = 0.187500s CPU (1.2%)
+
+RUN-1004 : used memory is 1363 MB, reserved memory is 1345 MB, peak memory is 1382 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.857726s wall, 0.218750s user + 0.078125s system = 0.296875s CPU (1.9%)
+
+RUN-1004 : used memory is 1363 MB, reserved memory is 1345 MB, peak memory is 1382 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(399)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-6001 WARNING: phy_1: run failed.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db" in 2.807668s wall, 2.765625s user + 0.187500s system = 2.953125s CPU (105.2%)
+
+RUN-1004 : used memory is 1061 MB, reserved memory is 1058 MB, peak memory is 1382 MB
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(399)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 701 feed throughs used by 508 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 8.813740s wall, 8.734375s user + 0.500000s system = 9.234375s CPU (104.8%)
+
+RUN-1004 : used memory is 1390 MB, reserved memory is 1377 MB, peak memory is 1397 MB
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1513)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1909)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 658 feed throughs used by 467 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 9.428582s wall, 9.390625s user + 0.437500s system = 9.828125s CPU (104.2%)
+
+RUN-1004 : used memory is 1394 MB, reserved memory is 1383 MB, peak memory is 1401 MB
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.637186s wall, 0.078125s user + 0.125000s system = 0.203125s CPU (1.3%)
+
+RUN-1004 : used memory is 1399 MB, reserved memory is 1384 MB, peak memory is 1418 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.860538s wall, 0.203125s user + 0.125000s system = 0.328125s CPU (2.1%)
+
+RUN-1004 : used memory is 1399 MB, reserved memory is 1384 MB, peak memory is 1418 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(399)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : stop_run phy_1.
+RUN-1001 : reset_run phy_1 -step bitgen.
+RUN-1001 : phy_1: run complete.
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1513)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1909)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-5010 WARNING: Net S_hs_last is skipped due to 0 input or output
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 388 feed throughs used by 299 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 8.809855s wall, 8.750000s user + 0.343750s system = 9.093750s CPU (103.2%)
+
+RUN-1004 : used memory is 1397 MB, reserved memory is 1383 MB, peak memory is 1418 MB
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.473575s wall, 0.109375s user + 0.015625s system = 0.125000s CPU (0.8%)
+
+RUN-1004 : used memory is 1398 MB, reserved memory is 1384 MB, peak memory is 1418 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.693830s wall, 0.187500s user + 0.046875s system = 0.234375s CPU (1.5%)
+
+RUN-1004 : used memory is 1398 MB, reserved memory is 1384 MB, peak memory is 1418 MB
+GUI-1001 : Downloading succeeded!
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+TMR-3509 : Import timing summary.
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.478575s wall, 0.640625s user + 0.640625s system = 1.281250s CPU (8.3%)
+
+RUN-1004 : used memory is 1403 MB, reserved memory is 1389 MB, peak memory is 1418 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.695313s wall, 0.734375s user + 0.656250s system = 1.390625s CPU (8.9%)
+
+RUN-1004 : used memory is 1403 MB, reserved memory is 1389 MB, peak memory is 1418 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(399)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : stop_run syn_1.
+RUN-1001 : reset_run syn_1 -step opt_rtl.
+RUN-1001 : syn_1: run complete.
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1513)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1909)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 674 feed throughs used by 484 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 8.985765s wall, 8.875000s user + 0.375000s system = 9.250000s CPU (102.9%)
+
+RUN-1004 : used memory is 1423 MB, reserved memory is 1407 MB, peak memory is 1429 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.632973s wall, 0.046875s user + 0.046875s system = 0.093750s CPU (0.6%)
+
+RUN-1004 : used memory is 1428 MB, reserved memory is 1413 MB, peak memory is 1447 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.853621s wall, 0.140625s user + 0.062500s system = 0.203125s CPU (1.3%)
+
+RUN-1004 : used memory is 1428 MB, reserved memory is 1413 MB, peak memory is 1447 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1513)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1909)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1513)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1909)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1513)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1909)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1513)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1909)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+RUN-1001 : open_run syn_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db" in 1.213865s wall, 1.203125s user + 0.031250s system = 1.234375s CPU (101.7%)
+
+RUN-1004 : used memory is 1325 MB, reserved memory is 1308 MB, peak memory is 1447 MB
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-6001 WARNING: phy_1: run failed.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db" in 2.328545s wall, 2.328125s user + 0.156250s system = 2.484375s CPU (106.7%)
+
+RUN-1004 : used memory is 1336 MB, reserved memory is 1318 MB, peak memory is 1447 MB
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+RUN-1001 : open_run syn_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 627 feed throughs used by 436 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 9.362863s wall, 9.406250s user + 0.437500s system = 9.843750s CPU (105.1%)
+
+RUN-1004 : used memory is 1500 MB, reserved memory is 1487 MB, peak memory is 1508 MB
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.607119s wall, 0.203125s user + 0.406250s system = 0.609375s CPU (3.9%)
+
+RUN-1004 : used memory is 1504 MB, reserved memory is 1488 MB, peak memory is 1523 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.824689s wall, 0.312500s user + 0.421875s system = 0.734375s CPU (4.6%)
+
+RUN-1004 : used memory is 1504 MB, reserved memory is 1488 MB, peak memory is 1523 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : undeclared symbol 'debug', assumed default net type 'wire' in ../../hg_mp/local_bus/ubus_top.v(250)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 627 feed throughs used by 436 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 9.015884s wall, 8.921875s user + 0.500000s system = 9.421875s CPU (104.5%)
+
+RUN-1004 : used memory is 1507 MB, reserved memory is 1494 MB, peak memory is 1523 MB
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.626525s wall, 0.125000s user + 0.125000s system = 0.250000s CPU (1.6%)
+
+RUN-1004 : used memory is 1509 MB, reserved memory is 1495 MB, peak memory is 1528 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.850565s wall, 0.250000s user + 0.125000s system = 0.375000s CPU (2.4%)
+
+RUN-1004 : used memory is 1509 MB, reserved memory is 1495 MB, peak memory is 1528 MB
+GUI-1001 : Downloading succeeded!
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.598279s wall, 0.234375s user + 0.109375s system = 0.343750s CPU (2.2%)
+
+RUN-1004 : used memory is 1510 MB, reserved memory is 1499 MB, peak memory is 1529 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.822440s wall, 0.328125s user + 0.125000s system = 0.453125s CPU (2.9%)
+
+RUN-1004 : used memory is 1510 MB, reserved memory is 1499 MB, peak memory is 1529 MB
+GUI-1001 : Downloading succeeded!
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-9525 ERROR: Chip validation failed! Please check the connection or type of chip!
+GUI-8702 ERROR: Downloading failed!
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.619596s wall, 0.296875s user + 0.359375s system = 0.656250s CPU (4.2%)
+
+RUN-1004 : used memory is 1510 MB, reserved memory is 1499 MB, peak memory is 1529 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.841780s wall, 0.406250s user + 0.359375s system = 0.765625s CPU (4.8%)
+
+RUN-1004 : used memory is 1510 MB, reserved memory is 1499 MB, peak memory is 1529 MB
+GUI-1001 : Downloading succeeded!
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.588534s wall, 0.203125s user + 0.203125s system = 0.406250s CPU (2.6%)
+
+RUN-1004 : used memory is 1509 MB, reserved memory is 1497 MB, peak memory is 1529 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.814699s wall, 0.312500s user + 0.234375s system = 0.546875s CPU (3.5%)
+
+RUN-1004 : used memory is 1509 MB, reserved memory is 1497 MB, peak memory is 1529 MB
+GUI-1001 : Downloading succeeded!
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.601488s wall, 0.234375s user + 0.359375s system = 0.593750s CPU (3.8%)
+
+RUN-1004 : used memory is 1509 MB, reserved memory is 1497 MB, peak memory is 1529 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.826398s wall, 0.343750s user + 0.375000s system = 0.718750s CPU (4.5%)
+
+RUN-1004 : used memory is 1509 MB, reserved memory is 1497 MB, peak memory is 1529 MB
+GUI-1001 : Downloading succeeded!
+TMR-3509 : Import timing summary.
+TMR-3509 : Import timing summary.
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-8007 ERROR: syntax error near '.' in ../../hg_mp/drx_top/huagao_mipi_top.v(709)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1697)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1698)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1699)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1700)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1701)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1703)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1704)
+HDL-8007 ERROR: ignore module module due to previous errors in ../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : Verilog file '../../hg_mp/drx_top/huagao_mipi_top.v' ignored due to errors
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1697)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1698)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1699)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1700)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1701)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1703)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1704)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1697)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1698)
+HDL-5007 Similar messages will be suppressed.
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1697)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1698)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1699)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1700)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1701)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1703)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1704)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1697)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1698)
+HDL-5007 Similar messages will be suppressed.
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1697)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1699)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1700)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1701)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1703)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1704)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1697)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1699)
+HDL-5007 WARNING: 'debug' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1700)
+HDL-5007 Similar messages will be suppressed.
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-5010 WARNING: Net S_hs_last is skipped due to 0 input or output
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 614 feed throughs used by 458 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 9.889173s wall, 9.921875s user + 0.390625s system = 10.312500s CPU (104.3%)
+
+RUN-1004 : used memory is 1526 MB, reserved memory is 1516 MB, peak memory is 1543 MB
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.605895s wall, 0.140625s user + 0.093750s system = 0.234375s CPU (1.5%)
+
+RUN-1004 : used memory is 1531 MB, reserved memory is 1517 MB, peak memory is 1550 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.841809s wall, 0.265625s user + 0.125000s system = 0.390625s CPU (2.5%)
+
+RUN-1004 : used memory is 1531 MB, reserved memory is 1517 MB, peak memory is 1550 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-6001 WARNING: Failed to reset phy_1: some files can't be removed in D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1
+RUN-6001 WARNING: Failed to reset syn_1: some files can't be removed in D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/syn_1
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 627 feed throughs used by 436 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 10.603130s wall, 10.500000s user + 0.437500s system = 10.937500s CPU (103.2%)
+
+RUN-1004 : used memory is 1534 MB, reserved memory is 1523 MB, peak memory is 1550 MB
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.625195s wall, 0.140625s user + 0.187500s system = 0.328125s CPU (2.1%)
+
+RUN-1004 : used memory is 1535 MB, reserved memory is 1524 MB, peak memory is 1554 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.848685s wall, 0.234375s user + 0.218750s system = 0.453125s CPU (2.9%)
+
+RUN-1004 : used memory is 1535 MB, reserved memory is 1524 MB, peak memory is 1554 MB
+GUI-1001 : Downloading succeeded!
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode program_spi -v -spd 7 -sec 64 -cable 0 -flashsize 128"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+PRG-1001 : SPI Flash ID is: ef
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m program_spi -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1003 : finish command "bit_to_vec -chip EAGLE_S20_EG176 -m program_spi -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit" in 1.977156s wall, 1.921875s user + 0.125000s system = 2.046875s CPU (103.5%)
+
+RUN-1004 : used memory is 1859 MB, reserved memory is 1860 MB, peak memory is 1870 MB
+RUN-1002 : start command "program_spi -cable 0 -spd 7"
+RUN-1003 : finish command "program_spi -cable 0 -spd 7" in 97.852221s wall, 4.359375s user + 1.203125s system = 5.562500s CPU (5.7%)
+
+RUN-1004 : used memory is 1860 MB, reserved memory is 1862 MB, peak memory is 1870 MB
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m verify_spi -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -spd 4"
+RUN-1003 : finish command "program -cable 0 -spd 4" in 23.479916s wall, 0.406250s user + 0.468750s system = 0.875000s CPU (3.7%)
+
+RUN-1004 : used memory is 1704 MB, reserved memory is 1696 MB, peak memory is 1870 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode program_spi -v -spd 7 -sec 64 -cable 0 -flashsize 128" in 127.662069s wall, 8.609375s user + 1.953125s system = 10.562500s CPU (8.3%)
+
+RUN-1004 : used memory is 1704 MB, reserved memory is 1696 MB, peak memory is 1870 MB
+GUI-1001 : Downloading succeeded!
+TMR-3509 : Import timing summary.
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(102)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/wrdpram_ctl.v
+HDL-1007 : undeclared symbol 'neg_dval_i', assumed default net type 'wire' in ../../hg_mp/fe/wrdpram_ctl.v(375)
+HDL-5007 WARNING: parameter 'DPI300_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(24)
+HDL-5007 WARNING: parameter 'DPI600_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(25)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 627 feed throughs used by 436 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 9.864875s wall, 9.921875s user + 0.453125s system = 10.375000s CPU (105.2%)
+
+RUN-1004 : used memory is 1704 MB, reserved memory is 1698 MB, peak memory is 1870 MB
+TMR-3509 : Import timing summary.
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/wrdpram_ctl.v
+HDL-1007 : undeclared symbol 'neg_dval_i', assumed default net type 'wire' in ../../hg_mp/fe/wrdpram_ctl.v(375)
+HDL-5007 WARNING: parameter 'DPI300_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(24)
+HDL-5007 WARNING: parameter 'DPI600_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(25)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.630392s wall, 0.234375s user + 0.218750s system = 0.453125s CPU (2.9%)
+
+RUN-1004 : used memory is 1723 MB, reserved memory is 1713 MB, peak memory is 1870 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.854840s wall, 0.343750s user + 0.218750s system = 0.562500s CPU (3.5%)
+
+RUN-1004 : used memory is 1723 MB, reserved memory is 1713 MB, peak memory is 1870 MB
+GUI-1001 : Downloading succeeded!
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 15.621738s wall, 0.359375s user + 0.468750s system = 0.828125s CPU (5.3%)
+
+RUN-1004 : used memory is 1719 MB, reserved memory is 1712 MB, peak memory is 1870 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 15.846315s wall, 0.453125s user + 0.515625s system = 0.968750s CPU (6.1%)
+
+RUN-1004 : used memory is 1719 MB, reserved memory is 1712 MB, peak memory is 1870 MB
+GUI-1001 : Downloading succeeded!
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 675 feed throughs used by 490 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 9.110726s wall, 9.078125s user + 0.468750s system = 9.546875s CPU (104.8%)
+
+RUN-1004 : used memory is 1733 MB, reserved memory is 1729 MB, peak memory is 1870 MB
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "get_ports clock_source"
diff --git a/src/prj/td_project/td_2024-02-02_10-29-15.log b/src/prj/td_project/td_2024-02-02_10-29-15.log
new file mode 100644
index 0000000..532a64c
--- /dev/null
+++ b/src/prj/td_project/td_2024-02-02_10-29-15.log
@@ -0,0 +1,101 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Fri Feb 2 10:29:15 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 675 feed throughs used by 490 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 11.838351s wall, 11.718750s user + 0.156250s system = 11.875000s CPU (100.3%)
+
+RUN-1004 : used memory is 972 MB, reserved memory is 933 MB, peak memory is 984 MB
+TMR-3509 : Import timing summary.
+TMR-3509 : Import timing summary.
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 716 feed throughs used by 509 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 11.062847s wall, 10.437500s user + 1.046875s system = 11.484375s CPU (103.8%)
+
+RUN-1004 : used memory is 956 MB, reserved memory is 980 MB, peak memory is 993 MB
+TMR-3509 : Import timing summary.
diff --git a/src/prj/td_project/td_2024-02-18_14-50-36.log b/src/prj/td_project/td_2024-02-18_14-50-36.log
new file mode 100644
index 0000000..7194e7a
--- /dev/null
+++ b/src/prj/td_project/td_2024-02-18_14-50-36.log
@@ -0,0 +1,31 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sun Feb 18 14:50:36 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+PRG-9500 ERROR: USB Error: read data failed
+
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
+PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
diff --git a/src/prj/td_project/td_2024-02-18_15-33-24.log b/src/prj/td_project/td_2024-02-18_15-33-24.log
new file mode 100644
index 0000000..e69de29
diff --git a/src/prj/td_project/td_20240122_164952.log b/src/prj/td_project/td_20240122_164952.log
index e69de29..3f0041c 100644
--- a/src/prj/td_project/td_20240122_164952.log
+++ b/src/prj/td_project/td_20240122_164952.log
@@ -0,0 +1,205 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Jan 22 16:49:52 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-001 : GUI based run...
+RUN-1002 : start command "open_project hg_anlogic.al -update"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/wrdpram_ctl.v
+HDL-1007 : undeclared symbol 'neg_dval_i', assumed default net type 'wire' in ../../hg_mp/fe/wrdpram_ctl.v(375)
+HDL-5007 WARNING: parameter 'DPI300_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(24)
+HDL-5007 WARNING: parameter 'DPI600_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(25)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(732)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(734)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(743)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1001)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1301)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1312)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1510)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1906)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(35)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(91)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(113)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(73)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(79)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(206)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(205)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 63 source files.
+RUN-1003 : finish command "open_project hg_anlogic.al -update" in 1.017002s wall, 0.468750s user + 0.390625s system = 0.859375s CPU (84.5%)
+
+RUN-1004 : used memory is 107 MB, reserved memory is 67 MB, peak memory is 107 MB
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
diff --git a/src/prj/td_project/td_20240124_150136.log b/src/prj/td_project/td_20240124_150136.log
new file mode 100644
index 0000000..228b151
--- /dev/null
+++ b/src/prj/td_project/td_20240124_150136.log
@@ -0,0 +1,11 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Wed Jan 24 15:01:36 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-001 : GUI based run...
diff --git a/src/prj/td_project/td_20240124_150143.log b/src/prj/td_project/td_20240124_150143.log
new file mode 100644
index 0000000..e40181b
--- /dev/null
+++ b/src/prj/td_project/td_20240124_150143.log
@@ -0,0 +1,12 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Wed Jan 24 15:01:43 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-001 : GUI based run...
+GUI-2000 : The IP files have been created successfully :{EG4D20EG176(D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/hg_mp/anlogic_ip/pll_lvds/pll_lvds.ipc)}
diff --git a/src/prj/td_project/td_20240218_145034.log b/src/prj/td_project/td_20240218_145034.log
new file mode 100644
index 0000000..fe097da
--- /dev/null
+++ b/src/prj/td_project/td_20240218_145034.log
@@ -0,0 +1,210 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sun Feb 18 14:50:34 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-001 : GUI based run...
+RUN-1002 : start command "open_project hg_anlogic.al -update"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(399)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/wrdpram_ctl.v
+HDL-1007 : undeclared symbol 'neg_dval_i', assumed default net type 'wire' in ../../hg_mp/fe/wrdpram_ctl.v(375)
+HDL-5007 WARNING: parameter 'DPI300_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(24)
+HDL-5007 WARNING: parameter 'DPI600_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(25)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(211)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(42)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(57)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(122)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(213)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(139)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 63 source files.
+RUN-1003 : finish command "open_project hg_anlogic.al -update" in 1.567662s wall, 0.328125s user + 0.265625s system = 0.593750s CPU (37.9%)
+
+RUN-1004 : used memory is 109 MB, reserved memory is 68 MB, peak memory is 109 MB
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
diff --git a/src/prj/td_project/td_20240218_153322.log b/src/prj/td_project/td_20240218_153322.log
new file mode 100644
index 0000000..e69de29