保存备份初始版
This commit is contained in:
17828169534
parent
146453b2fe
commit
c1965ff843
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#
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# Preferences
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#
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preferences set toolbar-SimControl-WatchList {
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usual
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position -anchor e
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}
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preferences set toolbar-SimControl-SrcBrowser {
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usual
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show step_out
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}
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preferences set plugin-enable-svdatabrowser-new 1
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preferences set cursorctl-dont-show-sync-warning 1
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preferences set user-toolbar-list {WatchList {}}
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preferences set toolbar-Standard-Console {
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usual
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position -pos 1
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}
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preferences set toolbar-Search-Console {
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usual
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position -pos 2
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}
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preferences set toolbar-Standard-WaveWindow {
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usual
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position -pos 4
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}
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preferences set plugin-enable-groupscope 0
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preferences set standard-methodology-filtering 1
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preferences set plugin-enable-interleaveandcompare 0
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preferences set plugin-enable-waveformfrequencyplot 0
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preferences set toolbar-Windows-WatchList {
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usual
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position -pos 2
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}
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preferences set savedlg-simulator ppe
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preferences set whats-new-dont-show-at-startup 1
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#
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# Mnemonic Maps
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#
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mmap new -reuse -name {Boolean as Logic} -radix %b -contents {{%c=FALSE -edgepriority 1 -shape low}
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{%c=TRUE -edgepriority 1 -shape high}}
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mmap new -reuse -name {Example Map} -radix %x -contents {{%b=11???? -bgcolor orange -label REG:%x -linecolor yellow -shape bus}
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{%x=1F -bgcolor red -label ERROR -linecolor white -shape EVENT}
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{%x=2C -bgcolor red -label ERROR -linecolor white -shape EVENT}
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{%x=* -label %x -linecolor gray -shape bus}}
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#
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# Waveform windows
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#
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if {[catch {window new WaveWindow -name "Waveform 1" -geometry 2293x828+0+31}] != ""} {
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window geometry "Waveform 1" 2293x828+0+31
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}
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window target "Waveform 1" on
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waveform using {Waveform 1}
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waveform sidebar select designbrowser
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waveform set \
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-primarycursor TimeA \
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-signalnames name \
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-signalwidth 175 \
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-units ns \
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-valuewidth 75
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waveform baseline set -time 0
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waveform xview limits 0 1000000000ns
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#
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# Waveform Window Links
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#
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#
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# Console windows
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#
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console set -windowname Console
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window geometry Console 600x250+0+0
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#
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# Layout selection
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#
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@ -1695,10 +1695,10 @@ always @(*) begin
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end
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assign debug[0] = a_vs ;
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assign debug[1] = debug_6 ;
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assign debug[2] = S_hs_valid ;
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assign debug[3] = O_clk_lp_n;
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assign debug[4] = O_clk_lp_p ;
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assign debug[1] = a_ad_sck;
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assign debug[2] = a_ad_sen ;
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assign debug[3] = a_ad_sdi;
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assign debug[4] = a_ad_sdo ;
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assign debug[5] = FV_MIPI ;
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assign debug[6] = sync_eot ;
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assign debug[7] = LV_MIPI;
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@ -215,7 +215,7 @@ local_bus_slve_cis u_local_bus_slve_cis(
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//,.nd2reg_0 ( scan_status_sync3d_8m ) //input [31:0]
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,.nd2reg_0 ( adc_cfg_data_o_sync3d_8m) //input [31:0]
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,.nd2reg_1 ( 32'h000a0001 ) //input [31:0]
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,.nd2reg_1 ( 32'h000a0002 ) //input [31:0]
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,.nd2reg_2 ( lv_cnt2bus_sync3d ) //input [31:0]
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,.nd2reg_3 ( fr_cnt2bus_sync3d ) //input [31:0]
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,.nd2reg_4 ( lv_cnt_a_sync3d ) //input [31:0]
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@ -13,28 +13,28 @@ set_pin_assignment { O_data_lp_p[0] } { LOCATION = P63; IOSTANDARD = LVCMOS25; D
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set_pin_assignment { O_data_lp_p[1] } { LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; }
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set_pin_assignment { O_data_lp_p[2] } { LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; }
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set_pin_assignment { O_data_lp_p[3] } { LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; }
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set_pin_assignment { a_ad_sck } { LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
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set_pin_assignment { a_ad_sdi } { LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
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set_pin_assignment { a_ad_sdo } { LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
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set_pin_assignment { a_ad_sen } { LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
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set_pin_assignment { a_lvds_clk_p } { LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { a_lvds_data_p[0] } { LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { a_lvds_data_p[1] } { LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { a_lvds_data_p[2] } { LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { a_lvds_data_p[3] } { LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { a_lvds_data_p[4] } { LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { a_sp_pad } { LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
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set_pin_assignment { b_ad_sck } { LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
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set_pin_assignment { b_ad_sdi } { LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
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set_pin_assignment { b_ad_sdo } { LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
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set_pin_assignment { b_ad_sen } { LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
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set_pin_assignment { b_lvds_clk_p } { LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { b_lvds_data_p[0] } { LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { b_lvds_data_p[1] } { LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { b_lvds_data_p[2] } { LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { b_lvds_data_p[3] } { LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { b_lvds_data_p[4] } { LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { b_sp_pad } { LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
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set_pin_assignment { b_ad_sck } { LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
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set_pin_assignment { b_ad_sdi } { LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
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set_pin_assignment { b_ad_sdo } { LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
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set_pin_assignment { b_ad_sen } { LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
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set_pin_assignment { b_lvds_clk_p } { LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { b_lvds_data_p[0] } { LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { b_lvds_data_p[1] } { LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { b_lvds_data_p[2] } { LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { b_lvds_data_p[3] } { LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { b_lvds_data_p[4] } { LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { b_sp_pad } { LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
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set_pin_assignment { a_ad_sck } { LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
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set_pin_assignment { a_ad_sdi } { LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
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set_pin_assignment { a_ad_sdo } { LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
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set_pin_assignment { a_ad_sen } { LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
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set_pin_assignment { a_lvds_clk_p } { LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { a_lvds_data_p[0] } { LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { a_lvds_data_p[1] } { LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { a_lvds_data_p[2] } { LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { a_lvds_data_p[3] } { LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { a_lvds_data_p[4] } { LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
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set_pin_assignment { a_sp_pad } { LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
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set_pin_assignment { clock_source } { LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
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set_pin_assignment { debug[0] } { LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
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set_pin_assignment { debug[1] } { LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
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File diff suppressed because it is too large
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@ -0,0 +1,444 @@
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============================================================
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Tang Dynasty, V5.6.71036
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Copyright (c) 2012-2023 Anlogic Inc.
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Executable = D:/Anlogic/TD5.6.2/bin/td.exe
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Built at = 20:34:38 Mar 21 2023
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Run by = holdtecs
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Run Date = Tue Jan 23 17:26:03 2024
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Run on = DESKTOP-5MQL5VE
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============================================================
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RUN-1002 : start command "open_project hg_anlogic.prj"
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RUN-1001 : Print Global Property
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RUN-1001 : ---------------------------------------------------------------
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RUN-1001 : Parameters | Settings | Default Values | Note
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RUN-1001 : ---------------------------------------------------------------
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RUN-1001 : message | standard | standard |
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RUN-1001 : mixed_pack_place_flow | on | on |
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RUN-1001 : qor_monitor | off | off |
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RUN-1001 : syn_ip_flow | off | off |
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RUN-1001 : thread | auto | auto |
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RUN-1001 : ---------------------------------------------------------------
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RUN-1001 : Print Design Property
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RUN-1001 : --------------------------------------------------------------
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RUN-1001 : Parameters | Settings | Default Values | Note
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RUN-1001 : --------------------------------------------------------------
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RUN-1001 : default_reg_initial | auto | auto |
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RUN-1001 : infer_add | on | on |
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RUN-1001 : infer_fsm | off | off |
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RUN-1001 : infer_mult | on | on |
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RUN-1001 : infer_ram | on | on |
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RUN-1001 : infer_reg | on | on |
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RUN-1001 : infer_reg_init_value | on | on |
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RUN-1001 : infer_rom | on | on |
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RUN-1001 : infer_shifter | on | on |
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RUN-1001 : --------------------------------------------------------------
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RUN-1001 : Print Rtl Property
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RUN-1001 : --------------------------------------------------------------
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RUN-1001 : Parameters | Settings | Default Values | Note
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RUN-1001 : --------------------------------------------------------------
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RUN-1001 : compress_add | ripple | ripple |
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RUN-1001 : elf_sload | off | off |
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RUN-1001 : fix_undriven | 0 | 0 |
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RUN-1001 : flatten | off | off |
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RUN-1001 : gate_sharing | on | on |
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RUN-1001 : hdl_warning_level | normal | normal |
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RUN-1001 : impl_internal_tribuf | on | on |
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RUN-1001 : impl_set_reset | on | on |
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RUN-1001 : infer_gsr | off | off |
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RUN-1001 : keep_hierarchy | auto | auto |
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RUN-1001 : max_fanout | 9999 | 9999 |
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RUN-1001 : max_oh2bin_len | 10 | 10 |
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RUN-1001 : merge_equal | on | on |
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RUN-1001 : merge_equiv | on | on |
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RUN-1001 : merge_mux | off | off |
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RUN-1001 : min_control_set | 8 | 8 |
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RUN-1001 : min_ripple_len | auto | auto |
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RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
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RUN-1001 : opt_adder_fanout | on | on |
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RUN-1001 : opt_arith | on | on |
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RUN-1001 : opt_big_gate | off | off |
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RUN-1001 : opt_const | on | on |
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RUN-1001 : opt_const_mult | on | on |
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RUN-1001 : opt_lessthan | on | on |
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RUN-1001 : opt_mux | off | off |
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RUN-1001 : opt_ram | high | high |
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RUN-1001 : rtl_sim_model | off | off |
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RUN-1001 : seq_syn | on | on |
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RUN-1001 : --------------------------------------------------------------
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HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
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HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
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HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
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HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
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HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
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HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
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HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
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HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
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HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
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HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
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HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
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HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
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HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
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HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
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HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
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HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
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HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
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HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
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HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
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HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
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HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
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HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
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HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
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HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
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HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
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HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
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HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
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HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
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HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
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HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
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HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
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HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
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HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
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HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
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HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
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HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
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HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
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HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
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HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
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HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
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HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
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HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
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HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
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HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
|
||||
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1698)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1699)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1700)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1701)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1703)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1704)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
|
||||
Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
|
||||
This product includes software developed by the OpenSSL Project
|
||||
for use in the OpenSSL Toolkit (http://www.openssl.org/)
|
||||
Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
|
||||
All rights reserved.
|
||||
This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
|
||||
HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
|
||||
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
|
||||
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
|
||||
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
|
||||
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
|
||||
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
|
||||
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1698)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1699)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1700)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1701)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1703)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1704)
|
||||
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
|
||||
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
|
||||
RUN-1001 : Project manager successfully analyzed 61 source files.
|
||||
RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
|
||||
ARC-1001 : done | P10 | gpio
|
||||
ARC-1001 : program_b | P134 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "elaborate -top huagao_mipi_top"
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : default_reg_initial | auto | auto |
|
||||
RUN-1001 : infer_add | on | on |
|
||||
RUN-1001 : infer_fsm | off | off |
|
||||
RUN-1001 : infer_mult | on | on |
|
||||
RUN-1001 : infer_ram | on | on |
|
||||
RUN-1001 : infer_reg | on | on |
|
||||
RUN-1001 : infer_reg_init_value | on | on |
|
||||
RUN-1001 : infer_rom | on | on |
|
||||
RUN-1001 : infer_shifter | on | on |
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple |
|
||||
RUN-1001 : elf_sload | off | off |
|
||||
RUN-1001 : fix_undriven | 0 | 0 |
|
||||
RUN-1001 : flatten | off | off |
|
||||
RUN-1001 : gate_sharing | on | on |
|
||||
RUN-1001 : hdl_warning_level | normal | normal |
|
||||
RUN-1001 : impl_internal_tribuf | on | on |
|
||||
RUN-1001 : impl_set_reset | on | on |
|
||||
RUN-1001 : infer_gsr | off | off |
|
||||
RUN-1001 : keep_hierarchy | auto | auto |
|
||||
RUN-1001 : max_fanout | 9999 | 9999 |
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10 |
|
||||
RUN-1001 : merge_equal | on | on |
|
||||
RUN-1001 : merge_equiv | on | on |
|
||||
RUN-1001 : merge_mux | off | off |
|
||||
RUN-1001 : min_control_set | 8 | 8 |
|
||||
RUN-1001 : min_ripple_len | auto | auto |
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
|
||||
RUN-1001 : opt_adder_fanout | on | on |
|
||||
RUN-1001 : opt_arith | on | on |
|
||||
RUN-1001 : opt_big_gate | off | off |
|
||||
RUN-1001 : opt_const | on | on |
|
||||
RUN-1001 : opt_const_mult | on | on |
|
||||
RUN-1001 : opt_lessthan | on | on |
|
||||
RUN-1001 : opt_mux | off | off |
|
||||
RUN-1001 : opt_ram | high | high |
|
||||
RUN-1001 : rtl_sim_model | off | off |
|
||||
RUN-1001 : seq_syn | on | on |
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Print Global Property
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : message | standard | standard |
|
||||
RUN-1001 : mixed_pack_place_flow | on | on |
|
||||
RUN-1001 : qor_monitor | off | off |
|
||||
RUN-1001 : syn_ip_flow | off | off |
|
||||
RUN-1001 : thread | auto | auto |
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : default_reg_initial | auto | auto |
|
||||
RUN-1001 : infer_add | on | on |
|
||||
RUN-1001 : infer_fsm | off | off |
|
||||
RUN-1001 : infer_mult | on | on |
|
||||
RUN-1001 : infer_ram | on | on |
|
||||
RUN-1001 : infer_reg | on | on |
|
||||
RUN-1001 : infer_reg_init_value | on | on |
|
||||
RUN-1001 : infer_rom | on | on |
|
||||
RUN-1001 : infer_shifter | on | on |
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
|
||||
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
|
||||
HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(677)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
|
||||
HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1009)
|
||||
HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1698)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1699)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1700)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1701)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1703)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1704)
|
||||
HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
|
||||
HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
|
||||
HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
|
||||
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
|
||||
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
|
||||
HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
|
||||
HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
|
||||
HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
|
||||
HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
|
||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||
HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
|
||||
HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
|
||||
HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
|
||||
HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
|
||||
HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
|
||||
HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
|
||||
HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
|
||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
|
||||
HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
|
||||
HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
|
||||
HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
|
||||
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
|
||||
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
|
||||
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
|
||||
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
|
||||
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
|
||||
HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
|
||||
HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(192)
|
||||
HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
|
||||
HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
|
||||
HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
|
||||
HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
|
||||
HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
|
||||
HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
|
||||
HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
|
||||
HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
|
||||
HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
|
||||
HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
|
||||
HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
|
||||
HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
|
||||
HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
|
||||
HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
|
||||
HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
|
||||
HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
|
||||
HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
|
||||
HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(36)
|
||||
HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
|
||||
HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
|
||||
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(335)
|
||||
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
|
||||
HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
|
||||
HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
|
||||
HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
|
||||
HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
|
||||
HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
|
||||
HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
|
||||
HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
|
||||
HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
|
||||
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
|
||||
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
|
||||
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
|
||||
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
|
||||
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
|
||||
HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(194)
|
||||
HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
|
||||
HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
|
||||
HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
|
||||
HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
|
||||
HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(38)
|
||||
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(367)
|
||||
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
|
||||
HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
|
||||
HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
|
||||
HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
|
||||
HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
|
||||
HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
|
||||
HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
|
||||
HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
|
||||
HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
|
||||
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
|
||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||
HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
|
||||
HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
|
||||
HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
|
||||
HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
|
||||
HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
|
||||
HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
|
||||
HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
|
||||
HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
|
||||
HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
|
||||
HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
|
||||
HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
|
||||
HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
|
||||
HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
|
||||
HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
|
||||
HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
|
||||
HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
|
||||
HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
|
||||
HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
|
||||
HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
|
||||
HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
|
||||
HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
|
||||
HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
|
||||
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
|
||||
HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
|
||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
|
||||
HDL-8007 ERROR: external reference 'debug' remains unresolved in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
|
||||
HDL-1007 : module 'huagao_mipi_top' remains a black box due to errors in its contents in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
|
||||
RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240123_172602.log"
|
||||
|
|
@ -0,0 +1,444 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.6.71036
|
||||
Copyright (c) 2012-2023 Anlogic Inc.
|
||||
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
|
||||
Built at = 20:34:38 Mar 21 2023
|
||||
Run by = holdtecs
|
||||
Run Date = Tue Jan 23 17:26:49 2024
|
||||
|
||||
Run on = DESKTOP-5MQL5VE
|
||||
============================================================
|
||||
RUN-1002 : start command "open_project hg_anlogic.prj"
|
||||
RUN-1001 : Print Global Property
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : message | standard | standard |
|
||||
RUN-1001 : mixed_pack_place_flow | on | on |
|
||||
RUN-1001 : qor_monitor | off | off |
|
||||
RUN-1001 : syn_ip_flow | off | off |
|
||||
RUN-1001 : thread | auto | auto |
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : default_reg_initial | auto | auto |
|
||||
RUN-1001 : infer_add | on | on |
|
||||
RUN-1001 : infer_fsm | off | off |
|
||||
RUN-1001 : infer_mult | on | on |
|
||||
RUN-1001 : infer_ram | on | on |
|
||||
RUN-1001 : infer_reg | on | on |
|
||||
RUN-1001 : infer_reg_init_value | on | on |
|
||||
RUN-1001 : infer_rom | on | on |
|
||||
RUN-1001 : infer_shifter | on | on |
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple |
|
||||
RUN-1001 : elf_sload | off | off |
|
||||
RUN-1001 : fix_undriven | 0 | 0 |
|
||||
RUN-1001 : flatten | off | off |
|
||||
RUN-1001 : gate_sharing | on | on |
|
||||
RUN-1001 : hdl_warning_level | normal | normal |
|
||||
RUN-1001 : impl_internal_tribuf | on | on |
|
||||
RUN-1001 : impl_set_reset | on | on |
|
||||
RUN-1001 : infer_gsr | off | off |
|
||||
RUN-1001 : keep_hierarchy | auto | auto |
|
||||
RUN-1001 : max_fanout | 9999 | 9999 |
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10 |
|
||||
RUN-1001 : merge_equal | on | on |
|
||||
RUN-1001 : merge_equiv | on | on |
|
||||
RUN-1001 : merge_mux | off | off |
|
||||
RUN-1001 : min_control_set | 8 | 8 |
|
||||
RUN-1001 : min_ripple_len | auto | auto |
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
|
||||
RUN-1001 : opt_adder_fanout | on | on |
|
||||
RUN-1001 : opt_arith | on | on |
|
||||
RUN-1001 : opt_big_gate | off | off |
|
||||
RUN-1001 : opt_const | on | on |
|
||||
RUN-1001 : opt_const_mult | on | on |
|
||||
RUN-1001 : opt_lessthan | on | on |
|
||||
RUN-1001 : opt_mux | off | off |
|
||||
RUN-1001 : opt_ram | high | high |
|
||||
RUN-1001 : rtl_sim_model | off | off |
|
||||
RUN-1001 : seq_syn | on | on |
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
|
||||
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
|
||||
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
|
||||
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
|
||||
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
|
||||
HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
|
||||
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
|
||||
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
|
||||
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
|
||||
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
|
||||
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
|
||||
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
|
||||
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
|
||||
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
|
||||
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
|
||||
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
|
||||
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
|
||||
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
|
||||
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
|
||||
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
|
||||
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
|
||||
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
|
||||
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1698)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1699)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1700)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1701)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1703)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1704)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
|
||||
Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
|
||||
This product includes software developed by the OpenSSL Project
|
||||
for use in the OpenSSL Toolkit (http://www.openssl.org/)
|
||||
Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
|
||||
All rights reserved.
|
||||
This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
|
||||
HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
|
||||
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
|
||||
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
|
||||
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
|
||||
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
|
||||
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
|
||||
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1698)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1699)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1700)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1701)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1703)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1704)
|
||||
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
|
||||
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
|
||||
RUN-1001 : Project manager successfully analyzed 61 source files.
|
||||
RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
|
||||
ARC-1001 : done | P10 | gpio
|
||||
ARC-1001 : program_b | P134 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "elaborate -top huagao_mipi_top"
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : default_reg_initial | auto | auto |
|
||||
RUN-1001 : infer_add | on | on |
|
||||
RUN-1001 : infer_fsm | off | off |
|
||||
RUN-1001 : infer_mult | on | on |
|
||||
RUN-1001 : infer_ram | on | on |
|
||||
RUN-1001 : infer_reg | on | on |
|
||||
RUN-1001 : infer_reg_init_value | on | on |
|
||||
RUN-1001 : infer_rom | on | on |
|
||||
RUN-1001 : infer_shifter | on | on |
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple |
|
||||
RUN-1001 : elf_sload | off | off |
|
||||
RUN-1001 : fix_undriven | 0 | 0 |
|
||||
RUN-1001 : flatten | off | off |
|
||||
RUN-1001 : gate_sharing | on | on |
|
||||
RUN-1001 : hdl_warning_level | normal | normal |
|
||||
RUN-1001 : impl_internal_tribuf | on | on |
|
||||
RUN-1001 : impl_set_reset | on | on |
|
||||
RUN-1001 : infer_gsr | off | off |
|
||||
RUN-1001 : keep_hierarchy | auto | auto |
|
||||
RUN-1001 : max_fanout | 9999 | 9999 |
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10 |
|
||||
RUN-1001 : merge_equal | on | on |
|
||||
RUN-1001 : merge_equiv | on | on |
|
||||
RUN-1001 : merge_mux | off | off |
|
||||
RUN-1001 : min_control_set | 8 | 8 |
|
||||
RUN-1001 : min_ripple_len | auto | auto |
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
|
||||
RUN-1001 : opt_adder_fanout | on | on |
|
||||
RUN-1001 : opt_arith | on | on |
|
||||
RUN-1001 : opt_big_gate | off | off |
|
||||
RUN-1001 : opt_const | on | on |
|
||||
RUN-1001 : opt_const_mult | on | on |
|
||||
RUN-1001 : opt_lessthan | on | on |
|
||||
RUN-1001 : opt_mux | off | off |
|
||||
RUN-1001 : opt_ram | high | high |
|
||||
RUN-1001 : rtl_sim_model | off | off |
|
||||
RUN-1001 : seq_syn | on | on |
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Print Global Property
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : message | standard | standard |
|
||||
RUN-1001 : mixed_pack_place_flow | on | on |
|
||||
RUN-1001 : qor_monitor | off | off |
|
||||
RUN-1001 : syn_ip_flow | off | off |
|
||||
RUN-1001 : thread | auto | auto |
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : default_reg_initial | auto | auto |
|
||||
RUN-1001 : infer_add | on | on |
|
||||
RUN-1001 : infer_fsm | off | off |
|
||||
RUN-1001 : infer_mult | on | on |
|
||||
RUN-1001 : infer_ram | on | on |
|
||||
RUN-1001 : infer_reg | on | on |
|
||||
RUN-1001 : infer_reg_init_value | on | on |
|
||||
RUN-1001 : infer_rom | on | on |
|
||||
RUN-1001 : infer_shifter | on | on |
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
|
||||
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
|
||||
HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(677)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
|
||||
HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1009)
|
||||
HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1698)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1699)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1700)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1701)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1703)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1704)
|
||||
HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
|
||||
HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
|
||||
HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
|
||||
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
|
||||
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
|
||||
HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
|
||||
HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
|
||||
HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
|
||||
HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
|
||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||
HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
|
||||
HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
|
||||
HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
|
||||
HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
|
||||
HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
|
||||
HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
|
||||
HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
|
||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
|
||||
HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
|
||||
HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
|
||||
HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
|
||||
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
|
||||
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
|
||||
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
|
||||
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
|
||||
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
|
||||
HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
|
||||
HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(192)
|
||||
HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
|
||||
HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
|
||||
HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
|
||||
HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
|
||||
HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
|
||||
HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
|
||||
HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
|
||||
HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
|
||||
HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
|
||||
HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
|
||||
HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
|
||||
HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
|
||||
HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
|
||||
HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
|
||||
HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
|
||||
HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
|
||||
HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
|
||||
HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(36)
|
||||
HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
|
||||
HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
|
||||
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(335)
|
||||
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
|
||||
HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
|
||||
HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
|
||||
HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
|
||||
HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
|
||||
HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
|
||||
HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
|
||||
HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
|
||||
HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
|
||||
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
|
||||
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
|
||||
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
|
||||
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
|
||||
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
|
||||
HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(194)
|
||||
HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
|
||||
HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
|
||||
HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
|
||||
HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
|
||||
HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(38)
|
||||
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(367)
|
||||
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
|
||||
HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
|
||||
HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
|
||||
HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
|
||||
HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
|
||||
HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
|
||||
HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
|
||||
HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
|
||||
HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
|
||||
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
|
||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||
HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
|
||||
HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
|
||||
HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
|
||||
HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
|
||||
HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
|
||||
HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
|
||||
HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
|
||||
HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
|
||||
HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
|
||||
HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
|
||||
HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
|
||||
HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
|
||||
HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
|
||||
HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
|
||||
HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
|
||||
HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
|
||||
HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
|
||||
HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
|
||||
HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
|
||||
HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
|
||||
HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
|
||||
HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
|
||||
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
|
||||
HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
|
||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
|
||||
HDL-8007 ERROR: external reference 'debug' remains unresolved in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
|
||||
HDL-1007 : module 'huagao_mipi_top' remains a black box due to errors in its contents in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
|
||||
RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240123_172649.log"
|
||||
|
|
@ -0,0 +1,441 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.6.71036
|
||||
Copyright (c) 2012-2023 Anlogic Inc.
|
||||
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
|
||||
Built at = 20:34:38 Mar 21 2023
|
||||
Run by = holdtecs
|
||||
Run Date = Tue Jan 23 17:28:01 2024
|
||||
|
||||
Run on = DESKTOP-5MQL5VE
|
||||
============================================================
|
||||
RUN-1002 : start command "open_project hg_anlogic.prj"
|
||||
RUN-1001 : Print Global Property
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : message | standard | standard |
|
||||
RUN-1001 : mixed_pack_place_flow | on | on |
|
||||
RUN-1001 : qor_monitor | off | off |
|
||||
RUN-1001 : syn_ip_flow | off | off |
|
||||
RUN-1001 : thread | auto | auto |
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : default_reg_initial | auto | auto |
|
||||
RUN-1001 : infer_add | on | on |
|
||||
RUN-1001 : infer_fsm | off | off |
|
||||
RUN-1001 : infer_mult | on | on |
|
||||
RUN-1001 : infer_ram | on | on |
|
||||
RUN-1001 : infer_reg | on | on |
|
||||
RUN-1001 : infer_reg_init_value | on | on |
|
||||
RUN-1001 : infer_rom | on | on |
|
||||
RUN-1001 : infer_shifter | on | on |
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple |
|
||||
RUN-1001 : elf_sload | off | off |
|
||||
RUN-1001 : fix_undriven | 0 | 0 |
|
||||
RUN-1001 : flatten | off | off |
|
||||
RUN-1001 : gate_sharing | on | on |
|
||||
RUN-1001 : hdl_warning_level | normal | normal |
|
||||
RUN-1001 : impl_internal_tribuf | on | on |
|
||||
RUN-1001 : impl_set_reset | on | on |
|
||||
RUN-1001 : infer_gsr | off | off |
|
||||
RUN-1001 : keep_hierarchy | auto | auto |
|
||||
RUN-1001 : max_fanout | 9999 | 9999 |
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10 |
|
||||
RUN-1001 : merge_equal | on | on |
|
||||
RUN-1001 : merge_equiv | on | on |
|
||||
RUN-1001 : merge_mux | off | off |
|
||||
RUN-1001 : min_control_set | 8 | 8 |
|
||||
RUN-1001 : min_ripple_len | auto | auto |
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
|
||||
RUN-1001 : opt_adder_fanout | on | on |
|
||||
RUN-1001 : opt_arith | on | on |
|
||||
RUN-1001 : opt_big_gate | off | off |
|
||||
RUN-1001 : opt_const | on | on |
|
||||
RUN-1001 : opt_const_mult | on | on |
|
||||
RUN-1001 : opt_lessthan | on | on |
|
||||
RUN-1001 : opt_mux | off | off |
|
||||
RUN-1001 : opt_ram | high | high |
|
||||
RUN-1001 : rtl_sim_model | off | off |
|
||||
RUN-1001 : seq_syn | on | on |
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
|
||||
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
|
||||
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
|
||||
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
|
||||
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
|
||||
HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(399)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
|
||||
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
|
||||
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
|
||||
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
|
||||
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
|
||||
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
|
||||
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
|
||||
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
|
||||
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
|
||||
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
|
||||
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
|
||||
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
|
||||
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
|
||||
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
|
||||
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
|
||||
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
|
||||
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
|
||||
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1699)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1700)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1701)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1703)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1704)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
|
||||
Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
|
||||
This product includes software developed by the OpenSSL Project
|
||||
for use in the OpenSSL Toolkit (http://www.openssl.org/)
|
||||
Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
|
||||
All rights reserved.
|
||||
This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
|
||||
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
|
||||
HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
|
||||
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(211)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
|
||||
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(42)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(42)
|
||||
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(57)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(57)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(122)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
|
||||
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(213)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
|
||||
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(44)
|
||||
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(59)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(139)
|
||||
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1699)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1700)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1701)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1703)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1704)
|
||||
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
|
||||
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
|
||||
RUN-1001 : Project manager successfully analyzed 61 source files.
|
||||
RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
|
||||
ARC-1001 : done | P10 | gpio
|
||||
ARC-1001 : program_b | P134 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "elaborate -top huagao_mipi_top"
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : default_reg_initial | auto | auto |
|
||||
RUN-1001 : infer_add | on | on |
|
||||
RUN-1001 : infer_fsm | off | off |
|
||||
RUN-1001 : infer_mult | on | on |
|
||||
RUN-1001 : infer_ram | on | on |
|
||||
RUN-1001 : infer_reg | on | on |
|
||||
RUN-1001 : infer_reg_init_value | on | on |
|
||||
RUN-1001 : infer_rom | on | on |
|
||||
RUN-1001 : infer_shifter | on | on |
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple |
|
||||
RUN-1001 : elf_sload | off | off |
|
||||
RUN-1001 : fix_undriven | 0 | 0 |
|
||||
RUN-1001 : flatten | off | off |
|
||||
RUN-1001 : gate_sharing | on | on |
|
||||
RUN-1001 : hdl_warning_level | normal | normal |
|
||||
RUN-1001 : impl_internal_tribuf | on | on |
|
||||
RUN-1001 : impl_set_reset | on | on |
|
||||
RUN-1001 : infer_gsr | off | off |
|
||||
RUN-1001 : keep_hierarchy | auto | auto |
|
||||
RUN-1001 : max_fanout | 9999 | 9999 |
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10 |
|
||||
RUN-1001 : merge_equal | on | on |
|
||||
RUN-1001 : merge_equiv | on | on |
|
||||
RUN-1001 : merge_mux | off | off |
|
||||
RUN-1001 : min_control_set | 8 | 8 |
|
||||
RUN-1001 : min_ripple_len | auto | auto |
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
|
||||
RUN-1001 : opt_adder_fanout | on | on |
|
||||
RUN-1001 : opt_arith | on | on |
|
||||
RUN-1001 : opt_big_gate | off | off |
|
||||
RUN-1001 : opt_const | on | on |
|
||||
RUN-1001 : opt_const_mult | on | on |
|
||||
RUN-1001 : opt_lessthan | on | on |
|
||||
RUN-1001 : opt_mux | off | off |
|
||||
RUN-1001 : opt_ram | high | high |
|
||||
RUN-1001 : rtl_sim_model | off | off |
|
||||
RUN-1001 : seq_syn | on | on |
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Print Global Property
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : message | standard | standard |
|
||||
RUN-1001 : mixed_pack_place_flow | on | on |
|
||||
RUN-1001 : qor_monitor | off | off |
|
||||
RUN-1001 : syn_ip_flow | off | off |
|
||||
RUN-1001 : thread | auto | auto |
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : default_reg_initial | auto | auto |
|
||||
RUN-1001 : infer_add | on | on |
|
||||
RUN-1001 : infer_fsm | off | off |
|
||||
RUN-1001 : infer_mult | on | on |
|
||||
RUN-1001 : infer_ram | on | on |
|
||||
RUN-1001 : infer_reg | on | on |
|
||||
RUN-1001 : infer_reg_init_value | on | on |
|
||||
RUN-1001 : infer_rom | on | on |
|
||||
RUN-1001 : infer_shifter | on | on |
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
|
||||
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
|
||||
HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(677)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
|
||||
HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1009)
|
||||
HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1699)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1700)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1701)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1703)
|
||||
HDL-5007 WARNING: 'debug' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1704)
|
||||
HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
|
||||
HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
|
||||
HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
|
||||
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
|
||||
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
|
||||
HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
|
||||
HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
|
||||
HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
|
||||
HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
|
||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||
HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
|
||||
HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
|
||||
HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
|
||||
HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
|
||||
HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
|
||||
HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
|
||||
HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
|
||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
|
||||
HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
|
||||
HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
|
||||
HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
|
||||
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
|
||||
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
|
||||
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
|
||||
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
|
||||
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
|
||||
HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(343)
|
||||
HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(192)
|
||||
HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
|
||||
HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
|
||||
HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
|
||||
HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
|
||||
HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
|
||||
HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
|
||||
HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
|
||||
HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
|
||||
HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
|
||||
HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
|
||||
HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
|
||||
HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
|
||||
HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
|
||||
HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
|
||||
HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
|
||||
HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
|
||||
HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
|
||||
HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
|
||||
HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(36)
|
||||
HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
|
||||
HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
|
||||
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(335)
|
||||
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
|
||||
HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
|
||||
HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
|
||||
HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
|
||||
HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
|
||||
HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
|
||||
HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
|
||||
HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
|
||||
HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
|
||||
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
|
||||
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
|
||||
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
|
||||
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
|
||||
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(377)
|
||||
HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
|
||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(194)
|
||||
HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
|
||||
HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
|
||||
HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
|
||||
HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
|
||||
HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(38)
|
||||
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(367)
|
||||
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
|
||||
HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
|
||||
HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
|
||||
HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
|
||||
HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
|
||||
HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
|
||||
HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
|
||||
HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
|
||||
HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
|
||||
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
|
||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||
HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
|
||||
HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
|
||||
HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
|
||||
HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
|
||||
HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
|
||||
HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
|
||||
HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
|
||||
HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
|
||||
HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
|
||||
HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
|
||||
HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
|
||||
HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
|
||||
HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
|
||||
HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
|
||||
HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
|
||||
HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
|
||||
HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
|
||||
HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
|
||||
HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
|
||||
HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
|
||||
HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
|
||||
HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
|
||||
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
|
||||
HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
|
||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
|
||||
HDL-8007 ERROR: external reference 'debug' remains unresolved in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1697)
|
||||
HDL-1007 : module 'huagao_mipi_top' remains a black box due to errors in its contents in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
|
||||
RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240123_172801.log"
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,5 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="14284">
|
||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="20868">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="14284">
|
||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="20868">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="14284">
|
||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="20868">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
|
|
@ -1,5 +1,5 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Project Version="3" Minor="2" RunTime="2024-01-23T14:15:59.140046">
|
||||
<Project Version="3" Minor="2" RunTime="2024-02-18T16:10:55.365260">
|
||||
<Project_Created_Time></Project_Created_Time>
|
||||
<TD_Encoding>UTF-8</TD_Encoding>
|
||||
<TD_Version>5.6.71036</TD_Version>
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
|
|
@ -8,12 +8,12 @@ IO Statistics
|
|||
#inout 0
|
||||
|
||||
Utilization Statistics
|
||||
#lut 10345 out of 19600 52.78%
|
||||
#reg 9356 out of 19600 47.73%
|
||||
#le 12483
|
||||
#lut only 3127 out of 12483 25.05%
|
||||
#reg only 2138 out of 12483 17.13%
|
||||
#lut® 7218 out of 12483 57.82%
|
||||
#lut 10320 out of 19600 52.65%
|
||||
#reg 9363 out of 19600 47.77%
|
||||
#le 12661
|
||||
#lut only 3298 out of 12661 26.05%
|
||||
#reg only 2341 out of 12661 18.49%
|
||||
#lut® 7022 out of 12661 55.46%
|
||||
#dsp 3 out of 29 10.34%
|
||||
#bram 54 out of 64 84.38%
|
||||
#bram9k 50
|
||||
|
|
@ -21,24 +21,24 @@ Utilization Statistics
|
|||
#bram32k 4 out of 16 25.00%
|
||||
#pad 75 out of 130 57.69%
|
||||
#ireg 13
|
||||
#oreg 21
|
||||
#oreg 18
|
||||
#treg 0
|
||||
#pll 3 out of 4 75.00%
|
||||
#gclk 6 out of 16 37.50%
|
||||
|
||||
Clock Resource Statistics
|
||||
Index ClockNet Type DriverType Driver Fanout
|
||||
#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1785
|
||||
#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1421
|
||||
#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1348
|
||||
#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 951
|
||||
#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 144
|
||||
#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
|
||||
#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
|
||||
#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
|
||||
#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1795
|
||||
#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1417
|
||||
#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1355
|
||||
#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 967
|
||||
#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 139
|
||||
#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70
|
||||
#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
|
||||
#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24
|
||||
#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
|
||||
#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg40_syn_225.f1 3
|
||||
#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg50_syn_208.f1 2
|
||||
#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg42_syn_219.f1 3
|
||||
#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_b/u_ADconfig/reg1_syn_191.f0 2
|
||||
#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
|
||||
#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
|
||||
#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
|
||||
|
|
@ -48,36 +48,36 @@ Index ClockNet Type
|
|||
Detailed IO Report
|
||||
|
||||
Name Direction Location IOStandard DriveStrength PullType PackReg
|
||||
a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
|
||||
a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
|
||||
b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
|
||||
b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
|
||||
a_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
|
||||
a_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
|
||||
a_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
|
||||
b_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
|
||||
b_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
|
||||
b_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
|
||||
clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
|
||||
global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
|
||||
onoff_in INPUT P140 LVCMOS33 N/A N/A NONE
|
||||
paper_in INPUT P17 LVCMOS25 N/A N/A NONE
|
||||
onoff_in INPUT P133 LVCMOS33 N/A N/A NONE
|
||||
paper_in INPUT P4 LVCMOS25 N/A N/A NONE
|
||||
rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
|
||||
O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
|
||||
O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
|
||||
|
|
@ -99,126 +99,128 @@ Detailed IO Report
|
|||
O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
|
||||
O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
|
||||
O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
|
||||
a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
|
||||
a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
|
||||
a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
|
||||
a_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
|
||||
a_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
|
||||
a_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
|
||||
a_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
|
||||
a_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
|
||||
a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
|
||||
b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
|
||||
b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
|
||||
b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
|
||||
b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
|
||||
b_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
|
||||
b_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
|
||||
b_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
|
||||
b_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
|
||||
debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
|
||||
debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
|
||||
debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
|
||||
debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
|
||||
debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
|
||||
debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
|
||||
debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
|
||||
debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
|
||||
debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
|
||||
debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
|
||||
debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
|
||||
fan_pwm OUTPUT P25 LVCMOS25 8 N/A NONE
|
||||
fan_pwm OUTPUT P138 LVCMOS33 8 N/A NONE
|
||||
frame_indicator OUTPUT P16 LVCMOS25 8 N/A OREG
|
||||
onoff_out OUTPUT P118 LVCMOS25 8 N/A NONE
|
||||
paper_out OUTPUT P104 LVCMOS25 8 N/A NONE
|
||||
scan_out OUTPUT P83 LVCMOS25 8 N/A NONE
|
||||
sys_initial_done OUTPUT P32 LVCMOS25 8 N/A NONE
|
||||
onoff_out OUTPUT P152 LVCMOS33 8 N/A NONE
|
||||
paper_out OUTPUT P17 LVCMOS25 8 N/A NONE
|
||||
scan_out OUTPUT P15 LVCMOS25 8 N/A NONE
|
||||
sys_initial_done OUTPUT P104 LVCMOS25 8 N/A NONE
|
||||
txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
|
||||
|
||||
Report Hierarchy Area:
|
||||
+---------------------------------------------------------------------------------------------------------+
|
||||
|Instance |Module |le |lut |ripple |seq |bram |dsp |
|
||||
+---------------------------------------------------------------------------------------------------------+
|
||||
|top |huagao_mipi_top |12483 |9318 |1027 |9390 |58 |3 |
|
||||
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |558 |470 |23 |457 |4 |1 |
|
||||
| U_fifo_w32_d8192 |fifo_w32_d8192 |103 |85 |4 |91 |4 |0 |
|
||||
| U_crc16_24b |crc16_24b |34 |34 |0 |21 |0 |0 |
|
||||
| U_ecc_gen |ecc_gen |9 |9 |0 |8 |0 |0 |
|
||||
| exdev_ctl_a |exdev_ctl |785 |405 |96 |577 |0 |0 |
|
||||
| u_ADconfig |AD_config |191 |139 |25 |145 |0 |0 |
|
||||
| u_gen_sp |gen_sp |276 |185 |71 |114 |0 |0 |
|
||||
| exdev_ctl_b |exdev_ctl |761 |400 |96 |555 |0 |0 |
|
||||
| u_ADconfig |AD_config |186 |137 |25 |123 |0 |0 |
|
||||
| u_gen_sp |gen_sp |259 |173 |71 |116 |0 |0 |
|
||||
| sampling_fe_a |sampling_fe |2929 |2427 |306 |1994 |25 |0 |
|
||||
| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||
| u_ad_sampling |ad_sampling |187 |138 |17 |141 |0 |0 |
|
||||
|top |huagao_mipi_top |12661 |9293 |1027 |9394 |58 |3 |
|
||||
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |545 |451 |23 |442 |4 |1 |
|
||||
| U_fifo_w32_d8192 |fifo_w32_d8192 |98 |83 |4 |90 |4 |0 |
|
||||
| U_crc16_24b |crc16_24b |29 |29 |0 |19 |0 |0 |
|
||||
| U_ecc_gen |ecc_gen |14 |14 |0 |10 |0 |0 |
|
||||
| exdev_ctl_a |exdev_ctl |767 |373 |96 |581 |0 |0 |
|
||||
| u_ADconfig |AD_config |188 |139 |25 |142 |0 |0 |
|
||||
| u_gen_sp |gen_sp |263 |160 |71 |123 |0 |0 |
|
||||
| exdev_ctl_b |exdev_ctl |752 |423 |96 |556 |0 |0 |
|
||||
| u_ADconfig |AD_config |178 |140 |25 |126 |0 |0 |
|
||||
| u_gen_sp |gen_sp |262 |168 |71 |118 |0 |0 |
|
||||
| sampling_fe_a |sampling_fe |3094 |2433 |306 |2032 |25 |0 |
|
||||
| u0_soft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
|
||||
| u_ad_sampling |ad_sampling |183 |97 |17 |141 |0 |0 |
|
||||
| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||
| u_sort |sort |2708 |2271 |289 |1819 |25 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
|
||||
| u0_wrsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
|
||||
| u_data_prebuffer |data_prebuffer |2358 |1986 |253 |1518 |22 |0 |
|
||||
| channelPart |channel_part_8478 |154 |151 |3 |138 |0 |0 |
|
||||
| fifo_adc |fifo_adc |61 |52 |9 |42 |0 |0 |
|
||||
| ram_switch |ram_switch |1853 |1549 |197 |1126 |0 |0 |
|
||||
| adc_addr_gen |adc_addr_gen |250 |223 |27 |124 |0 |0 |
|
||||
| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |8 |0 |0 |
|
||||
| [1]$ch_addr_gen |ch_addr_gen |27 |24 |3 |16 |0 |0 |
|
||||
| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
|
||||
| [3]$ch_addr_gen |ch_addr_gen |21 |18 |3 |9 |0 |0 |
|
||||
| [4]$ch_addr_gen |ch_addr_gen |29 |26 |3 |14 |0 |0 |
|
||||
| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
|
||||
| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
|
||||
| [7]$ch_addr_gen |ch_addr_gen |27 |24 |3 |12 |0 |0 |
|
||||
| [8]$ch_addr_gen |ch_addr_gen |30 |27 |3 |13 |0 |0 |
|
||||
| insert |insert |962 |685 |170 |654 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |641 |641 |0 |348 |0 |0 |
|
||||
| read_ram_i |read_ram |263 |208 |44 |185 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr |210 |170 |40 |146 |0 |0 |
|
||||
| read_ram_data |read_ram_data |51 |36 |4 |37 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
|
||||
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u_transfer_300_to_200 |transfer_300_to_200 |316 |259 |36 |267 |3 |0 |
|
||||
| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
|
||||
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
|
||||
| sampling_fe_b |sampling_fe_rev |3306 |2572 |349 |2092 |25 |1 |
|
||||
| u0_soft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
|
||||
| u_ad_sampling |ad_sampling |185 |101 |17 |148 |0 |0 |
|
||||
| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
|
||||
| u_sort |sort_rev |3087 |2458 |332 |1910 |25 |1 |
|
||||
| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
|
||||
| u0_wrsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
|
||||
| u_data_prebuffer_rev |data_prebuffer_rev |2665 |2161 |290 |1546 |22 |1 |
|
||||
| channelPart |channel_part_8478 |232 |228 |3 |136 |0 |0 |
|
||||
| fifo_adc |fifo_adc |60 |51 |9 |44 |0 |1 |
|
||||
| ram_switch |ram_switch |1981 |1613 |197 |1120 |0 |0 |
|
||||
| adc_addr_gen |adc_addr_gen |228 |201 |27 |105 |0 |0 |
|
||||
| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |4 |0 |0 |
|
||||
| [1]$ch_addr_gen |ch_addr_gen |28 |25 |3 |14 |0 |0 |
|
||||
| [2]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
|
||||
| [3]$ch_addr_gen |ch_addr_gen |21 |18 |3 |12 |0 |0 |
|
||||
| [4]$ch_addr_gen |ch_addr_gen |21 |18 |3 |8 |0 |0 |
|
||||
| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |6 |0 |0 |
|
||||
| [6]$ch_addr_gen |ch_addr_gen |27 |24 |3 |12 |0 |0 |
|
||||
| u_sort |sort |2875 |2311 |289 |1855 |25 |0 |
|
||||
| rddpram_ctl |rddpram_ctl |5 |5 |0 |5 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
|
||||
| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||
| u_data_prebuffer |data_prebuffer |2499 |2063 |253 |1538 |22 |0 |
|
||||
| channelPart |channel_part_8478 |133 |130 |3 |122 |0 |0 |
|
||||
| fifo_adc |fifo_adc |62 |53 |9 |44 |0 |0 |
|
||||
| ram_switch |ram_switch |1994 |1633 |197 |1144 |0 |0 |
|
||||
| adc_addr_gen |adc_addr_gen |244 |217 |27 |114 |0 |0 |
|
||||
| [0]$ch_addr_gen |ch_addr_gen |8 |5 |3 |4 |0 |0 |
|
||||
| [1]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
|
||||
| [2]$ch_addr_gen |ch_addr_gen |29 |26 |3 |14 |0 |0 |
|
||||
| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
|
||||
| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
|
||||
| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
|
||||
| [6]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
|
||||
| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
|
||||
| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 |
|
||||
| insert |insert |1007 |668 |170 |696 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |746 |744 |0 |319 |0 |0 |
|
||||
| read_ram_i |read_ram_rev |359 |248 |81 |213 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr_rev |286 |202 |73 |160 |0 |0 |
|
||||
| read_ram_data |read_ram_data_rev |73 |46 |8 |53 |0 |0 |
|
||||
| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |9 |0 |0 |
|
||||
| insert |insert |953 |620 |170 |654 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |797 |796 |0 |376 |0 |0 |
|
||||
| read_ram_i |read_ram |265 |209 |44 |186 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr |213 |173 |40 |147 |0 |0 |
|
||||
| read_ram_data |read_ram_data |51 |35 |4 |38 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
|
||||
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
|
||||
| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_5 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
|
||||
| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u_transfer_300_to_200 |transfer_300_to_200 |339 |233 |36 |280 |3 |0 |
|
||||
| u0_soft_n |cdc_sync |7 |7 |0 |7 |0 |0 |
|
||||
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
|
||||
| sampling_fe_b |sampling_fe_rev |3367 |2648 |349 |2114 |25 |1 |
|
||||
| u0_soft_n |cdc_sync |6 |1 |0 |6 |0 |0 |
|
||||
| u_ad_sampling |ad_sampling |166 |113 |17 |130 |0 |0 |
|
||||
| u0_soft_n |cdc_sync |6 |1 |0 |6 |0 |0 |
|
||||
| u_sort |sort_rev |3165 |2522 |332 |1948 |25 |1 |
|
||||
| rddpram_ctl |rddpram_ctl_rev |4 |3 |0 |4 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |7 |2 |0 |7 |0 |0 |
|
||||
| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||
| u_data_prebuffer_rev |data_prebuffer_rev |2731 |2228 |290 |1587 |22 |1 |
|
||||
| channelPart |channel_part_8478 |238 |235 |3 |135 |0 |0 |
|
||||
| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
|
||||
| ram_switch |ram_switch |1983 |1621 |197 |1142 |0 |0 |
|
||||
| adc_addr_gen |adc_addr_gen |221 |194 |27 |105 |0 |0 |
|
||||
| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |6 |0 |0 |
|
||||
| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
|
||||
| [2]$ch_addr_gen |ch_addr_gen |30 |27 |3 |18 |0 |0 |
|
||||
| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
|
||||
| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
|
||||
| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |8 |0 |0 |
|
||||
| [6]$ch_addr_gen |ch_addr_gen |21 |18 |3 |10 |0 |0 |
|
||||
| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
|
||||
| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
|
||||
| insert |insert |974 |641 |170 |669 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |788 |786 |0 |368 |0 |0 |
|
||||
| read_ram_i |read_ram_rev |424 |303 |81 |240 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr_rev |291 |206 |73 |159 |0 |0 |
|
||||
| read_ram_data |read_ram_data_rev |133 |97 |8 |81 |0 |0 |
|
||||
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
|
|
@ -241,65 +243,66 @@ Report Hierarchy Area:
|
|||
| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u_transfer_300_to_200 |transfer_300_to_200 |315 |215 |42 |278 |3 |0 |
|
||||
| u0_soft_n |cdc_sync |5 |1 |0 |5 |0 |0 |
|
||||
| u_transfer_300_to_200 |transfer_300_to_200 |327 |215 |42 |273 |3 |0 |
|
||||
| u0_soft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
|
||||
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
|
||||
| scan_start_diff |scan_start_diff |23 |22 |0 |15 |0 |0 |
|
||||
| u0_test_en |cdc_sync |3 |3 |0 |3 |0 |0 |
|
||||
| u1_test_en |cdc_sync |2 |1 |0 |2 |0 |0 |
|
||||
| u2_test_en |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||
| u_a_pclk |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||
| u_a_sp_sampling |cdc_sync |2 |2 |0 |2 |0 |0 |
|
||||
| u_a_sp_sampling_cam |cdc_sync |8 |4 |0 |8 |0 |0 |
|
||||
| u_a_sp_sampling_last |cdc_sync |2 |0 |0 |2 |0 |0 |
|
||||
| u_b_pclk |cdc_sync |3 |2 |0 |3 |0 |0 |
|
||||
| u_b_sp_sampling |cdc_sync |5 |3 |0 |5 |0 |0 |
|
||||
| u_b_sp_sampling_cam |cdc_sync |7 |4 |0 |7 |0 |0 |
|
||||
| scan_start_diff |scan_start_diff |23 |23 |0 |15 |0 |0 |
|
||||
| u0_test_en |cdc_sync |4 |2 |0 |4 |0 |0 |
|
||||
| u1_test_en |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||
| u2_test_en |cdc_sync |3 |3 |0 |3 |0 |0 |
|
||||
| u_a_pclk |cdc_sync |5 |5 |0 |5 |0 |0 |
|
||||
| u_a_sp_sampling |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||
| u_a_sp_sampling_cam |cdc_sync |5 |1 |0 |5 |0 |0 |
|
||||
| u_a_sp_sampling_last |cdc_sync |5 |4 |0 |5 |0 |0 |
|
||||
| u_b_pclk |cdc_sync |4 |3 |0 |4 |0 |0 |
|
||||
| u_b_sp_sampling |cdc_sync |6 |2 |0 |6 |0 |0 |
|
||||
| u_b_sp_sampling_cam |cdc_sync |6 |4 |0 |6 |0 |0 |
|
||||
| u_b_sp_sampling_last |cdc_sync |2 |2 |0 |2 |0 |0 |
|
||||
| u_bus_top |ubus_top |1329 |1076 |22 |1238 |0 |0 |
|
||||
| u_local_bus_slve_cis |local_bus_slve_cis |826 |729 |22 |735 |0 |0 |
|
||||
| u_uart_2dsp |uart_2dsp |110 |98 |12 |63 |0 |0 |
|
||||
| u_dpi_mode |cdc_sync |11 |11 |0 |11 |0 |0 |
|
||||
| u_lv_en_flag |cdc_sync |3 |3 |0 |3 |0 |0 |
|
||||
| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |277 |240 |20 |222 |4 |0 |
|
||||
| u_hs_tx_wrapper |hs_tx_wrapper |241 |204 |20 |194 |4 |0 |
|
||||
| [0]$u_data_lane_wrapper |data_lane_wrapper |115 |86 |15 |87 |1 |0 |
|
||||
| u_data_hs_generate |data_hs_generate |112 |83 |15 |84 |1 |0 |
|
||||
| u_dphy_tx_fifo |dphy_tx_fifo |2 |2 |0 |0 |1 |0 |
|
||||
| u_d1024_w8_fifo |d1024_w8_fifo |2 |2 |0 |0 |1 |0 |
|
||||
| u_data_lp_generate |data_lp_generate |3 |3 |0 |3 |0 |0 |
|
||||
| [1]$u_data_lane_wrapper |data_lane_wrapper |30 |29 |0 |29 |1 |0 |
|
||||
| u_data_hs_generate |data_hs_generate |30 |29 |0 |29 |1 |0 |
|
||||
| u_bus_top |ubus_top |1297 |1117 |22 |1208 |0 |0 |
|
||||
| u_local_bus_slve_cis |local_bus_slve_cis |800 |724 |22 |711 |0 |0 |
|
||||
| u_uart_2dsp |uart_2dsp |98 |86 |12 |61 |0 |0 |
|
||||
| u_dpi_mode |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||
| u_eot |cdc_sync |3 |3 |0 |3 |0 |0 |
|
||||
| u_lv_en_flag |cdc_sync |5 |5 |0 |5 |0 |0 |
|
||||
| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |275 |237 |20 |213 |4 |0 |
|
||||
| u_hs_tx_wrapper |hs_tx_wrapper |227 |189 |20 |185 |4 |0 |
|
||||
| [0]$u_data_lane_wrapper |data_lane_wrapper |112 |89 |15 |86 |1 |0 |
|
||||
| u_data_hs_generate |data_hs_generate |107 |84 |15 |81 |1 |0 |
|
||||
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
|
||||
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
|
||||
| [2]$u_data_lane_wrapper |data_lane_wrapper |28 |26 |0 |28 |1 |0 |
|
||||
| u_data_hs_generate |data_hs_generate |28 |26 |0 |28 |1 |0 |
|
||||
| u_data_lp_generate |data_lp_generate |5 |5 |0 |5 |0 |0 |
|
||||
| [1]$u_data_lane_wrapper |data_lane_wrapper |27 |17 |0 |27 |1 |0 |
|
||||
| u_data_hs_generate |data_hs_generate |27 |17 |0 |27 |1 |0 |
|
||||
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
|
||||
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
|
||||
| [3]$u_data_lane_wrapper |data_lane_wrapper |25 |25 |0 |25 |1 |0 |
|
||||
| u_data_hs_generate |data_hs_generate |25 |25 |0 |25 |1 |0 |
|
||||
| [2]$u_data_lane_wrapper |data_lane_wrapper |22 |22 |0 |22 |1 |0 |
|
||||
| u_data_hs_generate |data_hs_generate |22 |22 |0 |22 |1 |0 |
|
||||
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
|
||||
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
|
||||
| u_hs_tx_controler |hs_tx_controler |35 |30 |5 |17 |0 |0 |
|
||||
| u_clk_lane_wrapper |clk_lane_wrapper |7 |7 |0 |7 |0 |0 |
|
||||
| [3]$u_data_lane_wrapper |data_lane_wrapper |24 |24 |0 |24 |1 |0 |
|
||||
| u_data_hs_generate |data_hs_generate |24 |24 |0 |24 |1 |0 |
|
||||
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
|
||||
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
|
||||
| u_hs_tx_controler |hs_tx_controler |34 |29 |5 |18 |0 |0 |
|
||||
| u_clk_lane_wrapper |clk_lane_wrapper |8 |8 |0 |8 |0 |0 |
|
||||
| u_clk_lp_generate |clk_lp_generate |4 |4 |0 |4 |0 |0 |
|
||||
| u_clk_hs_generate |clk_hs_generate |3 |3 |0 |3 |0 |0 |
|
||||
| u_mipi_eot_min |cdc_sync |69 |68 |0 |69 |0 |0 |
|
||||
| u_mipi_sot_min |cdc_sync |60 |56 |0 |60 |0 |0 |
|
||||
| u_pic_cnt |cdc_sync |116 |46 |0 |116 |0 |0 |
|
||||
| u_pixel_cdc |pixel_cdc |712 |534 |0 |712 |0 |1 |
|
||||
| u_clk_cis_frame_num |cdc_sync |74 |60 |0 |74 |0 |0 |
|
||||
| u_clk_cis_pixel_y |cdc_sync |75 |54 |0 |75 |0 |0 |
|
||||
| u_clk_mipi_pixel_y |cdc_sync |74 |68 |0 |74 |0 |0 |
|
||||
| u_clka_cis_total_num |cdc_sync |106 |52 |0 |106 |0 |0 |
|
||||
| u_clka_mipi_total_num |cdc_sync |97 |72 |0 |97 |0 |0 |
|
||||
| u_clkb_cis_total_num |cdc_sync |106 |70 |0 |106 |0 |0 |
|
||||
| u_clkb_mipi_total_num |cdc_sync |108 |95 |0 |108 |0 |0 |
|
||||
| u_clk_hs_generate |clk_hs_generate |4 |4 |0 |4 |0 |0 |
|
||||
| u_mipi_eot_min |cdc_sync |58 |58 |0 |58 |0 |0 |
|
||||
| u_mipi_sot_min |cdc_sync |66 |65 |0 |66 |0 |0 |
|
||||
| u_pic_cnt |cdc_sync |117 |40 |0 |117 |0 |0 |
|
||||
| u_pixel_cdc |pixel_cdc |688 |412 |0 |688 |0 |1 |
|
||||
| u_clk_cis_frame_num |cdc_sync |75 |65 |0 |75 |0 |0 |
|
||||
| u_clk_cis_pixel_y |cdc_sync |74 |47 |0 |74 |0 |0 |
|
||||
| u_clk_mipi_pixel_y |cdc_sync |67 |45 |0 |67 |0 |0 |
|
||||
| u_clka_cis_total_num |cdc_sync |108 |33 |0 |108 |0 |0 |
|
||||
| u_clka_mipi_total_num |cdc_sync |108 |58 |0 |108 |0 |0 |
|
||||
| u_clkb_cis_total_num |cdc_sync |104 |65 |0 |104 |0 |0 |
|
||||
| u_clkb_mipi_total_num |cdc_sync |89 |58 |0 |89 |0 |0 |
|
||||
| u_pll |pll |0 |0 |0 |0 |0 |0 |
|
||||
| u_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |0 |
|
||||
| u_softrst_done |cdc_sync |3 |3 |0 |3 |0 |0 |
|
||||
| ua_lvds_rx |lvds_rx |290 |205 |19 |207 |0 |0 |
|
||||
| ub_lvds_rx |lvds_rx |288 |194 |19 |209 |0 |0 |
|
||||
| u_softrst_done |cdc_sync |2 |0 |0 |2 |0 |0 |
|
||||
| ua_lvds_rx |lvds_rx |286 |192 |19 |206 |0 |0 |
|
||||
| ub_lvds_rx |lvds_rx |287 |185 |19 |207 |0 |0 |
|
||||
| uu_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |0 |
|
||||
+---------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
|
@ -307,12 +310,12 @@ Report Hierarchy Area:
|
|||
DataNet Average Fanout:
|
||||
|
||||
Index Fanout Nets
|
||||
#1 1 9929
|
||||
#2 2 3890
|
||||
#3 3 1404
|
||||
#4 4 524
|
||||
#5 5-10 1204
|
||||
#6 11-50 601
|
||||
#7 51-100 23
|
||||
#1 1 9824
|
||||
#2 2 3937
|
||||
#3 3 1458
|
||||
#4 4 642
|
||||
#5 5-10 1062
|
||||
#6 11-50 587
|
||||
#7 51-100 24
|
||||
#8 >500 1
|
||||
Average 2.92
|
||||
Average 2.91
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
|
@ -1,5 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="30108">
|
||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="12880">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="30108">
|
||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="12880">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="30108">
|
||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="12880">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Project Version="3" Minor="2" RunTime="2024-01-23T14:15:59.018440">
|
||||
<Project Version="3" Minor="2" RunTime="2024-02-18T16:10:55.245054">
|
||||
<Project_Created_Time></Project_Created_Time>
|
||||
<TD_Encoding>UTF-8</TD_Encoding>
|
||||
<TD_Version>5.6.71036</TD_Version>
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -8,15 +8,15 @@ IO Statistics
|
|||
#inout 0
|
||||
|
||||
LUT Statistics
|
||||
#Total_luts 10043
|
||||
#lut4 5250
|
||||
#lut5 2238
|
||||
#Total_luts 9995
|
||||
#lut4 5129
|
||||
#lut5 2311
|
||||
#lut6 0
|
||||
#lut5_mx41 0
|
||||
#lut4_alu1b 2555
|
||||
|
||||
Utilization Statistics
|
||||
#lut 10043 out of 19600 51.24%
|
||||
#lut 9995 out of 19600 50.99%
|
||||
#reg 9170 out of 19600 46.79%
|
||||
#le 0
|
||||
#dsp 3 out of 29 10.34%
|
||||
|
|
@ -27,7 +27,7 @@ Utilization Statistics
|
|||
#dram 16
|
||||
#pad 75 out of 130 57.69%
|
||||
#ireg 13
|
||||
#oreg 21
|
||||
#oreg 18
|
||||
#treg 0
|
||||
#pll 3 out of 4 75.00%
|
||||
|
||||
|
|
@ -35,30 +35,30 @@ Report Hierarchy Area:
|
|||
+-------------------------------------------------------------------------------------------------+
|
||||
|Instance |Module |lut |ripple |seq |bram |dsp |
|
||||
+-------------------------------------------------------------------------------------------------+
|
||||
|top |huagao_mipi_top |7488 |2555 |9204 |58 |3 |
|
||||
|top |huagao_mipi_top |7440 |2555 |9201 |58 |3 |
|
||||
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |339 |81 |441 |4 |1 |
|
||||
| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 |
|
||||
| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
|
||||
| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
|
||||
| exdev_ctl_a |exdev_ctl |287 |234 |559 |0 |0 |
|
||||
| u_ADconfig |AD_config |100 |49 |138 |0 |0 |
|
||||
| u_gen_sp |gen_sp |129 |185 |104 |0 |0 |
|
||||
| exdev_ctl_b |exdev_ctl |275 |234 |546 |0 |0 |
|
||||
| exdev_ctl_a |exdev_ctl |282 |234 |559 |0 |0 |
|
||||
| u_ADconfig |AD_config |99 |49 |138 |0 |0 |
|
||||
| u_gen_sp |gen_sp |125 |185 |104 |0 |0 |
|
||||
| exdev_ctl_b |exdev_ctl |279 |234 |546 |0 |0 |
|
||||
| u_ADconfig |AD_config |91 |49 |125 |0 |0 |
|
||||
| u_gen_sp |gen_sp |126 |185 |104 |0 |0 |
|
||||
| sampling_fe_a |sampling_fe |2108 |738 |1894 |25 |0 |
|
||||
| u_gen_sp |gen_sp |130 |185 |104 |0 |0 |
|
||||
| sampling_fe_a |sampling_fe |2067 |738 |1894 |25 |0 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_sort |sort |2038 |691 |1712 |25 |0 |
|
||||
| u_sort |sort |1997 |691 |1712 |25 |0 |
|
||||
| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_data_prebuffer |data_prebuffer |1909 |615 |1391 |22 |0 |
|
||||
| u_data_prebuffer |data_prebuffer |1868 |615 |1391 |22 |0 |
|
||||
| channelPart |channel_part_8478 |147 |11 |144 |0 |0 |
|
||||
| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
|
||||
| ram_switch |ram_switch |1483 |422 |1023 |0 |0 |
|
||||
| ram_switch |ram_switch |1448 |422 |1023 |0 |0 |
|
||||
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
|
||||
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
|
||||
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
|
|
@ -70,10 +70,10 @@ Report Hierarchy Area:
|
|||
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| insert |insert |265 |323 |692 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |1089 |0 |216 |0 |0 |
|
||||
| read_ram_i |read_ram |192 |158 |164 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr |161 |145 |127 |0 |0 |
|
||||
| read_ram_data |read_ram_data |30 |13 |32 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |1054 |0 |216 |0 |0 |
|
||||
| read_ram_i |read_ram |186 |158 |164 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr |158 |145 |127 |0 |0 |
|
||||
| read_ram_data |read_ram_data |27 |13 |32 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
|
|
@ -100,19 +100,19 @@ Report Hierarchy Area:
|
|||
| u_transfer_300_to_200 |transfer_300_to_200 |122 |76 |276 |3 |0 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
|
||||
| sampling_fe_b |sampling_fe_rev |2299 |751 |1958 |25 |1 |
|
||||
| sampling_fe_b |sampling_fe_rev |2261 |751 |1958 |25 |1 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_sort |sort_rev |2229 |704 |1776 |25 |1 |
|
||||
| u_sort |sort_rev |2191 |704 |1776 |25 |1 |
|
||||
| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_data_prebuffer_rev |data_prebuffer_rev |2104 |628 |1405 |22 |1 |
|
||||
| u_data_prebuffer_rev |data_prebuffer_rev |2066 |628 |1405 |22 |1 |
|
||||
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
|
||||
| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
|
||||
| ram_switch |ram_switch |1478 |422 |1023 |0 |0 |
|
||||
| ram_switch |ram_switch |1441 |422 |1023 |0 |0 |
|
||||
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
|
||||
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
|
||||
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
|
|
@ -124,9 +124,9 @@ Report Hierarchy Area:
|
|||
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| insert |insert |265 |323 |692 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |1084 |0 |216 |0 |0 |
|
||||
| read_ram_i |read_ram_rev |391 |171 |178 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr_rev |177 |145 |136 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |1047 |0 |216 |0 |0 |
|
||||
| read_ram_i |read_ram_rev |390 |171 |178 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr_rev |176 |145 |136 |0 |0 |
|
||||
| read_ram_data |read_ram_data_rev |214 |26 |42 |0 |0 |
|
||||
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
|
|
@ -165,16 +165,16 @@ Report Hierarchy Area:
|
|||
| u_b_sp_sampling |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_b_sp_sampling_cam |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_b_sp_sampling_last |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_bus_top |ubus_top |809 |50 |1248 |0 |0 |
|
||||
| u_local_bus_slve_cis |local_bus_slve_cis |715 |50 |721 |0 |0 |
|
||||
| u_uart_2dsp |uart_2dsp |115 |31 |52 |0 |0 |
|
||||
| u_bus_top |ubus_top |826 |50 |1248 |0 |0 |
|
||||
| u_local_bus_slve_cis |local_bus_slve_cis |732 |50 |721 |0 |0 |
|
||||
| u_uart_2dsp |uart_2dsp |119 |31 |52 |0 |0 |
|
||||
| u_dpi_mode |cdc_sync |2 |0 |10 |0 |0 |
|
||||
| u_eot |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_lv_en_flag |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |163 |61 |226 |4 |0 |
|
||||
| u_hs_tx_wrapper |hs_tx_wrapper |108 |61 |198 |4 |0 |
|
||||
| [0]$u_data_lane_wrapper |data_lane_wrapper |50 |52 |93 |1 |0 |
|
||||
| u_data_hs_generate |data_hs_generate |46 |52 |87 |1 |0 |
|
||||
| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |170 |61 |226 |4 |0 |
|
||||
| u_hs_tx_wrapper |hs_tx_wrapper |111 |61 |198 |4 |0 |
|
||||
| [0]$u_data_lane_wrapper |data_lane_wrapper |54 |52 |93 |1 |0 |
|
||||
| u_data_hs_generate |data_hs_generate |50 |52 |87 |1 |0 |
|
||||
| u_dphy_tx_fifo |dphy_tx_fifo |2 |0 |0 |1 |0 |
|
||||
| u_d1024_w8_fifo |d1024_w8_fifo |2 |0 |0 |1 |0 |
|
||||
| u_data_lp_generate |data_lp_generate |4 |0 |6 |0 |0 |
|
||||
|
|
@ -193,7 +193,7 @@ Report Hierarchy Area:
|
|||
| u_clk_lane_wrapper |clk_lane_wrapper |3 |0 |8 |0 |0 |
|
||||
| u_clk_hs_generate |clk_hs_generate |3 |0 |4 |0 |0 |
|
||||
| u_clk_lp_generate |clk_lp_generate |0 |0 |4 |0 |0 |
|
||||
| u_hs_tx_controler |hs_tx_controler |25 |9 |12 |0 |0 |
|
||||
| u_hs_tx_controler |hs_tx_controler |24 |9 |12 |0 |0 |
|
||||
| u_mipi_eot_min |cdc_sync |20 |0 |65 |0 |0 |
|
||||
| u_mipi_sot_min |cdc_sync |20 |0 |65 |0 |0 |
|
||||
| u_pic_cnt |cdc_sync |38 |0 |120 |0 |0 |
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -43,16 +43,16 @@ Report Hierarchy Area:
|
|||
| exdev_ctl_b |exdev_ctl |158 |546 |41 |
|
||||
| u_ADconfig |AD_config |81 |125 |18 |
|
||||
| u_gen_sp |gen_sp |76 |104 |19 |
|
||||
| sampling_fe_a |sampling_fe |1837 |1894 |269 |
|
||||
| sampling_fe_a |sampling_fe |1838 |1894 |269 |
|
||||
| u0_soft_n |cdc_sync |2 |5 |0 |
|
||||
| u_ad_sampling |ad_sampling |40 |147 |10 |
|
||||
| u0_soft_n |cdc_sync |2 |5 |0 |
|
||||
| u_sort |sort |1793 |1712 |258 |
|
||||
| u_sort |sort |1794 |1712 |258 |
|
||||
| rddpram_ctl |rddpram_ctl |2 |5 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
|
||||
| u0_wrsoft_n |cdc_sync |2 |5 |0 |
|
||||
| u_data_prebuffer |data_prebuffer |1538 |1391 |118 |
|
||||
| u_data_prebuffer |data_prebuffer |1539 |1391 |118 |
|
||||
| channelPart |channel_part_8478 |865 |144 |8 |
|
||||
| fifo_adc |fifo_adc |112 |41 |4 |
|
||||
| ram_switch |ram_switch |60 |1023 |52 |
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -4,7 +4,7 @@
|
|||
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
|
||||
Built at = 20:34:38 Mar 21 2023
|
||||
Run by = holdtecs
|
||||
Run Date = Tue Jan 23 14:15:59 2024
|
||||
Run Date = Sun Feb 18 16:10:55 2024
|
||||
|
||||
Run on = DESKTOP-5MQL5VE
|
||||
============================================================
|
||||
|
|
@ -422,9 +422,9 @@ HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been re
|
|||
HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
|
||||
HDL-1200 : Current top model is huagao_mipi_top
|
||||
HDL-1100 : Inferred 1 RAMs.
|
||||
RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.034104s wall, 1.031250s user + 0.015625s system = 1.046875s CPU (101.2%)
|
||||
RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.135611s wall, 1.109375s user + 0.015625s system = 1.125000s CPU (99.1%)
|
||||
|
||||
RUN-1004 : used memory is 192 MB, reserved memory is 170 MB, peak memory is 232 MB
|
||||
RUN-1004 : used memory is 193 MB, reserved memory is 171 MB, peak memory is 233 MB
|
||||
RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
|
||||
RUN-1001 : Exported /
|
||||
RUN-1001 : Exported flow parameters
|
||||
|
|
@ -456,28 +456,28 @@ RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; I
|
|||
RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
|
||||
RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
|
||||
RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
|
||||
RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
|
||||
RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
|
||||
RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
|
||||
RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
|
||||
RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment a_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
|
||||
RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
|
||||
RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
|
||||
|
|
@ -654,7 +654,7 @@ RUN-1001 : ub_lvds_rx | false | lvds_rx |
|
|||
RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
|
||||
RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
|
||||
RUN-1001 : ------------------------------------------------------------------------------------------------
|
||||
SYN-1032 : 53811/19108 useful/useless nets, 20667/1811 useful/useless insts
|
||||
SYN-1032 : 53810/19109 useful/useless nets, 20666/1812 useful/useless insts
|
||||
SYN-1001 : Optimize 156 less-than instances
|
||||
SYN-1016 : Merged 38313 instances.
|
||||
SYN-1025 : Merged 24 RAM ports.
|
||||
|
|
@ -1318,9 +1318,9 @@ SYN-1032 : 25138/20 useful/useless nets, 22488/2 useful/useless insts
|
|||
SYN-1015 : Optimize round 2, 2 better
|
||||
SYN-1014 : Optimize round 3
|
||||
SYN-1015 : Optimize round 3, 0 better
|
||||
RUN-1003 : finish command "optimize_rtl" in 18.095703s wall, 16.078125s user + 2.015625s system = 18.093750s CPU (100.0%)
|
||||
RUN-1003 : finish command "optimize_rtl" in 19.412269s wall, 17.515625s user + 1.875000s system = 19.390625s CPU (99.9%)
|
||||
|
||||
RUN-1004 : used memory is 330 MB, reserved memory is 303 MB, peak memory is 349 MB
|
||||
RUN-1004 : used memory is 330 MB, reserved memory is 302 MB, peak memory is 350 MB
|
||||
RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
|
||||
RUN-1001 : standard
|
||||
***Report Model: huagao_mipi_top Device: EG4D20EG176***
|
||||
|
|
@ -1367,16 +1367,16 @@ Report Hierarchy Area:
|
|||
| exdev_ctl_b |exdev_ctl |158 |546 |41 |
|
||||
| u_ADconfig |AD_config |81 |125 |18 |
|
||||
| u_gen_sp |gen_sp |76 |104 |19 |
|
||||
| sampling_fe_a |sampling_fe |1837 |1894 |269 |
|
||||
| sampling_fe_a |sampling_fe |1838 |1894 |269 |
|
||||
| u0_soft_n |cdc_sync |2 |5 |0 |
|
||||
| u_ad_sampling |ad_sampling |40 |147 |10 |
|
||||
| u0_soft_n |cdc_sync |2 |5 |0 |
|
||||
| u_sort |sort |1793 |1712 |258 |
|
||||
| u_sort |sort |1794 |1712 |258 |
|
||||
| rddpram_ctl |rddpram_ctl |2 |5 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |2 |5 |0 |
|
||||
| u0_wrsoft_n |cdc_sync |2 |5 |0 |
|
||||
| u_data_prebuffer |data_prebuffer |1538 |1391 |118 |
|
||||
| u_data_prebuffer |data_prebuffer |1539 |1391 |118 |
|
||||
| channelPart |channel_part_8478 |865 |144 |8 |
|
||||
| fifo_adc |fifo_adc |112 |41 |4 |
|
||||
| ram_switch |ram_switch |60 |1023 |52 |
|
||||
|
|
@ -1475,9 +1475,9 @@ RUN-1001 : Exported congestions
|
|||
RUN-1001 : Exported violations
|
||||
RUN-1001 : Exported IO constraints
|
||||
RUN-1001 : Exported Inst constraints
|
||||
RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.046767s wall, 1.703125s user + 0.015625s system = 1.718750s CPU (164.2%)
|
||||
RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.150280s wall, 1.781250s user + 0.015625s system = 1.796875s CPU (156.2%)
|
||||
|
||||
RUN-1004 : used memory is 324 MB, reserved memory is 297 MB, peak memory is 398 MB
|
||||
RUN-1004 : used memory is 339 MB, reserved memory is 312 MB, peak memory is 399 MB
|
||||
RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
|
||||
RUN-1002 : start command "get_ports clock_source"
|
||||
RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
|
||||
|
|
@ -1673,12 +1673,12 @@ SYN-1016 : Merged 12104 instances.
|
|||
SYN-1032 : 36464/295 useful/useless nets, 33740/0 useful/useless insts
|
||||
RUN-1002 : start command "start_timer -prepack"
|
||||
TMR-2505 : Start building timing graph for model huagao_mipi_top.
|
||||
TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121626, tnet num: 36466, tinst num: 33740, tnode num: 155591, tedge num: 179075.
|
||||
TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121620, tnet num: 36466, tinst num: 33740, tnode num: 155576, tedge num: 179063.
|
||||
TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
|
||||
TMR-2501 : Timing graph initialized successfully.
|
||||
RUN-1003 : finish command "start_timer -prepack" in 1.250589s wall, 1.234375s user + 0.015625s system = 1.250000s CPU (100.0%)
|
||||
RUN-1003 : finish command "start_timer -prepack" in 1.483913s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (99.0%)
|
||||
|
||||
RUN-1004 : used memory is 515 MB, reserved memory is 494 MB, peak memory is 515 MB
|
||||
RUN-1004 : used memory is 518 MB, reserved memory is 495 MB, peak memory is 518 MB
|
||||
TMR-2503 : Start to update net delay, extr mode = 2.
|
||||
TMR-2504 : Update delay of 36466 nets completely.
|
||||
TMR-2502 : Annotate delay completely, extr mode = 2.
|
||||
|
|
@ -1689,11 +1689,11 @@ TMR-3501 : Forward propagation: start to calculate arrival time...
|
|||
TMR-3502 : Backward propagation: start to calculate required time...
|
||||
TMR-3503 : Timing propagation completes.
|
||||
SYN-3001 : Running gate level optimization.
|
||||
SYN-2581 : Mapping with K=5, #lut = 7522 (3.86), #lev = 9 (3.14)
|
||||
SYN-2581 : Mapping with K=5, #lut = 7519 (3.86), #lev = 10 (3.15)
|
||||
SYN-2551 : Post LUT mapping optimization.
|
||||
SYN-2581 : Mapping with K=5, #lut = 7440 (3.97), #lev = 7 (3.07)
|
||||
SYN-3001 : Logic optimization runtime opt = 1.25 sec, map = 0.00 sec
|
||||
SYN-3001 : Mapper mapped 18898 instances into 7468 LUTs, name keeping = 56%.
|
||||
SYN-2581 : Mapping with K=5, #lut = 7392 (3.95), #lev = 8 (3.06)
|
||||
SYN-3001 : Logic optimization runtime opt = 1.35 sec, map = 0.00 sec
|
||||
SYN-3001 : Mapper mapped 18898 instances into 7420 LUTs, name keeping = 59%.
|
||||
SYN-3001 : Mapper removed 2 lut buffers
|
||||
RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
|
||||
RUN-1001 : standard
|
||||
|
|
@ -1706,15 +1706,15 @@ IO Statistics
|
|||
#inout 0
|
||||
|
||||
LUT Statistics
|
||||
#Total_luts 10043
|
||||
#lut4 5250
|
||||
#lut5 2238
|
||||
#Total_luts 9995
|
||||
#lut4 5129
|
||||
#lut5 2311
|
||||
#lut6 0
|
||||
#lut5_mx41 0
|
||||
#lut4_alu1b 2555
|
||||
|
||||
Utilization Statistics
|
||||
#lut 10043 out of 19600 51.24%
|
||||
#lut 9995 out of 19600 50.99%
|
||||
#reg 9170 out of 19600 46.79%
|
||||
#le 0
|
||||
#dsp 3 out of 29 10.34%
|
||||
|
|
@ -1725,7 +1725,7 @@ Utilization Statistics
|
|||
#dram 16
|
||||
#pad 75 out of 130 57.69%
|
||||
#ireg 13
|
||||
#oreg 21
|
||||
#oreg 18
|
||||
#treg 0
|
||||
#pll 3 out of 4 75.00%
|
||||
|
||||
|
|
@ -1733,30 +1733,30 @@ Report Hierarchy Area:
|
|||
+-------------------------------------------------------------------------------------------------+
|
||||
|Instance |Module |lut |ripple |seq |bram |dsp |
|
||||
+-------------------------------------------------------------------------------------------------+
|
||||
|top |huagao_mipi_top |7488 |2555 |9204 |58 |3 |
|
||||
|top |huagao_mipi_top |7440 |2555 |9201 |58 |3 |
|
||||
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |339 |81 |441 |4 |1 |
|
||||
| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 |
|
||||
| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
|
||||
| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
|
||||
| exdev_ctl_a |exdev_ctl |287 |234 |559 |0 |0 |
|
||||
| u_ADconfig |AD_config |100 |49 |138 |0 |0 |
|
||||
| u_gen_sp |gen_sp |129 |185 |104 |0 |0 |
|
||||
| exdev_ctl_b |exdev_ctl |275 |234 |546 |0 |0 |
|
||||
| exdev_ctl_a |exdev_ctl |282 |234 |559 |0 |0 |
|
||||
| u_ADconfig |AD_config |99 |49 |138 |0 |0 |
|
||||
| u_gen_sp |gen_sp |125 |185 |104 |0 |0 |
|
||||
| exdev_ctl_b |exdev_ctl |279 |234 |546 |0 |0 |
|
||||
| u_ADconfig |AD_config |91 |49 |125 |0 |0 |
|
||||
| u_gen_sp |gen_sp |126 |185 |104 |0 |0 |
|
||||
| sampling_fe_a |sampling_fe |2108 |738 |1894 |25 |0 |
|
||||
| u_gen_sp |gen_sp |130 |185 |104 |0 |0 |
|
||||
| sampling_fe_a |sampling_fe |2067 |738 |1894 |25 |0 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_sort |sort |2038 |691 |1712 |25 |0 |
|
||||
| u_sort |sort |1997 |691 |1712 |25 |0 |
|
||||
| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_data_prebuffer |data_prebuffer |1909 |615 |1391 |22 |0 |
|
||||
| u_data_prebuffer |data_prebuffer |1868 |615 |1391 |22 |0 |
|
||||
| channelPart |channel_part_8478 |147 |11 |144 |0 |0 |
|
||||
| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
|
||||
| ram_switch |ram_switch |1483 |422 |1023 |0 |0 |
|
||||
| ram_switch |ram_switch |1448 |422 |1023 |0 |0 |
|
||||
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
|
||||
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
|
||||
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
|
|
@ -1768,10 +1768,10 @@ Report Hierarchy Area:
|
|||
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| insert |insert |265 |323 |692 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |1089 |0 |216 |0 |0 |
|
||||
| read_ram_i |read_ram |192 |158 |164 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr |161 |145 |127 |0 |0 |
|
||||
| read_ram_data |read_ram_data |30 |13 |32 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |1054 |0 |216 |0 |0 |
|
||||
| read_ram_i |read_ram |186 |158 |164 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr |158 |145 |127 |0 |0 |
|
||||
| read_ram_data |read_ram_data |27 |13 |32 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
|
|
@ -1798,19 +1798,19 @@ Report Hierarchy Area:
|
|||
| u_transfer_300_to_200 |transfer_300_to_200 |122 |76 |276 |3 |0 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
|
||||
| sampling_fe_b |sampling_fe_rev |2299 |751 |1958 |25 |1 |
|
||||
| sampling_fe_b |sampling_fe_rev |2261 |751 |1958 |25 |1 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_sort |sort_rev |2229 |704 |1776 |25 |1 |
|
||||
| u_sort |sort_rev |2191 |704 |1776 |25 |1 |
|
||||
| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_data_prebuffer_rev |data_prebuffer_rev |2104 |628 |1405 |22 |1 |
|
||||
| u_data_prebuffer_rev |data_prebuffer_rev |2066 |628 |1405 |22 |1 |
|
||||
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
|
||||
| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
|
||||
| ram_switch |ram_switch |1478 |422 |1023 |0 |0 |
|
||||
| ram_switch |ram_switch |1441 |422 |1023 |0 |0 |
|
||||
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
|
||||
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
|
||||
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
|
|
@ -1822,9 +1822,9 @@ Report Hierarchy Area:
|
|||
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| insert |insert |265 |323 |692 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |1084 |0 |216 |0 |0 |
|
||||
| read_ram_i |read_ram_rev |391 |171 |178 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr_rev |177 |145 |136 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |1047 |0 |216 |0 |0 |
|
||||
| read_ram_i |read_ram_rev |390 |171 |178 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr_rev |176 |145 |136 |0 |0 |
|
||||
| read_ram_data |read_ram_data_rev |214 |26 |42 |0 |0 |
|
||||
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
|
|
@ -1849,9 +1849,9 @@ SYN-4007 : Packing 0 gate4 to BLE ...
|
|||
SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
|
||||
SYN-4012 : Packed 0 FxMUX
|
||||
SYN-4013 : Packed 16 DRAM and 4 SEQ.
|
||||
RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 54.425753s wall, 54.062500s user + 0.343750s system = 54.406250s CPU (100.0%)
|
||||
RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 63.896196s wall, 63.531250s user + 0.296875s system = 63.828125s CPU (99.9%)
|
||||
|
||||
RUN-1004 : used memory is 396 MB, reserved memory is 390 MB, peak memory is 698 MB
|
||||
RUN-1004 : used memory is 395 MB, reserved memory is 386 MB, peak memory is 698 MB
|
||||
RUN-1002 : start command "legalize_phy_inst"
|
||||
SYN-1011 : Flatten model huagao_mipi_top
|
||||
SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
|
||||
|
|
@ -1871,8 +1871,8 @@ RUN-1001 : Exported violations
|
|||
RUN-1001 : Exported timing constraints
|
||||
RUN-1001 : Exported IO constraints
|
||||
RUN-1001 : Exported Inst constraints
|
||||
RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.531390s wall, 2.640625s user + 0.031250s system = 2.671875s CPU (174.5%)
|
||||
RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.634628s wall, 2.843750s user + 0.031250s system = 2.875000s CPU (175.9%)
|
||||
|
||||
RUN-1004 : used memory is 403 MB, reserved memory is 389 MB, peak memory is 698 MB
|
||||
RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240123_141559.log"
|
||||
RUN-1004 : used memory is 401 MB, reserved memory is 385 MB, peak memory is 698 MB
|
||||
RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240218_161055.log"
|
||||
RUN-1001 : Backing up run's log file succeed.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,101 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.6.71036
|
||||
Copyright (c) 2012-2023 Anlogic Inc.
|
||||
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
|
||||
Built at = 20:34:38 Mar 21 2023
|
||||
Run by = holdtecs
|
||||
Run Date = Fri Feb 2 10:29:15 2024
|
||||
|
||||
Run on = DESKTOP-5MQL5VE
|
||||
============================================================
|
||||
RUN-1001 : open_run phy_1.
|
||||
RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
|
||||
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
|
||||
RUN-1001 : Database version number 46146.
|
||||
RUN-1001 : Import flow parameters
|
||||
PHY-1001 : Generate detailed routing grids ...
|
||||
PHY-1001 : Generate nets ...
|
||||
PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||
PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||
PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
|
||||
PHY-5010 Similar messages will be suppressed.
|
||||
PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
|
||||
PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
|
||||
PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
|
||||
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
|
||||
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
|
||||
PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
|
||||
PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
|
||||
PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
|
||||
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
|
||||
PHY-1001 : eco open net = 0
|
||||
PHY-1001 : 675 feed throughs used by 490 nets
|
||||
RUN-1001 : Import timing constraints
|
||||
RUN-1001 : Import IO constraints
|
||||
RUN-1001 : Import Inst constraints
|
||||
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
|
||||
RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 11.838351s wall, 11.718750s user + 0.156250s system = 11.875000s CPU (100.3%)
|
||||
|
||||
RUN-1004 : used memory is 972 MB, reserved memory is 933 MB, peak memory is 984 MB
|
||||
TMR-3509 : Import timing summary.
|
||||
TMR-3509 : Import timing summary.
|
||||
RUN-1001 : reset_run syn_1 phy_1.
|
||||
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
|
||||
RUN-1001 : syn_1: run complete.
|
||||
RUN-1001 : phy_1: run complete.
|
||||
RUN-1001 : open_run phy_1.
|
||||
RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
|
||||
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
|
||||
RUN-1001 : Database version number 46146.
|
||||
RUN-1001 : Import flow parameters
|
||||
PHY-1001 : Generate detailed routing grids ...
|
||||
PHY-1001 : Generate nets ...
|
||||
PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||
PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||
PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
|
||||
PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
|
||||
PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
|
||||
PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
|
||||
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
|
||||
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
|
||||
PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
|
||||
PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
|
||||
PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
|
||||
PHY-5010 Similar messages will be suppressed.
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
|
||||
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
|
||||
PHY-1001 : eco open net = 0
|
||||
PHY-1001 : 716 feed throughs used by 509 nets
|
||||
RUN-1001 : Import timing constraints
|
||||
RUN-1001 : Import IO constraints
|
||||
RUN-1001 : Import Inst constraints
|
||||
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
|
||||
RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 11.062847s wall, 10.437500s user + 1.046875s system = 11.484375s CPU (103.8%)
|
||||
|
||||
RUN-1004 : used memory is 956 MB, reserved memory is 980 MB, peak memory is 993 MB
|
||||
TMR-3509 : Import timing summary.
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.6.71036
|
||||
Copyright (c) 2012-2023 Anlogic Inc.
|
||||
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
|
||||
Built at = 20:34:38 Mar 21 2023
|
||||
Run by = holdtecs
|
||||
Run Date = Sun Feb 18 14:50:36 2024
|
||||
|
||||
Run on = DESKTOP-5MQL5VE
|
||||
============================================================
|
||||
PRG-9500 ERROR: USB Error: read data failed
|
||||
|
||||
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
|
||||
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
|
||||
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
|
||||
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
|
||||
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
|
||||
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
|
||||
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
|
||||
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
|
||||
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
|
||||
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
|
||||
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
|
||||
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
|
||||
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
|
||||
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
|
||||
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
|
||||
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
|
||||
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
|
||||
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
|
||||
PRG-9505 ERROR: USB device open error, please re-connect the USB cable!
|
||||
|
|
@ -0,0 +1,205 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.6.71036
|
||||
Copyright (c) 2012-2023 Anlogic Inc.
|
||||
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
|
||||
Built at = 20:34:38 Mar 21 2023
|
||||
Run by = holdtecs
|
||||
Run Date = Mon Jan 22 16:49:52 2024
|
||||
|
||||
Run on = DESKTOP-5MQL5VE
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "open_project hg_anlogic.al -update"
|
||||
RUN-1001 : Print Global Property
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : message | standard | standard |
|
||||
RUN-1001 : mixed_pack_place_flow | on | on |
|
||||
RUN-1001 : qor_monitor | off | off |
|
||||
RUN-1001 : syn_ip_flow | off | off |
|
||||
RUN-1001 : thread | auto | auto |
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : default_reg_initial | auto | auto |
|
||||
RUN-1001 : infer_add | on | on |
|
||||
RUN-1001 : infer_fsm | off | off |
|
||||
RUN-1001 : infer_mult | on | on |
|
||||
RUN-1001 : infer_ram | on | on |
|
||||
RUN-1001 : infer_reg | on | on |
|
||||
RUN-1001 : infer_reg_init_value | on | on |
|
||||
RUN-1001 : infer_rom | on | on |
|
||||
RUN-1001 : infer_shifter | on | on |
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple |
|
||||
RUN-1001 : elf_sload | off | off |
|
||||
RUN-1001 : fix_undriven | 0 | 0 |
|
||||
RUN-1001 : flatten | off | off |
|
||||
RUN-1001 : gate_sharing | on | on |
|
||||
RUN-1001 : hdl_warning_level | normal | normal |
|
||||
RUN-1001 : impl_internal_tribuf | on | on |
|
||||
RUN-1001 : impl_set_reset | on | on |
|
||||
RUN-1001 : infer_gsr | off | off |
|
||||
RUN-1001 : keep_hierarchy | auto | auto |
|
||||
RUN-1001 : max_fanout | 9999 | 9999 |
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10 |
|
||||
RUN-1001 : merge_equal | on | on |
|
||||
RUN-1001 : merge_equiv | on | on |
|
||||
RUN-1001 : merge_mux | off | off |
|
||||
RUN-1001 : min_control_set | 8 | 8 |
|
||||
RUN-1001 : min_ripple_len | auto | auto |
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
|
||||
RUN-1001 : opt_adder_fanout | on | on |
|
||||
RUN-1001 : opt_arith | on | on |
|
||||
RUN-1001 : opt_big_gate | off | off |
|
||||
RUN-1001 : opt_const | on | on |
|
||||
RUN-1001 : opt_const_mult | on | on |
|
||||
RUN-1001 : opt_lessthan | on | on |
|
||||
RUN-1001 : opt_mux | off | off |
|
||||
RUN-1001 : opt_ram | high | high |
|
||||
RUN-1001 : rtl_sim_model | off | off |
|
||||
RUN-1001 : seq_syn | on | on |
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll/pll.v
|
||||
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll/pll.v(99)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
|
||||
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/cdc/cdc_sync.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/ad_sampling.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/exdev_ctl.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/fan_ctrl.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/gen_sp.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe_rev.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
|
||||
HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(397)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/wrdpram_ctl.v
|
||||
HDL-1007 : undeclared symbol 'neg_dval_i', assumed default net type 'wire' in ../../hg_mp/fe/wrdpram_ctl.v(375)
|
||||
HDL-5007 WARNING: parameter 'DPI300_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(24)
|
||||
HDL-5007 WARNING: parameter 'DPI600_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(25)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/local_bus/CRC4_D16.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/local_bus/local_bus_slve_cis.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/pixel_cdc/pixel_cdc.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/scan_start/scan_start_diff.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/sensor_lane/lscc_sensor.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
|
||||
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
|
||||
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
|
||||
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
|
||||
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
|
||||
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
|
||||
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
|
||||
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
|
||||
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(732)
|
||||
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(734)
|
||||
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(740)
|
||||
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(743)
|
||||
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
|
||||
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1001)
|
||||
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1301)
|
||||
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1312)
|
||||
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1510)
|
||||
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1906)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
|
||||
Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
|
||||
This product includes software developed by the OpenSSL Project
|
||||
for use in the OpenSSL Toolkit (http://www.openssl.org/)
|
||||
Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
|
||||
All rights reserved.
|
||||
This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
|
||||
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
|
||||
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
|
||||
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/AD_config.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/crc16_24b.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/ecc_gen.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
|
||||
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
|
||||
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_hs_generate.v
|
||||
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
|
||||
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lp_generate.v
|
||||
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/lvds_rx/lvds_rx_enc.v
|
||||
HDL-1007 : back to file '../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/transfer_300_to_200.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(35)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(91)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(113)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/ch_addr_gen.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/fifo_adc.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/insert.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(73)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(79)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/link_line.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/link_line.v(20)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/mapping.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_e.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/mux_e.v(16)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_i.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
|
||||
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(206)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr.v
|
||||
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(42)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(42)
|
||||
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(57)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(57)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(122)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
|
||||
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(205)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data_rev.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_rev.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr_rev.v
|
||||
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(44)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(44)
|
||||
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(59)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(59)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(139)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/local_bus/uart_2dsp_6M_921600.v
|
||||
RUN-1001 : Project manager successfully analyzed 63 source files.
|
||||
RUN-1003 : finish command "open_project hg_anlogic.al -update" in 1.017002s wall, 0.468750s user + 0.390625s system = 0.859375s CPU (84.5%)
|
||||
|
||||
RUN-1004 : used memory is 107 MB, reserved memory is 67 MB, peak memory is 107 MB
|
||||
RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
|
||||
ARC-1001 : done | P10 | gpio
|
||||
ARC-1001 : program_b | P134 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.6.71036
|
||||
Copyright (c) 2012-2023 Anlogic Inc.
|
||||
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
|
||||
Built at = 20:34:38 Mar 21 2023
|
||||
Run by = holdtecs
|
||||
Run Date = Wed Jan 24 15:01:36 2024
|
||||
|
||||
Run on = DESKTOP-5MQL5VE
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.6.71036
|
||||
Copyright (c) 2012-2023 Anlogic Inc.
|
||||
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
|
||||
Built at = 20:34:38 Mar 21 2023
|
||||
Run by = holdtecs
|
||||
Run Date = Wed Jan 24 15:01:43 2024
|
||||
|
||||
Run on = DESKTOP-5MQL5VE
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
GUI-2000 : The IP files have been created successfully :{EG4D20EG176(D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/hg_mp/anlogic_ip/pll_lvds/pll_lvds.ipc)}
|
||||
|
|
@ -0,0 +1,210 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.6.71036
|
||||
Copyright (c) 2012-2023 Anlogic Inc.
|
||||
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
|
||||
Built at = 20:34:38 Mar 21 2023
|
||||
Run by = holdtecs
|
||||
Run Date = Sun Feb 18 14:50:34 2024
|
||||
|
||||
Run on = DESKTOP-5MQL5VE
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "open_project hg_anlogic.al -update"
|
||||
RUN-1001 : Print Global Property
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : message | standard | standard |
|
||||
RUN-1001 : mixed_pack_place_flow | on | on |
|
||||
RUN-1001 : qor_monitor | off | off |
|
||||
RUN-1001 : syn_ip_flow | off | off |
|
||||
RUN-1001 : thread | auto | auto |
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : default_reg_initial | auto | auto |
|
||||
RUN-1001 : infer_add | on | on |
|
||||
RUN-1001 : infer_fsm | off | off |
|
||||
RUN-1001 : infer_mult | on | on |
|
||||
RUN-1001 : infer_ram | on | on |
|
||||
RUN-1001 : infer_reg | on | on |
|
||||
RUN-1001 : infer_reg_init_value | on | on |
|
||||
RUN-1001 : infer_rom | on | on |
|
||||
RUN-1001 : infer_shifter | on | on |
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple |
|
||||
RUN-1001 : elf_sload | off | off |
|
||||
RUN-1001 : fix_undriven | 0 | 0 |
|
||||
RUN-1001 : flatten | off | off |
|
||||
RUN-1001 : gate_sharing | on | on |
|
||||
RUN-1001 : hdl_warning_level | normal | normal |
|
||||
RUN-1001 : impl_internal_tribuf | on | on |
|
||||
RUN-1001 : impl_set_reset | on | on |
|
||||
RUN-1001 : infer_gsr | off | off |
|
||||
RUN-1001 : keep_hierarchy | auto | auto |
|
||||
RUN-1001 : max_fanout | 9999 | 9999 |
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10 |
|
||||
RUN-1001 : merge_equal | on | on |
|
||||
RUN-1001 : merge_equiv | on | on |
|
||||
RUN-1001 : merge_mux | off | off |
|
||||
RUN-1001 : min_control_set | 8 | 8 |
|
||||
RUN-1001 : min_ripple_len | auto | auto |
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
|
||||
RUN-1001 : opt_adder_fanout | on | on |
|
||||
RUN-1001 : opt_arith | on | on |
|
||||
RUN-1001 : opt_big_gate | off | off |
|
||||
RUN-1001 : opt_const | on | on |
|
||||
RUN-1001 : opt_const_mult | on | on |
|
||||
RUN-1001 : opt_lessthan | on | on |
|
||||
RUN-1001 : opt_mux | off | off |
|
||||
RUN-1001 : opt_ram | high | high |
|
||||
RUN-1001 : rtl_sim_model | off | off |
|
||||
RUN-1001 : seq_syn | on | on |
|
||||
RUN-1001 : --------------------------------------------------------------
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll/pll.v
|
||||
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll/pll.v(99)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
|
||||
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/cdc/cdc_sync.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/ad_sampling.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/exdev_ctl.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/fan_ctrl.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/gen_sp.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
|
||||
HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
|
||||
HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe_rev.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
|
||||
HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(399)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/wrdpram_ctl.v
|
||||
HDL-1007 : undeclared symbol 'neg_dval_i', assumed default net type 'wire' in ../../hg_mp/fe/wrdpram_ctl.v(375)
|
||||
HDL-5007 WARNING: parameter 'DPI300_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(24)
|
||||
HDL-5007 WARNING: parameter 'DPI600_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(25)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/local_bus/CRC4_D16.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/local_bus/local_bus_slve_cis.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/pixel_cdc/pixel_cdc.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/scan_start/scan_start_diff.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/sensor_lane/lscc_sensor.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
|
||||
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
|
||||
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
|
||||
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
|
||||
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
|
||||
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
|
||||
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
|
||||
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
|
||||
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
|
||||
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
|
||||
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
|
||||
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
|
||||
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
|
||||
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
|
||||
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
|
||||
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
|
||||
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1332)
|
||||
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
|
||||
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
|
||||
Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
|
||||
This product includes software developed by the OpenSSL Project
|
||||
for use in the OpenSSL Toolkit (http://www.openssl.org/)
|
||||
Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
|
||||
All rights reserved.
|
||||
This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
|
||||
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
|
||||
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
|
||||
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/AD_config.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/crc16_24b.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/ecc_gen.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
|
||||
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
|
||||
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_hs_generate.v
|
||||
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
|
||||
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lp_generate.v
|
||||
HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/lvds_rx/lvds_rx_enc.v
|
||||
HDL-1007 : back to file '../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/transfer_300_to_200.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(40)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(98)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(123)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/ch_addr_gen.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/fifo_adc.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/insert.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(77)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(83)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/link_line.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/link_line.v(20)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/mapping.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_e.v
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/mux_e.v(16)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_i.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
|
||||
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(211)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr.v
|
||||
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(42)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(42)
|
||||
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(57)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(57)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(122)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
|
||||
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(213)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data_rev.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_rev.v
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr_rev.v
|
||||
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(44)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(44)
|
||||
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(59)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(59)
|
||||
HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(139)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/local_bus/uart_2dsp_6M_921600.v
|
||||
HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
|
||||
HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
|
||||
RUN-1001 : Project manager successfully analyzed 63 source files.
|
||||
RUN-1003 : finish command "open_project hg_anlogic.al -update" in 1.567662s wall, 0.328125s user + 0.265625s system = 0.593750s CPU (37.9%)
|
||||
|
||||
RUN-1004 : used memory is 109 MB, reserved memory is 68 MB, peak memory is 109 MB
|
||||
RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
|
||||
ARC-1001 : done | P10 | gpio
|
||||
ARC-1001 : program_b | P134 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
Loading…
Reference in New Issue