更新sdc
This commit is contained in:
17828169534
parent
9287a41110
commit
c51f01e204
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@ -349,7 +349,7 @@ wire O_clk_lp_p_sync;
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wire O_clk_lp_n_sync;
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wire O_clk_lp_n_sync;
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cdc_sync # (
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cdc_sync # (
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.DEPTH (20),
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.DEPTH (20),
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.WIDTH (13)
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.WIDTH (1)
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) u_O_clk_lp_p( /* synthesis keep_hierarchy=true */
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) u_O_clk_lp_p( /* synthesis keep_hierarchy=true */
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.to_clk (clk_ubus ),
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.to_clk (clk_ubus ),
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.rest_n (rst_n ),
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.rest_n (rst_n ),
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@ -359,7 +359,7 @@ cdc_sync # (
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cdc_sync # (
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cdc_sync # (
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.DEPTH (20),
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.DEPTH (20),
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.WIDTH (13)
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.WIDTH (1)
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) u_O_clk_lp_n( /* synthesis keep_hierarchy=true */
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) u_O_clk_lp_n( /* synthesis keep_hierarchy=true */
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.to_clk (clk_ubus ),
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.to_clk (clk_ubus ),
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.rest_n (rst_n ),
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.rest_n (rst_n ),
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@ -565,6 +565,17 @@ reg frame_start_sync_d2_a/* synthesis syn_preserve=1 */;
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reg BUSY_MIPI_sync_d0;//synthesis keep
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reg BUSY_MIPI_sync_d0;//synthesis keep
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reg BUSY_MIPI_sync_d1;//synthesis keep
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reg BUSY_MIPI_sync_d1;//synthesis keep
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wire BUSY_MIPI_sync;
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cdc_sync # (
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.DEPTH (13),
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.WIDTH (1)
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) u1_BUSY_MIPI (
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.to_clk (clk_ubus ),
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.rest_n (rst_n ),
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.signal_from(BUSY_MIPI ),
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.signal_to (BUSY_MIPI_sync)
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);
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always @ (posedge clk_ubus ) begin
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always @ (posedge clk_ubus ) begin
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if (~rst_n) begin
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if (~rst_n) begin
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@ -576,7 +587,7 @@ always @ (posedge clk_ubus ) begin
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BUSY_MIPI_sync_d1 <= 1'b0;
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BUSY_MIPI_sync_d1 <= 1'b0;
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end
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end
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else begin
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else begin
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BUSY_MIPI_sync_d0 <= BUSY_MIPI;
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BUSY_MIPI_sync_d0 <= BUSY_MIPI_sync;
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BUSY_MIPI_sync_d1 <= BUSY_MIPI_sync_d0;
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BUSY_MIPI_sync_d1 <= BUSY_MIPI_sync_d0;
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end
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end
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end
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end
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@ -1717,8 +1728,8 @@ always @(*) begin
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end
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end
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assign debug[0] = a_vs ;
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assign debug[0] = a_vs ;
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assign debug[1] = debug_1[3];
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assign debug[1] = BUSY_MIPI;
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assign debug[2] = debug_1[2] ;
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assign debug[2] = BUSY_MIPI_sync ;
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assign debug[3] = debug_1[1];
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assign debug[3] = debug_1[1];
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assign debug[4] = debug_1[0] ;
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assign debug[4] = debug_1[0] ;
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assign debug[5] = FV_MIPI ;
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assign debug[5] = FV_MIPI ;
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@ -10,25 +10,22 @@ create_generated_clock -name S_clk_x4 -source [get_pins {u_pll/pll_inst.clkc[0]}
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create_generated_clock -name S_clk_x4_90d -source [get_pins {u_pll/pll_inst.clkc[0]}] -master_clock {S_clk} -phase 90 -multiply_by 4 -duty_cycle 0.5 [get_pins {u_pll/pll_inst.clkc[3]}]
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create_generated_clock -name S_clk_x4_90d -source [get_pins {u_pll/pll_inst.clkc[0]}] -master_clock {S_clk} -phase 90 -multiply_by 4 -duty_cycle 0.5 [get_pins {u_pll/pll_inst.clkc[3]}]
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create_generated_clock -name a_sclk -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -edges {1 2 3} -edge_shift {0 -7.441 -14.881} [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
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create_generated_clock -name a_sclk -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -edges {1 2 3} -edge_shift {0 -7.441 -14.881} [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
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create_generated_clock -name b_sclk -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -edges {1 2 3} -edge_shift {0 -7.441 -14.881} [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
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create_generated_clock -name b_sclk -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -edges {1 2 3} -edge_shift {0 -7.441 -14.881} [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
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set_false_path -from [get_nets {u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clka_mipi_total_num/temp[*]}]
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#set_false_path -from [get_nets {u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clka_mipi_total_num/temp[*]}]
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set_false_path -from [get_nets {u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clkb_mipi_total_num/temp[*]}]
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#set_false_path -from [get_nets {u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clkb_mipi_total_num/temp[*]}]
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set_false_path -from [get_nets {u_pixel_cdc/u_clka_cis_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clka_cis_total_num/temp[*]}]
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#set_false_path -from [get_nets {u_pixel_cdc/u_clka_cis_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clka_cis_total_num/temp[*]}]
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set_false_path -from [get_nets {u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clkb_cis_total_num/temp[*]}]
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#set_false_path -from [get_nets {u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clkb_cis_total_num/temp[*]}]
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set_false_path -from [get_nets {u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clk_cis_pixel_y/temp[*]}]
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#set_false_path -from [get_nets {u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clk_cis_pixel_y/temp[*]}]
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set_false_path -from [get_nets {u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]}]
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#set_false_path -from [get_nets {u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]}]
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set_false_path -from [get_nets {u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clk_cis_frame_num/temp[*]}]
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#set_false_path -from [get_nets {u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clk_cis_frame_num/temp[*]}]
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#set_input_delay -clock [get_clocks {clock_source}] 12.5 [get_ports {a_ad_sdi b_ad_sdi clock_source global_reset_n gpio_trigger onoff_in paper_in rxd_dsp scan_in}]
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#set_input_delay -clock [get_clocks {clock_source}] 12.5 [get_ports {a_ad_sdi b_ad_sdi clock_source global_reset_n gpio_trigger onoff_in paper_in rxd_dsp scan_in}]
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#set_input_delay -clock [get_clocks {a_lvds_clk_p}] 6.25 [get_ports {a_lvds_clk_p a_lvds_data_p a_lvds_data_p[0] a_lvds_data_p[1] a_lvds_data_p[2] a_lvds_data_p[3] a_lvds_data_p[4]}]
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#set_input_delay -clock [get_clocks {a_lvds_clk_p}] 6.25 [get_ports {a_lvds_clk_p a_lvds_data_p a_lvds_data_p[0] a_lvds_data_p[1] a_lvds_data_p[2] a_lvds_data_p[3] a_lvds_data_p[4]}]
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#set_input_delay -clock [get_clocks {b_lvds_clk_p}] 6.25 [get_ports {b_lvds_clk_p b_lvds_data_p b_lvds_data_p[0] b_lvds_data_p[1] b_lvds_data_p[2] b_lvds_data_p[3] b_lvds_data_p[4]}]
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#set_input_delay -clock [get_clocks {b_lvds_clk_p}] 6.25 [get_ports {b_lvds_clk_p b_lvds_data_p b_lvds_data_p[0] b_lvds_data_p[1] b_lvds_data_p[2] b_lvds_data_p[3] b_lvds_data_p[4]}]
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set_false_path -setup -from [get_pins {u_pll/pll_inst.clkc[3]}] -to [get_nets {u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d}]
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#set_false_path -setup -from [get_pins {u_pll/pll_inst.clkc[3]}] -to [get_nets {u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d}]
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set_false_path -setup -from [get_pins {u_pll/pll_inst.clkc[1]}] -to [get_nets {u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2}]
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#set_false_path -setup -from [get_pins {u_pll/pll_inst.clkc[1]}] -to [get_nets {u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2}]
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#create_generated_clock -name clk_adc -source [get_ports {clock_source}] -master_clock {clock_source} -edges {1 2 3} -edge_shift {0 -6.944 -13.889} [get_pins {u_pll/pll_inst.clkc[4]}]
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#create_generated_clock -name clk_adc -source [get_ports {clock_source}] -master_clock {clock_source} -edges {1 2 3} -edge_shift {0 -6.944 -13.889} [get_pins {u_pll/pll_inst.clkc[4]}]
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#set_false_path -setup -from [get_regs{u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5}] -to [get_regs {sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[41]_syn_8}]
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create_generated_clock -name clk_adc -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4 -phase 0 [get_pins {u_pll/pll_inst.clkc[4]}]
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create_generated_clock -name clk_adc -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4 -phase 0 [get_pins {u_pll/pll_inst.clkc[4]}]
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set_false_path -from [get_regs {BUSY_MIPI}] -to [get_regs {BUSY_MIPI_sync_d0}]
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#set_false_path -from [get_nets {u1_BUSY_MIPI/signal_from[*]}] -to [get_regs {u1_BUSY_MIPI/temp[*]}]
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set_false_path -from [get_regs {clkubus_rstn}] -to [get_nets {a_pclk_rstn}]
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#set_false_path -from [get_regs {clkubus_rstn}] -to [get_nets {a_pclk_rstn}]
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set_false_path -from [get_regs {clkubus_rstn}] -to [get_nets {b_pclk_rstn}]
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#set_false_path -from [get_regs {clkubus_rstn}] -to [get_nets {b_pclk_rstn}]
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#set_false_path -from [get_nets {u_bus_top/start_sp_a_tmp[*]}] -to [get_regs {u_bus_top/start_sp_a_sync1d_48m[*]}]
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#set_false_path -from [get_nets {u_bus_top/start_sp_b_tmp[*]}] -to [get_regs {u_bus_top/start_sp_b_sync1d_48m[*]}]
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set_false_path -from [get_nets {u_O_clk_lp_p/signal_from[*]}] -to [get_regs {u_O_clk_lp_p/temp[*]}]
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set_false_path -from [get_nets {u_O_clk_lp_p/signal_from[*]}] -to [get_regs {u_O_clk_lp_p/temp[*]}]
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set_false_path -from [get_nets {u_O_clk_lp_n/signal_from[*]}] -to [get_regs {u_O_clk_lp_n/temp[*]}]
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set_false_path -from [get_nets {u_O_clk_lp_n/signal_from[*]}] -to [get_regs {u_O_clk_lp_n/temp[*]}]
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
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File diff suppressed because it is too large
Load Diff
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@ -1,5 +1,5 @@
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<?xml version="1.0"?>
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<?xml version="1.0"?>
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<ProcessHandle Version="1" Minor="0">
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<ProcessHandle Version="1" Minor="0">
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<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="9868">
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<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="14768">
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</Process>
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</Process>
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</ProcessHandle>
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</ProcessHandle>
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@ -1,5 +1,5 @@
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<?xml version="1.0"?>
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<?xml version="1.0"?>
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<ProcessHandle Version="1" Minor="0">
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<ProcessHandle Version="1" Minor="0">
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<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="9868">
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<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="14768">
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</Process>
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</Process>
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</ProcessHandle>
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</ProcessHandle>
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@ -1,5 +1,5 @@
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<?xml version="1.0"?>
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<?xml version="1.0"?>
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<ProcessHandle Version="1" Minor="0">
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<ProcessHandle Version="1" Minor="0">
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<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="9868">
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<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="14768">
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</Process>
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</Process>
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</ProcessHandle>
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</ProcessHandle>
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Binary file not shown.
Binary file not shown.
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@ -1,5 +1,5 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<?xml version="1.0" encoding="UTF-8"?>
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<Project Version="3" Minor="2" RunTime="2024-03-12T14:50:44.847119">
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<Project Version="3" Minor="2" RunTime="2024-03-12T16:38:37.989622">
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<Project_Created_Time></Project_Created_Time>
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<Project_Created_Time></Project_Created_Time>
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<TD_Encoding>UTF-8</TD_Encoding>
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<TD_Encoding>UTF-8</TD_Encoding>
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<TD_Version>5.6.71036</TD_Version>
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<TD_Version>5.6.71036</TD_Version>
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Binary file not shown.
Binary file not shown.
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@ -8,12 +8,12 @@ IO Statistics
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#inout 0
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#inout 0
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Utilization Statistics
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Utilization Statistics
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#lut 10421 out of 19600 53.17%
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#lut 10230 out of 19600 52.19%
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#reg 9955 out of 19600 50.79%
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#reg 9451 out of 19600 48.22%
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#le 13076
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#le 12649
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#lut only 3121 out of 13076 23.87%
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#lut only 3198 out of 12649 25.28%
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#reg only 2655 out of 13076 20.30%
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#reg only 2419 out of 12649 19.12%
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#lut® 7300 out of 13076 55.83%
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#lut® 7032 out of 12649 55.59%
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#dsp 3 out of 29 10.34%
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#dsp 3 out of 29 10.34%
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#bram 54 out of 64 84.38%
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#bram 54 out of 64 84.38%
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#bram9k 50
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#bram9k 50
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@ -21,24 +21,24 @@ Utilization Statistics
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#bram32k 4 out of 16 25.00%
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#bram32k 4 out of 16 25.00%
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#pad 75 out of 130 57.69%
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#pad 75 out of 130 57.69%
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#ireg 13
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#ireg 13
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#oreg 19
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#oreg 21
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#treg 0
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#treg 0
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#pll 3 out of 4 75.00%
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#pll 3 out of 4 75.00%
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#gclk 6 out of 16 37.50%
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#gclk 6 out of 16 37.50%
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Clock Resource Statistics
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Clock Resource Statistics
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Index ClockNet Type DriverType Driver Fanout
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Index ClockNet Type DriverType Driver Fanout
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#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1825
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#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1798
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#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1432
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#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1415
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#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1342
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#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1345
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#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 1235
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#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 989
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#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 140
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#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 141
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#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 71
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#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 72
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#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70
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#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70
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#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
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#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
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#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
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#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
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#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_mipi_eot_min/reg1_syn_299.f1 3
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#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_272.f1 3
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#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg45_syn_163.f0 3
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#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_b/en_adc_cfg_all_d1_reg_syn_8.f1 2
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#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
|
#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
|
||||||
#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
|
#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
|
||||||
#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
|
#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
|
||||||
|
|
@ -77,7 +77,7 @@ Detailed IO Report
|
||||||
clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
|
clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
|
||||||
global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
|
global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
|
||||||
onoff_in INPUT P141 LVCMOS33 N/A N/A NONE
|
onoff_in INPUT P141 LVCMOS33 N/A N/A NONE
|
||||||
paper_in INPUT P16 LVCMOS25 N/A N/A NONE
|
paper_in INPUT P17 LVCMOS25 N/A N/A NONE
|
||||||
rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
|
rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
|
||||||
O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
|
O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
|
||||||
O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
|
O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
|
||||||
|
|
@ -103,7 +103,7 @@ Detailed IO Report
|
||||||
a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
|
a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
|
||||||
a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
|
a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
|
||||||
a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
|
a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
|
||||||
a_sp_sampling OUTPUT P25 LVCMOS25 8 N/A OREG
|
a_sp_sampling OUTPUT P133 LVCMOS33 8 N/A OREG
|
||||||
b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
|
b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
|
||||||
b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
|
b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
|
||||||
b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
|
b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
|
||||||
|
|
@ -113,114 +113,59 @@ Detailed IO Report
|
||||||
debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
|
debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
|
||||||
debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
|
debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
|
||||||
debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
|
debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
|
||||||
debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
|
debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
|
||||||
debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
|
debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
|
||||||
debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
|
debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
|
||||||
fan_pwm OUTPUT P139 LVCMOS33 8 N/A NONE
|
fan_pwm OUTPUT P143 LVCMOS33 8 N/A NONE
|
||||||
frame_indicator OUTPUT P107 LVCMOS25 8 N/A OREG
|
frame_indicator OUTPUT P107 LVCMOS25 8 N/A OREG
|
||||||
onoff_out OUTPUT P111 LVCMOS25 8 N/A NONE
|
onoff_out OUTPUT P118 LVCMOS25 8 N/A NONE
|
||||||
paper_out OUTPUT P106 LVCMOS25 8 N/A NONE
|
paper_out OUTPUT P106 LVCMOS25 8 N/A NONE
|
||||||
scan_out OUTPUT P84 LVCMOS25 8 N/A NONE
|
scan_out OUTPUT P91 LVCMOS25 8 N/A NONE
|
||||||
sys_initial_done OUTPUT P71 LVCMOS25 8 N/A NONE
|
sys_initial_done OUTPUT P83 LVCMOS25 8 N/A NONE
|
||||||
txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
|
txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
|
||||||
|
|
||||||
Report Hierarchy Area:
|
Report Hierarchy Area:
|
||||||
+---------------------------------------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------------------------------------+
|
||||||
|Instance |Module |le |lut |ripple |seq |bram |dsp |
|
|Instance |Module |le |lut |ripple |seq |bram |dsp |
|
||||||
+---------------------------------------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------------------------------------+
|
||||||
|top |huagao_mipi_top |13076 |9394 |1027 |9987 |58 |3 |
|
|top |huagao_mipi_top |12649 |9203 |1027 |9485 |58 |3 |
|
||||||
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |544 |438 |23 |443 |4 |1 |
|
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |559 |475 |23 |441 |4 |1 |
|
||||||
| U_fifo_w32_d8192 |fifo_w32_d8192 |100 |80 |4 |87 |4 |0 |
|
| U_fifo_w32_d8192 |fifo_w32_d8192 |104 |89 |4 |90 |4 |0 |
|
||||||
| U_crc16_24b |crc16_24b |35 |35 |0 |24 |0 |0 |
|
| U_crc16_24b |crc16_24b |52 |52 |0 |23 |0 |0 |
|
||||||
| U_ecc_gen |ecc_gen |8 |8 |0 |6 |0 |0 |
|
| U_ecc_gen |ecc_gen |9 |9 |0 |8 |0 |0 |
|
||||||
| exdev_ctl_a |exdev_ctl |779 |386 |96 |580 |0 |0 |
|
| exdev_ctl_a |exdev_ctl |761 |324 |96 |573 |0 |0 |
|
||||||
| u_ADconfig |AD_config |204 |138 |25 |151 |0 |0 |
|
| u_ADconfig |AD_config |189 |120 |25 |143 |0 |0 |
|
||||||
| u_gen_sp |gen_sp |263 |160 |71 |117 |0 |0 |
|
| u_gen_sp |gen_sp |265 |152 |71 |123 |0 |0 |
|
||||||
| exdev_ctl_b |exdev_ctl |739 |378 |96 |562 |0 |0 |
|
| exdev_ctl_b |exdev_ctl |766 |382 |96 |571 |0 |0 |
|
||||||
| u_ADconfig |AD_config |167 |122 |25 |125 |0 |0 |
|
| u_ADconfig |AD_config |184 |125 |25 |132 |0 |0 |
|
||||||
| u_gen_sp |gen_sp |255 |147 |71 |120 |0 |0 |
|
| u_gen_sp |gen_sp |262 |156 |71 |119 |0 |0 |
|
||||||
| sampling_fe_a |sampling_fe |3214 |2625 |306 |2077 |25 |0 |
|
| sampling_fe_a |sampling_fe |2990 |2397 |306 |2064 |25 |0 |
|
||||||
| u0_soft_n |cdc_sync |7 |2 |0 |7 |0 |0 |
|
| u0_soft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
|
||||||
| u_ad_sampling |ad_sampling |184 |145 |17 |136 |0 |0 |
|
| u_ad_sampling |ad_sampling |184 |114 |17 |146 |0 |0 |
|
||||||
| u0_soft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
|
| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||||
| u_sort |sort |2998 |2468 |289 |1909 |25 |0 |
|
| u_sort |sort |2777 |2276 |289 |1889 |25 |0 |
|
||||||
| rddpram_ctl |rddpram_ctl |5 |4 |0 |5 |0 |0 |
|
| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
|
||||||
| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
|
| u0_wrsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
|
||||||
| u0_rdsoft_n |cdc_sync |4 |0 |0 |4 |0 |0 |
|
| u_data_prebuffer |data_prebuffer |2369 |2001 |253 |1552 |22 |0 |
|
||||||
| u0_wrsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
|
| channelPart |channel_part_8478 |179 |175 |3 |146 |0 |0 |
|
||||||
| u_data_prebuffer |data_prebuffer |2596 |2148 |253 |1582 |22 |0 |
|
| fifo_adc |fifo_adc |58 |49 |9 |42 |0 |0 |
|
||||||
| channelPart |channel_part_8478 |160 |155 |3 |126 |0 |0 |
|
| ram_switch |ram_switch |1838 |1538 |197 |1145 |0 |0 |
|
||||||
| fifo_adc |fifo_adc |56 |47 |9 |39 |0 |0 |
|
| adc_addr_gen |adc_addr_gen |234 |206 |27 |125 |0 |0 |
|
||||||
| ram_switch |ram_switch |2024 |1637 |197 |1169 |0 |0 |
|
| [0]$ch_addr_gen |ch_addr_gen |14 |10 |3 |9 |0 |0 |
|
||||||
| adc_addr_gen |adc_addr_gen |255 |227 |27 |113 |0 |0 |
|
| [1]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 |
|
||||||
| [0]$ch_addr_gen |ch_addr_gen |11 |7 |3 |5 |0 |0 |
|
| [2]$ch_addr_gen |ch_addr_gen |30 |27 |3 |16 |0 |0 |
|
||||||
| [1]$ch_addr_gen |ch_addr_gen |25 |22 |3 |12 |0 |0 |
|
| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 |
|
||||||
| [2]$ch_addr_gen |ch_addr_gen |28 |25 |3 |14 |0 |0 |
|
| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 |
|
||||||
| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |9 |0 |0 |
|
| [5]$ch_addr_gen |ch_addr_gen |21 |18 |3 |8 |0 |0 |
|
||||||
| [4]$ch_addr_gen |ch_addr_gen |28 |25 |3 |13 |0 |0 |
|
| [6]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
|
||||||
| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 |
|
| [7]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 |
|
||||||
| [6]$ch_addr_gen |ch_addr_gen |30 |27 |3 |16 |0 |0 |
|
| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 |
|
||||||
| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
|
| insert |insert |955 |683 |170 |644 |0 |0 |
|
||||||
| [8]$ch_addr_gen |ch_addr_gen |28 |25 |3 |10 |0 |0 |
|
| ram_switch_state |ram_switch_state |649 |649 |0 |376 |0 |0 |
|
||||||
| insert |insert |987 |628 |170 |682 |0 |0 |
|
| read_ram_i |read_ram |265 |213 |44 |190 |0 |0 |
|
||||||
| ram_switch_state |ram_switch_state |782 |782 |0 |374 |0 |0 |
|
| read_ram_addr |read_ram_addr |215 |175 |40 |154 |0 |0 |
|
||||||
| read_ram_i |read_ram |313 |266 |44 |209 |0 |0 |
|
| read_ram_data |read_ram_data |48 |37 |4 |34 |0 |0 |
|
||||||
| read_ram_addr |read_ram_addr |251 |211 |40 |166 |0 |0 |
|
| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
|
||||||
| read_ram_data |read_ram_data |57 |51 |4 |38 |0 |0 |
|
|
||||||
| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
|
|
||||||
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
|
||||||
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
|
||||||
| u0_sort_ram_a_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
|
|
||||||
| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
|
||||||
| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
|
||||||
| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
|
||||||
| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
|
||||||
| u0_sort_ram_a_6 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
|
|
||||||
| u0_sort_ram_a_7 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
|
|
||||||
| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
|
||||||
| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
|
||||||
| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
|
||||||
| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
|
||||||
| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
|
||||||
| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
|
||||||
| u0_sort_ram_b_3 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
|
|
||||||
| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
|
||||||
| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
|
||||||
| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
|
||||||
| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
|
||||||
| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
|
||||||
| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
|
||||||
| u_transfer_300_to_200 |transfer_300_to_200 |326 |252 |36 |271 |3 |0 |
|
|
||||||
| u0_soft_n |cdc_sync |1 |0 |0 |1 |0 |0 |
|
|
||||||
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
|
|
||||||
| sampling_fe_b |sampling_fe_rev |3165 |2462 |349 |2109 |25 |1 |
|
|
||||||
| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
|
|
||||||
| u_ad_sampling |ad_sampling |187 |105 |17 |148 |0 |0 |
|
|
||||||
| u0_soft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
|
|
||||||
| u_sort |sort_rev |2946 |2342 |332 |1929 |25 |1 |
|
|
||||||
| rddpram_ctl |rddpram_ctl_rev |6 |5 |0 |6 |0 |0 |
|
|
||||||
| u0_rdsoft_n |cdc_sync |6 |5 |0 |6 |0 |0 |
|
|
||||||
| u0_rdsoft_n |cdc_sync |2 |0 |0 |2 |0 |0 |
|
|
||||||
| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
|
|
||||||
| u_data_prebuffer_rev |data_prebuffer_rev |2485 |1993 |290 |1576 |22 |1 |
|
|
||||||
| channelPart |channel_part_8478 |275 |272 |3 |151 |0 |0 |
|
|
||||||
| fifo_adc |fifo_adc |62 |53 |9 |45 |0 |1 |
|
|
||||||
| ram_switch |ram_switch |1756 |1391 |197 |1140 |0 |0 |
|
|
||||||
| adc_addr_gen |adc_addr_gen |198 |169 |27 |122 |0 |0 |
|
|
||||||
| [0]$ch_addr_gen |ch_addr_gen |13 |8 |3 |9 |0 |0 |
|
|
||||||
| [1]$ch_addr_gen |ch_addr_gen |26 |23 |3 |18 |0 |0 |
|
|
||||||
| [2]$ch_addr_gen |ch_addr_gen |18 |15 |3 |11 |0 |0 |
|
|
||||||
| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |18 |0 |0 |
|
|
||||||
| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |14 |0 |0 |
|
|
||||||
| [5]$ch_addr_gen |ch_addr_gen |16 |13 |3 |9 |0 |0 |
|
|
||||||
| [6]$ch_addr_gen |ch_addr_gen |18 |15 |3 |10 |0 |0 |
|
|
||||||
| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |11 |0 |0 |
|
|
||||||
| [8]$ch_addr_gen |ch_addr_gen |18 |15 |3 |8 |0 |0 |
|
|
||||||
| insert |insert |1012 |680 |170 |674 |0 |0 |
|
|
||||||
| ram_switch_state |ram_switch_state |546 |542 |0 |344 |0 |0 |
|
|
||||||
| read_ram_i |read_ram_rev |363 |258 |81 |213 |0 |0 |
|
|
||||||
| read_ram_addr |read_ram_addr_rev |298 |218 |73 |166 |0 |0 |
|
|
||||||
| read_ram_data |read_ram_data_rev |65 |40 |8 |47 |0 |0 |
|
|
||||||
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
|
@ -243,68 +188,120 @@ Report Hierarchy Area:
|
||||||
| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
| u_transfer_300_to_200 |transfer_300_to_200 |348 |260 |42 |273 |3 |0 |
|
| u_transfer_300_to_200 |transfer_300_to_200 |295 |175 |36 |264 |3 |0 |
|
||||||
|
| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||||
|
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
|
||||||
|
| sampling_fe_b |sampling_fe_rev |3425 |2768 |349 |2117 |25 |1 |
|
||||||
|
| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
|
||||||
|
| u_ad_sampling |ad_sampling |186 |118 |17 |151 |0 |0 |
|
||||||
|
| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||||
|
| u_sort |sort_rev |3208 |2632 |332 |1935 |25 |1 |
|
||||||
|
| rddpram_ctl |rddpram_ctl_rev |5 |5 |0 |5 |0 |0 |
|
||||||
|
| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
|
||||||
|
| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
|
||||||
|
| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
|
||||||
|
| u_data_prebuffer_rev |data_prebuffer_rev |2742 |2267 |290 |1583 |22 |1 |
|
||||||
|
| channelPart |channel_part_8478 |263 |250 |3 |149 |0 |0 |
|
||||||
|
| fifo_adc |fifo_adc |65 |56 |9 |46 |0 |1 |
|
||||||
|
| ram_switch |ram_switch |1999 |1658 |197 |1136 |0 |0 |
|
||||||
|
| adc_addr_gen |adc_addr_gen |221 |194 |27 |106 |0 |0 |
|
||||||
|
| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |5 |0 |0 |
|
||||||
|
| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |14 |0 |0 |
|
||||||
|
| [2]$ch_addr_gen |ch_addr_gen |23 |20 |3 |12 |0 |0 |
|
||||||
|
| [3]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
|
||||||
|
| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
|
||||||
|
| [5]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 |
|
||||||
|
| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |7 |0 |0 |
|
||||||
|
| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
|
||||||
|
| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
|
||||||
|
| insert |insert |972 |659 |170 |667 |0 |0 |
|
||||||
|
| ram_switch_state |ram_switch_state |806 |805 |0 |363 |0 |0 |
|
||||||
|
| read_ram_i |read_ram_rev |376 |267 |81 |214 |0 |0 |
|
||||||
|
| read_ram_addr |read_ram_addr_rev |307 |222 |73 |162 |0 |0 |
|
||||||
|
| read_ram_data |read_ram_data_rev |69 |45 |8 |52 |0 |0 |
|
||||||
|
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||||
|
| u0_sort_ram_b_9 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
|
||||||
|
| u_transfer_300_to_200 |transfer_300_to_200 |366 |288 |42 |281 |3 |0 |
|
||||||
| u0_soft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
|
| u0_soft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
|
||||||
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
|
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
|
||||||
| scan_start_diff |scan_start_diff |26 |26 |0 |14 |0 |0 |
|
| scan_start_diff |scan_start_diff |21 |20 |0 |14 |0 |0 |
|
||||||
| u0_test_en |cdc_sync |5 |5 |0 |5 |0 |0 |
|
| u0_test_en |cdc_sync |5 |1 |0 |5 |0 |0 |
|
||||||
| u1_test_en |cdc_sync |5 |5 |0 |5 |0 |0 |
|
| u1_BUSY_MIPI |cdc_sync |3 |2 |0 |3 |0 |0 |
|
||||||
| u2_test_en |cdc_sync |4 |3 |0 |4 |0 |0 |
|
| u1_test_en |cdc_sync |1 |1 |0 |1 |0 |0 |
|
||||||
| u_O_clk_lp_n |cdc_sync |270 |209 |0 |269 |0 |0 |
|
| u2_test_en |cdc_sync |7 |6 |0 |7 |0 |0 |
|
||||||
| u_O_clk_lp_p |cdc_sync |285 |48 |0 |285 |0 |0 |
|
| u_O_clk_lp_n |cdc_sync |17 |17 |0 |17 |0 |0 |
|
||||||
|
| u_O_clk_lp_p |cdc_sync |12 |12 |0 |12 |0 |0 |
|
||||||
| u_a_pclk |cdc_sync |4 |4 |0 |4 |0 |0 |
|
| u_a_pclk |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||||
| u_a_sp_sampling |cdc_sync |6 |6 |0 |6 |0 |0 |
|
| u_a_sp_sampling |cdc_sync |2 |2 |0 |2 |0 |0 |
|
||||||
| u_a_sp_sampling_cam |cdc_sync |3 |3 |0 |3 |0 |0 |
|
| u_a_sp_sampling_cam |cdc_sync |6 |5 |0 |6 |0 |0 |
|
||||||
| u_a_sp_sampling_last |cdc_sync |4 |4 |0 |4 |0 |0 |
|
| u_b_pclk |cdc_sync |5 |4 |0 |5 |0 |0 |
|
||||||
| u_b_pclk |cdc_sync |2 |2 |0 |2 |0 |0 |
|
| u_b_sp_sampling |cdc_sync |5 |5 |0 |5 |0 |0 |
|
||||||
| u_b_sp_sampling |cdc_sync |5 |2 |0 |5 |0 |0 |
|
| u_b_sp_sampling_cam |cdc_sync |3 |3 |0 |3 |0 |0 |
|
||||||
| u_b_sp_sampling_cam |cdc_sync |8 |1 |0 |8 |0 |0 |
|
| u_b_sp_sampling_last |cdc_sync |6 |6 |0 |6 |0 |0 |
|
||||||
| u_b_sp_sampling_last |cdc_sync |2 |2 |0 |2 |0 |0 |
|
| u_bus_top |ubus_top |1360 |952 |22 |1258 |0 |0 |
|
||||||
| u_bus_top |ubus_top |1297 |953 |22 |1222 |0 |0 |
|
| u_local_bus_slve_cis |local_bus_slve_cis |846 |713 |22 |744 |0 |0 |
|
||||||
| u_local_bus_slve_cis |local_bus_slve_cis |784 |645 |22 |709 |0 |0 |
|
| u_uart_2dsp |uart_2dsp |135 |120 |12 |66 |0 |0 |
|
||||||
| u_uart_2dsp |uart_2dsp |87 |72 |12 |56 |0 |0 |
|
| u_dpi_mode |cdc_sync |9 |6 |0 |9 |0 |0 |
|
||||||
| u_dpi_mode |cdc_sync |8 |8 |0 |8 |0 |0 |
|
| u_lv_en_flag |cdc_sync |6 |6 |0 |6 |0 |0 |
|
||||||
| u_eot |cdc_sync |3 |3 |0 |3 |0 |0 |
|
| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |275 |206 |20 |224 |4 |0 |
|
||||||
| u_lv_en_flag |cdc_sync |2 |2 |0 |2 |0 |0 |
|
| u_hs_tx_wrapper |hs_tx_wrapper |233 |164 |20 |195 |4 |0 |
|
||||||
| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |269 |213 |20 |220 |4 |0 |
|
| [0]$u_data_lane_wrapper |data_lane_wrapper |116 |85 |15 |89 |1 |0 |
|
||||||
| u_hs_tx_wrapper |hs_tx_wrapper |226 |170 |20 |188 |4 |0 |
|
| u_data_hs_generate |data_hs_generate |113 |82 |15 |86 |1 |0 |
|
||||||
| [0]$u_data_lane_wrapper |data_lane_wrapper |110 |77 |15 |85 |1 |0 |
|
|
||||||
| u_data_hs_generate |data_hs_generate |106 |73 |15 |81 |1 |0 |
|
|
||||||
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
|
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
|
||||||
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
|
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
|
||||||
| u_data_lp_generate |data_lp_generate |4 |4 |0 |4 |0 |0 |
|
| u_data_lp_generate |data_lp_generate |3 |3 |0 |3 |0 |0 |
|
||||||
| [1]$u_data_lane_wrapper |data_lane_wrapper |26 |15 |0 |26 |1 |0 |
|
| [1]$u_data_lane_wrapper |data_lane_wrapper |35 |20 |0 |35 |1 |0 |
|
||||||
| u_data_hs_generate |data_hs_generate |26 |15 |0 |26 |1 |0 |
|
| u_data_hs_generate |data_hs_generate |35 |20 |0 |35 |1 |0 |
|
||||||
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
|
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
|
||||||
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
|
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
|
||||||
| [2]$u_data_lane_wrapper |data_lane_wrapper |37 |32 |0 |36 |1 |0 |
|
| [2]$u_data_lane_wrapper |data_lane_wrapper |29 |13 |0 |29 |1 |0 |
|
||||||
| u_data_hs_generate |data_hs_generate |37 |32 |0 |36 |1 |0 |
|
| u_data_hs_generate |data_hs_generate |29 |13 |0 |29 |1 |0 |
|
||||||
| u_dphy_tx_fifo |dphy_tx_fifo |2 |2 |0 |1 |1 |0 |
|
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
|
||||||
| u_d1024_w8_fifo |d1024_w8_fifo |2 |2 |0 |1 |1 |0 |
|
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
|
||||||
| [3]$u_data_lane_wrapper |data_lane_wrapper |21 |19 |0 |19 |1 |0 |
|
| [3]$u_data_lane_wrapper |data_lane_wrapper |20 |18 |0 |20 |1 |0 |
|
||||||
| u_data_hs_generate |data_hs_generate |21 |19 |0 |19 |1 |0 |
|
| u_data_hs_generate |data_hs_generate |20 |18 |0 |20 |1 |0 |
|
||||||
| u_dphy_tx_fifo |dphy_tx_fifo |2 |2 |0 |1 |1 |0 |
|
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
|
||||||
| u_d1024_w8_fifo |d1024_w8_fifo |2 |2 |0 |1 |1 |0 |
|
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
|
||||||
| u_hs_tx_controler |hs_tx_controler |24 |19 |5 |14 |0 |0 |
|
| u_hs_tx_controler |hs_tx_controler |25 |20 |5 |14 |0 |0 |
|
||||||
| u_clk_lane_wrapper |clk_lane_wrapper |8 |8 |0 |8 |0 |0 |
|
| u_clk_lane_wrapper |clk_lane_wrapper |8 |8 |0 |8 |0 |0 |
|
||||||
| u_clk_lp_generate |clk_lp_generate |4 |4 |0 |4 |0 |0 |
|
|
||||||
| u_clk_hs_generate |clk_hs_generate |4 |4 |0 |4 |0 |0 |
|
| u_clk_hs_generate |clk_hs_generate |4 |4 |0 |4 |0 |0 |
|
||||||
| u_mipi_eot_min |cdc_sync |60 |57 |0 |60 |0 |0 |
|
| u_clk_lp_generate |clk_lp_generate |4 |4 |0 |4 |0 |0 |
|
||||||
| u_mipi_sot_min |cdc_sync |58 |55 |0 |58 |0 |0 |
|
| u_mipi_eot_min |cdc_sync |65 |58 |0 |65 |0 |0 |
|
||||||
| u_pic_cnt |cdc_sync |117 |58 |0 |117 |0 |0 |
|
| u_mipi_sot_min |cdc_sync |58 |56 |0 |58 |0 |0 |
|
||||||
| u_pixel_cdc |pixel_cdc |697 |517 |0 |695 |0 |1 |
|
| u_pic_cnt |cdc_sync |115 |72 |0 |115 |0 |0 |
|
||||||
| u_clk_cis_frame_num |cdc_sync |73 |62 |0 |73 |0 |0 |
|
| u_pixel_cdc |pixel_cdc |675 |580 |0 |672 |0 |1 |
|
||||||
| u_clk_cis_pixel_y |cdc_sync |77 |73 |0 |75 |0 |0 |
|
| u_clk_cis_frame_num |cdc_sync |68 |60 |0 |68 |0 |0 |
|
||||||
| u_clk_mipi_pixel_y |cdc_sync |73 |67 |0 |73 |0 |0 |
|
| u_clk_cis_pixel_y |cdc_sync |65 |59 |0 |65 |0 |0 |
|
||||||
| u_clka_cis_total_num |cdc_sync |100 |94 |0 |100 |0 |0 |
|
| u_clk_mipi_pixel_y |cdc_sync |74 |73 |0 |72 |0 |0 |
|
||||||
| u_clka_mipi_total_num |cdc_sync |101 |60 |0 |101 |0 |0 |
|
| u_clka_cis_total_num |cdc_sync |94 |83 |0 |94 |0 |0 |
|
||||||
| u_clkb_cis_total_num |cdc_sync |108 |46 |0 |108 |0 |0 |
|
| u_clka_mipi_total_num |cdc_sync |102 |88 |0 |102 |0 |0 |
|
||||||
| u_clkb_mipi_total_num |cdc_sync |98 |66 |0 |98 |0 |0 |
|
| u_clkb_cis_total_num |cdc_sync |100 |85 |0 |99 |0 |0 |
|
||||||
|
| u_clkb_mipi_total_num |cdc_sync |100 |77 |0 |100 |0 |0 |
|
||||||
| u_pll |pll |0 |0 |0 |0 |0 |0 |
|
| u_pll |pll |0 |0 |0 |0 |0 |0 |
|
||||||
| u_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |0 |
|
| u_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |0 |
|
||||||
| u_softrst_done |cdc_sync |5 |5 |0 |5 |0 |0 |
|
| u_softrst_done |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||||
| ua_lvds_rx |lvds_rx |278 |194 |19 |198 |0 |0 |
|
| ua_lvds_rx |lvds_rx |278 |218 |19 |197 |0 |0 |
|
||||||
| ub_lvds_rx |lvds_rx |288 |192 |19 |209 |0 |0 |
|
| ub_lvds_rx |lvds_rx |287 |192 |19 |207 |0 |0 |
|
||||||
| uu_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |0 |
|
| uu_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |0 |
|
||||||
+---------------------------------------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------------------------------------+
|
||||||
|
|
||||||
|
|
@ -312,12 +309,12 @@ Report Hierarchy Area:
|
||||||
DataNet Average Fanout:
|
DataNet Average Fanout:
|
||||||
|
|
||||||
Index Fanout Nets
|
Index Fanout Nets
|
||||||
#1 1 10415
|
#1 1 9801
|
||||||
#2 2 3902
|
#2 2 3950
|
||||||
#3 3 1365
|
#3 3 1453
|
||||||
#4 4 552
|
#4 4 623
|
||||||
#5 5-10 1241
|
#5 5-10 1031
|
||||||
#6 11-50 592
|
#6 11-50 602
|
||||||
#7 51-100 26
|
#7 51-100 22
|
||||||
#8 >500 1
|
#8 >500 1
|
||||||
Average 2.89
|
Average 2.91
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
|
@ -1,5 +1,5 @@
|
||||||
<?xml version="1.0"?>
|
<?xml version="1.0"?>
|
||||||
<ProcessHandle Version="1" Minor="0">
|
<ProcessHandle Version="1" Minor="0">
|
||||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="17512">
|
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="1576">
|
||||||
</Process>
|
</Process>
|
||||||
</ProcessHandle>
|
</ProcessHandle>
|
||||||
|
|
|
||||||
|
|
@ -1,5 +1,5 @@
|
||||||
<?xml version="1.0"?>
|
<?xml version="1.0"?>
|
||||||
<ProcessHandle Version="1" Minor="0">
|
<ProcessHandle Version="1" Minor="0">
|
||||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="17512">
|
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="1576">
|
||||||
</Process>
|
</Process>
|
||||||
</ProcessHandle>
|
</ProcessHandle>
|
||||||
|
|
|
||||||
|
|
@ -1,5 +1,5 @@
|
||||||
<?xml version="1.0"?>
|
<?xml version="1.0"?>
|
||||||
<ProcessHandle Version="1" Minor="0">
|
<ProcessHandle Version="1" Minor="0">
|
||||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="17512">
|
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="1576">
|
||||||
</Process>
|
</Process>
|
||||||
</ProcessHandle>
|
</ProcessHandle>
|
||||||
|
|
|
||||||
|
|
@ -1,5 +1,5 @@
|
||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<Project Version="3" Minor="2" RunTime="2024-03-12T14:50:44.727439">
|
<Project Version="3" Minor="2" RunTime="2024-03-12T16:38:37.869942">
|
||||||
<Project_Created_Time></Project_Created_Time>
|
<Project_Created_Time></Project_Created_Time>
|
||||||
<TD_Encoding>UTF-8</TD_Encoding>
|
<TD_Encoding>UTF-8</TD_Encoding>
|
||||||
<TD_Version>5.6.71036</TD_Version>
|
<TD_Version>5.6.71036</TD_Version>
|
||||||
|
|
|
||||||
Binary file not shown.
|
|
@ -8,16 +8,16 @@ IO Statistics
|
||||||
#inout 0
|
#inout 0
|
||||||
|
|
||||||
LUT Statistics
|
LUT Statistics
|
||||||
#Total_luts 10030
|
#Total_luts 9912
|
||||||
#lut4 5343
|
#lut4 5066
|
||||||
#lut5 2132
|
#lut5 2291
|
||||||
#lut6 0
|
#lut6 0
|
||||||
#lut5_mx41 0
|
#lut5_mx41 0
|
||||||
#lut4_alu1b 2555
|
#lut4_alu1b 2555
|
||||||
|
|
||||||
Utilization Statistics
|
Utilization Statistics
|
||||||
#lut 10030 out of 19600 51.17%
|
#lut 9912 out of 19600 50.57%
|
||||||
#reg 9745 out of 19600 49.72%
|
#reg 9232 out of 19600 47.10%
|
||||||
#le 0
|
#le 0
|
||||||
#dsp 3 out of 29 10.34%
|
#dsp 3 out of 29 10.34%
|
||||||
#bram 54 out of 64 84.38%
|
#bram 54 out of 64 84.38%
|
||||||
|
|
@ -27,7 +27,7 @@ Utilization Statistics
|
||||||
#dram 16
|
#dram 16
|
||||||
#pad 75 out of 130 57.69%
|
#pad 75 out of 130 57.69%
|
||||||
#ireg 13
|
#ireg 13
|
||||||
#oreg 19
|
#oreg 21
|
||||||
#treg 0
|
#treg 0
|
||||||
#pll 3 out of 4 75.00%
|
#pll 3 out of 4 75.00%
|
||||||
|
|
||||||
|
|
@ -35,30 +35,30 @@ Report Hierarchy Area:
|
||||||
+-------------------------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------------------------+
|
||||||
|Instance |Module |lut |ripple |seq |bram |dsp |
|
|Instance |Module |lut |ripple |seq |bram |dsp |
|
||||||
+-------------------------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------------------------+
|
||||||
|top |huagao_mipi_top |7475 |2555 |9777 |58 |3 |
|
|top |huagao_mipi_top |7357 |2555 |9266 |58 |3 |
|
||||||
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |336 |81 |441 |4 |1 |
|
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |343 |81 |441 |4 |1 |
|
||||||
| U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 |
|
| U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 |
|
||||||
| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
|
| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
|
||||||
| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
|
| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
|
||||||
| exdev_ctl_a |exdev_ctl |283 |234 |559 |0 |0 |
|
| exdev_ctl_a |exdev_ctl |288 |234 |559 |0 |0 |
|
||||||
| u_ADconfig |AD_config |98 |49 |138 |0 |0 |
|
| u_ADconfig |AD_config |102 |49 |138 |0 |0 |
|
||||||
| u_gen_sp |gen_sp |127 |185 |104 |0 |0 |
|
| u_gen_sp |gen_sp |128 |185 |104 |0 |0 |
|
||||||
| exdev_ctl_b |exdev_ctl |277 |234 |546 |0 |0 |
|
| exdev_ctl_b |exdev_ctl |276 |234 |546 |0 |0 |
|
||||||
| u_ADconfig |AD_config |93 |49 |125 |0 |0 |
|
| u_ADconfig |AD_config |92 |49 |125 |0 |0 |
|
||||||
| u_gen_sp |gen_sp |126 |185 |104 |0 |0 |
|
| u_gen_sp |gen_sp |126 |185 |104 |0 |0 |
|
||||||
| sampling_fe_a |sampling_fe |2334 |738 |1919 |25 |0 |
|
| sampling_fe_a |sampling_fe |2277 |738 |1919 |25 |0 |
|
||||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
|
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
|
||||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_sort |sort |2264 |691 |1737 |25 |0 |
|
| u_sort |sort |2207 |691 |1737 |25 |0 |
|
||||||
| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
|
| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
|
||||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_data_prebuffer |data_prebuffer |1922 |615 |1391 |22 |0 |
|
| u_data_prebuffer |data_prebuffer |1866 |615 |1391 |22 |0 |
|
||||||
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
|
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
|
||||||
| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
|
| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
|
||||||
| ram_switch |ram_switch |1483 |422 |1023 |0 |0 |
|
| ram_switch |ram_switch |1444 |422 |1023 |0 |0 |
|
||||||
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
|
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
|
||||||
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
|
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
|
||||||
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||||
|
|
@ -70,10 +70,10 @@ Report Hierarchy Area:
|
||||||
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||||
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||||
| insert |insert |265 |323 |692 |0 |0 |
|
| insert |insert |265 |323 |692 |0 |0 |
|
||||||
| ram_switch_state |ram_switch_state |1089 |0 |216 |0 |0 |
|
| ram_switch_state |ram_switch_state |1050 |0 |216 |0 |0 |
|
||||||
| read_ram_i |read_ram |206 |158 |164 |0 |0 |
|
| read_ram_i |read_ram |189 |158 |164 |0 |0 |
|
||||||
| read_ram_addr |read_ram_addr |173 |145 |127 |0 |0 |
|
| read_ram_addr |read_ram_addr |161 |145 |127 |0 |0 |
|
||||||
| read_ram_data |read_ram_data |32 |13 |32 |0 |0 |
|
| read_ram_data |read_ram_data |27 |13 |32 |0 |0 |
|
||||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||||
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||||
|
|
@ -100,19 +100,19 @@ Report Hierarchy Area:
|
||||||
| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 |
|
| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 |
|
||||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
|
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
|
||||||
| sampling_fe_b |sampling_fe_rev |2334 |751 |1936 |25 |1 |
|
| sampling_fe_b |sampling_fe_rev |2297 |751 |1936 |25 |1 |
|
||||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
|
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
|
||||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_sort |sort_rev |2264 |704 |1754 |25 |1 |
|
| u_sort |sort_rev |2227 |704 |1754 |25 |1 |
|
||||||
| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
|
| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
|
||||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_data_prebuffer_rev |data_prebuffer_rev |1925 |628 |1408 |22 |1 |
|
| u_data_prebuffer_rev |data_prebuffer_rev |1888 |628 |1408 |22 |1 |
|
||||||
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
|
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
|
||||||
| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
|
| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
|
||||||
| ram_switch |ram_switch |1484 |422 |1023 |0 |0 |
|
| ram_switch |ram_switch |1443 |422 |1023 |0 |0 |
|
||||||
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
|
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
|
||||||
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
|
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
|
||||||
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||||
|
|
@ -124,10 +124,10 @@ Report Hierarchy Area:
|
||||||
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||||
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||||
| insert |insert |265 |323 |692 |0 |0 |
|
| insert |insert |265 |323 |692 |0 |0 |
|
||||||
| ram_switch_state |ram_switch_state |1090 |0 |216 |0 |0 |
|
| ram_switch_state |ram_switch_state |1049 |0 |216 |0 |0 |
|
||||||
| read_ram_i |read_ram_rev |206 |171 |181 |0 |0 |
|
| read_ram_i |read_ram_rev |210 |171 |181 |0 |0 |
|
||||||
| read_ram_addr |read_ram_addr_rev |180 |145 |139 |0 |0 |
|
| read_ram_addr |read_ram_addr_rev |182 |145 |139 |0 |0 |
|
||||||
| read_ram_data |read_ram_data_rev |26 |26 |42 |0 |0 |
|
| read_ram_data |read_ram_data_rev |28 |26 |42 |0 |0 |
|
||||||
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||||
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||||
| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||||
|
|
@ -155,10 +155,11 @@ Report Hierarchy Area:
|
||||||
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
|
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
|
||||||
| scan_start_diff |scan_start_diff |30 |0 |12 |0 |0 |
|
| scan_start_diff |scan_start_diff |30 |0 |12 |0 |0 |
|
||||||
| u0_test_en |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_test_en |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
|
| u1_BUSY_MIPI |cdc_sync |1 |0 |15 |0 |0 |
|
||||||
| u1_test_en |cdc_sync |1 |0 |5 |0 |0 |
|
| u1_test_en |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u2_test_en |cdc_sync |1 |0 |5 |0 |0 |
|
| u2_test_en |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_O_clk_lp_n |cdc_sync |20 |0 |286 |0 |0 |
|
| u_O_clk_lp_n |cdc_sync |1 |0 |22 |0 |0 |
|
||||||
| u_O_clk_lp_p |cdc_sync |20 |0 |286 |0 |0 |
|
| u_O_clk_lp_p |cdc_sync |1 |0 |22 |0 |0 |
|
||||||
| u_a_pclk |cdc_sync |1 |0 |5 |0 |0 |
|
| u_a_pclk |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_a_sp_sampling |cdc_sync |1 |0 |5 |0 |0 |
|
| u_a_sp_sampling |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_a_sp_sampling_cam |cdc_sync |1 |0 |5 |0 |0 |
|
| u_a_sp_sampling_cam |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
|
|
@ -167,14 +168,14 @@ Report Hierarchy Area:
|
||||||
| u_b_sp_sampling |cdc_sync |1 |0 |5 |0 |0 |
|
| u_b_sp_sampling |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_b_sp_sampling_cam |cdc_sync |1 |0 |5 |0 |0 |
|
| u_b_sp_sampling_cam |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_b_sp_sampling_last |cdc_sync |1 |0 |5 |0 |0 |
|
| u_b_sp_sampling_last |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_bus_top |ubus_top |817 |50 |1248 |0 |0 |
|
| u_bus_top |ubus_top |811 |50 |1248 |0 |0 |
|
||||||
| u_local_bus_slve_cis |local_bus_slve_cis |723 |50 |721 |0 |0 |
|
| u_local_bus_slve_cis |local_bus_slve_cis |717 |50 |721 |0 |0 |
|
||||||
| u_uart_2dsp |uart_2dsp |120 |31 |52 |0 |0 |
|
| u_uart_2dsp |uart_2dsp |123 |31 |52 |0 |0 |
|
||||||
| u_dpi_mode |cdc_sync |2 |0 |10 |0 |0 |
|
| u_dpi_mode |cdc_sync |2 |0 |10 |0 |0 |
|
||||||
| u_eot |cdc_sync |1 |0 |5 |0 |0 |
|
| u_eot |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_lv_en_flag |cdc_sync |1 |0 |5 |0 |0 |
|
| u_lv_en_flag |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |167 |61 |226 |4 |0 |
|
| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |172 |61 |226 |4 |0 |
|
||||||
| u_hs_tx_wrapper |hs_tx_wrapper |111 |61 |198 |4 |0 |
|
| u_hs_tx_wrapper |hs_tx_wrapper |112 |61 |198 |4 |0 |
|
||||||
| [0]$u_data_lane_wrapper |data_lane_wrapper |54 |52 |93 |1 |0 |
|
| [0]$u_data_lane_wrapper |data_lane_wrapper |54 |52 |93 |1 |0 |
|
||||||
| u_data_hs_generate |data_hs_generate |50 |52 |87 |1 |0 |
|
| u_data_hs_generate |data_hs_generate |50 |52 |87 |1 |0 |
|
||||||
| u_dphy_tx_fifo |dphy_tx_fifo |2 |0 |0 |1 |0 |
|
| u_dphy_tx_fifo |dphy_tx_fifo |2 |0 |0 |1 |0 |
|
||||||
|
|
@ -195,7 +196,7 @@ Report Hierarchy Area:
|
||||||
| u_clk_lane_wrapper |clk_lane_wrapper |3 |0 |8 |0 |0 |
|
| u_clk_lane_wrapper |clk_lane_wrapper |3 |0 |8 |0 |0 |
|
||||||
| u_clk_hs_generate |clk_hs_generate |3 |0 |4 |0 |0 |
|
| u_clk_hs_generate |clk_hs_generate |3 |0 |4 |0 |0 |
|
||||||
| u_clk_lp_generate |clk_lp_generate |0 |0 |4 |0 |0 |
|
| u_clk_lp_generate |clk_lp_generate |0 |0 |4 |0 |0 |
|
||||||
| u_hs_tx_controler |hs_tx_controler |24 |9 |12 |0 |0 |
|
| u_hs_tx_controler |hs_tx_controler |25 |9 |12 |0 |0 |
|
||||||
| u_mipi_eot_min |cdc_sync |20 |0 |65 |0 |0 |
|
| u_mipi_eot_min |cdc_sync |20 |0 |65 |0 |0 |
|
||||||
| u_mipi_sot_min |cdc_sync |20 |0 |65 |0 |0 |
|
| u_mipi_sot_min |cdc_sync |20 |0 |65 |0 |0 |
|
||||||
| u_pic_cnt |cdc_sync |38 |0 |120 |0 |0 |
|
| u_pic_cnt |cdc_sync |38 |0 |120 |0 |0 |
|
||||||
|
|
@ -211,7 +212,7 @@ Report Hierarchy Area:
|
||||||
| u_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |
|
| u_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |
|
||||||
| u_softrst_done |cdc_sync |1 |0 |5 |0 |0 |
|
| u_softrst_done |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_softrst_fan_ctrl |cdc_sync |0 |0 |0 |0 |0 |
|
| u_softrst_fan_ctrl |cdc_sync |0 |0 |0 |0 |0 |
|
||||||
| ua_lvds_rx |lvds_rx |96 |67 |209 |0 |0 |
|
| ua_lvds_rx |lvds_rx |97 |67 |209 |0 |0 |
|
||||||
| ub_lvds_rx |lvds_rx |96 |67 |209 |0 |0 |
|
| ub_lvds_rx |lvds_rx |97 |67 |209 |0 |0 |
|
||||||
| uu_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |
|
| uu_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |
|
||||||
+-------------------------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------------------------+
|
||||||
|
|
|
||||||
Binary file not shown.
|
|
@ -8,31 +8,31 @@ IO Statistics
|
||||||
#inout 0
|
#inout 0
|
||||||
|
|
||||||
Gate Statistics
|
Gate Statistics
|
||||||
#Basic gates 14522
|
#Basic gates 14015
|
||||||
#and 2480
|
#and 2480
|
||||||
#nand 0
|
#nand 0
|
||||||
#or 1078
|
#or 1078
|
||||||
#nor 0
|
#nor 0
|
||||||
#xor 204
|
#xor 207
|
||||||
#xnor 0
|
#xnor 0
|
||||||
#buf 0
|
#buf 0
|
||||||
#not 469
|
#not 469
|
||||||
#bufif1 5
|
#bufif1 5
|
||||||
#MX21 615
|
#MX21 618
|
||||||
#FADD 0
|
#FADD 0
|
||||||
#DFF 9665
|
#DFF 9152
|
||||||
#LATCH 6
|
#LATCH 6
|
||||||
#MACRO_ADD 497
|
#MACRO_ADD 497
|
||||||
#MACRO_EQ 227
|
#MACRO_EQ 225
|
||||||
#MACRO_MULT 4
|
#MACRO_MULT 4
|
||||||
#MACRO_MUX 4839
|
#MACRO_MUX 4813
|
||||||
#MACRO_OTHERS 73
|
#MACRO_OTHERS 73
|
||||||
|
|
||||||
Report Hierarchy Area:
|
Report Hierarchy Area:
|
||||||
+----------------------------------------------------------------------------+
|
+----------------------------------------------------------------------------+
|
||||||
|Instance |Module |gates |seq |macros |
|
|Instance |Module |gates |seq |macros |
|
||||||
+----------------------------------------------------------------------------+
|
+----------------------------------------------------------------------------+
|
||||||
|top |huagao_mipi_top |4851 |9671 |801 |
|
|top |huagao_mipi_top |4857 |9158 |799 |
|
||||||
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
|
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
|
||||||
| U_crc16_24b |crc16_24b |67 |16 |0 |
|
| U_crc16_24b |crc16_24b |67 |16 |0 |
|
||||||
| U_ecc_gen |ecc_gen |37 |6 |0 |
|
| U_ecc_gen |ecc_gen |37 |6 |0 |
|
||||||
|
|
@ -162,10 +162,11 @@ Report Hierarchy Area:
|
||||||
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
|
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
|
||||||
| scan_start_diff |scan_start_diff |8 |12 |0 |
|
| scan_start_diff |scan_start_diff |8 |12 |0 |
|
||||||
| u0_test_en |cdc_sync |2 |5 |0 |
|
| u0_test_en |cdc_sync |2 |5 |0 |
|
||||||
|
| u1_BUSY_MIPI |cdc_sync |2 |15 |0 |
|
||||||
| u1_test_en |cdc_sync |2 |5 |0 |
|
| u1_test_en |cdc_sync |2 |5 |0 |
|
||||||
| u2_test_en |cdc_sync |2 |5 |0 |
|
| u2_test_en |cdc_sync |2 |5 |0 |
|
||||||
| u_O_clk_lp_n |cdc_sync |0 |286 |1 |
|
| u_O_clk_lp_n |cdc_sync |2 |22 |0 |
|
||||||
| u_O_clk_lp_p |cdc_sync |0 |286 |1 |
|
| u_O_clk_lp_p |cdc_sync |2 |22 |0 |
|
||||||
| u_a_pclk |cdc_sync |2 |5 |0 |
|
| u_a_pclk |cdc_sync |2 |5 |0 |
|
||||||
| u_a_sp_sampling |cdc_sync |2 |5 |0 |
|
| u_a_sp_sampling |cdc_sync |2 |5 |0 |
|
||||||
| u_a_sp_sampling_cam |cdc_sync |2 |5 |0 |
|
| u_a_sp_sampling_cam |cdc_sync |2 |5 |0 |
|
||||||
|
|
|
||||||
Binary file not shown.
|
|
@ -4,7 +4,7 @@
|
||||||
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
|
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
|
||||||
Built at = 20:34:38 Mar 21 2023
|
Built at = 20:34:38 Mar 21 2023
|
||||||
Run by = holdtecs
|
Run by = holdtecs
|
||||||
Run Date = Tue Mar 12 14:50:44 2024
|
Run Date = Tue Mar 12 16:38:38 2024
|
||||||
|
|
||||||
Run on = DESKTOP-5MQL5VE
|
Run on = DESKTOP-5MQL5VE
|
||||||
============================================================
|
============================================================
|
||||||
|
|
@ -97,19 +97,19 @@ HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in .
|
||||||
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
|
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
|
||||||
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
|
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
|
||||||
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
|
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
|
||||||
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(720)
|
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
|
||||||
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(729)
|
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
|
||||||
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(753)
|
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
|
||||||
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(755)
|
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
|
||||||
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(761)
|
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
|
||||||
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
|
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
|
||||||
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(935)
|
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
|
||||||
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1024)
|
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
|
||||||
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1325)
|
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
|
||||||
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
|
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
|
||||||
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1354)
|
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
|
||||||
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1536)
|
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
|
||||||
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1932)
|
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
|
||||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
|
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
|
||||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
|
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
|
||||||
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
|
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
|
||||||
|
|
@ -269,16 +269,16 @@ RUN-1001 : infer_shifter | on | on |
|
||||||
RUN-1001 : --------------------------------------------------------------
|
RUN-1001 : --------------------------------------------------------------
|
||||||
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
|
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
|
||||||
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
|
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
|
||||||
HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(596)
|
HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(607)
|
||||||
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(734)
|
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(745)
|
||||||
HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(959)
|
HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(970)
|
||||||
HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
|
HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
|
||||||
HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
|
HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
|
||||||
HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
|
HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
|
||||||
HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
|
HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
|
||||||
HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
|
HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
|
||||||
HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
|
HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
|
||||||
HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
|
HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
|
||||||
HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
|
HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
|
||||||
HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
|
HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
|
||||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
|
HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
|
||||||
|
|
@ -292,12 +292,9 @@ HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
|
||||||
HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
|
HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
|
||||||
HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
|
HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
|
||||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||||
HDL-1007 : elaborate module cdc_sync(DEPTH=20,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||||
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 13 for port 'signal_from' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(356)
|
|
||||||
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 13 for port 'signal_to' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(357)
|
|
||||||
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 13 for port 'signal_from' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(366)
|
|
||||||
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 13 for port 'signal_to' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(367)
|
|
||||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||||
|
HDL-1007 : elaborate module cdc_sync(DEPTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||||
HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
|
HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
|
||||||
HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
|
HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
|
||||||
HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
|
HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
|
||||||
|
|
@ -381,14 +378,14 @@ HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1
|
||||||
HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
|
HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
|
||||||
HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
|
HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
|
||||||
HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
|
HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
|
||||||
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
|
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
|
||||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||||
HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
|
HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
|
||||||
HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
|
HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
|
||||||
HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
|
HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
|
||||||
HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
|
HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
|
||||||
HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
|
HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
|
||||||
HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1415)
|
HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1426)
|
||||||
HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
|
HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
|
||||||
HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
|
HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
|
||||||
HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
|
HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
|
||||||
|
|
@ -405,24 +402,24 @@ HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEP
|
||||||
HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
|
HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
|
||||||
HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
|
HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
|
||||||
HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
|
HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
|
||||||
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1498)
|
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1509)
|
||||||
HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
|
HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
|
||||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||||
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
|
||||||
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1536)
|
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
|
||||||
HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
|
HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
|
||||||
HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
|
HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
|
||||||
HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
|
HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
|
||||||
HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1932)
|
HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
|
||||||
HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
|
HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
|
||||||
HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
|
HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
|
||||||
HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
|
HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
|
||||||
HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
|
HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
|
||||||
HDL-1200 : Current top model is huagao_mipi_top
|
HDL-1200 : Current top model is huagao_mipi_top
|
||||||
HDL-1100 : Inferred 1 RAMs.
|
HDL-1100 : Inferred 1 RAMs.
|
||||||
RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.071047s wall, 1.031250s user + 0.046875s system = 1.078125s CPU (100.7%)
|
RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.113594s wall, 1.046875s user + 0.062500s system = 1.109375s CPU (99.6%)
|
||||||
|
|
||||||
RUN-1004 : used memory is 202 MB, reserved memory is 177 MB, peak memory is 243 MB
|
RUN-1004 : used memory is 199 MB, reserved memory is 169 MB, peak memory is 240 MB
|
||||||
RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
|
RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
|
||||||
RUN-1001 : Exported /
|
RUN-1001 : Exported /
|
||||||
RUN-1001 : Exported flow parameters
|
RUN-1001 : Exported flow parameters
|
||||||
|
|
@ -603,7 +600,8 @@ SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBU
|
||||||
SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
|
SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
|
||||||
SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
|
SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
|
||||||
SYN-1012 : SanityCheck: Model "scan_start_diff"
|
SYN-1012 : SanityCheck: Model "scan_start_diff"
|
||||||
SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20,WIDTH=13)"
|
SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=13)"
|
||||||
|
SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20)"
|
||||||
SYN-1012 : SanityCheck: Model "ubus_top"
|
SYN-1012 : SanityCheck: Model "ubus_top"
|
||||||
SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
|
SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
|
||||||
SYN-1012 : SanityCheck: Model "CRC4_D16"
|
SYN-1012 : SanityCheck: Model "CRC4_D16"
|
||||||
|
|
@ -653,17 +651,17 @@ RUN-1001 : ua_lvds_rx | false | lvds_rx |
|
||||||
RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
|
RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
|
||||||
RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
|
RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
|
||||||
RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
|
RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
|
||||||
RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20,WIDTH... | ../../../../hg_mp/drx_t...
|
RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t...
|
||||||
RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20,WIDTH... | ../../../../hg_mp/drx_t...
|
RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t...
|
||||||
RUN-1001 : ------------------------------------------------------------------------------------------------
|
RUN-1001 : ------------------------------------------------------------------------------------------------
|
||||||
SYN-1032 : 55777/19243 useful/useless nets, 21967/1798 useful/useless insts
|
SYN-1032 : 54147/19277 useful/useless nets, 20876/1800 useful/useless insts
|
||||||
SYN-1001 : Optimize 156 less-than instances
|
SYN-1001 : Optimize 156 less-than instances
|
||||||
SYN-1016 : Merged 38316 instances.
|
SYN-1016 : Merged 38319 instances.
|
||||||
SYN-1025 : Merged 24 RAM ports.
|
SYN-1025 : Merged 24 RAM ports.
|
||||||
SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
|
SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
|
||||||
SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
|
SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
|
||||||
SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
|
SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
|
||||||
SYN-1032 : 44304/8976 useful/useless nets, 12214/4743 useful/useless insts
|
SYN-1032 : 42673/8976 useful/useless nets, 11122/4743 useful/useless insts
|
||||||
SYN-1016 : Merged 1876 instances.
|
SYN-1016 : Merged 1876 instances.
|
||||||
SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
|
SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
|
||||||
SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
|
SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
|
||||||
|
|
@ -1175,7 +1173,7 @@ SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16
|
||||||
SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
|
SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
|
||||||
SYN-5014 Similar messages will be suppressed.
|
SYN-5014 Similar messages will be suppressed.
|
||||||
SYN-5025 WARNING: Using 0 for all undriven pins and nets
|
SYN-5025 WARNING: Using 0 for all undriven pins and nets
|
||||||
SYN-1032 : 41977/363 useful/useless nets, 39174/558 useful/useless insts
|
SYN-1032 : 40346/363 useful/useless nets, 37543/558 useful/useless insts
|
||||||
SYN-1014 : Optimize round 1
|
SYN-1014 : Optimize round 1
|
||||||
SYN-1017 : Remove 16 const input seq instances
|
SYN-1017 : Remove 16 const input seq instances
|
||||||
SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
|
SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
|
||||||
|
|
@ -1201,10 +1199,10 @@ SYN-1020 : Optimized 3951 distributor mux.
|
||||||
SYN-1001 : Optimize 12 less-than instances
|
SYN-1001 : Optimize 12 less-than instances
|
||||||
SYN-1019 : Optimized 39 mux instances.
|
SYN-1019 : Optimized 39 mux instances.
|
||||||
SYN-1016 : Merged 6256 instances.
|
SYN-1016 : Merged 6256 instances.
|
||||||
SYN-1015 : Optimize round 1, 30452 better
|
SYN-1015 : Optimize round 1, 29939 better
|
||||||
SYN-1014 : Optimize round 2
|
SYN-1014 : Optimize round 2
|
||||||
SYN-1044 : Optimized 15 inv instances.
|
SYN-1044 : Optimized 15 inv instances.
|
||||||
SYN-1032 : 27603/1547 useful/useless nets, 24892/7583 useful/useless insts
|
SYN-1032 : 25972/1547 useful/useless nets, 23261/7583 useful/useless insts
|
||||||
SYN-1017 : Remove 29 const input seq instances
|
SYN-1017 : Remove 29 const input seq instances
|
||||||
SYN-1002 : reg18_syn_2
|
SYN-1002 : reg18_syn_2
|
||||||
SYN-1002 : reg22_syn_2
|
SYN-1002 : reg22_syn_2
|
||||||
|
|
@ -1239,7 +1237,7 @@ SYN-1019 : Optimized 24 mux instances.
|
||||||
SYN-1020 : Optimized 43 distributor mux.
|
SYN-1020 : Optimized 43 distributor mux.
|
||||||
SYN-1016 : Merged 118 instances.
|
SYN-1016 : Merged 118 instances.
|
||||||
SYN-1015 : Optimize round 2, 9427 better
|
SYN-1015 : Optimize round 2, 9427 better
|
||||||
SYN-1032 : 27354/80 useful/useless nets, 24675/112 useful/useless insts
|
SYN-1032 : 25723/80 useful/useless nets, 23044/112 useful/useless insts
|
||||||
SYN-3004 : Optimized 2 const0 DFF(s)
|
SYN-3004 : Optimized 2 const0 DFF(s)
|
||||||
SYN-3004 : Optimized 8 const0 DFF(s)
|
SYN-3004 : Optimized 8 const0 DFF(s)
|
||||||
SYN-3008 : Optimized 1 const1 DFF(s)
|
SYN-3008 : Optimized 1 const1 DFF(s)
|
||||||
|
|
@ -1306,20 +1304,20 @@ SYN-3003 : Optimized 1 equivalent DFF(s)
|
||||||
SYN-3003 : Optimized 1 equivalent DFF(s)
|
SYN-3003 : Optimized 1 equivalent DFF(s)
|
||||||
SYN-3003 : Optimized 1 equivalent DFF(s)
|
SYN-3003 : Optimized 1 equivalent DFF(s)
|
||||||
SYN-3004 : Optimized 2 const0 DFF(s)
|
SYN-3004 : Optimized 2 const0 DFF(s)
|
||||||
SYN-1032 : 27261/93 useful/useless nets, 24593/6 useful/useless insts
|
SYN-1032 : 25630/93 useful/useless nets, 22962/6 useful/useless insts
|
||||||
SYN-1014 : Optimize round 1
|
SYN-1014 : Optimize round 1
|
||||||
SYN-1019 : Optimized 228 mux instances.
|
SYN-1019 : Optimized 228 mux instances.
|
||||||
SYN-1020 : Optimized 2 distributor mux.
|
SYN-1020 : Optimized 2 distributor mux.
|
||||||
SYN-1016 : Merged 3 instances.
|
SYN-1016 : Merged 3 instances.
|
||||||
SYN-1015 : Optimize round 1, 279 better
|
SYN-1015 : Optimize round 1, 279 better
|
||||||
SYN-1014 : Optimize round 2
|
SYN-1014 : Optimize round 2
|
||||||
SYN-1032 : 26983/20 useful/useless nets, 24331/2 useful/useless insts
|
SYN-1032 : 25352/20 useful/useless nets, 22700/2 useful/useless insts
|
||||||
SYN-1015 : Optimize round 2, 2 better
|
SYN-1015 : Optimize round 2, 2 better
|
||||||
SYN-1014 : Optimize round 3
|
SYN-1014 : Optimize round 3
|
||||||
SYN-1015 : Optimize round 3, 0 better
|
SYN-1015 : Optimize round 3, 0 better
|
||||||
RUN-1003 : finish command "optimize_rtl" in 19.481519s wall, 16.921875s user + 2.562500s system = 19.484375s CPU (100.0%)
|
RUN-1003 : finish command "optimize_rtl" in 18.914664s wall, 16.640625s user + 2.218750s system = 18.859375s CPU (99.7%)
|
||||||
|
|
||||||
RUN-1004 : used memory is 340 MB, reserved memory is 308 MB, peak memory is 359 MB
|
RUN-1004 : used memory is 335 MB, reserved memory is 304 MB, peak memory is 354 MB
|
||||||
RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
|
RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
|
||||||
RUN-1001 : standard
|
RUN-1001 : standard
|
||||||
***Report Model: huagao_mipi_top Device: EG4D20EG176***
|
***Report Model: huagao_mipi_top Device: EG4D20EG176***
|
||||||
|
|
@ -1331,31 +1329,31 @@ IO Statistics
|
||||||
#inout 0
|
#inout 0
|
||||||
|
|
||||||
Gate Statistics
|
Gate Statistics
|
||||||
#Basic gates 14522
|
#Basic gates 14015
|
||||||
#and 2480
|
#and 2480
|
||||||
#nand 0
|
#nand 0
|
||||||
#or 1078
|
#or 1078
|
||||||
#nor 0
|
#nor 0
|
||||||
#xor 204
|
#xor 207
|
||||||
#xnor 0
|
#xnor 0
|
||||||
#buf 0
|
#buf 0
|
||||||
#not 469
|
#not 469
|
||||||
#bufif1 5
|
#bufif1 5
|
||||||
#MX21 615
|
#MX21 618
|
||||||
#FADD 0
|
#FADD 0
|
||||||
#DFF 9665
|
#DFF 9152
|
||||||
#LATCH 6
|
#LATCH 6
|
||||||
#MACRO_ADD 497
|
#MACRO_ADD 497
|
||||||
#MACRO_EQ 227
|
#MACRO_EQ 225
|
||||||
#MACRO_MULT 4
|
#MACRO_MULT 4
|
||||||
#MACRO_MUX 4839
|
#MACRO_MUX 4813
|
||||||
#MACRO_OTHERS 73
|
#MACRO_OTHERS 73
|
||||||
|
|
||||||
Report Hierarchy Area:
|
Report Hierarchy Area:
|
||||||
+----------------------------------------------------------------------------+
|
+----------------------------------------------------------------------------+
|
||||||
|Instance |Module |gates |seq |macros |
|
|Instance |Module |gates |seq |macros |
|
||||||
+----------------------------------------------------------------------------+
|
+----------------------------------------------------------------------------+
|
||||||
|top |huagao_mipi_top |4851 |9671 |801 |
|
|top |huagao_mipi_top |4857 |9158 |799 |
|
||||||
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
|
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
|
||||||
| U_crc16_24b |crc16_24b |67 |16 |0 |
|
| U_crc16_24b |crc16_24b |67 |16 |0 |
|
||||||
| U_ecc_gen |ecc_gen |37 |6 |0 |
|
| U_ecc_gen |ecc_gen |37 |6 |0 |
|
||||||
|
|
@ -1474,9 +1472,9 @@ RUN-1001 : Exported congestions
|
||||||
RUN-1001 : Exported violations
|
RUN-1001 : Exported violations
|
||||||
RUN-1001 : Exported IO constraints
|
RUN-1001 : Exported IO constraints
|
||||||
RUN-1001 : Exported Inst constraints
|
RUN-1001 : Exported Inst constraints
|
||||||
RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.122930s wall, 1.734375s user + 0.031250s system = 1.765625s CPU (157.2%)
|
RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.112412s wall, 1.718750s user + 0.015625s system = 1.734375s CPU (155.9%)
|
||||||
|
|
||||||
RUN-1004 : used memory is 336 MB, reserved memory is 306 MB, peak memory is 410 MB
|
RUN-1004 : used memory is 330 MB, reserved memory is 300 MB, peak memory is 404 MB
|
||||||
RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
|
RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
|
||||||
RUN-1002 : start command "get_ports clock_source"
|
RUN-1002 : start command "get_ports clock_source"
|
||||||
RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
|
RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
|
||||||
|
|
@ -1514,42 +1512,6 @@ RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_c
|
||||||
RUN-1002 : start command "get_ports clock_source"
|
RUN-1002 : start command "get_ports clock_source"
|
||||||
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
|
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
|
||||||
RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
|
RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
|
||||||
RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
|
|
||||||
RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
|
|
||||||
RUN-1002 : start command "set_false_path -from -to "
|
|
||||||
RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]"
|
|
||||||
RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]"
|
|
||||||
RUN-1002 : start command "set_false_path -from -to "
|
|
||||||
RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]"
|
|
||||||
RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]"
|
|
||||||
RUN-1002 : start command "set_false_path -from -to "
|
|
||||||
RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]"
|
|
||||||
RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]"
|
|
||||||
RUN-1002 : start command "set_false_path -from -to "
|
|
||||||
RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]"
|
|
||||||
RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]"
|
|
||||||
RUN-1002 : start command "set_false_path -from -to "
|
|
||||||
RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]"
|
|
||||||
RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]"
|
|
||||||
RUN-1002 : start command "set_false_path -from -to "
|
|
||||||
RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]"
|
|
||||||
RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]"
|
|
||||||
RUN-1002 : start command "set_false_path -from -to "
|
|
||||||
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
|
|
||||||
RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
|
|
||||||
RUN-1002 : start command "set_false_path -setup -from -to "
|
|
||||||
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
|
|
||||||
RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
|
|
||||||
RUN-1002 : start command "set_false_path -setup -from -to "
|
|
||||||
RUN-1002 : start command "get_regs BUSY_MIPI"
|
|
||||||
RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
|
|
||||||
RUN-1002 : start command "set_false_path -from -to "
|
|
||||||
RUN-1002 : start command "get_regs clkubus_rstn"
|
|
||||||
RUN-1002 : start command "get_nets a_pclk_rstn"
|
|
||||||
RUN-1002 : start command "set_false_path -from -to "
|
|
||||||
RUN-1002 : start command "get_regs clkubus_rstn"
|
|
||||||
RUN-1002 : start command "get_nets b_pclk_rstn"
|
|
||||||
RUN-1002 : start command "set_false_path -from -to "
|
|
||||||
RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
|
RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
|
||||||
RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
|
RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
|
||||||
RUN-1002 : start command "set_false_path -from -to "
|
RUN-1002 : start command "set_false_path -from -to "
|
||||||
|
|
@ -1590,7 +1552,7 @@ RUN-1001 : report | standard | standard |
|
||||||
RUN-1001 : retiming | off | off |
|
RUN-1001 : retiming | off | off |
|
||||||
RUN-1001 : ------------------------------------------------------------------
|
RUN-1001 : ------------------------------------------------------------------
|
||||||
SYN-2001 : Map 61 IOs to PADs
|
SYN-2001 : Map 61 IOs to PADs
|
||||||
SYN-1032 : 27017/24 useful/useless nets, 24380/26 useful/useless insts
|
SYN-1032 : 25386/24 useful/useless nets, 22749/26 useful/useless insts
|
||||||
RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
|
RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
|
||||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||||
SYN-2501 : 3 BUFG to GCLK
|
SYN-2501 : 3 BUFG to GCLK
|
||||||
|
|
@ -1654,7 +1616,7 @@ SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
|
||||||
SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
|
SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
|
||||||
SYN-2571 : Map 4 macro multiplier
|
SYN-2571 : Map 4 macro multiplier
|
||||||
SYN-2571 : Optimize after map_dsp, round 1
|
SYN-2571 : Optimize after map_dsp, round 1
|
||||||
SYN-1032 : 27335/670 useful/useless nets, 24714/580 useful/useless insts
|
SYN-1032 : 25704/670 useful/useless nets, 23083/580 useful/useless insts
|
||||||
SYN-1016 : Merged 11 instances.
|
SYN-1016 : Merged 11 instances.
|
||||||
SYN-2571 : Optimize after map_dsp, round 1, 1181 better
|
SYN-2571 : Optimize after map_dsp, round 1, 1181 better
|
||||||
SYN-2571 : Optimize after map_dsp, round 2
|
SYN-2571 : Optimize after map_dsp, round 2
|
||||||
|
|
@ -1662,7 +1624,7 @@ SYN-2571 : Optimize after map_dsp, round 2, 0 better
|
||||||
SYN-1001 : Throwback 317 control mux instances
|
SYN-1001 : Throwback 317 control mux instances
|
||||||
SYN-1001 : Convert 12 adder
|
SYN-1001 : Convert 12 adder
|
||||||
SYN-2501 : Optimize round 1
|
SYN-2501 : Optimize round 1
|
||||||
SYN-1032 : 30821/338 useful/useless nets, 28201/38 useful/useless insts
|
SYN-1032 : 29140/338 useful/useless nets, 26520/38 useful/useless insts
|
||||||
SYN-1016 : Merged 396 instances.
|
SYN-1016 : Merged 396 instances.
|
||||||
SYN-2501 : Optimize round 1, 1774 better
|
SYN-2501 : Optimize round 1, 1774 better
|
||||||
SYN-2501 : Optimize round 2
|
SYN-2501 : Optimize round 2
|
||||||
|
|
@ -1693,30 +1655,30 @@ SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
|
||||||
SYN-2501 : Inferred 22 ROM instances
|
SYN-2501 : Inferred 22 ROM instances
|
||||||
SYN-1019 : Optimized 9690 mux instances.
|
SYN-1019 : Optimized 9690 mux instances.
|
||||||
SYN-1016 : Merged 12105 instances.
|
SYN-1016 : Merged 12105 instances.
|
||||||
SYN-1032 : 38365/296 useful/useless nets, 35639/0 useful/useless insts
|
SYN-1032 : 36684/296 useful/useless nets, 33958/0 useful/useless insts
|
||||||
RUN-1002 : start command "start_timer -prepack"
|
RUN-1002 : start command "start_timer -prepack"
|
||||||
TMR-2505 : Start building timing graph for model huagao_mipi_top.
|
TMR-2505 : Start building timing graph for model huagao_mipi_top.
|
||||||
TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 126687, tnet num: 38367, tinst num: 35639, tnode num: 164251, tedge num: 187234.
|
TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122210, tnet num: 36686, tinst num: 33958, tnode num: 156562, tedge num: 180011.
|
||||||
TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
|
TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
|
||||||
TMR-2501 : Timing graph initialized successfully.
|
TMR-2501 : Timing graph initialized successfully.
|
||||||
RUN-1003 : finish command "start_timer -prepack" in 1.326087s wall, 1.281250s user + 0.046875s system = 1.328125s CPU (100.2%)
|
RUN-1003 : finish command "start_timer -prepack" in 1.289776s wall, 1.265625s user + 0.015625s system = 1.281250s CPU (99.3%)
|
||||||
|
|
||||||
RUN-1004 : used memory is 536 MB, reserved memory is 512 MB, peak memory is 536 MB
|
RUN-1004 : used memory is 521 MB, reserved memory is 497 MB, peak memory is 521 MB
|
||||||
TMR-2503 : Start to update net delay, extr mode = 2.
|
TMR-2503 : Start to update net delay, extr mode = 2.
|
||||||
TMR-2504 : Update delay of 38367 nets completely.
|
TMR-2504 : Update delay of 36686 nets completely.
|
||||||
TMR-2502 : Annotate delay completely, extr mode = 2.
|
TMR-2502 : Annotate delay completely, extr mode = 2.
|
||||||
TMR-3001 : Initiate 12 clocks from SDC.
|
TMR-3001 : Initiate 12 clocks from SDC.
|
||||||
TMR-3004 : Map sdc constraints, there are 14 constraints in total.
|
TMR-3004 : Map sdc constraints, there are 2 constraints in total.
|
||||||
TMR-3003 : Constraints initiated successfully.
|
TMR-3003 : Constraints initiated successfully.
|
||||||
TMR-3501 : Forward propagation: start to calculate arrival time...
|
TMR-3501 : Forward propagation: start to calculate arrival time...
|
||||||
TMR-3502 : Backward propagation: start to calculate required time...
|
TMR-3502 : Backward propagation: start to calculate required time...
|
||||||
TMR-3503 : Timing propagation completes.
|
TMR-3503 : Timing propagation completes.
|
||||||
SYN-3001 : Running gate level optimization.
|
SYN-3001 : Running gate level optimization.
|
||||||
SYN-2581 : Mapping with K=5, #lut = 7521 (3.86), #lev = 9 (3.15)
|
SYN-2581 : Mapping with K=5, #lut = 7492 (3.85), #lev = 9 (3.15)
|
||||||
SYN-2551 : Post LUT mapping optimization.
|
SYN-2551 : Post LUT mapping optimization.
|
||||||
SYN-2581 : Mapping with K=5, #lut = 7427 (3.95), #lev = 7 (3.06)
|
SYN-2581 : Mapping with K=5, #lut = 7309 (3.95), #lev = 7 (3.04)
|
||||||
SYN-3001 : Logic optimization runtime opt = 1.25 sec, map = 0.00 sec
|
SYN-3001 : Logic optimization runtime opt = 1.26 sec, map = 0.00 sec
|
||||||
SYN-3001 : Mapper mapped 18994 instances into 7455 LUTs, name keeping = 58%.
|
SYN-3001 : Mapper mapped 18922 instances into 7337 LUTs, name keeping = 61%.
|
||||||
SYN-3001 : Mapper removed 2 lut buffers
|
SYN-3001 : Mapper removed 2 lut buffers
|
||||||
RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
|
RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
|
||||||
RUN-1001 : standard
|
RUN-1001 : standard
|
||||||
|
|
@ -1729,16 +1691,16 @@ IO Statistics
|
||||||
#inout 0
|
#inout 0
|
||||||
|
|
||||||
LUT Statistics
|
LUT Statistics
|
||||||
#Total_luts 10030
|
#Total_luts 9912
|
||||||
#lut4 5343
|
#lut4 5066
|
||||||
#lut5 2132
|
#lut5 2291
|
||||||
#lut6 0
|
#lut6 0
|
||||||
#lut5_mx41 0
|
#lut5_mx41 0
|
||||||
#lut4_alu1b 2555
|
#lut4_alu1b 2555
|
||||||
|
|
||||||
Utilization Statistics
|
Utilization Statistics
|
||||||
#lut 10030 out of 19600 51.17%
|
#lut 9912 out of 19600 50.57%
|
||||||
#reg 9745 out of 19600 49.72%
|
#reg 9232 out of 19600 47.10%
|
||||||
#le 0
|
#le 0
|
||||||
#dsp 3 out of 29 10.34%
|
#dsp 3 out of 29 10.34%
|
||||||
#bram 54 out of 64 84.38%
|
#bram 54 out of 64 84.38%
|
||||||
|
|
@ -1748,7 +1710,7 @@ Utilization Statistics
|
||||||
#dram 16
|
#dram 16
|
||||||
#pad 75 out of 130 57.69%
|
#pad 75 out of 130 57.69%
|
||||||
#ireg 13
|
#ireg 13
|
||||||
#oreg 19
|
#oreg 21
|
||||||
#treg 0
|
#treg 0
|
||||||
#pll 3 out of 4 75.00%
|
#pll 3 out of 4 75.00%
|
||||||
|
|
||||||
|
|
@ -1756,30 +1718,30 @@ Report Hierarchy Area:
|
||||||
+-------------------------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------------------------+
|
||||||
|Instance |Module |lut |ripple |seq |bram |dsp |
|
|Instance |Module |lut |ripple |seq |bram |dsp |
|
||||||
+-------------------------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------------------------+
|
||||||
|top |huagao_mipi_top |7475 |2555 |9777 |58 |3 |
|
|top |huagao_mipi_top |7357 |2555 |9266 |58 |3 |
|
||||||
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |336 |81 |441 |4 |1 |
|
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |343 |81 |441 |4 |1 |
|
||||||
| U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 |
|
| U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 |
|
||||||
| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
|
| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
|
||||||
| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
|
| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
|
||||||
| exdev_ctl_a |exdev_ctl |283 |234 |559 |0 |0 |
|
| exdev_ctl_a |exdev_ctl |288 |234 |559 |0 |0 |
|
||||||
| u_ADconfig |AD_config |98 |49 |138 |0 |0 |
|
| u_ADconfig |AD_config |102 |49 |138 |0 |0 |
|
||||||
| u_gen_sp |gen_sp |127 |185 |104 |0 |0 |
|
| u_gen_sp |gen_sp |128 |185 |104 |0 |0 |
|
||||||
| exdev_ctl_b |exdev_ctl |277 |234 |546 |0 |0 |
|
| exdev_ctl_b |exdev_ctl |276 |234 |546 |0 |0 |
|
||||||
| u_ADconfig |AD_config |93 |49 |125 |0 |0 |
|
| u_ADconfig |AD_config |92 |49 |125 |0 |0 |
|
||||||
| u_gen_sp |gen_sp |126 |185 |104 |0 |0 |
|
| u_gen_sp |gen_sp |126 |185 |104 |0 |0 |
|
||||||
| sampling_fe_a |sampling_fe |2334 |738 |1919 |25 |0 |
|
| sampling_fe_a |sampling_fe |2277 |738 |1919 |25 |0 |
|
||||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
|
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
|
||||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_sort |sort |2264 |691 |1737 |25 |0 |
|
| u_sort |sort |2207 |691 |1737 |25 |0 |
|
||||||
| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
|
| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
|
||||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_data_prebuffer |data_prebuffer |1922 |615 |1391 |22 |0 |
|
| u_data_prebuffer |data_prebuffer |1866 |615 |1391 |22 |0 |
|
||||||
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
|
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
|
||||||
| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
|
| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
|
||||||
| ram_switch |ram_switch |1483 |422 |1023 |0 |0 |
|
| ram_switch |ram_switch |1444 |422 |1023 |0 |0 |
|
||||||
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
|
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
|
||||||
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
|
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
|
||||||
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||||
|
|
@ -1791,10 +1753,10 @@ Report Hierarchy Area:
|
||||||
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||||
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||||
| insert |insert |265 |323 |692 |0 |0 |
|
| insert |insert |265 |323 |692 |0 |0 |
|
||||||
| ram_switch_state |ram_switch_state |1089 |0 |216 |0 |0 |
|
| ram_switch_state |ram_switch_state |1050 |0 |216 |0 |0 |
|
||||||
| read_ram_i |read_ram |206 |158 |164 |0 |0 |
|
| read_ram_i |read_ram |189 |158 |164 |0 |0 |
|
||||||
| read_ram_addr |read_ram_addr |173 |145 |127 |0 |0 |
|
| read_ram_addr |read_ram_addr |161 |145 |127 |0 |0 |
|
||||||
| read_ram_data |read_ram_data |32 |13 |32 |0 |0 |
|
| read_ram_data |read_ram_data |27 |13 |32 |0 |0 |
|
||||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||||
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||||
|
|
@ -1821,19 +1783,19 @@ Report Hierarchy Area:
|
||||||
| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 |
|
| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 |
|
||||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
|
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
|
||||||
| sampling_fe_b |sampling_fe_rev |2334 |751 |1936 |25 |1 |
|
| sampling_fe_b |sampling_fe_rev |2297 |751 |1936 |25 |1 |
|
||||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
|
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
|
||||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_sort |sort_rev |2264 |704 |1754 |25 |1 |
|
| u_sort |sort_rev |2227 |704 |1754 |25 |1 |
|
||||||
| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
|
| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
|
||||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||||
| u_data_prebuffer_rev |data_prebuffer_rev |1925 |628 |1408 |22 |1 |
|
| u_data_prebuffer_rev |data_prebuffer_rev |1888 |628 |1408 |22 |1 |
|
||||||
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
|
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
|
||||||
| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
|
| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
|
||||||
| ram_switch |ram_switch |1484 |422 |1023 |0 |0 |
|
| ram_switch |ram_switch |1443 |422 |1023 |0 |0 |
|
||||||
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
|
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
|
||||||
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
|
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
|
||||||
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||||
|
|
@ -1845,10 +1807,10 @@ Report Hierarchy Area:
|
||||||
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||||
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||||
| insert |insert |265 |323 |692 |0 |0 |
|
| insert |insert |265 |323 |692 |0 |0 |
|
||||||
| ram_switch_state |ram_switch_state |1090 |0 |216 |0 |0 |
|
| ram_switch_state |ram_switch_state |1049 |0 |216 |0 |0 |
|
||||||
| read_ram_i |read_ram_rev |206 |171 |181 |0 |0 |
|
| read_ram_i |read_ram_rev |210 |171 |181 |0 |0 |
|
||||||
| read_ram_addr |read_ram_addr_rev |180 |145 |139 |0 |0 |
|
| read_ram_addr |read_ram_addr_rev |182 |145 |139 |0 |0 |
|
||||||
| read_ram_data |read_ram_data_rev |26 |26 |42 |0 |0 |
|
| read_ram_data |read_ram_data_rev |28 |26 |42 |0 |0 |
|
||||||
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||||
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||||
| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||||
|
|
@ -1864,7 +1826,7 @@ SYN-1001 : Packing model "huagao_mipi_top" ...
|
||||||
SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
|
SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
|
||||||
SYN-1014 : Optimize round 1
|
SYN-1014 : Optimize round 1
|
||||||
SYN-1015 : Optimize round 1, 0 better
|
SYN-1015 : Optimize round 1, 0 better
|
||||||
SYN-4002 : Packing 9745 DFF/LATCH to SEQ ...
|
SYN-4002 : Packing 9232 DFF/LATCH to SEQ ...
|
||||||
SYN-4009 : Pack 83 carry chain into lslice
|
SYN-4009 : Pack 83 carry chain into lslice
|
||||||
SYN-4007 : Packing 1278 adder to BLE ...
|
SYN-4007 : Packing 1278 adder to BLE ...
|
||||||
SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
|
SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
|
||||||
|
|
@ -1872,9 +1834,9 @@ SYN-4007 : Packing 0 gate4 to BLE ...
|
||||||
SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
|
SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
|
||||||
SYN-4012 : Packed 0 FxMUX
|
SYN-4012 : Packed 0 FxMUX
|
||||||
SYN-4013 : Packed 16 DRAM and 4 SEQ.
|
SYN-4013 : Packed 16 DRAM and 4 SEQ.
|
||||||
RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 60.377693s wall, 59.921875s user + 0.453125s system = 60.375000s CPU (100.0%)
|
RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 58.555008s wall, 58.328125s user + 0.187500s system = 58.515625s CPU (99.9%)
|
||||||
|
|
||||||
RUN-1004 : used memory is 399 MB, reserved memory is 376 MB, peak memory is 726 MB
|
RUN-1004 : used memory is 399 MB, reserved memory is 388 MB, peak memory is 704 MB
|
||||||
RUN-1002 : start command "legalize_phy_inst"
|
RUN-1002 : start command "legalize_phy_inst"
|
||||||
SYN-1011 : Flatten model huagao_mipi_top
|
SYN-1011 : Flatten model huagao_mipi_top
|
||||||
SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
|
SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
|
||||||
|
|
@ -1894,8 +1856,8 @@ RUN-1001 : Exported violations
|
||||||
RUN-1001 : Exported timing constraints
|
RUN-1001 : Exported timing constraints
|
||||||
RUN-1001 : Exported IO constraints
|
RUN-1001 : Exported IO constraints
|
||||||
RUN-1001 : Exported Inst constraints
|
RUN-1001 : Exported Inst constraints
|
||||||
RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.605917s wall, 2.781250s user + 0.015625s system = 2.796875s CPU (174.2%)
|
RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.568878s wall, 2.703125s user + 0.015625s system = 2.718750s CPU (173.3%)
|
||||||
|
|
||||||
RUN-1004 : used memory is 415 MB, reserved memory is 399 MB, peak memory is 726 MB
|
RUN-1004 : used memory is 406 MB, reserved memory is 382 MB, peak memory is 704 MB
|
||||||
RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_145044.log"
|
RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_163838.log"
|
||||||
RUN-1001 : Backing up run's log file succeed.
|
RUN-1001 : Backing up run's log file succeed.
|
||||||
|
|
|
||||||
|
|
@ -4394,3 +4394,238 @@ RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_m
|
||||||
RUN-1004 : used memory is 2212 MB, reserved memory is 2214 MB, peak memory is 2314 MB
|
RUN-1004 : used memory is 2212 MB, reserved memory is 2214 MB, peak memory is 2314 MB
|
||||||
RUN-1001 : reset_run syn_1 phy_1.
|
RUN-1001 : reset_run syn_1 phy_1.
|
||||||
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
|
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
|
||||||
|
RUN-1001 : stop_run syn_1.
|
||||||
|
RUN-1001 : reset_run syn_1 -step opt_gate.
|
||||||
|
RUN-1001 : syn_1: run complete.
|
||||||
|
RUN-1001 : open_run syn_1.
|
||||||
|
RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db"
|
||||||
|
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
|
||||||
|
RUN-1001 : Database version number 46146.
|
||||||
|
RUN-1001 : Import flow parameters
|
||||||
|
RUN-1001 : Import IO constraints
|
||||||
|
RUN-1001 : Import Inst constraints
|
||||||
|
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
|
||||||
|
RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db" in 1.717677s wall, 1.390625s user + 0.125000s system = 1.515625s CPU (88.2%)
|
||||||
|
|
||||||
|
RUN-1004 : used memory is 2225 MB, reserved memory is 2227 MB, peak memory is 2314 MB
|
||||||
|
HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
|
||||||
|
RUN-1001 : reset_run syn_1 phy_1.
|
||||||
|
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
|
||||||
|
RUN-1001 : syn_1: run complete.
|
||||||
|
RUN-1001 : phy_1: run complete.
|
||||||
|
RUN-1001 : open_run phy_1.
|
||||||
|
RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
|
||||||
|
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
|
||||||
|
RUN-1001 : Database version number 46146.
|
||||||
|
RUN-1001 : Import flow parameters
|
||||||
|
PHY-1001 : Generate detailed routing grids ...
|
||||||
|
PHY-1001 : Generate nets ...
|
||||||
|
PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||||
|
PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||||
|
PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
|
||||||
|
PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
|
||||||
|
PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
|
||||||
|
PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
|
||||||
|
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
|
||||||
|
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
|
||||||
|
PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
|
||||||
|
PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
|
||||||
|
PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
|
||||||
|
PHY-5010 Similar messages will be suppressed.
|
||||||
|
PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
|
||||||
|
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
|
||||||
|
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
|
||||||
|
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
|
||||||
|
PHY-1001 : eco open net = 0
|
||||||
|
PHY-1001 : 475 feed throughs used by 371 nets
|
||||||
|
RUN-1001 : Import timing constraints
|
||||||
|
RUN-1001 : Import IO constraints
|
||||||
|
RUN-1001 : Import Inst constraints
|
||||||
|
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
|
||||||
|
RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 8.883825s wall, 8.921875s user + 0.296875s system = 9.218750s CPU (103.8%)
|
||||||
|
|
||||||
|
RUN-1004 : used memory is 2322 MB, reserved memory is 2326 MB, peak memory is 2338 MB
|
||||||
|
TMR-3509 : Import timing summary.
|
||||||
|
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
|
||||||
|
PRG-2014 : Chip validation success: EAGLE_S20_EG176
|
||||||
|
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||||
|
RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
|
||||||
|
RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.733013s wall, 0.265625s user + 0.250000s system = 0.515625s CPU (2.9%)
|
||||||
|
|
||||||
|
RUN-1004 : used memory is 2330 MB, reserved memory is 2332 MB, peak memory is 2349 MB
|
||||||
|
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.948798s wall, 0.375000s user + 0.265625s system = 0.640625s CPU (3.6%)
|
||||||
|
|
||||||
|
RUN-1004 : used memory is 2330 MB, reserved memory is 2332 MB, peak memory is 2349 MB
|
||||||
|
GUI-1001 : Downloading succeeded!
|
||||||
|
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
|
||||||
|
PRG-2014 : Chip validation success: EAGLE_S20_EG176
|
||||||
|
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||||
|
RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
|
||||||
|
RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.766793s wall, 0.062500s user + 0.093750s system = 0.156250s CPU (0.9%)
|
||||||
|
|
||||||
|
RUN-1004 : used memory is 2330 MB, reserved memory is 2332 MB, peak memory is 2349 MB
|
||||||
|
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.984587s wall, 0.187500s user + 0.109375s system = 0.296875s CPU (1.7%)
|
||||||
|
|
||||||
|
RUN-1004 : used memory is 2330 MB, reserved memory is 2332 MB, peak memory is 2349 MB
|
||||||
|
GUI-1001 : Downloading succeeded!
|
||||||
|
TMR-3509 : Import timing summary.
|
||||||
|
HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
|
||||||
|
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
|
||||||
|
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
|
||||||
|
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
|
||||||
|
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
|
||||||
|
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
|
||||||
|
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(720)
|
||||||
|
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(729)
|
||||||
|
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(753)
|
||||||
|
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(755)
|
||||||
|
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(761)
|
||||||
|
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(764)
|
||||||
|
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(935)
|
||||||
|
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1024)
|
||||||
|
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1325)
|
||||||
|
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1336)
|
||||||
|
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1354)
|
||||||
|
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1536)
|
||||||
|
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1932)
|
||||||
|
RUN-1001 : reset_run syn_1 phy_1.
|
||||||
|
GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
|
||||||
|
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
|
||||||
|
RUN-1001 : syn_1: run complete.
|
||||||
|
RUN-1001 : phy_1: run complete.
|
||||||
|
RUN-1001 : open_run phy_1.
|
||||||
|
RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
|
||||||
|
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
|
||||||
|
RUN-1001 : Database version number 46146.
|
||||||
|
RUN-1001 : Import flow parameters
|
||||||
|
PHY-1001 : Generate detailed routing grids ...
|
||||||
|
PHY-1001 : Generate nets ...
|
||||||
|
PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||||
|
PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||||
|
PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
|
||||||
|
PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
|
||||||
|
PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
|
||||||
|
PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
|
||||||
|
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
|
||||||
|
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
|
||||||
|
PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
|
||||||
|
PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
|
||||||
|
PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
|
||||||
|
PHY-5010 Similar messages will be suppressed.
|
||||||
|
PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
|
||||||
|
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
|
||||||
|
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
|
||||||
|
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
|
||||||
|
PHY-1001 : eco open net = 0
|
||||||
|
PHY-1001 : 588 feed throughs used by 440 nets
|
||||||
|
RUN-1001 : Import timing constraints
|
||||||
|
RUN-1001 : Import IO constraints
|
||||||
|
RUN-1001 : Import Inst constraints
|
||||||
|
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
|
||||||
|
RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 9.152214s wall, 9.234375s user + 0.296875s system = 9.531250s CPU (104.1%)
|
||||||
|
|
||||||
|
RUN-1004 : used memory is 2375 MB, reserved memory is 2376 MB, peak memory is 2386 MB
|
||||||
|
TMR-3509 : Import timing summary.
|
||||||
|
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
|
||||||
|
PRG-2014 : Chip validation success: EAGLE_S20_EG176
|
||||||
|
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||||
|
RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
|
||||||
|
RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.713168s wall, 0.734375s user + 0.593750s system = 1.328125s CPU (7.5%)
|
||||||
|
|
||||||
|
RUN-1004 : used memory is 2380 MB, reserved memory is 2381 MB, peak memory is 2399 MB
|
||||||
|
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.931766s wall, 0.859375s user + 0.609375s system = 1.468750s CPU (8.2%)
|
||||||
|
|
||||||
|
RUN-1004 : used memory is 2380 MB, reserved memory is 2381 MB, peak memory is 2399 MB
|
||||||
|
GUI-1001 : Downloading succeeded!
|
||||||
|
RUN-1001 : reset_run phy_1 -step opt_place.
|
||||||
|
RUN-8001 ERROR: Run syn_1 should be up to date.
|
||||||
|
GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
|
||||||
|
RUN-1001 : reset_run syn_1 phy_1.
|
||||||
|
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
|
||||||
|
RUN-1001 : syn_1: run complete.
|
||||||
|
RUN-1001 : phy_1: run complete.
|
||||||
|
RUN-1001 : open_run phy_1.
|
||||||
|
RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
|
||||||
|
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
|
||||||
|
RUN-1001 : Database version number 46146.
|
||||||
|
RUN-1001 : Import flow parameters
|
||||||
|
PHY-1001 : Generate detailed routing grids ...
|
||||||
|
PHY-1001 : Generate nets ...
|
||||||
|
PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||||
|
PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||||
|
PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
|
||||||
|
PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
|
||||||
|
PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
|
||||||
|
PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
|
||||||
|
PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
|
||||||
|
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
|
||||||
|
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
|
||||||
|
PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
|
||||||
|
PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
|
||||||
|
PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
|
||||||
|
PHY-5010 Similar messages will be suppressed.
|
||||||
|
PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
|
||||||
|
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
|
||||||
|
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
|
||||||
|
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
|
||||||
|
PHY-1001 : eco open net = 0
|
||||||
|
PHY-1001 : 604 feed throughs used by 440 nets
|
||||||
|
RUN-1001 : Import timing constraints
|
||||||
|
RUN-1001 : Import IO constraints
|
||||||
|
RUN-1001 : Import Inst constraints
|
||||||
|
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
|
||||||
|
RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 9.117688s wall, 9.171875s user + 0.296875s system = 9.468750s CPU (103.9%)
|
||||||
|
|
||||||
|
RUN-1004 : used memory is 2398 MB, reserved memory is 2398 MB, peak memory is 2412 MB
|
||||||
|
TMR-3509 : Import timing summary.
|
||||||
|
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
|
||||||
|
PRG-2014 : Chip validation success: EAGLE_S20_EG176
|
||||||
|
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||||
|
RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
|
||||||
|
RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.801503s wall, 0.156250s user + 0.078125s system = 0.234375s CPU (1.3%)
|
||||||
|
|
||||||
|
RUN-1004 : used memory is 2402 MB, reserved memory is 2403 MB, peak memory is 2421 MB
|
||||||
|
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 18.014165s wall, 0.296875s user + 0.093750s system = 0.390625s CPU (2.2%)
|
||||||
|
|
||||||
|
RUN-1004 : used memory is 2402 MB, reserved memory is 2403 MB, peak memory is 2421 MB
|
||||||
|
GUI-1001 : Downloading succeeded!
|
||||||
|
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
|
||||||
|
PRG-2014 : Chip validation success: EAGLE_S20_EG176
|
||||||
|
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||||
|
RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
|
||||||
|
RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.758777s wall, 0.296875s user + 0.703125s system = 1.000000s CPU (5.6%)
|
||||||
|
|
||||||
|
RUN-1004 : used memory is 2402 MB, reserved memory is 2403 MB, peak memory is 2421 MB
|
||||||
|
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.970594s wall, 0.421875s user + 0.718750s system = 1.140625s CPU (6.3%)
|
||||||
|
|
||||||
|
RUN-1004 : used memory is 2402 MB, reserved memory is 2403 MB, peak memory is 2421 MB
|
||||||
|
GUI-1001 : Downloading succeeded!
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue