修改sdc时钟约束为derive_pll_clocks
This commit is contained in:
17828169534
parent
c51f01e204
commit
ffaa661020
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@ -561,17 +561,10 @@
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<Runs>
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<Run Name="syn_1" Type="Synthesis" ConstraintSet="constraint_1" Description="" Active="true">
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<Strategy Name="Default_Synthesis_Strategy">
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<GateProperty>
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<opt_area>low</opt_area>
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<opt_timing>high</opt_timing>
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</GateProperty>
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</Strategy>
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</Run>
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<Run Name="phy_1" Type="PhysicalDesign" ConstraintSet="constraint_1" Description="" SynRun="syn_1" Active="true">
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<Strategy Name="Default_PhysicalDesign_Strategy">
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<BitgenProperty::GeneralOption>
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<bin>on</bin>
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</BitgenProperty::GeneralOption>
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<PlaceProperty>
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<opt_timing>high</opt_timing>
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</PlaceProperty>
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@ -1,15 +1,15 @@
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create_clock -name clock_source -period 41.666 -waveform {0 20.833} [get_ports {clock_source}]
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create_clock -name a_lvds_clk_p -period 20.833 -waveform {0 10.417} [get_ports {a_lvds_clk_p}]
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create_clock -name b_lvds_clk_p -period 20.833 -waveform {0 10.417} [get_ports {b_lvds_clk_p}]
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create_generated_clock -name S_clk -source [get_ports {clock_source}] -master_clock {clock_source} -edges {1 2 3} -edge_shift {0 -16.203 -32.408} [get_pins {u_pll/pll_inst.clkc[0]}]
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create_generated_clock -name a_pclk -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -edges {1 2 3} -edge_shift {0 0 0} [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
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create_generated_clock -name b_pclk -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -edges {1 2 3} -edge_shift {0 0 0} [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
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#create_generated_clock -name S_clk -source [get_ports {clock_source}] -master_clock {clock_source} -edges {1 2 3} -edge_shift {0 -16.203 -32.408} [get_pins {u_pll/pll_inst.clkc[0]}]
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#create_generated_clock -name a_pclk -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -edges {1 2 3} -edge_shift {0 0 0} [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
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#create_generated_clock -name b_pclk -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -edges {1 2 3} -edge_shift {0 0 0} [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
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#set_output_delay -clock [get_clocks {clock_source}] 29.166 [all_outputs]
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create_generated_clock -name S_clk_x2 -source [get_pins {u_pll/pll_inst.clkc[0]}] -master_clock {S_clk} -phase 0 -multiply_by 2 -duty_cycle 0.5 [get_pins {u_pll/pll_inst.clkc[1]}]
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create_generated_clock -name S_clk_x4 -source [get_pins {u_pll/pll_inst.clkc[0]}] -master_clock {S_clk} -phase 0 -multiply_by 4 -duty_cycle 0.5 [get_pins {u_pll/pll_inst.clkc[2]}]
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create_generated_clock -name S_clk_x4_90d -source [get_pins {u_pll/pll_inst.clkc[0]}] -master_clock {S_clk} -phase 90 -multiply_by 4 -duty_cycle 0.5 [get_pins {u_pll/pll_inst.clkc[3]}]
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create_generated_clock -name a_sclk -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -edges {1 2 3} -edge_shift {0 -7.441 -14.881} [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
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create_generated_clock -name b_sclk -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -edges {1 2 3} -edge_shift {0 -7.441 -14.881} [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
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#create_generated_clock -name S_clk_x2 -source [get_pins {u_pll/pll_inst.clkc[0]}] -master_clock {S_clk} -phase 0 -multiply_by 2 -duty_cycle 0.5 [get_pins {u_pll/pll_inst.clkc[1]}]
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#create_generated_clock -name S_clk_x4 -source [get_pins {u_pll/pll_inst.clkc[0]}] -master_clock {S_clk} -phase 0 -multiply_by 4 -duty_cycle 0.5 [get_pins {u_pll/pll_inst.clkc[2]}]
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#create_generated_clock -name S_clk_x4_90d -source [get_pins {u_pll/pll_inst.clkc[0]}] -master_clock {S_clk} -phase 90 -multiply_by 4 -duty_cycle 0.5 [get_pins {u_pll/pll_inst.clkc[3]}]
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#create_generated_clock -name a_sclk -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -edges {1 2 3} -edge_shift {0 -7.441 -14.881} [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
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#create_generated_clock -name b_sclk -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -edges {1 2 3} -edge_shift {0 -7.441 -14.881} [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
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#set_false_path -from [get_nets {u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clka_mipi_total_num/temp[*]}]
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#set_false_path -from [get_nets {u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clkb_mipi_total_num/temp[*]}]
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#set_false_path -from [get_nets {u_pixel_cdc/u_clka_cis_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clka_cis_total_num/temp[*]}]
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@ -23,9 +23,19 @@ create_generated_clock -name b_sclk -source [get_ports {b_lvds_clk_p}] -master_c
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#set_false_path -setup -from [get_pins {u_pll/pll_inst.clkc[3]}] -to [get_nets {u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d}]
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#set_false_path -setup -from [get_pins {u_pll/pll_inst.clkc[1]}] -to [get_nets {u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2}]
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#create_generated_clock -name clk_adc -source [get_ports {clock_source}] -master_clock {clock_source} -edges {1 2 3} -edge_shift {0 -6.944 -13.889} [get_pins {u_pll/pll_inst.clkc[4]}]
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create_generated_clock -name clk_adc -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4 -phase 0 [get_pins {u_pll/pll_inst.clkc[4]}]
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#create_generated_clock -name clk_adc -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4 -phase 0 [get_pins {u_pll/pll_inst.clkc[4]}]
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#set_false_path -from [get_nets {u1_BUSY_MIPI/signal_from[*]}] -to [get_regs {u1_BUSY_MIPI/temp[*]}]
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#set_false_path -from [get_regs {clkubus_rstn}] -to [get_nets {a_pclk_rstn}]
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#set_false_path -from [get_regs {clkubus_rstn}] -to [get_nets {b_pclk_rstn}]
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set_false_path -from [get_nets {u_O_clk_lp_p/signal_from[*]}] -to [get_regs {u_O_clk_lp_p/temp[*]}]
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set_false_path -from [get_nets {u_O_clk_lp_n/signal_from[*]}] -to [get_regs {u_O_clk_lp_n/temp[*]}]
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derive_pll_clocks
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rename_clock -name {S_clk} -source [get_ports {clock_source}] -master_clock {clock_source} [get_pins {u_pll/pll_inst.clkc[0]}]
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rename_clock -name {S_clk_x2} -source [get_ports {clock_source}] -master_clock {clock_source} [get_pins {u_pll/pll_inst.clkc[1]}]
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rename_clock -name {S_clk_x4} -source [get_ports {clock_source}] -master_clock {clock_source} [get_pins {u_pll/pll_inst.clkc[2]}]
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rename_clock -name {S_clk_x4_90d} -source [get_ports {clock_source}] -master_clock {clock_source} [get_pins {u_pll/pll_inst.clkc[3]}]
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rename_clock -name {clk_adc} -source [get_ports {clock_source}] -master_clock {clock_source} [get_pins {u_pll/pll_inst.clkc[4]}]
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rename_clock -name {a_pclk} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
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rename_clock -name {a_sclk} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
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rename_clock -name {b_pclk} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
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rename_clock -name {b_sclk} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -1,5 +1,5 @@
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<?xml version="1.0"?>
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<ProcessHandle Version="1" Minor="0">
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<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="14768">
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<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="24880">
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</Process>
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</ProcessHandle>
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@ -1,5 +1,5 @@
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<?xml version="1.0"?>
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<ProcessHandle Version="1" Minor="0">
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<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="14768">
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<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="24880">
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</Process>
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</ProcessHandle>
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@ -1,5 +1,5 @@
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<?xml version="1.0"?>
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<ProcessHandle Version="1" Minor="0">
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<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="14768">
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<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="24880">
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</Process>
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</ProcessHandle>
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Binary file not shown.
Binary file not shown.
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@ -1,5 +1,5 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<Project Version="3" Minor="2" RunTime="2024-03-12T16:38:37.989622">
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<Project Version="3" Minor="2" RunTime="2024-03-13T17:53:17.490231">
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<Project_Created_Time></Project_Created_Time>
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<TD_Encoding>UTF-8</TD_Encoding>
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<TD_Version>5.6.71036</TD_Version>
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@ -553,9 +553,6 @@
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<CREATEINDEX>user</CREATEINDEX>
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</TOP_MODULE>
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<Property>
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<BitgenProperty::GeneralOption>
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<bin>on</bin>
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</BitgenProperty::GeneralOption>
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<PlaceProperty>
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<opt_timing>high</opt_timing>
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</PlaceProperty>
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Binary file not shown.
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@ -76,7 +76,7 @@ step_begin bitgen
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set ACTIVESTEP bitgen
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set rc [catch {
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export_bid hg_anlogic_inst.bid
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bitgen -bit "hg_anlogic.bit" -bin "hg_anlogic.bin"
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bitgen -bit "hg_anlogic.bit"
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} RESULT]
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if {$rc} {
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step_error bitgen
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@ -8,12 +8,12 @@ IO Statistics
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#inout 0
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Utilization Statistics
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#lut 10230 out of 19600 52.19%
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#reg 9451 out of 19600 48.22%
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#le 12649
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#lut only 3198 out of 12649 25.28%
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#reg only 2419 out of 12649 19.12%
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#lut® 7032 out of 12649 55.59%
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#lut 10181 out of 19600 51.94%
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#reg 9426 out of 19600 48.09%
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#le 12449
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#lut only 3023 out of 12449 24.28%
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#reg only 2268 out of 12449 18.22%
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#lut® 7158 out of 12449 57.50%
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#dsp 3 out of 29 10.34%
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#bram 54 out of 64 84.38%
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#bram9k 50
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@ -28,17 +28,17 @@ Utilization Statistics
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Clock Resource Statistics
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Index ClockNet Type DriverType Driver Fanout
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#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1798
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#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1415
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#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1345
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#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 989
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#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 141
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#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1783
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#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1374
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#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1268
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#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 960
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#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 139
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#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 72
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#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70
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#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
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#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
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#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_272.f1 3
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#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_b/en_adc_cfg_all_d1_reg_syn_8.f1 2
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#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_a/reg0_syn_140.f1 3
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#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_381.f1 2
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#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
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#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
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#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
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@ -76,8 +76,8 @@ Detailed IO Report
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b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
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clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
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global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
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onoff_in INPUT P141 LVCMOS33 N/A N/A NONE
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paper_in INPUT P17 LVCMOS25 N/A N/A NONE
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onoff_in INPUT P91 LVCMOS25 N/A N/A NONE
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paper_in INPUT P107 LVCMOS25 N/A N/A NONE
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rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
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O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
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O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
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@ -103,7 +103,7 @@ Detailed IO Report
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a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
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a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
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a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
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a_sp_sampling OUTPUT P133 LVCMOS33 8 N/A OREG
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a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
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b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
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b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
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b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
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@ -116,56 +116,109 @@ Detailed IO Report
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debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
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debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
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debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
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fan_pwm OUTPUT P143 LVCMOS33 8 N/A NONE
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frame_indicator OUTPUT P107 LVCMOS25 8 N/A OREG
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onoff_out OUTPUT P118 LVCMOS25 8 N/A NONE
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paper_out OUTPUT P106 LVCMOS25 8 N/A NONE
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scan_out OUTPUT P91 LVCMOS25 8 N/A NONE
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sys_initial_done OUTPUT P83 LVCMOS25 8 N/A NONE
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fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
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frame_indicator OUTPUT P110 LVCMOS25 8 N/A OREG
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onoff_out OUTPUT P104 LVCMOS25 8 N/A NONE
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paper_out OUTPUT P11 LVCMOS25 8 N/A NONE
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scan_out OUTPUT P119 LVCMOS25 8 N/A NONE
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sys_initial_done OUTPUT P140 LVCMOS33 8 N/A NONE
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txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
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Report Hierarchy Area:
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+---------------------------------------------------------------------------------------------------------+
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|Instance |Module |le |lut |ripple |seq |bram |dsp |
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+---------------------------------------------------------------------------------------------------------+
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|top |huagao_mipi_top |12649 |9203 |1027 |9485 |58 |3 |
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| U_rgb_to_csi_pakage |rgb_to_csi_pakage |559 |475 |23 |441 |4 |1 |
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| U_fifo_w32_d8192 |fifo_w32_d8192 |104 |89 |4 |90 |4 |0 |
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| U_crc16_24b |crc16_24b |52 |52 |0 |23 |0 |0 |
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| U_ecc_gen |ecc_gen |9 |9 |0 |8 |0 |0 |
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| exdev_ctl_a |exdev_ctl |761 |324 |96 |573 |0 |0 |
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| u_ADconfig |AD_config |189 |120 |25 |143 |0 |0 |
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| u_gen_sp |gen_sp |265 |152 |71 |123 |0 |0 |
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| exdev_ctl_b |exdev_ctl |766 |382 |96 |571 |0 |0 |
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| u_ADconfig |AD_config |184 |125 |25 |132 |0 |0 |
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| u_gen_sp |gen_sp |262 |156 |71 |119 |0 |0 |
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| sampling_fe_a |sampling_fe |2990 |2397 |306 |2064 |25 |0 |
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| u0_soft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
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| u_ad_sampling |ad_sampling |184 |114 |17 |146 |0 |0 |
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|top |huagao_mipi_top |12449 |9154 |1027 |9460 |58 |3 |
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| U_rgb_to_csi_pakage |rgb_to_csi_pakage |542 |448 |23 |441 |4 |1 |
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| U_fifo_w32_d8192 |fifo_w32_d8192 |108 |102 |4 |94 |4 |0 |
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| U_ecc_gen |ecc_gen |12 |12 |0 |6 |0 |0 |
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| U_crc16_24b |crc16_24b |34 |34 |0 |19 |0 |0 |
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| exdev_ctl_a |exdev_ctl |763 |384 |96 |581 |0 |0 |
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| u_ADconfig |AD_config |189 |108 |25 |145 |0 |0 |
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| u_gen_sp |gen_sp |256 |165 |71 |118 |0 |0 |
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| exdev_ctl_b |exdev_ctl |744 |356 |96 |567 |0 |0 |
|
||||
| u_ADconfig |AD_config |176 |94 |25 |131 |0 |0 |
|
||||
| u_gen_sp |gen_sp |251 |151 |71 |119 |0 |0 |
|
||||
| sampling_fe_a |sampling_fe |2985 |2409 |306 |2065 |25 |0 |
|
||||
| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
|
||||
| u_ad_sampling |ad_sampling |165 |117 |17 |136 |0 |0 |
|
||||
| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||
| u_sort |sort |2777 |2276 |289 |1889 |25 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
|
||||
| u0_wrsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
|
||||
| u_data_prebuffer |data_prebuffer |2369 |2001 |253 |1552 |22 |0 |
|
||||
| channelPart |channel_part_8478 |179 |175 |3 |146 |0 |0 |
|
||||
| fifo_adc |fifo_adc |58 |49 |9 |42 |0 |0 |
|
||||
| ram_switch |ram_switch |1838 |1538 |197 |1145 |0 |0 |
|
||||
| adc_addr_gen |adc_addr_gen |234 |206 |27 |125 |0 |0 |
|
||||
| [0]$ch_addr_gen |ch_addr_gen |14 |10 |3 |9 |0 |0 |
|
||||
| [1]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 |
|
||||
| [2]$ch_addr_gen |ch_addr_gen |30 |27 |3 |16 |0 |0 |
|
||||
| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 |
|
||||
| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 |
|
||||
| [5]$ch_addr_gen |ch_addr_gen |21 |18 |3 |8 |0 |0 |
|
||||
| [6]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
|
||||
| [7]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 |
|
||||
| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 |
|
||||
| insert |insert |955 |683 |170 |644 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |649 |649 |0 |376 |0 |0 |
|
||||
| read_ram_i |read_ram |265 |213 |44 |190 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr |215 |175 |40 |154 |0 |0 |
|
||||
| read_ram_data |read_ram_data |48 |37 |4 |34 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
|
||||
| u_sort |sort |2790 |2274 |289 |1899 |25 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
|
||||
| u0_wrsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
|
||||
| u_data_prebuffer |data_prebuffer |2371 |1946 |253 |1556 |22 |0 |
|
||||
| channelPart |channel_part_8478 |145 |141 |3 |137 |0 |0 |
|
||||
| fifo_adc |fifo_adc |52 |43 |9 |37 |0 |0 |
|
||||
| ram_switch |ram_switch |1860 |1503 |197 |1163 |0 |0 |
|
||||
| adc_addr_gen |adc_addr_gen |220 |193 |27 |116 |0 |0 |
|
||||
| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |7 |0 |0 |
|
||||
| [1]$ch_addr_gen |ch_addr_gen |27 |24 |3 |16 |0 |0 |
|
||||
| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
|
||||
| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
|
||||
| [4]$ch_addr_gen |ch_addr_gen |30 |27 |3 |15 |0 |0 |
|
||||
| [5]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
|
||||
| [6]$ch_addr_gen |ch_addr_gen |19 |16 |3 |9 |0 |0 |
|
||||
| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
|
||||
| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 |
|
||||
| insert |insert |982 |655 |170 |677 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |658 |655 |0 |370 |0 |0 |
|
||||
| read_ram_i |read_ram |283 |238 |44 |190 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr |232 |192 |40 |153 |0 |0 |
|
||||
| read_ram_data |read_ram_data |50 |45 |4 |36 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
|
||||
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
|
||||
| u0_sort_ram_b_9 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
|
||||
| u_transfer_300_to_200 |transfer_300_to_200 |321 |235 |36 |276 |3 |0 |
|
||||
| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
|
||||
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
|
||||
| sampling_fe_b |sampling_fe_rev |3240 |2551 |349 |2052 |25 |1 |
|
||||
| u0_soft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
|
||||
| u_ad_sampling |ad_sampling |182 |102 |17 |152 |0 |0 |
|
||||
| u0_soft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
|
||||
| u_sort |sort_rev |3022 |2433 |332 |1864 |25 |1 |
|
||||
| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
|
||||
| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||
| u_data_prebuffer_rev |data_prebuffer_rev |2599 |2106 |290 |1505 |22 |1 |
|
||||
| channelPart |channel_part_8478 |124 |120 |3 |119 |0 |0 |
|
||||
| fifo_adc |fifo_adc |62 |53 |9 |44 |0 |1 |
|
||||
| ram_switch |ram_switch |2021 |1673 |197 |1103 |0 |0 |
|
||||
| adc_addr_gen |adc_addr_gen |205 |178 |27 |105 |0 |0 |
|
||||
| [0]$ch_addr_gen |ch_addr_gen |10 |7 |3 |6 |0 |0 |
|
||||
| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
|
||||
| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
|
||||
| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
|
||||
| [4]$ch_addr_gen |ch_addr_gen |19 |16 |3 |10 |0 |0 |
|
||||
| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
|
||||
| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
|
||||
| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |7 |0 |0 |
|
||||
| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |7 |0 |0 |
|
||||
| insert |insert |969 |648 |170 |671 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |847 |847 |0 |327 |0 |0 |
|
||||
| read_ram_i |read_ram_rev |363 |244 |81 |211 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr_rev |298 |213 |73 |165 |0 |0 |
|
||||
| read_ram_data |read_ram_data_rev |65 |31 |8 |46 |0 |0 |
|
||||
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
|
|
@ -188,120 +241,69 @@ Report Hierarchy Area:
|
|||
| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u_transfer_300_to_200 |transfer_300_to_200 |295 |175 |36 |264 |3 |0 |
|
||||
| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||
| u_transfer_300_to_200 |transfer_300_to_200 |324 |240 |42 |278 |3 |0 |
|
||||
| u0_soft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
|
||||
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
|
||||
| sampling_fe_b |sampling_fe_rev |3425 |2768 |349 |2117 |25 |1 |
|
||||
| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
|
||||
| u_ad_sampling |ad_sampling |186 |118 |17 |151 |0 |0 |
|
||||
| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||
| u_sort |sort_rev |3208 |2632 |332 |1935 |25 |1 |
|
||||
| rddpram_ctl |rddpram_ctl_rev |5 |5 |0 |5 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
|
||||
| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
|
||||
| u_data_prebuffer_rev |data_prebuffer_rev |2742 |2267 |290 |1583 |22 |1 |
|
||||
| channelPart |channel_part_8478 |263 |250 |3 |149 |0 |0 |
|
||||
| fifo_adc |fifo_adc |65 |56 |9 |46 |0 |1 |
|
||||
| ram_switch |ram_switch |1999 |1658 |197 |1136 |0 |0 |
|
||||
| adc_addr_gen |adc_addr_gen |221 |194 |27 |106 |0 |0 |
|
||||
| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |5 |0 |0 |
|
||||
| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |14 |0 |0 |
|
||||
| [2]$ch_addr_gen |ch_addr_gen |23 |20 |3 |12 |0 |0 |
|
||||
| [3]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
|
||||
| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
|
||||
| [5]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 |
|
||||
| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |7 |0 |0 |
|
||||
| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
|
||||
| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
|
||||
| insert |insert |972 |659 |170 |667 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |806 |805 |0 |363 |0 |0 |
|
||||
| read_ram_i |read_ram_rev |376 |267 |81 |214 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr_rev |307 |222 |73 |162 |0 |0 |
|
||||
| read_ram_data |read_ram_data_rev |69 |45 |8 |52 |0 |0 |
|
||||
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_9 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
|
||||
| u_transfer_300_to_200 |transfer_300_to_200 |366 |288 |42 |281 |3 |0 |
|
||||
| u0_soft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
|
||||
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
|
||||
| scan_start_diff |scan_start_diff |21 |20 |0 |14 |0 |0 |
|
||||
| u0_test_en |cdc_sync |5 |1 |0 |5 |0 |0 |
|
||||
| u1_BUSY_MIPI |cdc_sync |3 |2 |0 |3 |0 |0 |
|
||||
| u1_test_en |cdc_sync |1 |1 |0 |1 |0 |0 |
|
||||
| u2_test_en |cdc_sync |7 |6 |0 |7 |0 |0 |
|
||||
| u_O_clk_lp_n |cdc_sync |17 |17 |0 |17 |0 |0 |
|
||||
| u_O_clk_lp_p |cdc_sync |12 |12 |0 |12 |0 |0 |
|
||||
| u_a_pclk |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||
| u_a_sp_sampling |cdc_sync |2 |2 |0 |2 |0 |0 |
|
||||
| u_a_sp_sampling_cam |cdc_sync |6 |5 |0 |6 |0 |0 |
|
||||
| u_b_pclk |cdc_sync |5 |4 |0 |5 |0 |0 |
|
||||
| u_b_sp_sampling |cdc_sync |5 |5 |0 |5 |0 |0 |
|
||||
| u_b_sp_sampling_cam |cdc_sync |3 |3 |0 |3 |0 |0 |
|
||||
| u_b_sp_sampling_last |cdc_sync |6 |6 |0 |6 |0 |0 |
|
||||
| u_bus_top |ubus_top |1360 |952 |22 |1258 |0 |0 |
|
||||
| u_local_bus_slve_cis |local_bus_slve_cis |846 |713 |22 |744 |0 |0 |
|
||||
| u_uart_2dsp |uart_2dsp |135 |120 |12 |66 |0 |0 |
|
||||
| u_dpi_mode |cdc_sync |9 |6 |0 |9 |0 |0 |
|
||||
| scan_start_diff |scan_start_diff |27 |26 |0 |17 |0 |0 |
|
||||
| u0_test_en |cdc_sync |3 |2 |0 |3 |0 |0 |
|
||||
| u1_BUSY_MIPI |cdc_sync |15 |1 |0 |15 |0 |0 |
|
||||
| u1_test_en |cdc_sync |5 |4 |0 |5 |0 |0 |
|
||||
| u2_test_en |cdc_sync |3 |0 |0 |3 |0 |0 |
|
||||
| u_O_clk_lp_n |cdc_sync |23 |23 |0 |23 |0 |0 |
|
||||
| u_O_clk_lp_p |cdc_sync |18 |7 |0 |18 |0 |0 |
|
||||
| u_a_pclk |cdc_sync |15 |15 |0 |10 |0 |0 |
|
||||
| u_a_sp_sampling |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||
| u_a_sp_sampling_cam |cdc_sync |7 |5 |0 |7 |0 |0 |
|
||||
| u_a_sp_sampling_last |cdc_sync |1 |1 |0 |1 |0 |0 |
|
||||
| u_b_pclk |cdc_sync |7 |6 |0 |7 |0 |0 |
|
||||
| u_b_sp_sampling |cdc_sync |2 |2 |0 |2 |0 |0 |
|
||||
| u_b_sp_sampling_cam |cdc_sync |6 |4 |0 |6 |0 |0 |
|
||||
| u_b_sp_sampling_last |cdc_sync |6 |0 |0 |6 |0 |0 |
|
||||
| u_bus_top |ubus_top |1304 |1020 |22 |1248 |0 |0 |
|
||||
| u_local_bus_slve_cis |local_bus_slve_cis |794 |717 |22 |738 |0 |0 |
|
||||
| u_uart_2dsp |uart_2dsp |93 |77 |12 |60 |0 |0 |
|
||||
| u_dpi_mode |cdc_sync |8 |6 |0 |8 |0 |0 |
|
||||
| u_eot |cdc_sync |6 |3 |0 |6 |0 |0 |
|
||||
| u_lv_en_flag |cdc_sync |6 |6 |0 |6 |0 |0 |
|
||||
| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |275 |206 |20 |224 |4 |0 |
|
||||
| u_hs_tx_wrapper |hs_tx_wrapper |233 |164 |20 |195 |4 |0 |
|
||||
| [0]$u_data_lane_wrapper |data_lane_wrapper |116 |85 |15 |89 |1 |0 |
|
||||
| u_data_hs_generate |data_hs_generate |113 |82 |15 |86 |1 |0 |
|
||||
| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |294 |247 |20 |226 |4 |0 |
|
||||
| u_hs_tx_wrapper |hs_tx_wrapper |256 |209 |20 |203 |4 |0 |
|
||||
| [0]$u_data_lane_wrapper |data_lane_wrapper |129 |102 |15 |98 |1 |0 |
|
||||
| u_data_hs_generate |data_hs_generate |123 |96 |15 |92 |1 |0 |
|
||||
| u_dphy_tx_fifo |dphy_tx_fifo |4 |4 |0 |2 |1 |0 |
|
||||
| u_d1024_w8_fifo |d1024_w8_fifo |4 |4 |0 |2 |1 |0 |
|
||||
| u_data_lp_generate |data_lp_generate |6 |6 |0 |6 |0 |0 |
|
||||
| [1]$u_data_lane_wrapper |data_lane_wrapper |30 |28 |0 |29 |1 |0 |
|
||||
| u_data_hs_generate |data_hs_generate |30 |28 |0 |29 |1 |0 |
|
||||
| u_dphy_tx_fifo |dphy_tx_fifo |2 |2 |0 |1 |1 |0 |
|
||||
| u_d1024_w8_fifo |d1024_w8_fifo |2 |2 |0 |1 |1 |0 |
|
||||
| [2]$u_data_lane_wrapper |data_lane_wrapper |27 |23 |0 |27 |1 |0 |
|
||||
| u_data_hs_generate |data_hs_generate |27 |23 |0 |27 |1 |0 |
|
||||
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
|
||||
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
|
||||
| u_data_lp_generate |data_lp_generate |3 |3 |0 |3 |0 |0 |
|
||||
| [1]$u_data_lane_wrapper |data_lane_wrapper |35 |20 |0 |35 |1 |0 |
|
||||
| u_data_hs_generate |data_hs_generate |35 |20 |0 |35 |1 |0 |
|
||||
| [3]$u_data_lane_wrapper |data_lane_wrapper |26 |17 |0 |25 |1 |0 |
|
||||
| u_data_hs_generate |data_hs_generate |26 |17 |0 |25 |1 |0 |
|
||||
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
|
||||
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
|
||||
| [2]$u_data_lane_wrapper |data_lane_wrapper |29 |13 |0 |29 |1 |0 |
|
||||
| u_data_hs_generate |data_hs_generate |29 |13 |0 |29 |1 |0 |
|
||||
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
|
||||
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
|
||||
| [3]$u_data_lane_wrapper |data_lane_wrapper |20 |18 |0 |20 |1 |0 |
|
||||
| u_data_hs_generate |data_hs_generate |20 |18 |0 |20 |1 |0 |
|
||||
| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 |
|
||||
| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 |
|
||||
| u_hs_tx_controler |hs_tx_controler |25 |20 |5 |14 |0 |0 |
|
||||
| u_hs_tx_controler |hs_tx_controler |34 |29 |5 |14 |0 |0 |
|
||||
| u_clk_lane_wrapper |clk_lane_wrapper |8 |8 |0 |8 |0 |0 |
|
||||
| u_clk_hs_generate |clk_hs_generate |4 |4 |0 |4 |0 |0 |
|
||||
| u_clk_lp_generate |clk_lp_generate |4 |4 |0 |4 |0 |0 |
|
||||
| u_mipi_eot_min |cdc_sync |65 |58 |0 |65 |0 |0 |
|
||||
| u_mipi_sot_min |cdc_sync |58 |56 |0 |58 |0 |0 |
|
||||
| u_pic_cnt |cdc_sync |115 |72 |0 |115 |0 |0 |
|
||||
| u_pixel_cdc |pixel_cdc |675 |580 |0 |672 |0 |1 |
|
||||
| u_clk_cis_frame_num |cdc_sync |68 |60 |0 |68 |0 |0 |
|
||||
| u_clk_cis_pixel_y |cdc_sync |65 |59 |0 |65 |0 |0 |
|
||||
| u_clk_mipi_pixel_y |cdc_sync |74 |73 |0 |72 |0 |0 |
|
||||
| u_clka_cis_total_num |cdc_sync |94 |83 |0 |94 |0 |0 |
|
||||
| u_clka_mipi_total_num |cdc_sync |102 |88 |0 |102 |0 |0 |
|
||||
| u_clkb_cis_total_num |cdc_sync |100 |85 |0 |99 |0 |0 |
|
||||
| u_clkb_mipi_total_num |cdc_sync |100 |77 |0 |100 |0 |0 |
|
||||
| u_clk_hs_generate |clk_hs_generate |4 |4 |0 |4 |0 |0 |
|
||||
| u_mipi_eot_min |cdc_sync |61 |52 |0 |61 |0 |0 |
|
||||
| u_mipi_sot_min |cdc_sync |54 |54 |0 |54 |0 |0 |
|
||||
| u_pic_cnt |cdc_sync |111 |66 |0 |111 |0 |0 |
|
||||
| u_pixel_cdc |pixel_cdc |678 |530 |0 |678 |0 |1 |
|
||||
| u_clk_cis_frame_num |cdc_sync |78 |65 |0 |78 |0 |0 |
|
||||
| u_clk_cis_pixel_y |cdc_sync |65 |55 |0 |65 |0 |0 |
|
||||
| u_clk_mipi_pixel_y |cdc_sync |70 |66 |0 |70 |0 |0 |
|
||||
| u_clka_cis_total_num |cdc_sync |101 |84 |0 |101 |0 |0 |
|
||||
| u_clka_mipi_total_num |cdc_sync |105 |68 |0 |105 |0 |0 |
|
||||
| u_clkb_cis_total_num |cdc_sync |98 |81 |0 |98 |0 |0 |
|
||||
| u_clkb_mipi_total_num |cdc_sync |99 |75 |0 |99 |0 |0 |
|
||||
| u_pll |pll |0 |0 |0 |0 |0 |0 |
|
||||
| u_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |0 |
|
||||
| u_softrst_done |cdc_sync |4 |4 |0 |4 |0 |0 |
|
||||
| ua_lvds_rx |lvds_rx |278 |218 |19 |197 |0 |0 |
|
||||
| ub_lvds_rx |lvds_rx |287 |192 |19 |207 |0 |0 |
|
||||
| ua_lvds_rx |lvds_rx |280 |196 |19 |200 |0 |0 |
|
||||
| ub_lvds_rx |lvds_rx |288 |203 |19 |209 |0 |0 |
|
||||
| uu_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |0 |
|
||||
+---------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
|
@ -309,12 +311,12 @@ Report Hierarchy Area:
|
|||
DataNet Average Fanout:
|
||||
|
||||
Index Fanout Nets
|
||||
#1 1 9801
|
||||
#2 2 3950
|
||||
#3 3 1453
|
||||
#4 4 623
|
||||
#5 5-10 1031
|
||||
#6 11-50 602
|
||||
#7 51-100 22
|
||||
#1 1 9914
|
||||
#2 2 4230
|
||||
#3 3 1690
|
||||
#4 4 579
|
||||
#5 5-10 783
|
||||
#6 11-50 550
|
||||
#7 51-100 11
|
||||
#8 >500 1
|
||||
Average 2.91
|
||||
Average 2.72
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,5 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="1576">
|
||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="20180">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="1576">
|
||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="20180">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="1576">
|
||||
<Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="20180">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Project Version="3" Minor="2" RunTime="2024-03-12T16:38:37.869942">
|
||||
<Project Version="3" Minor="2" RunTime="2024-03-13T17:53:17.350613">
|
||||
<Project_Created_Time></Project_Created_Time>
|
||||
<TD_Encoding>UTF-8</TD_Encoding>
|
||||
<TD_Version>5.6.71036</TD_Version>
|
||||
|
|
@ -553,10 +553,6 @@
|
|||
<CREATEINDEX>user</CREATEINDEX>
|
||||
</TOP_MODULE>
|
||||
<Property>
|
||||
<GateProperty>
|
||||
<opt_area>low</opt_area>
|
||||
<opt_timing>high</opt_timing>
|
||||
</GateProperty>
|
||||
</Property>
|
||||
<Device_Settings>
|
||||
</Device_Settings>
|
||||
|
|
|
|||
|
|
@ -8,15 +8,15 @@ IO Statistics
|
|||
#inout 0
|
||||
|
||||
LUT Statistics
|
||||
#Total_luts 9912
|
||||
#lut4 5066
|
||||
#lut5 2291
|
||||
#Total_luts 10217
|
||||
#lut4 6529
|
||||
#lut5 1133
|
||||
#lut6 0
|
||||
#lut5_mx41 0
|
||||
#lut4_alu1b 2555
|
||||
|
||||
Utilization Statistics
|
||||
#lut 9912 out of 19600 50.57%
|
||||
#lut 10217 out of 19600 52.13%
|
||||
#reg 9232 out of 19600 47.10%
|
||||
#le 0
|
||||
#dsp 3 out of 29 10.34%
|
||||
|
|
@ -35,31 +35,31 @@ Report Hierarchy Area:
|
|||
+-------------------------------------------------------------------------------------------------+
|
||||
|Instance |Module |lut |ripple |seq |bram |dsp |
|
||||
+-------------------------------------------------------------------------------------------------+
|
||||
|top |huagao_mipi_top |7357 |2555 |9266 |58 |3 |
|
||||
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |343 |81 |441 |4 |1 |
|
||||
| U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 |
|
||||
|top |huagao_mipi_top |7662 |2555 |9266 |58 |3 |
|
||||
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |360 |81 |441 |4 |1 |
|
||||
| U_crc16_24b |crc16_24b |52 |0 |16 |0 |0 |
|
||||
| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
|
||||
| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
|
||||
| exdev_ctl_a |exdev_ctl |288 |234 |559 |0 |0 |
|
||||
| u_ADconfig |AD_config |102 |49 |138 |0 |0 |
|
||||
| u_gen_sp |gen_sp |128 |185 |104 |0 |0 |
|
||||
| exdev_ctl_b |exdev_ctl |276 |234 |546 |0 |0 |
|
||||
| u_ADconfig |AD_config |92 |49 |125 |0 |0 |
|
||||
| u_gen_sp |gen_sp |126 |185 |104 |0 |0 |
|
||||
| sampling_fe_a |sampling_fe |2277 |738 |1919 |25 |0 |
|
||||
| U_fifo_w32_d8192 |fifo_w32_d8192 |55 |14 |90 |4 |0 |
|
||||
| exdev_ctl_a |exdev_ctl |326 |234 |559 |0 |0 |
|
||||
| u_ADconfig |AD_config |116 |49 |138 |0 |0 |
|
||||
| u_gen_sp |gen_sp |139 |185 |104 |0 |0 |
|
||||
| exdev_ctl_b |exdev_ctl |314 |234 |546 |0 |0 |
|
||||
| u_ADconfig |AD_config |105 |49 |125 |0 |0 |
|
||||
| u_gen_sp |gen_sp |138 |185 |104 |0 |0 |
|
||||
| sampling_fe_a |sampling_fe |2318 |738 |1919 |25 |0 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
|
||||
| u_ad_sampling |ad_sampling |43 |47 |147 |0 |0 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_sort |sort |2207 |691 |1737 |25 |0 |
|
||||
| u_sort |sort |2243 |691 |1737 |25 |0 |
|
||||
| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_data_prebuffer |data_prebuffer |1866 |615 |1391 |22 |0 |
|
||||
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
|
||||
| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
|
||||
| ram_switch |ram_switch |1444 |422 |1023 |0 |0 |
|
||||
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
|
||||
| u_data_prebuffer |data_prebuffer |1913 |615 |1391 |22 |0 |
|
||||
| channelPart |channel_part_8478 |150 |11 |144 |0 |0 |
|
||||
| fifo_adc |fifo_adc |52 |24 |41 |0 |0 |
|
||||
| ram_switch |ram_switch |1476 |422 |1023 |0 |0 |
|
||||
| adc_addr_gen |adc_addr_gen |130 |99 |115 |0 |0 |
|
||||
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
|
||||
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
|
|
@ -69,11 +69,11 @@ Report Hierarchy Area:
|
|||
| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| insert |insert |265 |323 |692 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |1050 |0 |216 |0 |0 |
|
||||
| read_ram_i |read_ram |189 |158 |164 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr |161 |145 |127 |0 |0 |
|
||||
| read_ram_data |read_ram_data |27 |13 |32 |0 |0 |
|
||||
| insert |insert |264 |323 |692 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |1082 |0 |216 |0 |0 |
|
||||
| read_ram_i |read_ram |199 |158 |164 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr |169 |145 |127 |0 |0 |
|
||||
| read_ram_data |read_ram_data |29 |13 |32 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
|
|
@ -97,23 +97,23 @@ Report Hierarchy Area:
|
|||
| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 |
|
||||
| u_transfer_300_to_200 |transfer_300_to_200 |108 |76 |276 |3 |0 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
|
||||
| sampling_fe_b |sampling_fe_rev |2297 |751 |1936 |25 |1 |
|
||||
| sampling_fe_b |sampling_fe_rev |2332 |751 |1936 |25 |1 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
|
||||
| u_ad_sampling |ad_sampling |44 |47 |147 |0 |0 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_sort |sort_rev |2227 |704 |1754 |25 |1 |
|
||||
| u_sort |sort_rev |2256 |704 |1754 |25 |1 |
|
||||
| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_data_prebuffer_rev |data_prebuffer_rev |1888 |628 |1408 |22 |1 |
|
||||
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
|
||||
| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
|
||||
| ram_switch |ram_switch |1443 |422 |1023 |0 |0 |
|
||||
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
|
||||
| u_data_prebuffer_rev |data_prebuffer_rev |1928 |628 |1408 |22 |1 |
|
||||
| channelPart |channel_part_8478 |150 |11 |144 |0 |0 |
|
||||
| fifo_adc |fifo_adc |52 |24 |41 |0 |1 |
|
||||
| ram_switch |ram_switch |1473 |422 |1023 |0 |0 |
|
||||
| adc_addr_gen |adc_addr_gen |130 |99 |115 |0 |0 |
|
||||
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
|
||||
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
|
|
@ -123,11 +123,11 @@ Report Hierarchy Area:
|
|||
| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| insert |insert |265 |323 |692 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |1049 |0 |216 |0 |0 |
|
||||
| read_ram_i |read_ram_rev |210 |171 |181 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr_rev |182 |145 |139 |0 |0 |
|
||||
| read_ram_data |read_ram_data_rev |28 |26 |42 |0 |0 |
|
||||
| insert |insert |264 |323 |692 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |1079 |0 |216 |0 |0 |
|
||||
| read_ram_i |read_ram_rev |215 |171 |181 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr_rev |185 |145 |139 |0 |0 |
|
||||
| read_ram_data |read_ram_data_rev |30 |26 |42 |0 |0 |
|
||||
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
|
|
@ -150,10 +150,10 @@ Report Hierarchy Area:
|
|||
| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
| u_transfer_300_to_200 |transfer_300_to_200 |126 |76 |276 |3 |0 |
|
||||
| u_transfer_300_to_200 |transfer_300_to_200 |108 |76 |276 |3 |0 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
|
||||
| scan_start_diff |scan_start_diff |30 |0 |12 |0 |0 |
|
||||
| scan_start_diff |scan_start_diff |29 |0 |12 |0 |0 |
|
||||
| u0_test_en |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u1_BUSY_MIPI |cdc_sync |1 |0 |15 |0 |0 |
|
||||
| u1_test_en |cdc_sync |1 |0 |5 |0 |0 |
|
||||
|
|
@ -168,16 +168,16 @@ Report Hierarchy Area:
|
|||
| u_b_sp_sampling |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_b_sp_sampling_cam |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_b_sp_sampling_last |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_bus_top |ubus_top |811 |50 |1248 |0 |0 |
|
||||
| u_local_bus_slve_cis |local_bus_slve_cis |717 |50 |721 |0 |0 |
|
||||
| u_uart_2dsp |uart_2dsp |123 |31 |52 |0 |0 |
|
||||
| u_bus_top |ubus_top |866 |50 |1248 |0 |0 |
|
||||
| u_local_bus_slve_cis |local_bus_slve_cis |752 |50 |721 |0 |0 |
|
||||
| u_uart_2dsp |uart_2dsp |129 |31 |52 |0 |0 |
|
||||
| u_dpi_mode |cdc_sync |2 |0 |10 |0 |0 |
|
||||
| u_eot |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_lv_en_flag |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |172 |61 |226 |4 |0 |
|
||||
| u_hs_tx_wrapper |hs_tx_wrapper |112 |61 |198 |4 |0 |
|
||||
| [0]$u_data_lane_wrapper |data_lane_wrapper |54 |52 |93 |1 |0 |
|
||||
| u_data_hs_generate |data_hs_generate |50 |52 |87 |1 |0 |
|
||||
| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |173 |61 |226 |4 |0 |
|
||||
| u_hs_tx_wrapper |hs_tx_wrapper |114 |61 |198 |4 |0 |
|
||||
| [0]$u_data_lane_wrapper |data_lane_wrapper |55 |52 |93 |1 |0 |
|
||||
| u_data_hs_generate |data_hs_generate |51 |52 |87 |1 |0 |
|
||||
| u_dphy_tx_fifo |dphy_tx_fifo |2 |0 |0 |1 |0 |
|
||||
| u_d1024_w8_fifo |d1024_w8_fifo |2 |0 |0 |1 |0 |
|
||||
| u_data_lp_generate |data_lp_generate |4 |0 |6 |0 |0 |
|
||||
|
|
@ -196,23 +196,23 @@ Report Hierarchy Area:
|
|||
| u_clk_lane_wrapper |clk_lane_wrapper |3 |0 |8 |0 |0 |
|
||||
| u_clk_hs_generate |clk_hs_generate |3 |0 |4 |0 |0 |
|
||||
| u_clk_lp_generate |clk_lp_generate |0 |0 |4 |0 |0 |
|
||||
| u_hs_tx_controler |hs_tx_controler |25 |9 |12 |0 |0 |
|
||||
| u_mipi_eot_min |cdc_sync |20 |0 |65 |0 |0 |
|
||||
| u_mipi_sot_min |cdc_sync |20 |0 |65 |0 |0 |
|
||||
| u_pic_cnt |cdc_sync |38 |0 |120 |0 |0 |
|
||||
| u_pixel_cdc |pixel_cdc |211 |0 |762 |0 |1 |
|
||||
| u_clk_cis_frame_num |cdc_sync |25 |0 |80 |0 |0 |
|
||||
| u_clk_cis_pixel_y |cdc_sync |25 |0 |80 |0 |0 |
|
||||
| u_clk_mipi_pixel_y |cdc_sync |25 |0 |80 |0 |0 |
|
||||
| u_clka_cis_total_num |cdc_sync |34 |0 |110 |0 |0 |
|
||||
| u_clka_mipi_total_num |cdc_sync |34 |0 |110 |0 |0 |
|
||||
| u_clkb_cis_total_num |cdc_sync |34 |0 |110 |0 |0 |
|
||||
| u_clkb_mipi_total_num |cdc_sync |34 |0 |110 |0 |0 |
|
||||
| u_hs_tx_controler |hs_tx_controler |26 |9 |12 |0 |0 |
|
||||
| u_mipi_eot_min |cdc_sync |22 |0 |65 |0 |0 |
|
||||
| u_mipi_sot_min |cdc_sync |22 |0 |65 |0 |0 |
|
||||
| u_pic_cnt |cdc_sync |41 |0 |120 |0 |0 |
|
||||
| u_pixel_cdc |pixel_cdc |229 |0 |762 |0 |1 |
|
||||
| u_clk_cis_frame_num |cdc_sync |27 |0 |80 |0 |0 |
|
||||
| u_clk_cis_pixel_y |cdc_sync |27 |0 |80 |0 |0 |
|
||||
| u_clk_mipi_pixel_y |cdc_sync |27 |0 |80 |0 |0 |
|
||||
| u_clka_cis_total_num |cdc_sync |37 |0 |110 |0 |0 |
|
||||
| u_clka_mipi_total_num |cdc_sync |37 |0 |110 |0 |0 |
|
||||
| u_clkb_cis_total_num |cdc_sync |37 |0 |110 |0 |0 |
|
||||
| u_clkb_mipi_total_num |cdc_sync |37 |0 |110 |0 |0 |
|
||||
| u_pll |pll |1 |0 |0 |0 |0 |
|
||||
| u_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |
|
||||
| u_softrst_done |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_softrst_fan_ctrl |cdc_sync |0 |0 |0 |0 |0 |
|
||||
| ua_lvds_rx |lvds_rx |97 |67 |209 |0 |0 |
|
||||
| ub_lvds_rx |lvds_rx |97 |67 |209 |0 |0 |
|
||||
| ua_lvds_rx |lvds_rx |103 |67 |209 |0 |0 |
|
||||
| ub_lvds_rx |lvds_rx |103 |67 |209 |0 |0 |
|
||||
| uu_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |
|
||||
+-------------------------------------------------------------------------------------------------+
|
||||
|
|
|
|||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -4,7 +4,7 @@
|
|||
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
|
||||
Built at = 20:34:38 Mar 21 2023
|
||||
Run by = holdtecs
|
||||
Run Date = Tue Mar 12 16:38:38 2024
|
||||
Run Date = Wed Mar 13 17:53:17 2024
|
||||
|
||||
Run on = DESKTOP-5MQL5VE
|
||||
============================================================
|
||||
|
|
@ -417,9 +417,9 @@ HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been re
|
|||
HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
|
||||
HDL-1200 : Current top model is huagao_mipi_top
|
||||
HDL-1100 : Inferred 1 RAMs.
|
||||
RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.113594s wall, 1.046875s user + 0.062500s system = 1.109375s CPU (99.6%)
|
||||
RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.059191s wall, 1.046875s user + 0.015625s system = 1.062500s CPU (100.3%)
|
||||
|
||||
RUN-1004 : used memory is 199 MB, reserved memory is 169 MB, peak memory is 240 MB
|
||||
RUN-1004 : used memory is 195 MB, reserved memory is 172 MB, peak memory is 236 MB
|
||||
RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
|
||||
RUN-1001 : Exported /
|
||||
RUN-1001 : Exported flow parameters
|
||||
|
|
@ -1315,9 +1315,9 @@ SYN-1032 : 25352/20 useful/useless nets, 22700/2 useful/useless insts
|
|||
SYN-1015 : Optimize round 2, 2 better
|
||||
SYN-1014 : Optimize round 3
|
||||
SYN-1015 : Optimize round 3, 0 better
|
||||
RUN-1003 : finish command "optimize_rtl" in 18.914664s wall, 16.640625s user + 2.218750s system = 18.859375s CPU (99.7%)
|
||||
RUN-1003 : finish command "optimize_rtl" in 18.934808s wall, 16.671875s user + 2.265625s system = 18.937500s CPU (100.0%)
|
||||
|
||||
RUN-1004 : used memory is 335 MB, reserved memory is 304 MB, peak memory is 354 MB
|
||||
RUN-1004 : used memory is 333 MB, reserved memory is 304 MB, peak memory is 352 MB
|
||||
RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
|
||||
RUN-1001 : standard
|
||||
***Report Model: huagao_mipi_top Device: EG4D20EG176***
|
||||
|
|
@ -1472,9 +1472,9 @@ RUN-1001 : Exported congestions
|
|||
RUN-1001 : Exported violations
|
||||
RUN-1001 : Exported IO constraints
|
||||
RUN-1001 : Exported Inst constraints
|
||||
RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.112412s wall, 1.718750s user + 0.015625s system = 1.734375s CPU (155.9%)
|
||||
RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.103894s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (155.7%)
|
||||
|
||||
RUN-1004 : used memory is 330 MB, reserved memory is 300 MB, peak memory is 404 MB
|
||||
RUN-1004 : used memory is 341 MB, reserved memory is 312 MB, peak memory is 402 MB
|
||||
RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
|
||||
RUN-1002 : start command "get_ports clock_source"
|
||||
RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
|
||||
|
|
@ -1485,33 +1485,79 @@ RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise:
|
|||
RUN-1002 : start command "get_ports b_lvds_clk_p"
|
||||
RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
|
||||
RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
|
||||
RUN-1002 : start command "derive_pll_clocks"
|
||||
USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
|
||||
RUN-1002 : start command "get_ports clock_source"
|
||||
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
|
||||
RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
|
||||
RUN-1002 : start command "get_ports a_lvds_clk_p"
|
||||
RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
|
||||
RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
|
||||
RUN-1002 : start command "get_ports b_lvds_clk_p"
|
||||
RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
|
||||
RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
|
||||
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
|
||||
RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
|
||||
USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
|
||||
RUN-1002 : start command "get_ports clock_source"
|
||||
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
|
||||
RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
|
||||
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
|
||||
RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
|
||||
USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
|
||||
RUN-1002 : start command "get_ports clock_source"
|
||||
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
|
||||
RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
|
||||
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
|
||||
RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
|
||||
USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
|
||||
RUN-1002 : start command "get_ports clock_source"
|
||||
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
|
||||
RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
|
||||
RUN-1002 : start command "get_ports a_lvds_clk_p"
|
||||
RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
|
||||
RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
|
||||
RUN-1002 : start command "get_ports b_lvds_clk_p"
|
||||
RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
|
||||
RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
|
||||
RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
|
||||
USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
|
||||
RUN-1002 : start command "get_ports clock_source"
|
||||
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
|
||||
RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
|
||||
RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
|
||||
USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
|
||||
RUN-1002 : start command "get_ports a_lvds_clk_p"
|
||||
RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
|
||||
RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
|
||||
USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
|
||||
RUN-1002 : start command "get_ports a_lvds_clk_p"
|
||||
RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
|
||||
RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
|
||||
USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
|
||||
RUN-1002 : start command "get_ports b_lvds_clk_p"
|
||||
RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
|
||||
RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
|
||||
USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
|
||||
RUN-1002 : start command "get_ports b_lvds_clk_p"
|
||||
RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
|
||||
RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
|
||||
RUN-1002 : start command "get_ports clock_source"
|
||||
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
|
||||
RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
|
||||
RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
|
||||
RUN-1002 : start command "get_ports clock_source"
|
||||
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
|
||||
RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
|
||||
RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
|
||||
RUN-1002 : start command "get_ports clock_source"
|
||||
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
|
||||
RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
|
||||
RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
|
||||
RUN-1002 : start command "get_ports clock_source"
|
||||
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
|
||||
RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
|
||||
RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
|
||||
RUN-1002 : start command "get_ports clock_source"
|
||||
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
|
||||
RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
|
||||
RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
|
||||
RUN-1002 : start command "get_ports a_lvds_clk_p"
|
||||
RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
|
||||
RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
|
||||
RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
|
||||
RUN-1002 : start command "get_ports a_lvds_clk_p"
|
||||
RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
|
||||
RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
|
||||
RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
|
||||
RUN-1002 : start command "get_ports b_lvds_clk_p"
|
||||
RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
|
||||
RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
|
||||
RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
|
||||
RUN-1002 : start command "get_ports b_lvds_clk_p"
|
||||
RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
|
||||
RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
|
||||
RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
|
||||
RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
|
||||
RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
|
||||
RUN-1002 : start command "set_false_path -from -to "
|
||||
|
|
@ -1530,8 +1576,6 @@ RUN-1001 : qor_monitor | off | off |
|
|||
RUN-1001 : syn_ip_flow | off | off |
|
||||
RUN-1001 : thread | auto | auto |
|
||||
RUN-1001 : ---------------------------------------------------------------
|
||||
RUN-1002 : start command "set_param gate opt_area low"
|
||||
RUN-1002 : start command "set_param gate opt_timing high"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ------------------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values | Note
|
||||
|
|
@ -1541,8 +1585,8 @@ RUN-1001 : cascade_eram | off | off |
|
|||
RUN-1001 : gate_sim_model | off | off |
|
||||
RUN-1001 : map_sim_model | off | off |
|
||||
RUN-1001 : map_strategy | 1 | 1 |
|
||||
RUN-1001 : opt_area | low | medium | *
|
||||
RUN-1001 : opt_timing | high | auto | *
|
||||
RUN-1001 : opt_area | medium | medium |
|
||||
RUN-1001 : opt_timing | auto | auto |
|
||||
RUN-1001 : pack_effort | medium | medium |
|
||||
RUN-1001 : pack_lslice_ripple | on | on |
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
|
||||
|
|
@ -1661,9 +1705,9 @@ TMR-2505 : Start building timing graph for model huagao_mipi_top.
|
|||
TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122210, tnet num: 36686, tinst num: 33958, tnode num: 156562, tedge num: 180011.
|
||||
TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
|
||||
TMR-2501 : Timing graph initialized successfully.
|
||||
RUN-1003 : finish command "start_timer -prepack" in 1.289776s wall, 1.265625s user + 0.015625s system = 1.281250s CPU (99.3%)
|
||||
RUN-1003 : finish command "start_timer -prepack" in 1.319259s wall, 1.281250s user + 0.031250s system = 1.312500s CPU (99.5%)
|
||||
|
||||
RUN-1004 : used memory is 521 MB, reserved memory is 497 MB, peak memory is 521 MB
|
||||
RUN-1004 : used memory is 523 MB, reserved memory is 498 MB, peak memory is 523 MB
|
||||
TMR-2503 : Start to update net delay, extr mode = 2.
|
||||
TMR-2504 : Update delay of 36686 nets completely.
|
||||
TMR-2502 : Annotate delay completely, extr mode = 2.
|
||||
|
|
@ -1674,11 +1718,11 @@ TMR-3501 : Forward propagation: start to calculate arrival time...
|
|||
TMR-3502 : Backward propagation: start to calculate required time...
|
||||
TMR-3503 : Timing propagation completes.
|
||||
SYN-3001 : Running gate level optimization.
|
||||
SYN-2581 : Mapping with K=5, #lut = 7492 (3.85), #lev = 9 (3.15)
|
||||
SYN-2581 : Mapping with K=5, #lut = 7686 (3.74), #lev = 9 (3.22)
|
||||
SYN-2551 : Post LUT mapping optimization.
|
||||
SYN-2581 : Mapping with K=5, #lut = 7309 (3.95), #lev = 7 (3.04)
|
||||
SYN-3001 : Logic optimization runtime opt = 1.26 sec, map = 0.00 sec
|
||||
SYN-3001 : Mapper mapped 18922 instances into 7337 LUTs, name keeping = 61%.
|
||||
SYN-2581 : Mapping with K=5, #lut = 7614 (3.68), #lev = 8 (3.57)
|
||||
SYN-3001 : Logic optimization runtime opt = 1.22 sec, map = 0.00 sec
|
||||
SYN-3001 : Mapper mapped 18922 instances into 7642 LUTs, name keeping = 57%.
|
||||
SYN-3001 : Mapper removed 2 lut buffers
|
||||
RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
|
||||
RUN-1001 : standard
|
||||
|
|
@ -1691,15 +1735,15 @@ IO Statistics
|
|||
#inout 0
|
||||
|
||||
LUT Statistics
|
||||
#Total_luts 9912
|
||||
#lut4 5066
|
||||
#lut5 2291
|
||||
#Total_luts 10217
|
||||
#lut4 6529
|
||||
#lut5 1133
|
||||
#lut6 0
|
||||
#lut5_mx41 0
|
||||
#lut4_alu1b 2555
|
||||
|
||||
Utilization Statistics
|
||||
#lut 9912 out of 19600 50.57%
|
||||
#lut 10217 out of 19600 52.13%
|
||||
#reg 9232 out of 19600 47.10%
|
||||
#le 0
|
||||
#dsp 3 out of 29 10.34%
|
||||
|
|
@ -1718,31 +1762,31 @@ Report Hierarchy Area:
|
|||
+-------------------------------------------------------------------------------------------------+
|
||||
|Instance |Module |lut |ripple |seq |bram |dsp |
|
||||
+-------------------------------------------------------------------------------------------------+
|
||||
|top |huagao_mipi_top |7357 |2555 |9266 |58 |3 |
|
||||
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |343 |81 |441 |4 |1 |
|
||||
| U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 |
|
||||
|top |huagao_mipi_top |7662 |2555 |9266 |58 |3 |
|
||||
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |360 |81 |441 |4 |1 |
|
||||
| U_crc16_24b |crc16_24b |52 |0 |16 |0 |0 |
|
||||
| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
|
||||
| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
|
||||
| exdev_ctl_a |exdev_ctl |288 |234 |559 |0 |0 |
|
||||
| u_ADconfig |AD_config |102 |49 |138 |0 |0 |
|
||||
| u_gen_sp |gen_sp |128 |185 |104 |0 |0 |
|
||||
| exdev_ctl_b |exdev_ctl |276 |234 |546 |0 |0 |
|
||||
| u_ADconfig |AD_config |92 |49 |125 |0 |0 |
|
||||
| u_gen_sp |gen_sp |126 |185 |104 |0 |0 |
|
||||
| sampling_fe_a |sampling_fe |2277 |738 |1919 |25 |0 |
|
||||
| U_fifo_w32_d8192 |fifo_w32_d8192 |55 |14 |90 |4 |0 |
|
||||
| exdev_ctl_a |exdev_ctl |326 |234 |559 |0 |0 |
|
||||
| u_ADconfig |AD_config |116 |49 |138 |0 |0 |
|
||||
| u_gen_sp |gen_sp |139 |185 |104 |0 |0 |
|
||||
| exdev_ctl_b |exdev_ctl |314 |234 |546 |0 |0 |
|
||||
| u_ADconfig |AD_config |105 |49 |125 |0 |0 |
|
||||
| u_gen_sp |gen_sp |138 |185 |104 |0 |0 |
|
||||
| sampling_fe_a |sampling_fe |2318 |738 |1919 |25 |0 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
|
||||
| u_ad_sampling |ad_sampling |43 |47 |147 |0 |0 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_sort |sort |2207 |691 |1737 |25 |0 |
|
||||
| u_sort |sort |2243 |691 |1737 |25 |0 |
|
||||
| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_data_prebuffer |data_prebuffer |1866 |615 |1391 |22 |0 |
|
||||
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
|
||||
| fifo_adc |fifo_adc |51 |24 |41 |0 |0 |
|
||||
| ram_switch |ram_switch |1444 |422 |1023 |0 |0 |
|
||||
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
|
||||
| u_data_prebuffer |data_prebuffer |1913 |615 |1391 |22 |0 |
|
||||
| channelPart |channel_part_8478 |150 |11 |144 |0 |0 |
|
||||
| fifo_adc |fifo_adc |52 |24 |41 |0 |0 |
|
||||
| ram_switch |ram_switch |1476 |422 |1023 |0 |0 |
|
||||
| adc_addr_gen |adc_addr_gen |130 |99 |115 |0 |0 |
|
||||
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
|
||||
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
|
|
@ -1752,11 +1796,11 @@ Report Hierarchy Area:
|
|||
| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| insert |insert |265 |323 |692 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |1050 |0 |216 |0 |0 |
|
||||
| read_ram_i |read_ram |189 |158 |164 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr |161 |145 |127 |0 |0 |
|
||||
| read_ram_data |read_ram_data |27 |13 |32 |0 |0 |
|
||||
| insert |insert |264 |323 |692 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |1082 |0 |216 |0 |0 |
|
||||
| read_ram_i |read_ram |199 |158 |164 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr |169 |145 |127 |0 |0 |
|
||||
| read_ram_data |read_ram_data |29 |13 |32 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
|
|
@ -1780,23 +1824,23 @@ Report Hierarchy Area:
|
|||
| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 |
|
||||
| u_transfer_300_to_200 |transfer_300_to_200 |108 |76 |276 |3 |0 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
|
||||
| sampling_fe_b |sampling_fe_rev |2297 |751 |1936 |25 |1 |
|
||||
| sampling_fe_b |sampling_fe_rev |2332 |751 |1936 |25 |1 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 |
|
||||
| u_ad_sampling |ad_sampling |44 |47 |147 |0 |0 |
|
||||
| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_sort |sort_rev |2227 |704 |1754 |25 |1 |
|
||||
| u_sort |sort_rev |2256 |704 |1754 |25 |1 |
|
||||
| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
|
||||
| u_data_prebuffer_rev |data_prebuffer_rev |1888 |628 |1408 |22 |1 |
|
||||
| channelPart |channel_part_8478 |146 |11 |144 |0 |0 |
|
||||
| fifo_adc |fifo_adc |51 |24 |41 |0 |1 |
|
||||
| ram_switch |ram_switch |1443 |422 |1023 |0 |0 |
|
||||
| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 |
|
||||
| u_data_prebuffer_rev |data_prebuffer_rev |1928 |628 |1408 |22 |1 |
|
||||
| channelPart |channel_part_8478 |150 |11 |144 |0 |0 |
|
||||
| fifo_adc |fifo_adc |52 |24 |41 |0 |1 |
|
||||
| ram_switch |ram_switch |1473 |422 |1023 |0 |0 |
|
||||
| adc_addr_gen |adc_addr_gen |130 |99 |115 |0 |0 |
|
||||
| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
|
||||
| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
|
|
@ -1806,11 +1850,11 @@ Report Hierarchy Area:
|
|||
| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
|
||||
| insert |insert |265 |323 |692 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |1049 |0 |216 |0 |0 |
|
||||
| read_ram_i |read_ram_rev |210 |171 |181 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr_rev |182 |145 |139 |0 |0 |
|
||||
| read_ram_data |read_ram_data_rev |28 |26 |42 |0 |0 |
|
||||
| insert |insert |264 |323 |692 |0 |0 |
|
||||
| ram_switch_state |ram_switch_state |1079 |0 |216 |0 |0 |
|
||||
| read_ram_i |read_ram_rev |215 |171 |181 |0 |0 |
|
||||
| read_ram_addr |read_ram_addr_rev |185 |145 |139 |0 |0 |
|
||||
| read_ram_data |read_ram_data_rev |30 |26 |42 |0 |0 |
|
||||
| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
|
||||
|
|
@ -1834,9 +1878,9 @@ SYN-4007 : Packing 0 gate4 to BLE ...
|
|||
SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
|
||||
SYN-4012 : Packed 0 FxMUX
|
||||
SYN-4013 : Packed 16 DRAM and 4 SEQ.
|
||||
RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 58.555008s wall, 58.328125s user + 0.187500s system = 58.515625s CPU (99.9%)
|
||||
RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 40.879261s wall, 40.546875s user + 0.312500s system = 40.859375s CPU (100.0%)
|
||||
|
||||
RUN-1004 : used memory is 399 MB, reserved memory is 388 MB, peak memory is 704 MB
|
||||
RUN-1004 : used memory is 396 MB, reserved memory is 380 MB, peak memory is 700 MB
|
||||
RUN-1002 : start command "legalize_phy_inst"
|
||||
SYN-1011 : Flatten model huagao_mipi_top
|
||||
SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
|
||||
|
|
@ -1856,8 +1900,8 @@ RUN-1001 : Exported violations
|
|||
RUN-1001 : Exported timing constraints
|
||||
RUN-1001 : Exported IO constraints
|
||||
RUN-1001 : Exported Inst constraints
|
||||
RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.568878s wall, 2.703125s user + 0.015625s system = 2.718750s CPU (173.3%)
|
||||
RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.547657s wall, 2.703125s user + 0.015625s system = 2.718750s CPU (175.7%)
|
||||
|
||||
RUN-1004 : used memory is 406 MB, reserved memory is 382 MB, peak memory is 704 MB
|
||||
RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_163838.log"
|
||||
RUN-1004 : used memory is 407 MB, reserved memory is 385 MB, peak memory is 700 MB
|
||||
RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240313_175317.log"
|
||||
RUN-1001 : Backing up run's log file succeed.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -4629,3 +4629,762 @@ RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -m
|
|||
|
||||
RUN-1004 : used memory is 2402 MB, reserved memory is 2403 MB, peak memory is 2421 MB
|
||||
GUI-1001 : Downloading succeeded!
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
|
||||
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
|
||||
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
|
||||
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
|
||||
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
|
||||
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
|
||||
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(720)
|
||||
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(729)
|
||||
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(753)
|
||||
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(755)
|
||||
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(761)
|
||||
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(764)
|
||||
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(935)
|
||||
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1024)
|
||||
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1325)
|
||||
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1336)
|
||||
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1354)
|
||||
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1536)
|
||||
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1932)
|
||||
RUN-1001 : reset_run syn_1 phy_1.
|
||||
GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
|
||||
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
|
||||
RUN-1001 : stop_run syn_1.
|
||||
RUN-1001 : reset_run syn_1 -step opt_rtl.
|
||||
RUN-1001 : syn_1: run complete.
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
|
||||
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
|
||||
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
|
||||
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
|
||||
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
|
||||
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
|
||||
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(720)
|
||||
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(729)
|
||||
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(753)
|
||||
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(755)
|
||||
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(761)
|
||||
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(764)
|
||||
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(935)
|
||||
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1024)
|
||||
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1325)
|
||||
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1336)
|
||||
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1354)
|
||||
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1536)
|
||||
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1932)
|
||||
RUN-1001 : reset_run syn_1 phy_1.
|
||||
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
|
||||
RUN-1001 : syn_1: run complete.
|
||||
RUN-1001 : phy_1: run complete.
|
||||
RUN-1001 : open_run phy_1.
|
||||
RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
|
||||
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
|
||||
RUN-1001 : Database version number 46146.
|
||||
RUN-1001 : Import flow parameters
|
||||
PHY-1001 : Generate detailed routing grids ...
|
||||
PHY-1001 : Generate nets ...
|
||||
PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||
PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||
PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
|
||||
PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
|
||||
PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
|
||||
PHY-5010 Similar messages will be suppressed.
|
||||
PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
|
||||
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
|
||||
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
|
||||
PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
|
||||
PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
|
||||
PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
|
||||
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
|
||||
PHY-1001 : eco open net = 0
|
||||
PHY-1001 : 565 feed throughs used by 440 nets
|
||||
RUN-1001 : Import timing constraints
|
||||
RUN-1001 : Import IO constraints
|
||||
RUN-1001 : Import Inst constraints
|
||||
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
|
||||
RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 10.070509s wall, 10.109375s user + 0.515625s system = 10.625000s CPU (105.5%)
|
||||
|
||||
RUN-1004 : used memory is 2397 MB, reserved memory is 2399 MB, peak memory is 2421 MB
|
||||
TMR-3509 : Import timing summary.
|
||||
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
|
||||
PRG-2014 : Chip validation success: EAGLE_S20_EG176
|
||||
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||
RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
|
||||
RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 8.351717s wall, 0.140625s user + 0.328125s system = 0.468750s CPU (5.6%)
|
||||
|
||||
RUN-1004 : used memory is 2404 MB, reserved memory is 2403 MB, peak memory is 2423 MB
|
||||
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 8.533473s wall, 0.250000s user + 0.343750s system = 0.593750s CPU (7.0%)
|
||||
|
||||
RUN-1004 : used memory is 2404 MB, reserved memory is 2403 MB, peak memory is 2423 MB
|
||||
GUI-8702 ERROR: Downloading failed!
|
||||
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode program_spi -v -spd 7 -sec 64 -cable 0 -flashsize 128"
|
||||
PRG-2014 : Chip validation success: EAGLE_S20_EG176
|
||||
PRG-1001 : SPI Flash ID is: ef
|
||||
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m program_spi -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||
RUN-1003 : finish command "bit_to_vec -chip EAGLE_S20_EG176 -m program_spi -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit" in 2.166066s wall, 2.109375s user + 0.109375s system = 2.218750s CPU (102.4%)
|
||||
|
||||
RUN-1004 : used memory is 2570 MB, reserved memory is 2581 MB, peak memory is 2581 MB
|
||||
RUN-1002 : start command "program_spi -cable 0 -spd 7"
|
||||
RUN-1003 : finish command "program_spi -cable 0 -spd 7" in 110.313478s wall, 6.546875s user + 3.734375s system = 10.281250s CPU (9.3%)
|
||||
|
||||
RUN-1004 : used memory is 2572 MB, reserved memory is 2583 MB, peak memory is 2581 MB
|
||||
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m verify_spi -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||
RUN-1002 : start command "program -cable 0 -spd 4"
|
||||
RUN-1003 : finish command "program -cable 0 -spd 4" in 23.201341s wall, 0.875000s user + 0.703125s system = 1.578125s CPU (6.8%)
|
||||
|
||||
RUN-1004 : used memory is 2352 MB, reserved memory is 2350 MB, peak memory is 2581 MB
|
||||
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode program_spi -v -spd 7 -sec 64 -cable 0 -flashsize 128" in 139.906760s wall, 11.468750s user + 4.640625s system = 16.109375s CPU (11.5%)
|
||||
|
||||
RUN-1004 : used memory is 2352 MB, reserved memory is 2350 MB, peak memory is 2581 MB
|
||||
GUI-1001 : Downloading succeeded!
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
|
||||
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
|
||||
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
|
||||
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
|
||||
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
|
||||
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
|
||||
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(730)
|
||||
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
|
||||
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(763)
|
||||
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(765)
|
||||
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(771)
|
||||
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(774)
|
||||
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(945)
|
||||
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1034)
|
||||
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1335)
|
||||
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1346)
|
||||
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1364)
|
||||
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1546)
|
||||
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1942)
|
||||
RUN-1001 : reset_run syn_1 phy_1.
|
||||
GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
|
||||
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
|
||||
RUN-6001 WARNING: syn_1: run failed.
|
||||
RUN-1001 : reset_run syn_1 phy_1.
|
||||
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
|
||||
RUN-1001 : stop_run syn_1.
|
||||
RUN-1001 : reset_run syn_1 -step opt_gate.
|
||||
RUN-1001 : syn_1: run complete.
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
|
||||
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
|
||||
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
|
||||
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
|
||||
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
|
||||
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
|
||||
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(730)
|
||||
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
|
||||
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(763)
|
||||
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(765)
|
||||
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(771)
|
||||
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(774)
|
||||
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(945)
|
||||
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1034)
|
||||
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1335)
|
||||
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1346)
|
||||
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1364)
|
||||
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1546)
|
||||
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1942)
|
||||
RUN-1001 : reset_run syn_1 phy_1.
|
||||
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
|
||||
RUN-1001 : syn_1: run complete.
|
||||
RUN-1001 : phy_1: run complete.
|
||||
RUN-1001 : open_run phy_1.
|
||||
RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
|
||||
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
|
||||
RUN-1001 : Database version number 46146.
|
||||
RUN-1001 : Import flow parameters
|
||||
PHY-1001 : Generate detailed routing grids ...
|
||||
PHY-1001 : Generate nets ...
|
||||
PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||
PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||
PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
|
||||
PHY-5010 Similar messages will be suppressed.
|
||||
PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
|
||||
PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
|
||||
PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
|
||||
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
|
||||
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
|
||||
PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
|
||||
PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
|
||||
PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
|
||||
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
|
||||
PHY-1001 : eco open net = 0
|
||||
PHY-1001 : 565 feed throughs used by 415 nets
|
||||
RUN-1001 : Import timing constraints
|
||||
RUN-1001 : Import IO constraints
|
||||
RUN-1001 : Import Inst constraints
|
||||
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
|
||||
RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 9.039164s wall, 9.046875s user + 0.390625s system = 9.437500s CPU (104.4%)
|
||||
|
||||
RUN-1004 : used memory is 2409 MB, reserved memory is 2411 MB, peak memory is 2581 MB
|
||||
TMR-3509 : Import timing summary.
|
||||
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode program_spi -v -spd 7 -sec 64 -cable 0 -flashsize 128"
|
||||
PRG-2014 : Chip validation success: EAGLE_S20_EG176
|
||||
PRG-1001 : SPI Flash ID is: ef
|
||||
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m program_spi -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||
RUN-1003 : finish command "bit_to_vec -chip EAGLE_S20_EG176 -m program_spi -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit" in 2.170944s wall, 2.203125s user + 0.109375s system = 2.312500s CPU (106.5%)
|
||||
|
||||
RUN-1004 : used memory is 2583 MB, reserved memory is 2597 MB, peak memory is 2594 MB
|
||||
RUN-1002 : start command "program_spi -cable 0 -spd 7"
|
||||
RUN-1003 : finish command "program_spi -cable 0 -spd 7" in 110.485585s wall, 4.578125s user + 2.656250s system = 7.234375s CPU (6.5%)
|
||||
|
||||
RUN-1004 : used memory is 2584 MB, reserved memory is 2599 MB, peak memory is 2594 MB
|
||||
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m verify_spi -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||
RUN-1002 : start command "program -cable 0 -spd 4"
|
||||
RUN-1003 : finish command "program -cable 0 -spd 4" in 23.196154s wall, 0.437500s user + 0.062500s system = 0.500000s CPU (2.2%)
|
||||
|
||||
RUN-1004 : used memory is 2488 MB, reserved memory is 2495 MB, peak memory is 2594 MB
|
||||
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode program_spi -v -spd 7 -sec 64 -cable 0 -flashsize 128" in 140.071367s wall, 9.078125s user + 2.921875s system = 12.000000s CPU (8.6%)
|
||||
|
||||
RUN-1004 : used memory is 2488 MB, reserved memory is 2495 MB, peak memory is 2594 MB
|
||||
GUI-1001 : Downloading succeeded!
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
|
||||
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
|
||||
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
|
||||
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
|
||||
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
|
||||
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
|
||||
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(720)
|
||||
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(729)
|
||||
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(753)
|
||||
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(755)
|
||||
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(761)
|
||||
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(764)
|
||||
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(935)
|
||||
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1024)
|
||||
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1325)
|
||||
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1336)
|
||||
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1354)
|
||||
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1536)
|
||||
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1932)
|
||||
RUN-1001 : reset_run syn_1 phy_1.
|
||||
GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
|
||||
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
|
||||
RUN-1001 : syn_1: run complete.
|
||||
RUN-1001 : phy_1: run complete.
|
||||
RUN-1001 : open_run phy_1.
|
||||
RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
|
||||
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
|
||||
RUN-1001 : Database version number 46146.
|
||||
RUN-1001 : Import flow parameters
|
||||
PHY-1001 : Generate detailed routing grids ...
|
||||
PHY-1001 : Generate nets ...
|
||||
PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||
PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||
PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
|
||||
PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
|
||||
PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
|
||||
PHY-5010 Similar messages will be suppressed.
|
||||
PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
|
||||
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
|
||||
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
|
||||
PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
|
||||
PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
|
||||
PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
|
||||
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
|
||||
PHY-1001 : eco open net = 0
|
||||
PHY-1001 : 565 feed throughs used by 440 nets
|
||||
RUN-1001 : Import timing constraints
|
||||
RUN-1001 : Import IO constraints
|
||||
RUN-1001 : Import Inst constraints
|
||||
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
|
||||
RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 8.961547s wall, 9.093750s user + 0.359375s system = 9.453125s CPU (105.5%)
|
||||
|
||||
RUN-1004 : used memory is 2508 MB, reserved memory is 2513 MB, peak memory is 2594 MB
|
||||
TMR-3509 : Import timing summary.
|
||||
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
|
||||
PRG-2014 : Chip validation success: EAGLE_S20_EG176
|
||||
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||
RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
|
||||
RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.750061s wall, 0.265625s user + 0.328125s system = 0.593750s CPU (3.3%)
|
||||
|
||||
RUN-1004 : used memory is 2512 MB, reserved memory is 2517 MB, peak memory is 2594 MB
|
||||
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.965720s wall, 0.375000s user + 0.328125s system = 0.703125s CPU (3.9%)
|
||||
|
||||
RUN-1004 : used memory is 2512 MB, reserved memory is 2517 MB, peak memory is 2594 MB
|
||||
GUI-1001 : Downloading succeeded!
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
|
||||
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
|
||||
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
|
||||
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
|
||||
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
|
||||
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
|
||||
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
|
||||
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(740)
|
||||
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(764)
|
||||
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(766)
|
||||
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(772)
|
||||
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(775)
|
||||
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(946)
|
||||
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1035)
|
||||
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1336)
|
||||
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1347)
|
||||
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1365)
|
||||
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1547)
|
||||
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1943)
|
||||
RUN-1001 : reset_run syn_1 phy_1.
|
||||
GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
|
||||
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
|
||||
RUN-1001 : syn_1: run complete.
|
||||
RUN-1001 : phy_1: run complete.
|
||||
RUN-1001 : open_run phy_1.
|
||||
RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
|
||||
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
|
||||
RUN-1001 : Database version number 46146.
|
||||
RUN-1001 : Import flow parameters
|
||||
PHY-1001 : Generate detailed routing grids ...
|
||||
PHY-1001 : Generate nets ...
|
||||
PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||
PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||
PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
|
||||
PHY-5010 Similar messages will be suppressed.
|
||||
PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
|
||||
PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
|
||||
PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
|
||||
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
|
||||
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
|
||||
PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
|
||||
PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
|
||||
PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
|
||||
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
|
||||
PHY-1001 : eco open net = 0
|
||||
PHY-1001 : 606 feed throughs used by 414 nets
|
||||
RUN-1001 : Import timing constraints
|
||||
RUN-1001 : Import IO constraints
|
||||
RUN-1001 : Import Inst constraints
|
||||
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
|
||||
RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 9.096658s wall, 9.093750s user + 0.171875s system = 9.265625s CPU (101.9%)
|
||||
|
||||
RUN-1004 : used memory is 2524 MB, reserved memory is 2529 MB, peak memory is 2594 MB
|
||||
TMR-3509 : Import timing summary.
|
||||
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
|
||||
PRG-2014 : Chip validation success: EAGLE_S20_EG176
|
||||
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||
RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
|
||||
RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.772692s wall, 0.437500s user + 0.484375s system = 0.921875s CPU (5.2%)
|
||||
|
||||
RUN-1004 : used memory is 2528 MB, reserved memory is 2533 MB, peak memory is 2594 MB
|
||||
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.999087s wall, 0.562500s user + 0.500000s system = 1.062500s CPU (5.9%)
|
||||
|
||||
RUN-1004 : used memory is 2528 MB, reserved memory is 2533 MB, peak memory is 2594 MB
|
||||
GUI-1001 : Downloading succeeded!
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
|
||||
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
|
||||
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
|
||||
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
|
||||
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
|
||||
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
|
||||
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(721)
|
||||
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(730)
|
||||
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(754)
|
||||
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(756)
|
||||
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(762)
|
||||
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(765)
|
||||
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(936)
|
||||
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1025)
|
||||
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1326)
|
||||
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1337)
|
||||
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1355)
|
||||
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1537)
|
||||
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1933)
|
||||
RUN-1001 : reset_run syn_1 phy_1.
|
||||
GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
|
||||
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
|
||||
RUN-6001 WARNING: syn_1: run failed.
|
||||
RUN-1001 : reset_run syn_1 phy_1.
|
||||
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
|
||||
RUN-1001 : syn_1: run complete.
|
||||
RUN-1001 : phy_1: run complete.
|
||||
RUN-1001 : open_run phy_1.
|
||||
RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
|
||||
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
|
||||
RUN-1001 : Database version number 46146.
|
||||
RUN-1001 : Import flow parameters
|
||||
PHY-1001 : Generate detailed routing grids ...
|
||||
PHY-1001 : Generate nets ...
|
||||
PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||
PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||
PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
|
||||
PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
|
||||
PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
|
||||
PHY-5010 Similar messages will be suppressed.
|
||||
PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
|
||||
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
|
||||
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
|
||||
PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
|
||||
PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
|
||||
PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
|
||||
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
|
||||
PHY-1001 : eco open net = 0
|
||||
PHY-1001 : 565 feed throughs used by 440 nets
|
||||
RUN-1001 : Import timing constraints
|
||||
RUN-1001 : Import IO constraints
|
||||
RUN-1001 : Import Inst constraints
|
||||
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
|
||||
RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 8.984890s wall, 9.093750s user + 0.125000s system = 9.218750s CPU (102.6%)
|
||||
|
||||
RUN-1004 : used memory is 2511 MB, reserved memory is 2516 MB, peak memory is 2594 MB
|
||||
TMR-3509 : Import timing summary.
|
||||
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
|
||||
PRG-2014 : Chip validation success: EAGLE_S20_EG176
|
||||
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||
RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
|
||||
RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.759113s wall, 0.312500s user + 0.546875s system = 0.859375s CPU (4.8%)
|
||||
|
||||
RUN-1004 : used memory is 2515 MB, reserved memory is 2520 MB, peak memory is 2594 MB
|
||||
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.987019s wall, 0.421875s user + 0.578125s system = 1.000000s CPU (5.6%)
|
||||
|
||||
RUN-1004 : used memory is 2515 MB, reserved memory is 2520 MB, peak memory is 2594 MB
|
||||
GUI-1001 : Downloading succeeded!
|
||||
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode program_spi -v -spd 9 -sec 64 -cable 0 -flashsize 128"
|
||||
PRG-2014 : Chip validation success: EAGLE_S20_EG176
|
||||
PRG-1001 : SPI Flash ID is: ef
|
||||
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m program_spi -freq 12 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||
RUN-1003 : finish command "bit_to_vec -chip EAGLE_S20_EG176 -m program_spi -freq 12 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit" in 2.098053s wall, 2.093750s user + 0.062500s system = 2.156250s CPU (102.8%)
|
||||
|
||||
RUN-1004 : used memory is 2610 MB, reserved memory is 2624 MB, peak memory is 2621 MB
|
||||
RUN-1002 : start command "program_spi -cable 0 -spd 9"
|
||||
RUN-1003 : finish command "program_spi -cable 0 -spd 9" in 110.842869s wall, 4.140625s user + 3.171875s system = 7.312500s CPU (6.6%)
|
||||
|
||||
RUN-1004 : used memory is 2607 MB, reserved memory is 2622 MB, peak memory is 2621 MB
|
||||
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m verify_spi -freq 12 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||
RUN-1002 : start command "program -cable 0 -spd 4"
|
||||
RUN-1003 : finish command "program -cable 0 -spd 4" in 23.222147s wall, 0.875000s user + 0.609375s system = 1.484375s CPU (6.4%)
|
||||
|
||||
RUN-1004 : used memory is 2388 MB, reserved memory is 2394 MB, peak memory is 2621 MB
|
||||
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode program_spi -v -spd 9 -sec 64 -cable 0 -flashsize 128" in 140.404922s wall, 8.921875s user + 4.031250s system = 12.953125s CPU (9.2%)
|
||||
|
||||
RUN-1004 : used memory is 2388 MB, reserved memory is 2394 MB, peak memory is 2621 MB
|
||||
GUI-1001 : Downloading succeeded!
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
|
||||
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
|
||||
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
|
||||
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
|
||||
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
|
||||
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
|
||||
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
|
||||
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(740)
|
||||
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(764)
|
||||
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(766)
|
||||
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(772)
|
||||
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(775)
|
||||
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(946)
|
||||
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1035)
|
||||
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1336)
|
||||
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1347)
|
||||
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1365)
|
||||
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1547)
|
||||
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1943)
|
||||
HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
|
||||
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
|
||||
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
|
||||
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
|
||||
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
|
||||
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
|
||||
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
|
||||
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(740)
|
||||
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(764)
|
||||
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(766)
|
||||
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(772)
|
||||
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(775)
|
||||
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(946)
|
||||
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1035)
|
||||
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1336)
|
||||
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1347)
|
||||
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1365)
|
||||
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1547)
|
||||
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1943)
|
||||
RUN-1001 : reset_run syn_1 phy_1.
|
||||
GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
|
||||
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
|
||||
RUN-1001 : syn_1: run complete.
|
||||
RUN-1001 : phy_1: run complete.
|
||||
RUN-1001 : open_run phy_1.
|
||||
RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
|
||||
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
|
||||
RUN-1001 : Database version number 46146.
|
||||
RUN-1001 : Import flow parameters
|
||||
PHY-1001 : Generate detailed routing grids ...
|
||||
PHY-1001 : Generate nets ...
|
||||
PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||
PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||
PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
|
||||
PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
|
||||
PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
|
||||
PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
|
||||
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
|
||||
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
|
||||
PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
|
||||
PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
|
||||
PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
|
||||
PHY-5010 Similar messages will be suppressed.
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
|
||||
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
|
||||
PHY-1001 : eco open net = 0
|
||||
PHY-1001 : 542 feed throughs used by 413 nets
|
||||
RUN-1001 : Import timing constraints
|
||||
RUN-1001 : Import IO constraints
|
||||
RUN-1001 : Import Inst constraints
|
||||
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
|
||||
RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 9.161801s wall, 9.078125s user + 0.484375s system = 9.562500s CPU (104.4%)
|
||||
|
||||
RUN-1004 : used memory is 2449 MB, reserved memory is 2462 MB, peak memory is 2621 MB
|
||||
TMR-3509 : Import timing summary.
|
||||
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
|
||||
PRG-2014 : Chip validation success: EAGLE_S20_EG176
|
||||
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||
RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
|
||||
RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.793795s wall, 0.187500s user + 0.281250s system = 0.468750s CPU (2.6%)
|
||||
|
||||
RUN-1004 : used memory is 2458 MB, reserved memory is 2468 MB, peak memory is 2621 MB
|
||||
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 18.010599s wall, 0.312500s user + 0.312500s system = 0.625000s CPU (3.5%)
|
||||
|
||||
RUN-1004 : used memory is 2458 MB, reserved memory is 2468 MB, peak memory is 2621 MB
|
||||
GUI-1001 : Downloading succeeded!
|
||||
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
|
||||
PRG-2014 : Chip validation success: EAGLE_S20_EG176
|
||||
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||
RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
|
||||
RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.697184s wall, 0.171875s user + 0.109375s system = 0.281250s CPU (1.6%)
|
||||
|
||||
RUN-1004 : used memory is 2457 MB, reserved memory is 2468 MB, peak memory is 2621 MB
|
||||
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.913611s wall, 0.265625s user + 0.171875s system = 0.437500s CPU (2.4%)
|
||||
|
||||
RUN-1004 : used memory is 2457 MB, reserved memory is 2468 MB, peak memory is 2621 MB
|
||||
GUI-1001 : Downloading succeeded!
|
||||
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode program_spi -v -spd 9 -sec 64 -cable 0 -flashsize 128"
|
||||
PRG-2014 : Chip validation success: EAGLE_S20_EG176
|
||||
PRG-1001 : SPI Flash ID is: ef
|
||||
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m program_spi -freq 12 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||
RUN-1003 : finish command "bit_to_vec -chip EAGLE_S20_EG176 -m program_spi -freq 12 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit" in 2.194974s wall, 2.187500s user + 0.078125s system = 2.265625s CPU (103.2%)
|
||||
|
||||
RUN-1004 : used memory is 2619 MB, reserved memory is 2636 MB, peak memory is 2630 MB
|
||||
RUN-1002 : start command "program_spi -cable 0 -spd 9"
|
||||
RUN-1003 : finish command "program_spi -cable 0 -spd 9" in 110.266327s wall, 8.093750s user + 4.015625s system = 12.109375s CPU (11.0%)
|
||||
|
||||
RUN-1004 : used memory is 2622 MB, reserved memory is 2639 MB, peak memory is 2630 MB
|
||||
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m verify_spi -freq 12 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||
RUN-1002 : start command "program -cable 0 -spd 4"
|
||||
RUN-1003 : finish command "program -cable 0 -spd 4" in 23.248897s wall, 1.328125s user + 0.687500s system = 2.015625s CPU (8.7%)
|
||||
|
||||
RUN-1004 : used memory is 2411 MB, reserved memory is 2411 MB, peak memory is 2630 MB
|
||||
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode program_spi -v -spd 9 -sec 64 -cable 0 -flashsize 128" in 139.980172s wall, 13.578125s user + 4.968750s system = 18.546875s CPU (13.2%)
|
||||
|
||||
RUN-1004 : used memory is 2411 MB, reserved memory is 2411 MB, peak memory is 2630 MB
|
||||
GUI-1001 : Downloading succeeded!
|
||||
RUN-1001 : reset_run syn_1 phy_1.
|
||||
GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
|
||||
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
|
||||
RUN-1001 : syn_1: run complete.
|
||||
RUN-1001 : phy_1: run complete.
|
||||
RUN-1001 : open_run phy_1.
|
||||
RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
|
||||
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
|
||||
RUN-1001 : Database version number 46146.
|
||||
RUN-1001 : Import flow parameters
|
||||
PHY-1001 : Generate detailed routing grids ...
|
||||
PHY-1001 : Generate nets ...
|
||||
PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||
PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||
PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
|
||||
PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
|
||||
PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
|
||||
PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
|
||||
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
|
||||
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
|
||||
PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
|
||||
PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
|
||||
PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
|
||||
PHY-5010 Similar messages will be suppressed.
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
|
||||
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
|
||||
PHY-1001 : eco open net = 0
|
||||
PHY-1001 : 549 feed throughs used by 408 nets
|
||||
RUN-1001 : Import timing constraints
|
||||
RUN-1001 : Import IO constraints
|
||||
RUN-1001 : Import Inst constraints
|
||||
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
|
||||
RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 9.798709s wall, 9.812500s user + 0.312500s system = 10.125000s CPU (103.3%)
|
||||
|
||||
RUN-1004 : used memory is 2459 MB, reserved memory is 2472 MB, peak memory is 2630 MB
|
||||
TMR-3509 : Import timing summary.
|
||||
RUN-1001 : reset_run syn_1 phy_1.
|
||||
RUN-1001 : launch_runs syn_1 phy_1 -jobs 6.
|
||||
RUN-1001 : syn_1: run complete.
|
||||
RUN-1001 : phy_1: run complete.
|
||||
RUN-1001 : open_run phy_1.
|
||||
RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
|
||||
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
|
||||
RUN-1001 : Database version number 46146.
|
||||
RUN-1001 : Import flow parameters
|
||||
PHY-1001 : Generate detailed routing grids ...
|
||||
PHY-1001 : Generate nets ...
|
||||
PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||
PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
|
||||
PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
|
||||
PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
|
||||
PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
|
||||
PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
|
||||
PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
|
||||
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
|
||||
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
|
||||
PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
|
||||
PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
|
||||
PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
|
||||
PHY-5010 Similar messages will be suppressed.
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
|
||||
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
|
||||
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
|
||||
PHY-1001 : eco open net = 0
|
||||
PHY-1001 : 539 feed throughs used by 407 nets
|
||||
RUN-1001 : Import timing constraints
|
||||
RUN-1001 : Import IO constraints
|
||||
RUN-1001 : Import Inst constraints
|
||||
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
|
||||
RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 8.805354s wall, 8.843750s user + 0.437500s system = 9.281250s CPU (105.4%)
|
||||
|
||||
RUN-1004 : used memory is 2482 MB, reserved memory is 2495 MB, peak memory is 2630 MB
|
||||
TMR-3509 : Import timing summary.
|
||||
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
|
||||
PRG-2014 : Chip validation success: EAGLE_S20_EG176
|
||||
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||
RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
|
||||
RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.688468s wall, 0.250000s user + 0.484375s system = 0.734375s CPU (4.2%)
|
||||
|
||||
RUN-1004 : used memory is 2489 MB, reserved memory is 2501 MB, peak memory is 2630 MB
|
||||
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.911673s wall, 0.359375s user + 0.515625s system = 0.875000s CPU (4.9%)
|
||||
|
||||
RUN-1004 : used memory is 2489 MB, reserved memory is 2501 MB, peak memory is 2630 MB
|
||||
GUI-1001 : Downloading succeeded!
|
||||
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
|
||||
PRG-2014 : Chip validation success: EAGLE_S20_EG176
|
||||
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||
RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
|
||||
RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.747338s wall, 0.156250s user + 0.093750s system = 0.250000s CPU (1.4%)
|
||||
|
||||
RUN-1004 : used memory is 2486 MB, reserved memory is 2500 MB, peak memory is 2630 MB
|
||||
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.966988s wall, 0.265625s user + 0.125000s system = 0.390625s CPU (2.2%)
|
||||
|
||||
RUN-1004 : used memory is 2486 MB, reserved memory is 2500 MB, peak memory is 2630 MB
|
||||
GUI-1001 : Downloading succeeded!
|
||||
RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode program_spi -v -spd 9 -sec 64 -cable 0 -flashsize 128"
|
||||
PRG-2014 : Chip validation success: EAGLE_S20_EG176
|
||||
PRG-1001 : SPI Flash ID is: ef
|
||||
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m program_spi -freq 12 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||
RUN-1003 : finish command "bit_to_vec -chip EAGLE_S20_EG176 -m program_spi -freq 12 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit" in 2.186125s wall, 2.156250s user + 0.093750s system = 2.250000s CPU (102.9%)
|
||||
|
||||
RUN-1004 : used memory is 2653 MB, reserved memory is 2673 MB, peak memory is 2664 MB
|
||||
RUN-1002 : start command "program_spi -cable 0 -spd 9"
|
||||
RUN-1003 : finish command "program_spi -cable 0 -spd 9" in 111.706911s wall, 3.812500s user + 0.656250s system = 4.468750s CPU (4.0%)
|
||||
|
||||
RUN-1004 : used memory is 2650 MB, reserved memory is 2671 MB, peak memory is 2664 MB
|
||||
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m verify_spi -freq 12 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
|
||||
RUN-1002 : start command "program -cable 0 -spd 4"
|
||||
RUN-1003 : finish command "program -cable 0 -spd 4" in 23.281692s wall, 0.406250s user + 0.140625s system = 0.546875s CPU (2.3%)
|
||||
|
||||
RUN-1004 : used memory is 2559 MB, reserved memory is 2572 MB, peak memory is 2664 MB
|
||||
RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode program_spi -v -spd 9 -sec 64 -cable 0 -flashsize 128" in 141.411065s wall, 8.187500s user + 1.015625s system = 9.203125s CPU (6.5%)
|
||||
|
||||
RUN-1004 : used memory is 2559 MB, reserved memory is 2572 MB, peak memory is 2664 MB
|
||||
GUI-1001 : Downloading succeeded!
|
||||
TMR-3509 : Import timing summary.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,12 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.6.71036
|
||||
Copyright (c) 2012-2023 Anlogic Inc.
|
||||
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
|
||||
Built at = 20:34:38 Mar 21 2023
|
||||
Run by = holdtecs
|
||||
Run Date = Wed Mar 13 14:55:51 2024
|
||||
|
||||
Run on = DESKTOP-5MQL5VE
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
GUI-2000 : The IP files have been created successfully :Set_ip_dir=D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/hg_mp/anlogic_ip/pll
|
||||
Loading…
Reference in New Issue