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lvds-mono-16m
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7 Commits 1 Branch 0 Tags 221 MiB
Verilog 87.4%
VHDL 9.6%
Tcl 1.4%
Perl 1%
Stata 0.3%
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17828169534 ffaa661020 修改sdc时钟约束为derive_pll_clocks 2024-03-13 17:58:42 +08:00
sim/1123 update mipi.dat, 2024-03-08 22:26:06 -05:00
src 修改sdc时钟约束为derive_pll_clocks 2024-03-13 17:58:42 +08:00