2023-12-19 07:27:16 +00:00
|
|
|
#pragma once
|
|
|
|
#include <string>
|
|
|
|
#include <memory>
|
2024-01-23 07:07:17 +00:00
|
|
|
#include <vector>
|
2023-12-19 07:27:16 +00:00
|
|
|
#include "../uart/regsaccess.h"
|
|
|
|
|
|
|
|
#ifdef HAS_UV
|
|
|
|
#define MAX_REGS 0x0e
|
|
|
|
#else
|
2024-01-05 09:36:50 +00:00
|
|
|
#define MAX_REGS 0x10
|
2023-12-19 07:27:16 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
typedef struct Frame_FPGA
|
|
|
|
{
|
|
|
|
unsigned short int height;
|
|
|
|
unsigned short int num : 8;
|
|
|
|
unsigned short int reserved : 8;
|
|
|
|
|
|
|
|
} FrameFpga;
|
|
|
|
|
|
|
|
typedef struct Mode_FPGA
|
|
|
|
{
|
|
|
|
unsigned short int colorMode : 1;
|
2024-01-11 09:59:23 +00:00
|
|
|
unsigned short int dpi : 2; //0x01 200dpi 0x02 300dpi 0x03 600dpi
|
2023-12-19 07:27:16 +00:00
|
|
|
unsigned short int led : 1;
|
|
|
|
unsigned short sample : 9;
|
|
|
|
unsigned short int adcA : 1;
|
|
|
|
unsigned short int adcB : 1;
|
|
|
|
unsigned short int selftest : 1;
|
2024-01-13 09:14:12 +00:00
|
|
|
|
2023-12-19 07:27:16 +00:00
|
|
|
unsigned short int sp;
|
|
|
|
} ModeFpga;
|
|
|
|
|
|
|
|
typedef struct CMD_FPGA
|
|
|
|
{
|
|
|
|
unsigned int cmd : 1; //start : 1 , stop : 0
|
|
|
|
unsigned int reserved : 31;
|
|
|
|
} CmdFpga;
|
|
|
|
|
|
|
|
typedef struct STATUS_FPGA
|
|
|
|
{
|
|
|
|
unsigned int status : 1; //start : 1 , stop : 0
|
|
|
|
unsigned int reserved : 31;
|
|
|
|
} StatusFpga;
|
|
|
|
|
|
|
|
|
|
|
|
typedef struct CIS_AD_Gain
|
|
|
|
{
|
2024-01-11 09:59:23 +00:00
|
|
|
unsigned short int ad0_value : 8; //!< 数据位
|
|
|
|
unsigned short int ad0_reserved : 2; //!< 保留位
|
2023-12-19 07:27:16 +00:00
|
|
|
unsigned short int ad0_addr : 5; //!< 寄存器地址
|
2024-01-11 09:59:23 +00:00
|
|
|
unsigned short int ad0_rw : 1; //!< 读写位 1:读, 0:写
|
|
|
|
unsigned short int ad1_value : 8; //!< 数据位
|
|
|
|
unsigned short int ad1_reserved : 2; //!< 保留位
|
2023-12-19 07:27:16 +00:00
|
|
|
unsigned short int ad1_addr : 5; //!< 寄存器地址
|
2024-01-11 09:59:23 +00:00
|
|
|
unsigned short int ad1_rw : 1; //!< 读写位 1:读, 0:写;
|
2023-12-19 07:27:16 +00:00
|
|
|
} CisAdGain;
|
|
|
|
|
|
|
|
typedef struct CIS_LED_R
|
|
|
|
{
|
|
|
|
unsigned short int ledEnable : 1;
|
|
|
|
unsigned short int sample : 9;
|
|
|
|
unsigned short int reserved : 6;
|
|
|
|
unsigned short int ledR;
|
|
|
|
} CisLedR;
|
|
|
|
|
|
|
|
typedef struct CIS_LED_GB
|
|
|
|
{
|
|
|
|
unsigned short int ledG;
|
|
|
|
unsigned short int ledB;
|
|
|
|
} CisLedGB;
|
|
|
|
|
2024-01-16 09:51:34 +00:00
|
|
|
typedef struct Ad_Gain
|
|
|
|
{
|
|
|
|
unsigned short int gain_low8 : 8;
|
|
|
|
unsigned short int gain_hight : 1;
|
|
|
|
unsigned int reserved : 23;
|
|
|
|
} AdGain;
|
|
|
|
|
|
|
|
typedef struct CIS_LED_RF
|
|
|
|
{
|
|
|
|
unsigned short int ledEnable : 1;
|
|
|
|
unsigned short int fanMode : 2;
|
|
|
|
unsigned short int jamEnable : 1;
|
|
|
|
unsigned short int sample : 9;
|
|
|
|
unsigned short int reserved : 3;
|
|
|
|
unsigned short int ledR;
|
|
|
|
} CisLedRF;
|
|
|
|
|
2023-12-19 07:27:16 +00:00
|
|
|
typedef struct CIS_LED_UV
|
|
|
|
{
|
|
|
|
unsigned short int ledASide;
|
|
|
|
unsigned short int ledBSide;
|
|
|
|
} CisLedUv;
|
|
|
|
|
2024-01-19 08:54:58 +00:00
|
|
|
typedef union CIS_VSP
|
|
|
|
{
|
|
|
|
struct
|
|
|
|
{
|
|
|
|
unsigned int ASide_VSP:9;
|
|
|
|
unsigned int BSide_VSP:9;
|
|
|
|
unsigned int reserved : 14;
|
|
|
|
} bits;
|
|
|
|
int value;
|
|
|
|
} CISVSP;
|
|
|
|
|
2023-12-19 07:27:16 +00:00
|
|
|
typedef union Fpga_Params
|
|
|
|
{
|
|
|
|
struct
|
|
|
|
{
|
|
|
|
FrameFpga frame; //0x00
|
|
|
|
ModeFpga mode; //0x01
|
|
|
|
CmdFpga cmd; //0x02
|
|
|
|
StatusFpga status; //0x03
|
|
|
|
CisAdGain Aad; //0x04
|
|
|
|
CisLedR AledR; //0x05
|
|
|
|
CisLedGB AledGB; //0x06
|
|
|
|
CisAdGain Bad; //0x07
|
|
|
|
#ifndef G300
|
|
|
|
CisLedRF BledR; //0x08
|
|
|
|
#else
|
|
|
|
CisLedR BledR; //0x08
|
|
|
|
#endif
|
|
|
|
CisLedGB BledGB; //0x09
|
|
|
|
unsigned int ExpIncr; //0x0a
|
|
|
|
unsigned int TrigMode; //0x0b
|
|
|
|
unsigned int DelayTime; //0x0c
|
2024-01-19 08:54:58 +00:00
|
|
|
CISVSP vsp; // 0x0d
|
2023-12-19 07:27:16 +00:00
|
|
|
CisLedUv UVLed;
|
|
|
|
};
|
2024-01-05 09:36:50 +00:00
|
|
|
unsigned int regs[MAX_REGS];
|
2023-12-19 07:27:16 +00:00
|
|
|
} FpgaParams;
|
|
|
|
|
|
|
|
#define FPGA_UART "/dev/ttyUSB0"
|
|
|
|
#define MOTOR_UART "/dev/ttyS4"
|
|
|
|
|
|
|
|
enum
|
|
|
|
{
|
|
|
|
GRAY_MODE = 0,
|
|
|
|
COLOR_MODE,
|
|
|
|
};
|
2024-01-16 09:51:34 +00:00
|
|
|
|
2023-12-19 07:27:16 +00:00
|
|
|
enum
|
|
|
|
{
|
2024-01-16 09:51:34 +00:00
|
|
|
DPI_300 = 2,
|
2024-01-11 09:59:23 +00:00
|
|
|
DPI_600,
|
2023-12-19 07:27:16 +00:00
|
|
|
};
|
2023-12-20 07:23:24 +00:00
|
|
|
|
|
|
|
class GpioOut;
|
|
|
|
class Gpio;
|
2023-12-19 07:27:16 +00:00
|
|
|
|
|
|
|
class FpgaComm : public IRegsAccess
|
|
|
|
{
|
2024-01-05 09:36:50 +00:00
|
|
|
int bauds_ = 921600;
|
|
|
|
bool ok_ = true;
|
2023-12-19 07:27:16 +00:00
|
|
|
|
2023-12-20 07:23:24 +00:00
|
|
|
class controller
|
|
|
|
{
|
|
|
|
enum ports
|
|
|
|
{
|
|
|
|
PORT_STATUS = 69,
|
|
|
|
PORT_RELOAD = 70,
|
|
|
|
PORT_CONFIG = 71,
|
2024-01-11 07:23:05 +00:00
|
|
|
PORT_VDD_3VOFF = 96,
|
|
|
|
PORT_VDD_5VEN = 98,
|
|
|
|
PORT_INIT_DONE = 99,
|
|
|
|
PORT_IMAGE_TX = 101,
|
2023-12-20 07:23:24 +00:00
|
|
|
PORT_RESET = 232,
|
|
|
|
};
|
|
|
|
std::unique_ptr<Gpio> status_; // status reader - port 69
|
2024-01-05 09:36:50 +00:00
|
|
|
std::unique_ptr<Gpio> reload_; // codes reload - port 70
|
2023-12-20 07:23:24 +00:00
|
|
|
std::unique_ptr<Gpio> cfg_; // configuration reload - port 71
|
2024-01-05 09:36:50 +00:00
|
|
|
std::unique_ptr<Gpio> reset_; // circuit reset - port Fpga_Reset
|
2024-01-11 07:23:05 +00:00
|
|
|
std::unique_ptr<Gpio> vdd_3voff_;
|
|
|
|
std::unique_ptr<Gpio> vdd_5ven_;
|
|
|
|
std::unique_ptr<Gpio> init_done_;
|
|
|
|
std::unique_ptr<Gpio> img_tx_;
|
2023-12-20 07:23:24 +00:00
|
|
|
|
|
|
|
public:
|
|
|
|
controller();
|
|
|
|
~controller();
|
|
|
|
|
|
|
|
public:
|
|
|
|
void reset(void);
|
|
|
|
void reload(void);
|
|
|
|
};
|
|
|
|
std::unique_ptr<controller> controller_;
|
|
|
|
|
2023-12-19 07:27:16 +00:00
|
|
|
public:
|
2024-01-05 09:36:50 +00:00
|
|
|
FpgaComm(int bauds = 921600, bool query = false);
|
2023-12-19 07:27:16 +00:00
|
|
|
virtual ~FpgaComm(){}
|
|
|
|
|
|
|
|
void reset();
|
|
|
|
void regsAccess_reset(bool enable);
|
|
|
|
void setRegs(int addr, int value);
|
|
|
|
int getRegs(int addr);
|
|
|
|
void setFrameHeight(int height);
|
|
|
|
int getFrameHeight();
|
2024-01-17 08:54:06 +00:00
|
|
|
int get_real_height(void);
|
2023-12-19 07:27:16 +00:00
|
|
|
void setFrameNum(int num);
|
|
|
|
void enableLed(bool bEnable);
|
|
|
|
void enableUV(bool enable);
|
|
|
|
void capture();
|
|
|
|
void setAGain(int indexGain, int value);
|
|
|
|
void setBGain(int indexGain, int value);
|
|
|
|
void setAOffset(int indexOffset, int value);
|
|
|
|
void setBOffset(int indexOffset, int value);
|
|
|
|
|
|
|
|
void setAExposureR(int value);
|
|
|
|
void setAExposureG(int value);
|
|
|
|
void setAExposureB(int value);
|
|
|
|
void setAExposureUV(int value);
|
|
|
|
|
|
|
|
void setBExposureR(int value);
|
|
|
|
void setBExposureG(int value);
|
|
|
|
void setBExposureB(int value);
|
|
|
|
void setBExpousreUV(int value);
|
|
|
|
|
|
|
|
void setSp(int value);
|
|
|
|
int getSp();
|
|
|
|
|
|
|
|
void EnableTest(bool bTest);
|
|
|
|
int IsTest();
|
|
|
|
|
|
|
|
void setColorMode(int mode);
|
|
|
|
int getColorMode();
|
|
|
|
|
|
|
|
void setDpi(int dpi);
|
|
|
|
int getDpi();
|
|
|
|
|
|
|
|
void setSample(int sample);
|
|
|
|
int getSample();
|
|
|
|
|
|
|
|
//20190626 YHP autoTrig function
|
|
|
|
void setDelayTime(int value);
|
|
|
|
void setTrigMode(bool isArmMode);
|
|
|
|
|
2024-01-23 07:07:17 +00:00
|
|
|
bool update(std::vector<int>* data = nullptr);
|
2023-12-19 07:27:16 +00:00
|
|
|
void enableJamCheck(bool b);
|
|
|
|
void resetADC();
|
|
|
|
virtual bool write(unsigned int addr, unsigned int val);
|
|
|
|
virtual bool read(unsigned int addr, unsigned int& val);
|
|
|
|
|
2024-01-05 09:36:50 +00:00
|
|
|
bool is_ok(void);
|
2024-01-19 08:54:58 +00:00
|
|
|
void setVsp(unsigned int Aside,unsigned int BSide);
|
2024-01-05 09:36:50 +00:00
|
|
|
|
2023-12-19 07:27:16 +00:00
|
|
|
private:
|
|
|
|
FpgaParams fpgaParams;
|
|
|
|
std::shared_ptr<IRegsAccess> m_regsAccess;
|
|
|
|
};
|