//
// Created by Nick on 2019/4/7.
//
#include "FpgaComm.h"
#include <thread>
#include "uartregsaccess.h"
#include "config.h"
#include <iostream>

#define Reg(x) (fpgaParams.x)
#define RegIndex(x) (std::distance((unsigned int *)&fpgaParams, (unsigned int *)&fpgaParams.x))
#define ReadReg(x) read(RegIndex(x), *((unsigned int *)&fpgaParams.x))
#define WriteReg(x) write(RegIndex(x), *((unsigned int *)&fpgaParams.x))
#define WR_Reg(x) (WriteReg(x), ReadReg(x))

#define CO(x) std::cout << #x << " : " << RegIndex(x) << std::endl

FpgaComm::FpgaComm()
{
    m_regsAccess.reset(new UartRegsAccess(FPGA_UART, 921600, 0x03, 0x83));
    // update(0);

    // Reg(AledR).sample = 256;
    // WR_Reg(AledR);
}

void FpgaComm::regsAccess_reset(bool enable)
{
    if (enable)
    {
        if (!m_regsAccess.get())
            m_regsAccess.reset(new UartRegsAccess(FPGA_UART, 921600, 0x03, 0x83));
        return;
    }
    if (m_regsAccess.get())
        m_regsAccess.reset();
}

bool FpgaComm::read(unsigned int addr, unsigned int &val)
{
    if (m_regsAccess.get())
        return m_regsAccess->read(addr, val);
    return false;
}

bool FpgaComm::write(unsigned int addr, unsigned int val)
{
    if (m_regsAccess.get())
        return m_regsAccess->write(addr, val);
    return false;
}

void FpgaComm::setFrameHeight(int height)
{
    Reg(frame).height = height;
    WR_Reg(frame);
}

int FpgaComm::getFrameHeight()
{
    return Reg(frame).height;
}

void FpgaComm::setFrameNum(int num)
{
    Reg(frame).num = num;
    WR_Reg(frame);
}

void FpgaComm::enableLed(bool bEnable)
{
    Reg(AledR).ledEnable = bEnable;
    WR_Reg(AledR);
#ifdef HAS_UV
    Reg(BledR).ledEnable = bEnable;
    WR_Reg(BledR);
#else
    Reg(BledR).ledEnable = !bEnable;
    WR_Reg(BledR);
#endif
}

void FpgaComm::enableUV(bool enable)
{
#ifdef HAS_UV
    isUVEnable = enable;
    Reg(BledR).ledEnable = isUVEnable;
    WR_Reg(BledR);
#endif
}

void FpgaComm::capture()
{
    ReadReg(cmd);
    Reg(cmd).cmd = 0;
    WriteReg(cmd);
    Reg(cmd).cmd = 1;
    WriteReg(cmd);
}

int FpgaComm::getRegs(int addr)
{
    return fpgaParams.regs[addr];
}

void FpgaComm::setRegs(int addr, int value)
{
    fpgaParams.regs[addr] = value;
    write(addr, value);
    read(addr, fpgaParams.regs[addr]);
}

void FpgaComm::setAGain(int indexGain, int value)
{
    int index = indexGain;
    int val; // = value
    value >= 511 ? val = 511 : val = value;
    index++;
    fpgaParams.Aad.ad0_addr = index * 2;
    fpgaParams.Aad.ad1_addr = fpgaParams.Aad.ad0_addr + 1;
    fpgaParams.Aad.ad0_value = val;
    fpgaParams.Aad.ad1_value = val > 255 ? 1 : 0;
    fpgaParams.Aad.ad0_rw = 0;
    fpgaParams.Aad.ad1_rw = 0;
    write(0x04, *(int *)&fpgaParams.Aad);
    Reg(mode).adcA = 1;
    WriteReg(mode);
    Reg(mode).adcA = 0;
    WriteReg(mode);
}

void FpgaComm::setBGain(int indexGain, int value)
{
    int index = indexGain;
    int val; // = value
    value >= 511 ? val = 511 : val = value;
    index++;
    fpgaParams.Bad.ad0_addr = index * 2;
    fpgaParams.Bad.ad1_addr = index * 2 + 1;
    fpgaParams.Bad.ad0_value = val;
    fpgaParams.Bad.ad1_value = val > 255 ? 1 : 0;
    fpgaParams.Bad.ad0_rw = 0;
    fpgaParams.Bad.ad1_rw = 0;
    write(0x07, *(int *)&fpgaParams.Bad);
    Reg(mode).adcB = 1;
    WriteReg(mode);
    Reg(mode).adcB = 0;
    WriteReg(mode);
}

void FpgaComm::setAOffset(int indexOffset, int value)
{
    Reg(Aad).ad0_rw = 0;
    Reg(Aad).ad1_rw = 0;
    Reg(Aad).ad0_addr = indexOffset + 0x0e;
    Reg(Aad).ad1_addr = 0x14;
    Reg(Aad).ad0_value = value;
    WriteReg(Aad);
    Reg(mode).adcA = 1;
    WriteReg(mode);
    Reg(mode).adcA = 0;
    WriteReg(mode);
}

void FpgaComm::setBOffset(int indexOffset, int value)
{
    Reg(Bad).ad0_rw = 0;
    Reg(Bad).ad1_rw = 0;
    Reg(Bad).ad0_addr = indexOffset + 0x0e;
    Reg(Bad).ad1_addr = 0x14;
    Reg(Bad).ad0_value = value;
    WriteReg(Bad);
    Reg(mode).adcB = 1;
    WriteReg(mode);
    Reg(mode).adcB = 0;
    WriteReg(mode);
}

void FpgaComm::setAExposureR(int value)
{
    Reg(AledR).ledR = value;
    WR_Reg(AledR);
}

void FpgaComm::setAExposureG(int value)
{
    Reg(AledGB).ledG = value;
    WR_Reg(AledGB);
}

void FpgaComm::setAExposureB(int value)
{
    Reg(AledGB).ledB = value;
    WR_Reg(AledGB);
}

void FpgaComm::setAExposureUV(int value)
{
#ifdef HAS_UV
    Reg(UVLed).ledASide = value;
    WR_Reg(UVLed);
#endif
}

void FpgaComm::setBExposureR(int value)
{
    Reg(BledR).ledR = value;
    WR_Reg(BledR);
}

void FpgaComm::setBExposureG(int value)
{
    Reg(BledGB).ledG = value;
    WR_Reg(BledGB);
}

void FpgaComm::setBExposureB(int value)
{
    Reg(BledGB).ledB = value;
    WR_Reg(BledGB);
}

void FpgaComm::setBExpousreUV(int value)
{
#ifdef HAS_UV
    Reg(UVLed).ledBSide = value;
    WR_Reg(UVLed);
#endif
}

void FpgaComm::setSp(int value)
{
    Reg(mode).sp = value;
    WR_Reg(mode);
}

int FpgaComm::getSp()
{
    return Reg(mode).sp;
}

void FpgaComm::setColorMode(int mode)
{
    Reg(mode).colorMode = mode;
    WR_Reg(mode);
}

int FpgaComm::getColorMode()
{
    return Reg(mode).colorMode;
}

void FpgaComm::setSample(int sample)
{
    Reg(mode).sample = sample;
    WR_Reg(mode);
    Reg(AledR).sample = sample;
    WR_Reg(AledR);
}

void FpgaComm::EnableTest(bool bTest)
{
    Reg(mode).selftest = bTest;
    WR_Reg(mode);
}

int FpgaComm::IsTest()
{
    return Reg(mode).selftest;
}

int FpgaComm::getSample()
{
    return Reg(mode).sample;
}

void FpgaComm::setDpi(int dpi)
{
    Reg(mode).dpi = dpi;
    WR_Reg(mode);
}

int FpgaComm::getDpi()
{
    return Reg(mode).dpi;
}

// 20190626 YHP autoTrig function
void FpgaComm::setTrigMode(bool isArmMode)
{
    unsigned int tmp;
    read(0x0b, tmp);
    if (!isArmMode)
    { // default value+ ARM MODE,bit27 =0;
        fpgaParams.TrigMode = tmp & 0XFBFFFFFF;
    }
    else
    {
        fpgaParams.TrigMode = tmp | (1 << 26);
    }
    WR_Reg(TrigMode);
}
void FpgaComm::setDelayTime(int value)
{
    // Reg(DelayTime) = value;
    // WR_Reg(DelayTime);
}

void FpgaComm::update(int times)
{
    std::uint32_t tmp_reg = 0;
    for (int i = 0; i < 22; i++)
    {
        read(i, tmp_reg);
        printf("times[%d] reg[%d]  = 0x%08x \n", times, i, tmp_reg);
    }
}

void FpgaComm::enableJamCheck(bool b)
{
    // Reg(BledR).user_define.led_sample.jamEnable = b;
    // WR_Regs(0x08);
}

void FpgaComm::resetADC()
{

    fpgaParams.Aad.ad0_rw = 0;
    fpgaParams.Aad.ad0_addr = 0;
    fpgaParams.Aad.ad0_value = 0;
    fpgaParams.Aad.ad1_rw = 0;
    fpgaParams.Aad.ad1_addr = 0;
    fpgaParams.Aad.ad1_value = 0;
    WR_Reg(Aad);
    fpgaParams.mode.adcA = 1;
    WR_Reg(mode);
    fpgaParams.mode.adcA = 0;
    WR_Reg(mode);
    fpgaParams.Bad.ad0_rw = 0;
    fpgaParams.Bad.ad0_addr = 0;
    fpgaParams.Bad.ad0_value = 0;
    fpgaParams.Bad.ad1_rw = 0;
    fpgaParams.Bad.ad1_addr = 0;
    fpgaParams.Bad.ad1_value = 0;
    WR_Reg(Bad);
    fpgaParams.mode.adcB = 1;
    WR_Reg(mode);
    fpgaParams.mode.adcB = 0;
    WR_Reg(mode);
    std::this_thread::sleep_for(std::chrono::milliseconds(100));
    fpgaParams.Aad.ad0_rw = 0;
    fpgaParams.Aad.ad0_addr = 0;
    fpgaParams.Aad.ad0_value = 7;
    fpgaParams.Aad.ad1_rw = 0;
    fpgaParams.Aad.ad1_addr = 0;
    fpgaParams.Aad.ad1_value = 7;
    WR_Reg(Aad);
    fpgaParams.mode.adcA = 1;
    WR_Reg(mode);
    fpgaParams.mode.adcA = 0;
    WR_Reg(mode);
    fpgaParams.Bad.ad0_rw = 0;
    fpgaParams.Bad.ad0_addr = 0;
    fpgaParams.Bad.ad0_value = 7;
    fpgaParams.Bad.ad1_rw = 0;
    fpgaParams.Bad.ad1_addr = 0;
    fpgaParams.Bad.ad1_value = 7;
    WR_Reg(Bad);
    fpgaParams.mode.adcB = 1;
    WR_Reg(mode);
    fpgaParams.mode.adcB = 0;
    WR_Reg(mode);
    fpgaParams.Aad.ad0_rw = 0;
    fpgaParams.Aad.ad0_addr = 1;
    fpgaParams.Aad.ad0_value = 0x50;
    fpgaParams.Aad.ad1_rw = 0;
    fpgaParams.Aad.ad1_addr = 1;
    fpgaParams.Aad.ad1_value = 0x50;
    WR_Reg(Aad);
    fpgaParams.mode.adcA = 1;
    WR_Reg(mode);
    fpgaParams.mode.adcA = 0;
    WR_Reg(mode);
    fpgaParams.Bad.ad0_rw = 0;
    fpgaParams.Bad.ad0_addr = 1;
    fpgaParams.Bad.ad0_value = 0x50;
    fpgaParams.Bad.ad1_rw = 0;
    fpgaParams.Bad.ad1_addr = 1;
    fpgaParams.Bad.ad1_value = 0x50;
    WR_Reg(Bad);
    fpgaParams.mode.adcB = 1;
    WR_Reg(mode);
    fpgaParams.mode.adcB = 0;
    WR_Reg(mode);
}

void FpgaComm::setEnTestCol(bool en)
{
    Reg(AledR).en_test_color = en ? 1 : 0;
    WR_Reg(AledR);
}

void FpgaComm::setEnTestBit(bool en)
{
    Reg(AledR).en_test = en ? 1 : 0;
    WR_Reg(AledR);
}

void FpgaComm::setVsp(unsigned int Aside, unsigned int BSide)
{
    CISVSP vsp;
    vsp.bits.ASide_VSP = Aside;
    vsp.bits.BSide_VSP = BSide;
    vsp.bits.reserved = 0;
    printf("setVsp A side =%d  B side=%d  vspint=%08x  \n", vsp.bits.ASide_VSP, vsp.bits.BSide_VSP, vsp.value);
    m_regsAccess->write(13, vsp.value);
}

void FpgaComm::setFrame_interval_min(int min)
{
    fpgaParams.FrameInterval.Frame_Interval_min = min;
    fpgaParams.FrameInterval.reversed = 0;
    WR_Reg(FrameInterval);
}

int FpgaComm::getFrame_interval_min()
{
    uint32_t value = 0;
    fpgaParams.FrameInterval.reversed = 0;
    read(0x0c, value);
    fpgaParams.FrameInterval = *(CisFrameInterval *)&value;
    return fpgaParams.FrameInterval.Frame_Interval_min;
}

void FpgaComm::setFrame_interval_max(int max)
{
    fpgaParams.FrameInterval.Frame_Interval_max = max;
    fpgaParams.FrameInterval.reversed = 0;
    WR_Reg(FrameInterval);
}

int FpgaComm::getFrame_interval_max()
{
    uint32_t value = 0;
    fpgaParams.FrameInterval.reversed = 0;
    read(0x0c, value);
    fpgaParams.FrameInterval = *(CisFrameInterval *)&value;
    return fpgaParams.FrameInterval.Frame_Interval_max;
}

unsigned int FpgaComm::getFrame_counter_val()
{
    uint32_t crt_frame_count = 0;
    uint32_t reg8 = 0;

    read(8, reg8);
    // write(8,reg8 & 0x8);
    //  std::this_thread::sleep_for(std::chrono::milliseconds(2));
    write(8, reg8 & 0xfffffff7); // off stop snap
    read(8, reg8);
    // std::this_thread::sleep_for(std::chrono::milliseconds(2));
    read(0x10, crt_frame_count);

    if (crt_frame_count & 0xffff <= 0)
    {
        for (int i = 0; i < 3; i++)
        {
            read(0x10, crt_frame_count);
            printf("try %d times read frame count,frame_count = %d \n", i, crt_frame_count);
            if (crt_frame_count & 0xffff > 0)
                break;
        }
    }
    write(8, reg8 | 0x8); // on  reset counter
    // std::this_thread::sleep_for(std::chrono::milliseconds(2));
    // printf("TWO height reg[14] = %d  reg[16] = %d  \n", read(14) & 0xffff,read(16));
    return crt_frame_count & 0xffff;
}

int FpgaComm::getFrameNum()
{
    return fpgaParams.frame.num;
}

void FpgaComm::set_cis_type(bool isA3_CIS)
{
    fpgaParams.AledR.cis_type = isA3_CIS ? 1 : 0;
}

void FpgaComm::set_8478_type(bool is_HL)
{
    ReadReg(cmd);
    Reg(cmd).cis_HL = is_HL;
    WriteReg(cmd);
}